WO2020133651A1 - 像素电极结构及其制作方法 - Google Patents

像素电极结构及其制作方法 Download PDF

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Publication number
WO2020133651A1
WO2020133651A1 PCT/CN2019/075595 CN2019075595W WO2020133651A1 WO 2020133651 A1 WO2020133651 A1 WO 2020133651A1 CN 2019075595 W CN2019075595 W CN 2019075595W WO 2020133651 A1 WO2020133651 A1 WO 2020133651A1
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Prior art keywords
electrode
gate
metal layer
source
drain
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PCT/CN2019/075595
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English (en)
French (fr)
Inventor
徐洪远
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020133651A1 publication Critical patent/WO2020133651A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, and in particular to a pixel electrode structure and a manufacturing method thereof.
  • Liquid crystal display (Liquid Crystal Display, LCD) is one of the most widely used flat panel displays, and the liquid crystal panel is the core component of the liquid crystal display.
  • the liquid crystal panel is usually composed of a color filter substrate (Color Filter, CF), a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • pixel electrodes and common electrodes are provided on the array substrate and the color filter substrate, respectively. When a voltage is applied to the pixel electrode and the common electrode, an electric field is generated in the liquid crystal layer. The electric field determines the orientation of the liquid crystal molecules, thereby adjusting the polarization of the light incident on the liquid crystal layer and causing the liquid crystal panel to display an image.
  • the prior art divides a pixel unit into a primary area and a secondary area, an independent primary area pixel electrode is provided in the primary area, and an independent secondary area pixel electrode is provided in the secondary area.
  • Both the pixel electrode in the main area and the pixel electrode in the sub area are used "Mi" shape structure design.
  • the existing pixel driving circuits provided on the TFT array substrate all include a charge sharing thin film transistor, a main area thin film transistor, a sub area thin film transistor, a main area pixel electrode, a sub area pixel electrode, a main area storage capacitor, and a sub area storage capacitor,
  • the gates of the main area thin film transistor, the secondary area thin film transistor and the charge sharing thin film transistor are all electrically connected to a gate line, and the sources of the main area thin film transistor and the secondary area thin film transistor are electrically connected to a source line
  • the drains of the thin film transistors in the main region and the thin film transistors in the secondary region are electrically connected to the pixel electrodes in the main region and the pixel electrodes in the secondary region, respectively, the source of the charge sharing thin film transistor is electrically connected to the common electrode line, and the drain of the charge sharing thin film transistor is electrically connected In the sub-region pixel electrode, one end of the main region storage capacitor is electrically connected to the drain of the main region thin film transistor, the other end is
  • the gates, gate lines and common electrode lines of the main area thin film transistor, the secondary area thin film transistor and the charge sharing thin film transistor are located in the first metal layer, and the source electrodes of the main area thin film transistor, the secondary area thin film transistor and the charge sharing thin film transistor
  • the drain and source lines are located in the second metal layer, the pixel electrodes in the main region and the pixel electrodes in the secondary region are located in the transparent metal layer, and a float located in the transparent metal layer needs to be used between the source and common electrode lines of the charge sharing thin film transistor
  • the electrodes are electrically connected through a deep and shallow hole, as shown in FIG.
  • the deep and shallow hole includes a deep hole 100c passing through the insulating layer between the floating electrode 100a and the common electrode line 100b, and a signal passing through the floating electrode 100a and the charge sharing thin film transistor
  • the insulating layer between the source electrode 100d and the shallow hole 100e communicating with the deep hole 100c, the existing deep shallow hole unit is likely to appear at a position 100f below the source electrode 100d of the charge sharing thin film transistor during the manufacturing process Undercut causes the floating electrode 100a to break when climbing, which leads to poor display.
  • the object of the present invention is to provide a pixel electrode structure, which can prevent the floating electrode from being broken in the deep and shallow holes and avoid poor display.
  • the object of the present invention is also to provide a manufacturing method of a pixel circuit structure, which can prevent the floating electrode from being broken in the deep and shallow holes and avoid display defects.
  • the present invention provides a pixel circuit structure, including: a base substrate, a first metal layer provided on the base substrate, a gate provided on the first metal layer and the base substrate Electrode insulating layer, semiconductor layer provided on the gate insulating layer, second metal layer provided on the semiconductor layer, passivation layer provided on the second metal layer and the semiconductor layer, and provided on the The transparent metal layer on the passivation layer;
  • the first metal layer includes a first gate and a common electrode line spaced apart from the first gate;
  • the second metal layer includes a first source disposed corresponding to the first gate and spaced apart from each other and A first drain;
  • the transparent metal layer includes a floating electrode;
  • the first source electrode partially overlaps the common electrode line, and a shallow hole is formed in an area where the common electrode line overlaps the first source electrode, the deep hole includes passing through the passivation layer and the gate An insulating layer and a deep hole exposing a part of the common electrode line, a first shallow hole passing through the passivation layer on one side of the deep hole and part of the gate insulating layer and communicating with the deep hole, passing through the first A second shallow hole far away from the passivation layer on the side of the deep hole and communicating with the first shallow hole and exposing a part of the first source electrode;
  • the floating electrode is electrically connected to the first source electrode and the common electrode line through the deep and shallow holes.
  • the first metal layer further includes spaced second and third gates, and a gate line electrically connecting the first gate, the second gate, and the third gate, the common electrode line and the gate The second grid, the third grid and the gate line spacing;
  • the second metal layer further includes a second source electrode and a second drain electrode disposed and spaced apart corresponding to the second gate, and a third source electrode and a third drain electrode disposed and spaced apart from each other corresponding to the third gate electrode Electrode and a source line electrically connecting the second source electrode and the third source electrode, the second drain electrode is electrically connected to the first drain electrode, and the third drain electrode is electrically connected to the transparent metal layer .
  • the second source electrode and the common electrode line partly overlap to form a first storage capacitor, and the third source electrode and the common electrode line partly overlap to form a second storage capacitor.
  • the transparent metal layer further includes spaced-apart pixel electrodes and sub-region pixel electrodes.
  • the floating electrodes are spaced apart from the main-region pixel electrodes and the sub-region pixel electrodes.
  • the main-region pixel electrodes are electrically connected to the Three drains, the pixel electrode in the sub-region is electrically connected to the second drain.
  • the pixel electrodes in the primary area and the pixel electrodes in the secondary area are both "meter" shaped electrodes.
  • the invention also provides a method for manufacturing a pixel circuit structure, including the following steps:
  • Step S1 providing a base substrate, forming a first metal layer on the base substrate, and forming a gate insulating layer on the first metal layer and the base substrate;
  • the first metal layer includes the first A grid and a common electrode line spaced apart from the first grid;
  • Step S2 forming a semiconductor film, a second metal film, and a first photoresist film that are sequentially stacked on the gate insulating layer;
  • Step S3 Expose and develop the first photoresist film through a photomask process to form a first photoresist segment on the area where the first source and the first drain are to be formed and on the first shallow to be formed A second photoresist segment on the area of the hole, the thickness of the first photoresist segment is greater than that of the second photoresist segment;
  • Step S4 Using the first photoresist segment and the second photoresist segment as shields, the semiconductor film and the second metal film are etched to remove areas not blocked by the first photoresist segment and the second photoresist segment Semiconductor thin film and second metal thin film;
  • Step S5. Remove the second photoresist segment and thin the first photoresist segment. Using the remaining first photoresist segment as a shield, etch the second metal thin film to remove the first part of the area not blocked by the first photoresist segment Two metal thin films to form a second metal layer, the second metal layer includes a first source electrode and a first drain electrode disposed corresponding to the first gate electrode and spaced apart from each other, the first source electrode and the common electrode Lines partially overlap;
  • Step S6 removing the remaining first photoresist segment, forming a passivation layer on the gate insulating layer, the second metal layer and the semiconductor film, and forming a second photoresist film on the passivation layer;
  • Step S7 Expose and develop the second photoresist film through a photomask, remove the second photoresist film on the area where the deep and shallow holes are to be formed, and use the remaining second photoresist film as a shield against the passivation layer and the semiconductor
  • the thin film and the gate insulating layer are etched to form a deep hole passing through the passivation layer and the gate insulating layer and exposing a part of the common electrode line, a passivation layer and a part of the gate passing through the deep hole side
  • the second shallow hole, the deep hole, the first shallow hole and the second shallow hole together form a deep shallow hole;
  • Step S8 forming a transparent metal layer on the passivation layer and the shallow hole, the transparent metal layer includes a floating electrode, and the floating electrode is electrically connected to the first source electrode and the common electrode through the deep hole line.
  • the step S1 specifically includes: forming a first metal film on the base substrate, and patterning the first metal film through a photomask process to form a first metal layer, and the first metal layer is also provided at intervals A second gate and a third gate and a gate line electrically connecting the first gate, the second gate and the third gate, the common electrode line and the second gate, the third gate and Gate line spacing;
  • the first photoresist segment in the step S3 is also formed in the area where the second source, the second drain, the third source, the third drain and the source line are to be formed; the second formed in the step S5
  • the metal layer further includes a second source electrode and a second drain electrode disposed and spaced apart from each other, a third source electrode and a third drain electrode disposed and spaced apart from each other, and electrical properties
  • a source line connecting the second source electrode and the third source electrode, the second drain electrode is electrically connected to the first drain electrode, and the third drain electrode is electrically connected to the transparent metal layer.
  • the second source electrode and the common electrode line partly overlap to form a first storage capacitor, and the third source electrode and the common electrode line partly overlap to form a second storage capacitor.
  • the step S8 specifically includes: forming a transparent metal film on the passivation layer and the shallow holes, and patterning the transparent metal film through a mask to form a transparent metal layer; the transparent metal layer further includes a spacer
  • the pixel electrodes of the main area and the pixel electrodes of the sub area are distributed.
  • the floating electrodes are spaced apart from the pixel electrodes of the main area and the pixel electrodes of the sub area.
  • the pixel electrodes of the main area are electrically connected to the third drain.
  • the pixel electrode is electrically connected to the second drain.
  • the pixel electrodes in the primary area and the pixel electrodes in the secondary area are both "meter" shaped electrodes.
  • the present invention provides a pixel circuit structure, including: a base substrate, a first metal layer provided on the base substrate, a gate provided on the first metal layer and the base substrate Electrode insulating layer, semiconductor layer provided on the gate insulating layer, second metal layer provided on the semiconductor layer, passivation layer provided on the second metal layer and the semiconductor layer, and provided on the A transparent metal layer on the passivation layer;
  • the first metal layer includes a first gate and a common electrode line spaced apart from the first gate;
  • the second metal layer includes corresponding to the first gate A first source electrode and a first drain electrode provided and spaced apart from each other;
  • the transparent metal layer includes a floating electrode; the first source electrode partially overlaps with the common electrode line, and the common electrode line is A deep and shallow hole is formed in a region where the source electrodes overlap, and the floating electrode is electrically connected to the first source electrode and the common electrode line through the deep and shallow hole, the deep and shallow hole is a deep hole and a first shallow
  • Figure 1 is a schematic diagram of the structure of the existing deep and shallow holes
  • FIG. 2 is a schematic diagram of the pixel circuit structure of the present invention.
  • step S1 and step S2 of the manufacturing method of the pixel circuit structure of the present invention are schematic diagrams of step S1 and step S2 of the manufacturing method of the pixel circuit structure of the present invention.
  • step S3 is a schematic diagram of step S3 of the method for manufacturing a pixel circuit structure of the present invention.
  • step S4 of the manufacturing method of the pixel circuit structure of the present invention
  • step S5 is a schematic diagram of step S5 of the manufacturing method of the pixel circuit structure of the present invention.
  • step S6 is a schematic diagram of step S6 of the manufacturing method of the pixel circuit structure of the present invention.
  • step S7 of the manufacturing method of the pixel circuit structure of the present invention is a schematic diagram of step S7 of the manufacturing method of the pixel circuit structure of the present invention.
  • step S8 of the manufacturing method of the pixel circuit structure of the present invention is a schematic diagram of step S8 of the manufacturing method of the pixel circuit structure of the present invention and a schematic diagram of the structure of the deep and shallow holes in the pixel circuit structure of the present invention;
  • FIG. 11 is a flowchart of a method for manufacturing a pixel circuit structure of the present invention.
  • the present invention provides a pixel circuit structure, including: a base substrate 10, a first metal layer 20 disposed on the base substrate 10, the first metal layer 20 and The gate insulating layer 30 on the base substrate 10, the semiconductor layer 40 provided on the gate insulating layer 30, the second metal layer 50 provided on the semiconductor layer 40, and the second metal layer 50 and a passivation layer 70 on the semiconductor layer 40 and a transparent metal layer 80 provided on the passivation layer 70;
  • the first metal layer 20 includes a first gate 21 and a common electrode line 22 spaced apart from the first gate 21; the second metal layer 50 includes a space corresponding to the first gate 21 and spaced apart from each other The first source electrode 51 and the first drain electrode 52; the transparent metal layer 80 includes a floating electrode 81;
  • the first source electrode 51 and the common electrode line 22 partially overlap, and a deep and shallow hole 100 is formed in an area where the common electrode line 22 and the first source electrode 51 overlap, and the deep and shallow hole 100 includes crossing the
  • the passivation layer 70 and the gate insulating layer 30 expose a part of the deep hole 101 of the common electrode line 22, the passivation layer 70 and part of the gate insulating layer 30 passing through the deep hole 101 side
  • the first shallow hole 102 communicating with the deep hole 101 and the passivation layer 70 passing through the side of the first shallow hole 102 away from the deep hole 101 and communicating with the first shallow hole 102 and exposing the first source electrode 51 Part of the second shallow hole 103;
  • the floating electrode 81 is electrically connected to the first source electrode 51 and the common electrode line 22 through the deep and shallow holes 100.
  • the first metal layer 20 further includes a second gate 23 and a third gate 24 spaced apart and a gate electrically connected to the first gate 21, the second gate 23, and the third gate 24 Line 25, the common electrode line 22 is spaced from the second gate 23, the third gate 24 and the gate line 25;
  • the second metal layer 50 further includes a second source 53 and a second drain 54 disposed corresponding to the second gate 23 and spaced apart from each other, and a third source disposed corresponding to the third gate 24 and spaced apart from each other
  • the second drain electrode 54 is electrically connected to the first drain electrode 52
  • the third drain 56 is electrically connected to the transparent metal layer 80.
  • the semiconductor layer 40 is disposed under the second metal layer 50, between the first source electrode 51 and the first drain electrode 52 in the first channel region, the second source electrode 53 and the second drain electrode The second channel region between 54 and the third channel region between the third source 55 and the third drain 56.
  • the transparent metal layer 80 further includes a main area pixel electrode 82 and a sub area pixel electrode 83 which are distributed at intervals.
  • the floating electrode 81 is spaced apart from the main area pixel electrode 82 and the sub area pixel electrode 83.
  • the pixel electrode 82 in the main region is electrically connected to the third drain 56, and the pixel electrode 83 in the sub region is electrically connected to the second drain 54.
  • the pixel electrode 82 in the main area and the pixel electrode 83 in the sub area are both "meter" shaped electrodes.
  • the pixel electrode 82 in the main area is electrically connected to the third drain 56 through a first via 91 passing through the passivation layer 70, and the pixel electrode 83 in the sub area passes through a second through the passivation layer 70
  • the via 92 is electrically connected to the second drain 54.
  • the base substrate 10 is a glass substrate
  • the materials of the first metal layer 20 and the second metal layer 50 are one or more combinations of molybdenum, titanium, aluminum and copper
  • the gate insulating layer The material of 30 and the passivation layer 70 is one or a combination of silicon oxide and silicon nitride
  • the material of the semiconductor layer 40 is amorphous silicon
  • the material of the transparent metal layer 80 is indium tin oxide.
  • the first gate 21, the first source 51 and the first drain 52 form a first thin film transistor T1
  • the second gate 23, the second source 53 and the second drain 54 form A second thin film transistor T2
  • a third gate 24, a second source 53 and a second drain 54 form a third thin film transistor T3, the second source 53 and the common electrode line 22 partially overlap to form a first
  • the storage capacitor C1, the third source electrode 55 and the common electrode line 22 partially overlap to form a second storage capacitor C2, and finally a pixel driving circuit with a charge sharing function as shown in FIG. 10 is formed.
  • the potential of the sub-region pixel electrode 83 is pulled down by the first thin film transistor T1, so that the main-region pixel electrode 82 and the sub-region pixel electrode 83 have different potentials, forming an eight-domain structure to expand the viewing angle of the liquid crystal display panel.
  • providing the deep and shallow holes 100 includes a deep hole 101 passing through the passivation layer 70 and the gate insulating layer 30 and exposing a part of the common electrode line 22, passing through the deep hole A passivation layer 70 on the side of 101 and a portion of the gate insulating layer 30 and the first shallow hole 102 communicating with the deep hole 101 pass through the passivation of the side of the first shallow hole 102 away from the deep hole 101 Layer 70 and the second shallow hole 103 communicating with the first shallow hole 102 and exposing a part of the first source 51, by providing a three-level deep shallow hole with a deep hole 101, a first shallow hole 102 and a second shallow hole 103 This can reduce the climbing angle of the floating electrode 81, prevent the floating electrode 81 from being broken in the shallow hole 100, and avoid poor display.
  • the present invention also provides a method for manufacturing a pixel circuit structure, including the following steps:
  • Step S1 as shown in FIG. 3, a base substrate 10 is provided, a first metal layer 20 is formed on the base substrate 10, and a gate insulation is formed on the first metal layer 20 and the base substrate 10 Layer 30;
  • the first metal layer 20 includes a first gate 21 and a common electrode line 22 spaced apart from the first gate 21.
  • the step S1 specifically includes: forming a first metal film on the base substrate 10, and patterning the first metal film through a photomask process to form a first metal layer 20, the first metal
  • the layer 20 further includes a second gate 23 and a third gate 24 spaced apart and a gate line 25 electrically connected to the first gate 21, the second gate 23, and the third gate 24, and the common electrode line 22
  • the second gate 23, the third gate 24 and the gate line 25 are spaced apart.
  • Step S2 As shown in FIG. 3, a semiconductor film 400, a second metal film 500, and a first photoresist film 600 that are sequentially stacked on the gate insulating layer 30 are formed.
  • Step S3 the first photoresist film 600 is exposed and developed through a photomask process to form the first light on the area where the first source 51 and the first drain 52 are to be formed.
  • the thickness of the first photoresist section 601 is greater than that of the second photoresist section 602.
  • the first photoresist segment 601 is also formed in a region where the second source electrode 53, the second drain electrode 54, the third source electrode 55, the third drain electrode 56, and the source line 57 are to be formed.
  • the second photoresist segment 602 is also formed between the first channel region to be formed between the first source electrode 51 and the first drain electrode 52, and the second source electrode 53 and the second drain electrode 54 to be formed Between the second channel region and the third channel region between the third source 55 and the third drain 56 to be formed.
  • Step S4 As shown in FIG. 5, using the first photoresist section 601 and the second photoresist section 602 as shields, the semiconductor film 400 and the second metal film 500 are etched to remove the first photoresist The semiconductor film 400 and the second metal film 500 in the region blocked by the segment 601 and the second photoresist segment 602.
  • the semiconductor thin film 400 and the second metal thin film 500 removed in the step S4 are the third source except the first source 51, the first drain 52, the second source 53, and the second drain 54 to be formed
  • the semiconductor thin film 400 and the second metal thin film 500 other than the region of the electrode 55, the third drain 56, the gate line 57, the first channel region, the second channel region, the third channel region, and the first shallow hole 102 .
  • Step S5 As shown in FIG. 6, the second photoresist segment 602 is removed and the first photoresist segment 601 is thinned. Using the remaining first photoresist segment 601 as a shield, the second metal film 500 is etched to remove The second metal film 500 in the area blocked by the first photoresist section 601 forms a second metal layer 50, the second metal layer 50 includes a first source electrode 51 disposed corresponding to the first gate electrode 21 and spaced apart from each other A first drain 52, the first source 51 and the common electrode line 22 partially overlap.
  • the second metal film 500 removed in the step S5 is the second metal film to be formed on the regions of the first channel region, the second channel region, the third channel region and the first shallow hole 102 500.
  • the second metal layer 50 formed in the step S5 further includes a second source electrode 53 and a second drain electrode 54 spaced apart and corresponding to the second gate electrode 23, and corresponding to the third gate electrode 24
  • a third source 55 and a third drain 56 are provided and spaced apart from each other, and a source line 57 electrically connecting the second source 53 and the third source 55, the second drain 54 and the first A drain 52 is electrically connected, and the third drain 56 is electrically connected to the transparent metal layer 80.
  • Step S6 As shown in FIG. 7, the remaining first photoresist segment 601 is removed, and a passivation layer 70 is formed on the gate insulating layer 30, the second metal layer 50, and the semiconductor film 400.
  • the second photoresist film 700 is formed on 70.
  • Step S7 the second photoresist film 700 is exposed and developed through a photomask to remove the second photoresist film 700 on the area where the deep and shallow holes 100 are to be formed, so that the second photoresist remains
  • the thin film 700 shields the passivation layer 70, the semiconductor film 400, and the gate insulating layer 30 from being etched, forming a deep hole that passes through the passivation layer 70 and the gate insulating layer 30 and exposes a part of the common electrode line 22 101.
  • the passivation layer 70 on one side of 101 communicates with the first shallow hole 102 and exposes a second shallow hole 103 of a part of the first source electrode 51, the deep hole 101, the first shallow hole 102 and the second shallow hole 103 Commonly form the deep and shallow holes 100.
  • the second metal thin film 500 on the region where the first via 91 and the second via 92 are to be formed is also removed, and the step S7 further forms a pass through the passivation layer 70 and exposes the first A first via 91 that is a part of the three drains 56 and a second via 92 that passes through the passivation layer 70 and exposes a part of the second drain 54.
  • Step S8 As shown in FIG. 9, a transparent metal layer 80 is formed on the passivation layer 70 and the deep and shallow holes 100.
  • the transparent metal layer 80 includes a floating electrode 81, and the floating electrode 81 passes through the deep and shallow holes 100 is electrically connected to the first source electrode 51 and the common electrode line 22.
  • the step S8 specifically includes: forming a transparent metal film on the passivation layer 70 and the deep and shallow holes 100, and patterning the transparent metal film through a mask to form a transparent metal layer 80;
  • the transparent metal layer 80 further includes a main area pixel electrode 82 and a sub area pixel electrode 83 distributed at intervals, the floating electrode 81 is spaced from the main area pixel electrode 82 and the sub area pixel electrode 83, and the main area pixel electrode 82 is electrically connected to the third drain electrode 56, and the sub-region pixel electrode 83 is electrically connected to the second drain electrode 54.
  • the pixel electrode 82 in the main area is electrically connected to the third drain 56 through a first via 91 passing through the passivation layer 70, and the pixel electrode 83 in the sub area passes through a second through the passivation layer 70
  • the via 92 is electrically connected to the second drain 54.
  • the gate insulating layer 30 at the bottom of the first shallow hole 102 is not completely removed, but a part is left, thereby making the first shallow hole 102 phase
  • a step is formed compared to the deep hole 101, and the area of the second shallow hole 101 cannot be further etched after being etched to the first source 52, thereby forming a second shallow hole 103 which is shallower than the first shallow hole 102
  • the manufacturing method of the pixel circuit structure of the present invention can be completed through four mask processes without additional number of masks, in which the masks for making the second metal layer 50 and the semiconductor layer 40 are half Hue mask or gray scale mask.
  • the base substrate 10 is a glass substrate
  • the materials of the first metal layer 20 and the second metal layer 50 are one or more combinations of molybdenum, titanium, aluminum and copper
  • the gate insulating layer The material of 30 and the passivation layer 70 is one or a combination of silicon oxide and silicon nitride
  • the material of the semiconductor layer 40 is amorphous silicon
  • the material of the transparent metal layer 80 is indium tin oxide.
  • the first gate 21, the first source 51 and the first drain 52 form a first thin film transistor T1
  • the second gate 23, the second source 53 and the second drain 54 form A second thin film transistor T2
  • a third gate 24, a second source 53 and a second drain 54 form a third thin film transistor T3, the second source 53 and the common electrode line 22 partially overlap to form a first
  • the storage capacitor C1, the third source electrode 55 and the common electrode line 22 partially overlap to form a second storage capacitor C2, and finally a pixel driving circuit with a charge sharing function as shown in FIG. 10 is formed.
  • the potential of the sub-region pixel electrode 83 is pulled down by the first thin film transistor T1, so that the main-region pixel electrode 82 and the sub-region pixel electrode 83 have different potentials, forming an eight-domain structure to expand the viewing angle of the liquid crystal display panel.
  • providing the deep and shallow holes 100 includes a deep hole 101 passing through the passivation layer 70 and the gate insulating layer 30 and exposing a part of the common electrode line 22, passing through the deep hole A passivation layer 70 on the side of 101 and a portion of the gate insulating layer 30 and the first shallow hole 102 communicating with the deep hole 101 pass through the passivation of the side of the first shallow hole 102 away from the deep hole 101 Layer 70 and the second shallow hole 103 communicating with the first shallow hole 102 and exposing a part of the first source 51, by providing a three-level deep shallow hole with a deep hole 101, a first shallow hole 102 and a second shallow hole 103 This can reduce the climbing angle of the floating electrode 81, prevent the floating electrode 81 from being broken in the shallow hole 100, and avoid poor display.
  • the present invention provides a pixel circuit structure, including: a base substrate, a first metal layer provided on the base substrate, a gate provided on the first metal layer and the base substrate An insulating layer, a semiconductor layer provided on the gate insulating layer, a second metal layer provided on the semiconductor layer, a passivation layer provided on the second metal layer and the semiconductor layer, and the A transparent metal layer on the passivation layer;
  • the first metal layer includes a first gate and a common electrode line spaced apart from the first gate;
  • the second metal layer includes a setting corresponding to the first gate And a first source electrode and a first drain electrode that are spaced apart from each other;
  • the transparent metal layer includes a floating electrode; the first source electrode partially overlaps with the common electrode line, and the first electrode and the first source A deep and shallow hole is formed in a region where the electrodes overlap, and the floating electrode is electrically connected to the first source electrode and the common electrode line through the deep and shallow hole, and the deep and shallow hole is a deep hole and a first

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Abstract

一种像素电路结构及其制作方法。像素电路结构包括：衬底基板、设于衬底基板上的第一金属层、设于第一金属层及衬底基板上的栅极绝缘层、设于栅极绝缘层上的半导体层、设于半导体层上的第二金属层、设于第二金属层和半导体层上的钝化层以及设于钝化层上的透明金属层；第一金属层包括第一栅极及与第一栅极间隔设置的公共电极线；第二金属层包括对应第一栅极设置且相互间隔的第一源极和第一漏极；透明金属层包括浮置电极；在公共电极线与第一源极交叠的区域形成有深浅孔，浮置电极通过深浅孔电性连接第一源极和公共电极线，深浅孔为具有依次连通的深孔、第一浅孔和第二浅孔的三层结构，能够防止浮置电极在深浅孔中出现断线。

Description

像素电极结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种像素电极结构及其制作方法。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）是目前最广泛使用的平板显示器之一，液晶面板是液晶显示器的核心组成部分。液晶面板通常是由一彩色滤光片基板（Color Filter，CF）、一薄膜晶体管阵列基板（Thin Film Transistor Array Substrate，TFT Array Substrate）以及一配置于两基板间的液晶层（Liquid Crystal Layer）所构成。一般阵列基板、彩色滤光片基板上分别设置像素电极、公共电极。当电压被施加到像素电极与公共电极便会在液晶层中产生电场，该电场决定了液晶分子的取向，从而调整入射到液晶层的光的偏振，使液晶面板显示图像。
为了改善视觉色差或视觉色偏，现有技术会将一个像素单元分成主区和次区，在主区内设置一个独立的主区像素电极、在次区内设置一个独立的次区像素电极，主区像素电极与次区像素电极均采用 “米”字型结构设计。现有的设置于TFT阵列基板上的像素驱动电路均包括电荷共享薄膜晶体管、主区薄膜晶体管、次区薄膜晶体管、主区像素电极、次区像素电极、主区存储电容和次区存储电容，主区薄膜晶体管、次区薄膜晶体管及电荷共享薄膜晶体管的栅极均电性连接一栅极线，主区薄膜晶体管的源极和次区薄膜晶体管的源极均电性连接一源极线，主区薄膜晶体管和次区薄膜晶体管的漏极分别电性连接主区像素电极和次区像素电极，电荷共享薄膜晶体管的源极电性连接公共电极线，电荷共享薄膜晶体管的漏极电性连接次区像素电极，主区存储电容的一端电性连接主区薄膜晶体管的漏极，另一端电性连接公共电极线，次区存储电容的一端电性连接次区薄膜晶体管的漏极，另一端电性连接公共电极线。
其中，主区薄膜晶体管、次区薄膜晶体管及电荷共享薄膜晶体管的栅极、栅极线及公共电极线位于第一金属层，主区薄膜晶体管、次区薄膜晶体管及电荷共享薄膜晶体管的源极和漏极及源极线位于第二金属层，主区像素电极和次区像素电极位于透明金属层，电荷共享薄膜晶体管的源极和公共电极线之间需要利用一位于透明金属层的浮置电极经由一深浅孔电性连接，如图1所示，该深浅孔包括穿越浮置电极100a和公共电极线100b之间的绝缘层的深孔100c以及穿越浮置电极100a和电荷共享薄膜晶体管的源极100d之间的绝缘层且与所述深孔100c的连通的浅孔100e组成，现有的深浅孔单元在制作过程中容易在电荷共享薄膜晶体管的源极100d的下方的位置100f处出现底切（Undercut），导致浮置电极100a在爬坡时出现断线，进而导致显示不良。
 技术问题
本发明的目的在于提供一种像素电极结构，能够防止浮置电极在深浅孔中出现断线，避免显示不良。
本发明的目的还在于提供一种像素电路结构的制作方法，能够防止浮置电极在深浅孔中出现断线，避免显示不良。
 技术解决方案
为实现上述目的，本发明提供了一种像素电路结构，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的第二金属层、设于所述第二金属层和半导体层上的钝化层以及设于所述钝化层上的透明金属层；
所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极；所述透明金属层包括浮置电极；
所述第一源极与所述公共电极线部分交叠，在所述公共电极线与第一源极交叠的区域形成有深浅孔，所述深浅孔包括穿越所述钝化层及栅极绝缘层并暴露出所述公共电极线的一部分的深孔，穿越所述深孔一侧的钝化层及部分栅极绝缘层并与所述深孔连通的第一浅孔，穿越所述第一浅孔远离所述深孔的一侧的钝化层且与第一浅孔连通并暴露出第一源极的一部分的第二浅孔；
所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线。
所述第一金属层还包括间隔设置的第二栅极和第三栅极以及电性连接第一栅极、第二栅极及第三栅极的栅极线，所述公共电极线与所述第二栅极、第三栅极及栅极线间隔；
所述第二金属层还包括对应所述第二栅极设置且相互间隔的第二源极和第二漏极、对应所述第三栅极设置且相互间隔的第三源极和第三漏极以及电性连接所述第二源极和第三源极的源极线，所述第二漏极与所述第一漏极电性连接，所述第三漏极电性连接透明金属层。
所述第二源极与所述公共电极线部分交叠形成第一存储电容，所述第三源极与所述公共电极线部分交叠形成第二存储电容。
所述透明金属层还包括间隔分布的主区像素电极及次区像素电极，所述浮置电极与所述主区像素电极及次区像素电极均间隔，所述主区像素电极电性连接第三漏极，所述次区像素电极电性连接第二漏极。
所述主区像素电极及次区像素电极均为“米”字型电极。
本发明还提供一种像素电路结构的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成第一金属层，并在所述第一金属层及衬底基板上形成栅极绝缘层；所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；
步骤S2、在所述栅极绝缘层上形成依次层叠的半导体薄膜、第二金属薄膜及第一光阻薄膜；
步骤S3、通过一道光罩制程对所述第一光阻薄膜进行曝光及显影，形成位于待形成第一源极和第一漏极的区域上的第一光阻段以及位于待形成第一浅孔的区域上的第二光阻段，所述第一光阻段的厚度大于第二光阻段；
步骤S4、以所述第一光阻段和第二光阻段为遮挡，对所述半导体薄膜及第二金属薄膜进行蚀刻，去除未被第一光阻段和第二光阻段遮挡的区域的半导体薄膜及第二金属薄膜；
步骤S5、去除第二光阻段并减薄第一光阻段，以剩余的第一光阻段为遮挡，对第二金属薄膜进行蚀刻，去除未被第一光阻段遮挡的区域的第二金属薄膜，形成第二金属层，所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极，所述第一源极与所述公共电极线部分交叠；
步骤S6、去除剩余的第一光阻段，在所述栅极绝缘层、第二金属层及半导体薄膜上形成钝化层，在所述钝化层上形成第二光阻薄膜；
步骤S7、通过一道光罩对第二光阻薄膜进行曝光和显影，去除待形成深浅孔的区域上的第二光阻薄膜，以剩余所述第二光阻薄膜为遮挡对钝化层、半导体薄膜及栅极绝缘层进行蚀刻，形成穿越所述钝化层及栅极绝缘层并暴露出所述公共电极线的一部分的深孔、穿越所述深孔一侧的钝化层及部分栅极绝缘层并与所述深孔连通的第一浅孔以及穿越所述第一浅孔远离所述深孔的一侧的钝化层且与第一浅孔连通并暴露出第一源极的一部分的第二浅孔，所述深孔、第一浅孔及第二浅孔共同形成深浅孔；
步骤S8、在所述钝化层及深浅孔上形成透明金属层，所述透明金属层包括浮置电极，所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线。
所述步骤S1具体包括：在所述衬底基板上形成第一金属薄膜，并通过一道光罩制程图案化所述第一金属薄膜形成第一金属层，所述第一金属层还间隔设置的第二栅极和第三栅极以及电性连接第一栅极、第二栅极及第三栅极的栅极线，所述公共电极线与所述第二栅极、第三栅极及栅极线间隔；
所述步骤S3中第一光阻段还形成于待形成第二源极、第二漏极、第三源极、第三漏极及源极线的区域；所述步骤S5中形成的第二金属层还包括对应所述第二栅极设置且相互间隔的第二源极和第二漏极、对应所述第三栅极设置且相互间隔的第三源极和第三漏极以及电性连接所述第二源极和第三源极的源极线，所述第二漏极与所述第一漏极电性连接，所述第三漏极电性连接透明金属层。
所述第二源极与所述公共电极线部分交叠形成第一存储电容，所述第三源极与所述公共电极线部分交叠形成第二存储电容。
所述步骤S8中具体包括：在在所述钝化层及深浅孔上形成透明金属薄膜，并通过一道光罩图案化所述透明金属薄膜，形成透明金属层；所述透明金属层还包括间隔分布的主区像素电极及次区像素电极，所述浮置电极与所述主区像素电极及次区像素电极均间隔，所述主区像素电极电性连接第三漏极，所述次区像素电极电性连接第二漏极。
所述主区像素电极及次区像素电极均为“米”字型电极。
 有益效果
本发明的有益效果：本发明提供一种像素电路结构，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的第二金属层、设于所述第二金属层和半导体层上的钝化层以及设于所述钝化层上的透明金属层；所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极；所述透明金属层包括浮置电极；所述第一源极与所述公共电极线部分交叠，在所述公共电极线与第一源极交叠的区域形成有深浅孔，所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线，所述深浅孔为具有依次连通的深孔、第一浅孔和第二浅孔的三层结构，能够防止浮置电极在深浅孔中出现断线，避免显示不良。本发明还提供一种像素电路结构的制作方法，能够防止浮置电极在深浅孔中出现断线，避免显示不良。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的深浅孔的结构示意图；
图2为本发明的像素电路结构的示意图；
图3为本发明的像素电路结构的制作方法的步骤S1和步骤S2的示意图；
图4为本发明的像素电路结构的制作方法的步骤S3的示意图；
图5为本发明的像素电路结构的制作方法的步骤S4的示意图；
图6为本发明的像素电路结构的制作方法的步骤S5的示意图；
图7为本发明的像素电路结构的制作方法的步骤S6的示意图；
图8为本发明的像素电路结构的制作方法的步骤S7的示意图；
图9为本发明的像素电路结构的制作方法的步骤S8的示意图暨本发明的像素电路结构中深浅孔的结构示意图；
图10为本发明的像素电路结构的等效电路图；
图11为本发明的像素电路结构的制作方法的流程图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2及图9，本发明提供一种像素电路结构，包括：衬底基板10、设于所述衬底基板10上的第一金属层20、设于所述第一金属层20及衬底基板10上的栅极绝缘层30、设于所述栅极绝缘层30上的半导体层40、设于所述半导体层40上的第二金属层50、设于所述第二金属层50和半导体层40上的钝化层70以及设于所述钝化层70上的透明金属层80；
所述第一金属层20包括第一栅极21及与所述第一栅极21间隔设置的公共电极线22；所述第二金属层50包括对应所述第一栅极21设置且相互间隔的第一源极51和第一漏极52；所述透明金属层80包括浮置电极81；
所述第一源极51与所述公共电极线22部分交叠，在所述公共电极线22与第一源极51交叠的区域形成有深浅孔100，所述深浅孔100包括穿越所述钝化层70及栅极绝缘层30并暴露出所述公共电极线22的一部分的深孔101、穿越所述深孔101一侧的钝化层70及部分栅极绝缘层30并与所述深孔101连通的第一浅孔102及穿越所述第一浅孔102远离所述深孔101的一侧的钝化层70且与第一浅孔102连通并暴露出第一源极51的一部分的第二浅孔103；
所述浮置电极81通过所述深浅孔100电性连接所述第一源极51和公共电极线22。
具体地，所述第一金属层20还包括间隔设置的第二栅极23和第三栅极24以及电性连接第一栅极21、第二栅极23及第三栅极24的栅极线25，所述公共电极线22与所述第二栅极23、第三栅极24及栅极线25间隔；
所述第二金属层50还包括对应所述第二栅极23设置且相互间隔的第二源极53和第二漏极54、对应所述第三栅极24设置且相互间隔的第三源极55和第三漏极56以及电性连接所述第二源极53和第三源极55的源极线57，所述第二漏极54与所述第一漏极52电性连接，所述第三漏极56电性连接透明金属层80。
进一步地，所述半导体层40设于所述第二金属层50的下方、第一源极51和第一漏极52之间的第一沟道区、第二源极53和第二漏极54之间的第二沟道区以及第三源极55和第三漏极56之间的第三沟道区。
具体地，所述透明金属层80还包括间隔分布的主区像素电极82及次区像素电极83，所述浮置电极81与所述主区像素电极82及次区像素电极83均间隔，所述主区像素电极82电性连接第三漏极56，所述次区像素电极83电性连接第二漏极54。
具体地，所述主区像素电极82及次区像素电极83均为“米”字型电极。
进一步地，所述主区像素电极82通过一穿越钝化层70的第一过孔91与第三漏极56电性连接，所述次区像素电极83通过一穿越钝化层70的第二过孔92与第二漏极54电性连接。
优选地，所述衬底基板10为玻璃基板，第一金属层20及第二金属层50的材料为钼、钛、铝及铜中的一种或多种的组合，所述栅极绝缘层30和钝化层70的材料为氧化硅和氮化硅中的一种或多种的组合，所述半导体层40的材料为非晶硅，所述透明金属层80的材料为氧化铟锡。
如图10所示，所述第一栅极21、第一源极51和第一漏极52形成第一薄膜晶体管T1，第二栅极23、第二源极53和第二漏极54形成第二薄膜晶体管T2，第三栅极24、第二源极53和第二漏极54形成第三薄膜晶体管T3，所述第二源极53与所述公共电极线22部分交叠形成第一存储电容C1，所述第三源极55与所述公共电极线22部分交叠形成第二存储电容C2，从最终形成如图10所示的具有电荷共享功能的像素驱动电路，驱动时，可通过第一薄膜晶体管T1下拉次区像素电极83的电位，从而使得主区像素电极82和次区像素电极83具有不同的电位，形成八畴结构，以扩大液晶显示面板的视角。
本发明的像素驱动电路结构中，设置所述深浅孔100包括穿越所述钝化层70及栅极绝缘层30并暴露出所述公共电极线22的一部分的深孔101，穿越所述深孔101一侧的钝化层70及部分栅极绝缘层30并与所述深孔101连通的第一浅孔102，穿越所述第一浅孔102远离所述深孔101的一侧的钝化层70且与第一浅孔102连通并暴露出第一源极51的一部分的第二浅孔103，通过设置具有深孔101、第一浅孔102及第二浅孔103的三级深浅孔，能够降低浮置电极81的爬坡角度，防止浮置电极81在深浅孔100中出现断线，避免显示不良。
如图11所示，本发明还提供一种像素电路结构的制作方法，包括如下步骤：
步骤S1、如图3所示，提供一衬底基板10，在所述衬底基板10上形成第一金属层20，并在所述第一金属层20及衬底基板10上形成栅极绝缘层30；所述第一金属层20包括第一栅极21及与所述第一栅极21间隔设置的公共电极线22。
具体地，所述步骤S1具体包括：在所述衬底基板10上形成第一金属薄膜，并通过一道光罩制程图案化所述第一金属薄膜形成第一金属层20，所述第一金属层20还间隔设置的第二栅极23和第三栅极24以及电性连接第一栅极21、第二栅极23及第三栅极24的栅极线25，所述公共电极线22与所述第二栅极23、第三栅极24及栅极线25间隔。
步骤S2、如图3所示，在所述栅极绝缘层30上形成依次层叠的半导体薄膜400、第二金属薄膜500及第一光阻薄膜600。
步骤S3、如图4所示，通过一道光罩制程对所述第一光阻薄膜600进行曝光及显影，形成位于待形成第一源极51和第一漏极52的区域上的第一光阻段601以及位于待形成第一浅孔102的区域上的第二光阻段602，所述第一光阻段601的厚度大于第二光阻段602。
具体地，所述步骤S3中第一光阻段601还形成于待形成第二源极53、第二漏极54、第三源极55、第三漏极56及源极线57的区域。
进一步地，所述第二光阻段602还形成于待形成第一源极51和第一漏极52之间的第一沟道区、待形成第二源极53和第二漏极54之间的第二沟道区以及待形成第三源极55和第三漏极56之间的第三沟道区。
步骤S4、如图5所示，以所述第一光阻段601和第二光阻段602为遮挡，对所述半导体薄膜400及第二金属薄膜500进行蚀刻，去除未被第一光阻段601和第二光阻段602遮挡的区域的半导体薄膜400及第二金属薄膜500。
具体地，所述步骤S4中去除的半导体薄膜400及第二金属薄膜500为除位于待形成第一源极51、第一漏极52、第二源极53、第二漏极54第三源极55、第三漏极56、栅极线57、第一沟道区、第二沟道区、第三沟道区及第一浅孔102的区域以外的半导体薄膜400及第二金属薄膜500。
步骤S5、如图6所示，去除第二光阻段602并减薄第一光阻段601，以剩余的第一光阻段601为遮挡，对第二金属薄膜500进行蚀刻，去除未被第一光阻段601遮挡的区域的第二金属薄膜500，形成第二金属层50，所述第二金属层50包括对应所述第一栅极21设置且相互间隔的第一源极51和第一漏极52，所述第一源极51与所述公共电极线22部分交叠。
具体地，所述步骤S5中去除的第二金属薄膜500为待形成位于第一沟道区、第二沟道区、第三沟道区及第一浅孔102的区域上的第二金属薄膜500。
具体地，所述步骤S5中形成的第二金属层50还包括对应所述第二栅极23设置且相互间隔的第二源极53和第二漏极54、对应所述第三栅极24设置且相互间隔的第三源极55和第三漏极56以及电性连接所述第二源极53和第三源极55的源极线57，所述第二漏极54与所述第一漏极52电性连接，所述第三漏极56电性连接透明金属层80。
步骤S6、如图7所示，去除剩余的第一光阻段601，在所述栅极绝缘层30、第二金属层50及半导体薄膜400上形成钝化层70，在所述钝化层70上形成第二光阻薄膜700。
步骤S7、如图8所示，通过一道光罩对第二光阻薄膜700进行曝光和显影，去除待形成深浅孔100的区域上的第二光阻薄膜700，以剩余所述第二光阻薄膜700为遮挡对钝化层70、半导体薄膜400及栅极绝缘层30进行蚀刻，形成穿越所述钝化层70及栅极绝缘层30并暴露出所述公共电极线22的一部分的深孔101、穿越所述深孔101一侧的钝化层70及部分栅极绝缘层30并与所述深孔101连通的第一浅孔102以及穿越所述第一浅孔102远离所述深孔101的一侧的钝化层70且与第一浅孔102连通并暴露出第一源极51的一部分的第二浅孔103，所述深孔101、第一浅孔102及第二浅孔103共同形成深浅孔100。
具体地，所述步骤S7中还去除待形成第一过孔91和第二过孔92的区域上的第二金属薄膜500，所述步骤S7还形成穿越所述钝化层70并暴露出第三漏极56的一部分的第一过孔91以及穿越所述钝化层70并暴露出第二漏极54的一部分的第二过孔92。
步骤S8、如图9所示，在所述钝化层70及深浅孔100上形成透明金属层80，所述透明金属层80包括浮置电极81，所述浮置电极81通过所述深浅孔100电性连接所述第一源极51和公共电极线22。
具体地，所述步骤S8中具体包括：在在所述钝化层70及深浅孔100上形成透明金属薄膜，并通过一道光罩图案化所述透明金属薄膜，形成透明金属层80；所述透明金属层80还包括间隔分布的主区像素电极82及次区像素电极83，所述浮置电极81与所述主区像素电极82及次区像素电极83均间隔，所述主区像素电极82电性连接第三漏极56，所述次区像素电极83电性连接第二漏极54。
进一步地，所述主区像素电极82通过一穿越钝化层70的第一过孔91与第三漏极56电性连接，所述次区像素电极83通过一穿越钝化层70的第二过孔92与第二漏极54电性连接。
需要说明的是，如图8所示，由于在待形成第一浅孔102的区域在蚀刻前存在半导体薄膜400，因此在蚀刻过程中，第一浅孔102的区域的蚀刻速度会比深孔101所在的区域更慢，蚀刻完成之后，如图9所示，第一浅孔102的底部的栅极绝缘层30并未被完全去除，而是保留了一部分，从而使得第一浅孔102相比于深孔101形成一个台阶，而第二浅孔101的区域在蚀刻到第一源极52之后则无法继续蚀刻，从而形成一个相比于第一浅孔102更浅的第二浅孔103，通过三级深浅孔的设置，既可以避免在蚀刻过程中第一源极52下方出现底切，还可以避免浮置电极81的爬坡角度过大引起断线，有效保证显示面板的稳定性。
值得一提的是，本发明的像素电路结构的制作方法，能够通过四道光罩制程即可完成制作，无需额外增加光罩数量，其中制作第二金属层50和半导体层40的光罩为半色调光罩或灰阶光罩。
优选地，所述衬底基板10为玻璃基板，第一金属层20及第二金属层50的材料为钼、钛、铝及铜中的一种或多种的组合，所述栅极绝缘层30和钝化层70的材料为氧化硅和氮化硅中的一种或多种的组合，所述半导体层40的材料为非晶硅，所述透明金属层80的材料为氧化铟锡。
如图10所示，所述第一栅极21、第一源极51和第一漏极52形成第一薄膜晶体管T1，第二栅极23、第二源极53和第二漏极54形成第二薄膜晶体管T2，第三栅极24、第二源极53和第二漏极54形成第三薄膜晶体管T3，所述第二源极53与所述公共电极线22部分交叠形成第一存储电容C1，所述第三源极55与所述公共电极线22部分交叠形成第二存储电容C2，从最终形成如图10所示的具有电荷共享功能的像素驱动电路，驱动时，可通过第一薄膜晶体管T1下拉次区像素电极83的电位，从而使得主区像素电极82和次区像素电极83具有不同的电位，形成八畴结构，以扩大液晶显示面板的视角。
本发明的像素驱动电路结构中，设置所述深浅孔100包括穿越所述钝化层70及栅极绝缘层30并暴露出所述公共电极线22的一部分的深孔101，穿越所述深孔101一侧的钝化层70及部分栅极绝缘层30并与所述深孔101连通的第一浅孔102，穿越所述第一浅孔102远离所述深孔101的一侧的钝化层70且与第一浅孔102连通并暴露出第一源极51的一部分的第二浅孔103，通过设置具有深孔101、第一浅孔102及第二浅孔103的三级深浅孔，能够降低浮置电极81的爬坡角度，防止浮置电极81在深浅孔100中出现断线，避免显示不良。
综上所述，本发明提供一种像素电路结构，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的第二金属层、设于所述第二金属层和半导体层上的钝化层以及设于所述钝化层上的透明金属层；所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极；所述透明金属层包括浮置电极；所述第一源极与所述公共电极线部分交叠，在所述公共电极线与第一源极交叠的区域形成有深浅孔，所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线，所述深浅孔为具有依次连通的深孔、第一浅孔和第二浅孔的三层结构，能够防止浮置电极在深浅孔中出现断线，避免显示不良。本发明还提供一种像素电路结构的制作方法，能够防止浮置电极在深浅孔中出现断线，避免显示不良。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种像素电路结构，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的第二金属层、设于所述第二金属层和半导体层上的钝化层以及设于所述钝化层上的透明金属层；
    所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极；所述透明金属层包括浮置电极；
    所述第一源极与所述公共电极线部分交叠，在所述公共电极线与第一源极交叠的区域形成有深浅孔，所述深浅孔包括穿越所述钝化层及栅极绝缘层并暴露出所述公共电极线的一部分的深孔、穿越所述深孔一侧的钝化层及部分栅极绝缘层并与所述深孔连通的第一浅孔及穿越所述第一浅孔远离所述深孔的一侧的钝化层且与第一浅孔连通并暴露出第一源极的一部分的第二浅孔；
    所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线。
  2. 如权利要求1所述的像素电路结构，其中，所述第一金属层还包括间隔设置的第二栅极和第三栅极以及电性连接第一栅极、第二栅极及第三栅极的栅极线，所述公共电极线与所述第二栅极、第三栅极及栅极线间隔；
    所述第二金属层还包括对应所述第二栅极设置且相互间隔的第二源极和第二漏极、对应所述第三栅极设置且相互间隔的第三源极和第三漏极以及电性连接所述第二源极和第三源极的源极线，所述第二漏极与所述第一漏极电性连接，所述第三漏极电性连接透明金属层。
  3. 如权利要求2所述的像素电路结构，其中，所述第二源极与所述公共电极线部分交叠形成第一存储电容，所述第三源极与所述公共电极线部分交叠形成第二存储电容。
  4. 如权利要求2所述的像素电路结构，其中，所述透明金属层还包括间隔分布的主区像素电极及次区像素电极，所述浮置电极与所述主区像素电极及次区像素电极均间隔，所述主区像素电极电性连接第三漏极，所述次区像素电极电性连接第二漏极。
  5. 如权利要求4所述的像素电路结构，其中，所述主区像素电极及次区像素电极均为“米”字型电极。
  6. 一种像素电路结构的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成第一金属层，并在所述第一金属层及衬底基板上形成栅极绝缘层；所述第一金属层包括第一栅极及与所述第一栅极间隔设置的公共电极线；
    步骤S2、在所述栅极绝缘层上形成依次层叠的半导体薄膜、第二金属薄膜及第一光阻薄膜；
    步骤S3、通过一道光罩制程对所述第一光阻薄膜进行曝光及显影，形成位于待形成第一源极和第一漏极的区域上的第一光阻段以及位于待形成第一浅孔的区域上的第二光阻段，所述第一光阻段的厚度大于第二光阻段；
    步骤S4、以所述第一光阻段和第二光阻段为遮挡，对所述半导体薄膜及第二金属薄膜进行蚀刻，去除未被第一光阻段和第二光阻段遮挡的区域的半导体薄膜及第二金属薄膜；
    步骤S5、去除第二光阻段并减薄第一光阻段，以剩余的第一光阻段为遮挡，对第二金属薄膜进行蚀刻，去除未被第一光阻段遮挡的区域的第二金属薄膜，形成第二金属层，所述第二金属层包括对应所述第一栅极设置且相互间隔的第一源极和第一漏极，所述第一源极与所述公共电极线部分交叠；
    步骤S6、去除剩余的第一光阻段，在所述栅极绝缘层、第二金属层及半导体薄膜上形成钝化层，在所述钝化层上形成第二光阻薄膜；
    步骤S7、通过一道光罩对第二光阻薄膜进行曝光和显影，去除待形成深浅孔的区域上的第二光阻薄膜，以剩余所述第二光阻薄膜为遮挡对钝化层、半导体薄膜及栅极绝缘层进行蚀刻，形成穿越所述钝化层及栅极绝缘层并暴露出所述公共电极线的一部分的深孔、穿越所述深孔一侧的钝化层及部分栅极绝缘层并与所述深孔连通的第一浅孔以及穿越所述第一浅孔远离所述深孔的一侧的钝化层且与第一浅孔连通并暴露出第一源极的一部分的第二浅孔，所述深孔、第一浅孔及第二浅孔共同形成深浅孔；
    步骤S8、在所述钝化层及深浅孔上形成透明金属层，所述透明金属层包括浮置电极，所述浮置电极通过所述深浅孔电性连接所述第一源极和公共电极线。
  7. 如权利要求6所述的像素电路结构的制作方法，其中，所述步骤S1具体包括：在所述衬底基板上形成第一金属薄膜，并通过一道光罩制程图案化所述第一金属薄膜形成第一金属层，所述第一金属层还间隔设置的第二栅极和第三栅极以及电性连接第一栅极、第二栅极及第三栅极的栅极线，所述公共电极线与所述第二栅极、第三栅极及栅极线间隔；
    所述步骤S3中第一光阻段还形成于待形成第二源极、第二漏极、第三源极、第三漏极及源极线的区域；所述步骤S5中形成的第二金属层还包括对应所述第二栅极设置且相互间隔的第二源极和第二漏极、对应所述第三栅极设置且相互间隔的第三源极和第三漏极以及电性连接所述第二源极和第三源极的源极线，所述第二漏极与所述第一漏极电性连接，所述第三漏极电性连接透明金属层。
  8. 如权利要求7所述的像素电路结构的制作方法，其中，所述第二源极与所述公共电极线部分交叠形成第一存储电容，所述第三源极与所述公共电极线部分交叠形成第二存储电容。
  9. 如权利要求7所述的像素电路结构的制作方法，其中，所述步骤S8中具体包括：在在所述钝化层及深浅孔上形成透明金属薄膜，并通过一道光罩图案化所述透明金属薄膜，形成透明金属层；所述透明金属层还包括间隔分布的主区像素电极及次区像素电极，所述浮置电极与所述主区像素电极及次区像素电极均间隔，所述主区像素电极电性连接第三漏极，所述次区像素电极电性连接第二漏极。
  10. 如权利要求9所述的像素电路结构的制作方法，其中，所述主区像素电极及次区像素电极均为“米”字型电极。
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