WO2016041349A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2016041349A1
WO2016041349A1 PCT/CN2015/076917 CN2015076917W WO2016041349A1 WO 2016041349 A1 WO2016041349 A1 WO 2016041349A1 CN 2015076917 W CN2015076917 W CN 2015076917W WO 2016041349 A1 WO2016041349 A1 WO 2016041349A1
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Prior art keywords
region
photoresist
layer
array substrate
forming
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PCT/CN2015/076917
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English (en)
French (fr)
Inventor
李春
王晏酩
宋瑞涛
吴涛
孙宏伟
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/787,574 priority Critical patent/US9905591B2/en
Publication of WO2016041349A1 publication Critical patent/WO2016041349A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the ground is used in the field of high performance display.
  • the TFT-LCD includes a color filter substrate and an array substrate disposed on a pair of boxes, and a liquid crystal layer is disposed in the array substrate and the color filter substrate, and the deflection of the liquid crystal molecules in the liquid crystal layer is controlled to achieve control of the intensity of the light to achieve display.
  • the purpose of the image is a color filter substrate and an array substrate disposed on a pair of boxes, and a liquid crystal layer is disposed in the array substrate and the color filter substrate, and the deflection of the liquid crystal molecules in the liquid crystal layer is controlled to achieve control of the intensity of the light to achieve display. The purpose of the image.
  • the structure of the array substrate may be as shown in FIG. 1a, including a plurality of horizontally intersecting gate lines 10 and data lines 11.
  • the gate line 10 and the data line 11 cross define a plurality of pixel units 12 arranged in a matrix, and each of the pixel units 12 is provided with a pixel electrode 104.
  • a cross-sectional view of the array substrate in the A-A' direction is shown in Fig. 1b, and includes a multilayer film layer structure from bottom to top.
  • the film layer structure can be prepared by sequentially forming a thin film layer, a photoresist on a substrate, and then using a mask, exposure, development, etching, lift-off, and the like.
  • the film layer that should be etched may remain on the substrate due to the external environment or the influence of the production process.
  • the semiconductor active layer 103 or the pixel electrode 104 (corresponding to the photoresist completely removed region) located between the two adjacent pixel units 12 should be completely etched away.
  • the photoresist in the completely removed region of the photoresist is affected by the front plating process and its own process, the photoresist cannot be completely exposed to form an excess photoresist retention region.
  • a residual portion (constituting the conductive layer 20) of the pixel electrode 104 as shown in FIG. 1c is formed between two adjacent pixel units 12, or as shown in FIG.
  • the laser spot or the cutting process is generally used to repair the pixel points with bright spot defects.
  • the array substrate is detected by an optical detecting instrument. After the bright spot defect is found, the conductive layer 20 may be cut so that the adjacent two pixel units 12 are not electrically connected.
  • the thickness of the pixel electrode 104 is thin, the degree of recognition of the optical detection is lowered, resulting in an increase in the missed detection rate.
  • other thin film layer structures that have been formed are destroyed while performing the above-described repair process, such as a passivation layer, a common electrode layer, and the like (not shown) on the surface of the pixel electrode 104. Thereby reducing the repair effect of bright spot defects and affecting the quality of the product.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device, which can avoid damage to an excessive thin film layer on an array substrate during a process of reducing bright spot defects.
  • An embodiment of the present invention provides a method for fabricating an array substrate, including a method of forming a plurality of pixel electrodes arranged in a matrix form. When forming the pixel electrodes, a guide for electrically connecting two adjacent pixel electrodes is formed.
  • the method further includes: forming a photoresist layer on a surface of the substrate on which the conductive layer is formed; forming a first photoresist removal region and a photoresist retention region by a one-time exposure development process, the first a photoresist removal region corresponding to a position of the conduction layer, the photoresist retention region corresponding to another region of the substrate surface on which the conduction layer is formed; and etching the first photoresist removal region a conductive layer forming a blocking region for avoiding electrical connection between two adjacent pixel electrodes; peeling off a photoresist layer of the photoresist remaining region; forming a metal layer on a surface of the substrate on which the above structure is formed Forming a metal line non-electrically connected to two adjacent pixel electrodes in the partition region by one patterning process.
  • An embodiment of the present invention further provides an array substrate, including a plurality of pixel electrodes arranged in a matrix form, a blocking region for avoiding electrical connection between two adjacent pixel electrodes, and a phase in the partition region. Two adjacent metal electrodes of the pixel electrode are not electrically connected.
  • the embodiment of the invention further provides a display device comprising any of the array substrates as described above.
  • 1a is a schematic structural view of an array substrate
  • 1b is a cross-sectional structural view of an array substrate
  • 1c is a schematic structural view of an array substrate having a conductive layer
  • FIG. 1d is a schematic structural view of another array substrate having a conduction layer
  • FIG. 2 is a flowchart of a method for preparing an array substrate according to an embodiment of the present invention
  • FIG. 3 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • 4a-4f are schematic structural diagrams of various stages in the preparation process of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of still another method for preparing an array substrate according to an embodiment of the present invention.
  • 6a-6h are schematic structural diagrams of various stages in the preparation process of another array substrate according to an embodiment of the present invention.
  • the embodiment of the present invention provides a method for fabricating an array substrate, which may include forming a plurality of pixel electrodes 104 arranged in a matrix form as shown in FIG. 1a. When the method for forming the pixel electrodes 104 is used, a phase is formed. As shown in FIG. 2, the method for preparing the array substrate may further include:
  • the first photoresist removal area A corresponds to the position of the conductive layer 20, and the photoresist retention area B is formed correspondingly. There are other areas of the substrate surface of the conductive layer 20.
  • S105 Form a metal line that is not electrically connected to the adjacent two pixel electrodes 104 in the blocking region 106 by one patterning process.
  • the width of the blocking region 106 can be set to be larger than the width of the metal line to ensure that the metal lines are not electrically connected to the pixel electrodes 104 located on both sides thereof.
  • the first conductive layer 20 may be composed of a residual portion of the pixel electrode 104 as shown in FIG. 1c; or, as shown in FIG. 1d, may be composed of a residual portion of the semiconductor active layer 103. Or, it may be composed of the remaining portion of the pixel electrode 104 and the remaining portion of the semiconductor active layer 103 at the same time.
  • the residual portion is produced for various reasons. For example, during exposure and development, since the surface of the photoresist between two adjacent pixel units 12 is covered with dust, the photoresist cannot be completely exposed to form excess light. Glue retention area. Alternatively, due to defects in the exposure process, the photoresist between two adjacent pixel cells 12 is not fully exposed, and an excess photoresist retention region is also formed. Or, due to defects in the development process, the photoresist between two adjacent pixel units 12 is not completely developed, and an unnecessary photoresist retention area is formed, and the like. On this basis, the remaining portion is formed between two adjacent pixel units 12 by a subsequent fabrication process.
  • the above metal layer may include a gate metal layer for forming the gate line 10; or a source/drain metal layer 105 for forming the data line 11.
  • each of the pixel units 12 of the array substrate may include a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the thin film transistor is a semiconductor unit having a switching characteristic, and may be, for example, an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an oxide thin film transistor, or an organic thin film transistor, which is not limited herein.
  • the thin film transistor may be of a top gate type or a bottom gate type, which is not limited herein.
  • the top gate and the bottom gate are dependent on the positions of the gate electrode 101 and the gate insulating layer 102.
  • the substrate 101 when the substrate 101 is a transparent substrate, when the gate 101 is Near the substrate substrate, when the gate insulating layer 102 is away from the base substrate 01, it is a bottom gate type thin film transistor. At this time, since the metal layer is located on the surface of the gate insulating layer 102 and not on the side close to the base substrate 01, the metal layer may be the source/drain metal layer 105 constituting the data line 11.
  • the gate electrode 101 when the gate electrode 101 is away from the base substrate 01 and the gate insulating layer 102 is close to the base substrate, it is a top gate type thin film transistor. At this time, since the metal layer is located on the surface of the gate insulating layer 102, the metal layer may be a gate metal layer constituting the gate electrode 101.
  • the positive photoresist may be used, that is, the photoresist layer in the exposed region is removed during the development process, and is not exposed.
  • the photoresist of the region is retained during development.
  • a reverse photoresist in which the photoresist layer in the exposed region is retained during development, and the photoresist in the unexposed region is removed during development.
  • the invention is not limited thereto. However, the following embodiments are described by using a positive photoresist, that is, a photoresist layer of an exposed region is removed during development, and a photoresist of an unexposed region is retained during development.
  • the patterning process may include a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the one-time patterning process in the embodiment of the present invention is an example in which different exposure regions are formed by one mask exposure process, and then multiple etching, ashing, and the like removal processes are performed on different exposure regions to finally obtain an intended pattern. .
  • Embodiments of the present invention provide a method of fabricating an array substrate, including a method of forming a plurality of pixel electrodes arranged in a matrix on a substrate.
  • a conduction layer that electrically connects adjacent two pixel electrodes.
  • the pixel units corresponding to the adjacent two pixel electrodes are electrically connected, and when one of the pixel units is controlled to display, the pixel unit adjacent to and electrically connected is also illuminated, thereby causing uncontrolled
  • the occurrence of bright pixels (bright spot defects) adversely affects the display effect and product quality.
  • the embodiment of the present invention further includes: first, forming A surface of the substrate having the above structure is formed with a photoresist layer; then, a first photoresist removal region and a photoresist retention region are formed by a one-time exposure development process.
  • the first photoresist removal region corresponds to the position of the conduction layer; the photoresist retention region corresponds to other regions of the substrate surface on which the conduction layer is formed.
  • the conductive layer of the first photoresist removal region is etched to form a blocking region for avoiding electrical connection of pixel electrodes of two adjacent pixel units, and photolithography is performed on the photoresist retention region.
  • the glue is peeled off.
  • a metal layer is formed on the surface of the substrate on which the above structure is formed; finally, a metal line electrically connected to the adjacent two pixel electrodes is formed in the blocking region by a patterning process.
  • the above-mentioned cutting treatment process is completed before the formation of the metal wires, and thus the film layer structure formed by the subsequent fabrication process of the array substrate is not damaged or affected. Thereby, it is possible to avoid damage to excessive thin film layers on the array substrate in the process of reducing bright spot defects. Improves the effect of spot defect repair and the quality of the product.
  • the method can include:
  • the first photoresist removal region A corresponds to a pre-formed isolation region 106 corresponding to other regions of the substrate surface on which the conduction layer 20 is formed.
  • the preparation method of the array substrate on which the above-described barrier region 106 is formed will be described in detail below. As shown in FIG. 3 and FIGS. 4a to 4f, the method includes the following steps.
  • the substrate further includes a gate electrode 101, a semiconductor active layer 103, and a pixel electrode, not shown, sequentially formed on the base substrate 01. 104) Forming a photoresist layer 30.
  • a source/drain metal layer 105 (metal layer) is formed on the surface of the substrate on which the above structure is formed.
  • S205 is formed in the partition region 106 by a patterning process (for example, after applying a photoresist, performing a mask exposure process, and then performing development, etching, stripping, etc.)
  • the pixel electrodes 104 are non-electrically connected to the data lines 11 (metal lines).
  • the conduction layer 20 (the remaining portion of the pixel electrode 104) in the above-described barrier region 106 is completely removed. And the data line 11 located in the partition region 106 and the pixel electrodes 104 located on both sides thereof are not electrically connected. In this way, it can be ensured that the data line 11 can normally receive the data signal, so that the array substrate can work normally, and the destruction of the excessive thin film layer on the array substrate during the process of reducing the bright spot defects can also be avoided by the blocking region 106.
  • the first step S203 when the conductive layer 20 of the first photoresist removal region is etched, part of the gate insulating layer 102 is also etched. In this way, the data line 11 and the pixel electrode 104 located on both sides thereof can have a certain step difference, and the distance between the data line 11 and the pixel electrode 104 is increased, so that the data line 11 and the pixel electrode 104 can be effectively avoided.
  • Crosstalk between signals can be effectively avoid signal crosstalk between the gate line 10 and the pixel electrode 104.
  • the height of the step can be controlled by a person skilled in the art according to actual needs.
  • the height of the step can be set to be greater than or equal to the thickness of the data line 11 or the gate line 10.
  • the height of the above step can be reduced. The invention is not limited thereto.
  • the above embodiment is described by taking the conduction layer 20 as a residual portion of the pixel electrode 104 as an example.
  • the conduction layer 20 is similarly obtained when it is composed of the remaining portion of the semiconductor active layer 103. I will not repeat them here.
  • the method can include:
  • the first photoresist removal region A corresponds to the pre-formed recess 1061
  • the photoresist retention region B corresponds to other regions of the substrate surface on which the conductive layer 20 is formed. That is, the photoresist retention area B Corresponding to other regions of the substrate surface other than the first photoresist removal region A.
  • the pre-formed partition region 106 includes two of the above-described grooves 1061 and an insulating portion 1062 between the two grooves 1061.
  • the preparation method of the array substrate on which the above-described barrier region 106 is formed will be described in detail below. As shown in FIG. 5 and FIGS. 6a-6h, the method includes the following steps.
  • the substrate further includes a gate electrode 101, not shown, sequentially formed on the base substrate 01, and the gate line 10 and the gate insulating layer
  • the layer 102, the semiconductor active layer 103, and the pixel electrode 104) form a photoresist layer 30.
  • the conductive layer 20 is composed of a residual portion of the semiconductor active layer 103.
  • the pre-formed partition region 106 includes two such recesses 1061 and an insulating portion 1062 between the two recesses 1061, as shown in Figure 6c.
  • a source/drain metal layer 105 (metal layer) is formed on the surface of the substrate on which the above structure is formed.
  • S305 is formed in the partition region 106 by a patterning process (for example, after applying a photoresist, performing a mask exposure process, and then performing development, etching, stripping, etc.)
  • the pixel electrode 104 is not electrically connected to the data line 11 (metal line). That is, the above-described data line 11 is formed on the surface of the insulating portion 1062.
  • a lead 108 may be formed in the above-described lead via 107. Through the lead via 107 described above, the leads 108 located in the lead region of the array substrate are electrically connected to the gate lines 10 on the array substrate.
  • a passivation layer 109 is formed on the surface of the substrate on which the above structure is formed.
  • the partial conduction layer 20 is completely removed by the two grooves 1061 of the above-described barrier region 106, so that the adjacent two pixel electrodes 104 are in a non-electrically connected state, and the data line 11 is located at the insulation of the barrier region 106.
  • the surface of the portion 1062 is not electrically connected to the pixel electrodes 104 on both sides thereof. In this way, it can be ensured that the data line 11 can normally receive the data signal, so that the array substrate can work normally, and the destruction of the excessive thin film layer on the array substrate during the process of reducing the bright spot defects can also be avoided by the blocking region 106.
  • the preparation of the lead via 107 can be completed while forming the recess 1061, so that the manufacturing process can be simplified. And the method is equally applicable to the first embodiment.
  • the pixel electrode 104 and the common electrode layer 110 are disposed in different layers.
  • the common electrode layer 110 located at the uppermost portion of the array substrate may have a slit shape, and the pixel electrode 104 adjacent to the base substrate 01 may be planar.
  • a display device comprising the above array substrate is an AD-SDS (Advanced-Super Dimensional Switching, abbreviated as ADS, advanced super-dimensional field switch) type display device.
  • the AD-SDS technology forms a multi-dimensional electric field by a parallel electric field generated by the edge of the common electrode layer 110 in the same plane and a longitudinal electric field generated between the pixel electrode 104 and the common electrode layer 110, so that all the liquid crystals are directly between the pixel electrodes in the liquid crystal cell and directly above the electrode.
  • the molecules are capable of producing a rotational transition, thereby improving the planar orientation liquid crystal working efficiency and increasing the light transmission efficiency.
  • the method of preparing the above-described common electrode layer 110 is also applicable to the first embodiment.
  • the display device when the common electrode layer 110 is formed on the color filter substrate facing the array substrate, the display device is a TN (Twist Nematic) type display device.
  • the TN type display device uses a vertical electric field principle liquid crystal display to drive the nematic mode by forming a vertical electric field between the common electrode layer 110 disposed on the color filter substrate and the pixel electrode 104 on the array substrate.
  • LCD liquid crystal display
  • the TN type display device has the advantage of a large aperture ratio, but has a disadvantage of a narrow viewing angle of about 90°. Those skilled in the art can select the setting of the common electrode layer 110 according to actual needs.
  • the above embodiment has been described by taking the conduction layer 20 as a residual portion of the semiconductor active layer 103 as an example. The same is true when the conduction layer 20 is composed of the remaining portion of the pixel electrode 104. I will not repeat them here.
  • the blocking region 106 in the second embodiment it can be seen that in the first embodiment, when the blocking region 106 is formed, most of the conductive layer 20 needs to be etched, and the etching time is long, but The etching precision is low, and the effect of preventing the electrical connection between the adjacent two pixel electrodes 104 is good.
  • the partition region 106 when the partition region 106 is formed, only a small portion of the conductive layer 20 needs to be etched to form the recess 1061, so the etching speed is fast, but the etching precision is high, and the adjacent is prevented.
  • the effect of electrically connecting the two pixel electrodes 104 is lower than that of the first embodiment. Therefore, those skilled in the art can select a scheme for making the partition region 106 according to actual needs.
  • the partition region 106 may have a width ranging from 12 ⁇ m to 20 ⁇ m. In this way, it is possible to ensure that the metal lines (the data lines 11 or the gate lines 10) have sufficient wiring space to avoid a problem of signal crosstalk with the pixel electrodes 104 located on both sides thereof.
  • the embodiment of the present invention provides an array substrate, which includes a plurality of pixel electrodes 104 arranged in a matrix form as shown in FIG. 1a, and further includes:
  • a blocking region 106 for avoiding electrical connection between two adjacent pixel electrodes 104; and a metal line located in the blocking region and electrically disconnected from the adjacent two pixel electrodes 106.
  • An embodiment of the present invention provides an array substrate including a plurality of pixel electrodes arranged in a matrix form, and further includes a partition region for avoiding electrical connection between two adjacent pixel electrodes, and is located in the partition region and adjacent to the two A metal wire in which the pixel electrode is not electrically connected.
  • the conductive layer formed by electrically connecting the adjacent two pixel electrodes is caused to result in the adjacent two pixel electrodes corresponding to each other due to factors such as preparation process or transportation, storage, and the like.
  • the pixel units are electrically connected.
  • the conduction layer can be cut off by the blocking region, thereby avoiding electrical connection between two adjacent pixel electrodes and reducing the occurrence of bright spot defects.
  • the setting of the partition region is completed before the metal wire is prepared, so that the film layer structure formed by the subsequent fabrication process of the array substrate does not cause damage and influence. Thereby, it is possible to avoid damage to excessive thin film layers on the array substrate in the process of reducing bright spot defects. Improves the effect of spot defect repair and the quality of the product.
  • the blocking region 106 may be completely removed from the conductive layer 20 (the remaining portion of the pixel electrode) in the blocking region 106, and only the metal line (for example, the data line 11) is disposed in the blocking region 106. And the data line 11 located in the blocking area 106 and the pixels located on both sides thereof None of the electrodes 104 are electrically connected. In this way, it can be ensured that the data line 11 can normally receive the data signal, so that the array substrate can work normally, and the destruction of the excessive thin film layer on the array substrate during the process of reducing the bright spot defects can also be avoided by the blocking region 106.
  • the partition region 106 may also be as shown in FIG. 6d.
  • the partition region 106 includes two recesses 1061, and an insulating portion 1062 between the two recesses 1061.
  • the metal wires eg, the data lines 11
  • the partial conduction layer 20 is completely removed by the two grooves 1061 of the above-described barrier region 106, so that the adjacent two pixel electrodes 104 are in a non-electrically connected state, and the data line 11 is located at the insulation of the barrier region 106.
  • the surface of the portion 1062 is not electrically connected to the pixel electrodes 104 on both sides thereof.
  • the data line 11 can normally receive the data signal, so that the array substrate can work normally, and the destruction of the excessive thin film layer on the array substrate during the process of reducing the bright spot defects can also be avoided by the blocking region 106.
  • Embodiments of the present invention provide a display device including any of the array substrates described above. It has the same advantageous effects as the array substrate in the foregoing embodiment. Since the detailed structure and advantageous effects of the array substrate have been described in detail in the foregoing embodiments, they are not described herein again.
  • the display device may include a liquid crystal display device, for example, the display device may be any display product such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a watch, a tablet computer, a notebook computer, or a navigator. component.
  • the display device may be any display product such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a watch, a tablet computer, a notebook computer, or a navigator. component.

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Abstract

一种阵列基板及其制备方法、显示装置。阵列基板的制备方法包括形成像素电极（104）的同时形成将相邻两个像素电极（104）电连接的导通层（20）。具体包括：在形成有导通层（20）的基板表面形成光刻胶层（30）；通过一次曝光显影工艺，形成第一光刻胶去除区域（A）和光刻胶保留区域（B）。第一光刻胶去除区域（A）对应导通层（20）的位置；对第一光刻胶去除区域（A）的导通层（20）进行刻蚀，形成用于避免相邻两个像素单元的像素电极（104）电连接的隔断区域（106），在隔断区域（106）内，形成与相邻两个像素电极（104）非电连接的金属线。阵列基板及其制备方法能够避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
TFT-LCD包括相互对盒设置的彩膜基板和阵列基板，在阵列基板和彩膜基板中设置有液晶层，通过控制液晶层中液晶分子的偏转，以实现对光线强弱的控制而达到显示图像的目的。
通常，阵列基板的结构可以如图1a所示，包括多条横纵交叉的栅线10和数据线11。所述栅线10和所述数据线11交叉界定多个呈矩阵形式排列的像素单元12，每个像素单元12内设置有像素电极104。阵列基板沿A-A’方向的剖视图如图1b所示，自下而上包括多层薄膜层结构。例如，栅极101、栅极绝缘层102、半导体有源层103、像素电极104、源漏金属层105。例如，可以通过在基板上依次形成薄膜层、光刻胶，然后采用掩膜、曝光、显影、刻蚀、剥离等工艺制备上述薄膜层结构。
然而，在生产加工过程中，由于受到外部环境或者受到生产工艺的影响，导致应当被刻蚀掉的薄膜层可能残留于基板上。例如，位于两个相邻像素单元12之间区域的半导体有源层103或像素电极104(对应光刻胶完全去除区域)应当被完全刻蚀掉。然而，在曝光显影的过程中，由于上述光刻胶完全去除区域的光刻胶受前层镀膜工艺及自身工艺影响，导致光刻胶无法完全曝光而形成多余的光刻胶保留区域。在此基础上，通过后续的制作工艺，就会在两个相邻像素单元12之间形成如图1c所示的像素电极104的残留部分(构成导通层20)，或如图1d所示的半导体有源层103的残留部分(构成导通层20)。这样一来，相邻的两个像素单元12中的像素电极104被电连接，当其中一个像素单元12受控进行显示时，与其相邻并电连接的像素单元12也被点亮，从而造成了不受控的亮像素点(亮点缺陷)的产生，对显示效果 和产品质量造成不利的影响。
为了解决上述问题，一般采用激光焊接或切割工艺对存在亮点缺陷的像素点进行修复。例如，通过光学检测仪器对阵列基板进行检测，当发现亮点缺陷后，可以对上述导通层20进行切割，以使得相邻的两个像素单元12不被电连接。然而由于像素电极104的厚度较薄，降低了光学检测的识别度，导致漏检率升高。并且在实施上述修复工艺的同时会对已经形成的其它薄膜层结构进行破坏，例如位于像素电极104表面的钝化层、公共电极层等(图中未示出)。从而降低亮点缺陷的修复效果，并对产品的质量造成影响。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、显示装置，能够避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。
本发明实施例提供一种阵列基板的制备方法，包括形成多个呈矩阵形式排列的像素电极的方法，在形成所述像素电极时，形成有将相邻两个所述像素电极电连接的导通层，该方法还包括：在形成有所述导通层的基板表面形成光刻胶层；通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域，所述第一光刻胶去除区域对应所述导通层的位置，所述光刻胶保留区域对应形成有所述导通层的基板表面的其它区域；刻蚀所述第一光刻胶去除区域的所述导通层，形成用于避免相邻两个所述像素电极电连接的隔断区域；并对所述光刻胶保留区域的光刻胶层进行剥离；在形成有上述结构的基板表面形成金属层；通过一次构图工艺在所述隔断区域内，形成与相邻两个所述像素电极非电连接的金属线。
本发明实施例的还提供一种阵列基板，包括多个呈矩阵形式排列的像素电极、用于避免相邻两个所述像素电极电连接的隔断区域、以及位于所述隔断区域内，与相邻两个所述像素电极非电连接的金属线。
本发明实施例还提供一种显示装置，包括如上所述的任意一种阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为一种阵列基板的结构示意图；
图1b为一种阵列基板的剖视结构示意图；
图1c为一种具有导通层的阵列基板的结构示意图；
图1d为另一种具有导通层的阵列基板的结构示意图；
图2为本发明实施例提供的一种阵列基板的制备方法流程图；
图3为本发明实施例提供的另一种阵列基板的制备方法流程图；
图4a-4f为本发明实施例提供的一种阵列基板的制备过程中各个阶段的结构示意图；
图5为本发明实施例提供的又一种阵列基板的制备方法流程图；
图6a-6h为本发明实施例提供的另一种阵列基板的制备过程中各个阶段的结构示意图。
附图标记：
01-衬底基板；10-栅线；11-数据线(金属线)；12-像素单元；101-栅极；102-栅极绝缘层；103-半导体有源层；104-像素电极；105-源漏金属层；106-隔断区域；1061-凹槽；1062-绝缘部；107-引线过孔；108-引线；109-钝化层；110-公共电极层；20-导通层；30-光刻胶层；A-第一光刻胶去除区域；B-光刻胶保留区域；C-第二光刻胶去除区域。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板的制备方法，可以包括形成如图1a所示的多个呈矩阵形式排列的像素电极104的方法，在采用形成上述像素电极104的方法时，还形成将相邻两个像素电极104电连接的导通层20，如图2所示，上述阵列基板的制备方法还可以包括：
S101、在形成有导通层20的基板表面形成光刻胶层30。
S102、通过一次曝光显影工艺，形成第一光刻胶去除区域A和光刻胶保留区域B，第一光刻胶去除区域A对应上述导通层20的位置，光刻胶保留区域B对应形成有导通层20的基板表面的其它区域。
S103、刻蚀第一光刻胶去除区域A的导通层20，形成用于避免相邻两个像素电极104电连接的隔断区域106。并对光刻胶保留区域B的光刻胶层进行剥离。
S104、在形成有上述结构的基板表面形成金属层。
S105、通过一次构图工艺在上述隔断区域106内，形成与相邻两个像素电极104非电连接的金属线。例如，可以将隔断区域106的宽度设置为大于金属线的宽度，以保证金属线不会与位于其两侧的像素电极104电连接。
需要说明的是，第一、上述导通层20可以如图1c所示，由像素电极104的残留部分构成；或，如图1d所示的，还可以由半导体有源层103的残留部分构成；或，还可以同时由像素电极104的残留部分以及半导体有源层103的残留部分构成。
上述残留部分产生的原因有多种，例如，在曝光显影的过程中，由于相邻两个像素单元12之间的光刻胶表面被灰尘覆盖，导致光刻胶无法完全曝光而形成多余的光刻胶保留区域。或者，由于曝光工艺的缺陷导致两个相邻像素单元12之间的光刻胶未被完全曝光，同样形成了多余的光刻胶保留区域。又或者，由于显影工艺的缺陷导致两个相邻像素单元12之间的光刻胶未被完全显影掉，而形成了多余的光刻胶保留区域，等等因素。在此基础上，通过后续的制作工艺，就会在两个相邻像素单元12之间形成上述残留部分。
第二、上述金属层可以包括用于形成栅线10的栅极金属层；或，用于形成数据线11的源漏金属层105。
例如，如图1a所示，上述阵列基板的每一个像素单元12可以包括一个薄膜晶体管(Thin Film Transistor，简称TFT)。所述薄膜晶体管是一种具有开关特性的半导体单元，例如可以是非晶硅型薄膜晶体管、低温多晶硅型薄膜晶体管、氧化物型薄膜晶体管、或有机物型薄膜晶体管等，在此不做限定。
所述薄膜晶体管可以是顶栅型，也可以是底栅型，在此不作限定。顶栅、底栅是相对所述栅极101和栅极绝缘层102的位置而定的。
例如，如图1b所示，相对衬底基板01即透明基板而言，当栅极101靠 近所述衬底基底，栅极绝缘层102远离所述衬底基板01时，为底栅型薄膜晶体管。这时，由于上述金属层位于栅极绝缘层102的表面，而并非靠近衬底基板01的一侧，所以该金属层可以为构成数据线11的源漏金属层105。
又例如，当栅极101远离所述衬底基板01，栅极绝缘层102靠近所述衬底基板时，为顶栅型薄膜晶体管。这时，由于金属层位于栅极绝缘层102的表面，因此，该金属层可以为构成栅极101的栅极金属层。
本发明以下实施例均是以具有底栅型薄膜晶体管的阵列基板为例进行的说明。
第三、本发明实施例中的光刻胶层，在经过掩膜版的曝光显影后，可以是采用正性光刻胶，即曝光区域的光刻胶层在显影过程中被去除，未曝光区域的光刻胶在显影过程中被保留。也可以采用一种反性光刻胶，即在曝光区域的光刻胶层在显影过程中被保留，而未曝光区域的光刻胶在显影过程中被去除。本发明对此不作限制。但是以下实施例，均是以采用正性光刻胶，即曝光区域的光刻胶层在显影过程中被去除，未曝光区域的光刻胶在显影过程中被保留为例进行的说明。
第四、在本发明中，构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。本发明实施例中的一次构图工艺，是以通过一次掩膜曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例进行的说明。
本发明实施例提供一种阵列基板的制备方法，包括在衬底基板上形成多个呈矩阵形式排列的像素电极的方法。然而由于制备工艺或者运输、储藏等因素，在采用上述方法制备像素电极的过程中，还可能形成将相邻两个像素电极电连接的导通层。这样一来，相邻的两个像素电极对应的像素单元被电连接，当其中一个像素单元受控进行显示时，与其相邻并电连接的像素单元也被点亮，从而造成了不受控的亮像素点(亮点缺陷)的产生，对显示效果和产品质量造成不利的影响。
因此，本发明实施例在上述制备方法的基础上，还包括：首先，在形成 有上述结构的基板表面形成光刻胶层；接着，通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域。第一光刻胶去除区域对应导通层的位置；光刻胶保留区域对应形成有导通层的基板表面的其它区域。接下来，对所述第一光刻胶去除区域的导通层进行刻蚀，形成用于避免相邻两个像素单元的像素电极电连接的隔断区域，并对光刻胶保留区域的光刻胶进行剥离。接着，在形成有上述结构的基板表面形成金属层；最后通过构图工艺在隔断区域内，形成与相邻两个像素电极非电连接的金属线。这样一来，由于对导通层进行切断处理，避免了两个相邻像素电极之间的电连接，减小了亮点缺陷的产生。并且上述切断处理工艺是在形成金属线之前完成的，因此对阵列基板通过后续制作工艺形成的薄膜层结构不会造成破坏和影响。从而能够避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。提高了亮点缺陷修复效果，以及产品的质量。
实施例一
在上述通过一次曝光显影工艺，在形成第一光刻胶去除区域A和光刻胶保留区域B的步骤之后，在上述刻蚀第一光刻胶去除区域A的导通层20的步骤之前，所述方法可以包括：
第一光刻胶去除区域A对应预形成的隔断区域106，所述光刻胶保留区域B对应形成有导通层20的基板表面的其它区域。
以下对形成有上述隔断区域106的阵列基板的制备方法进行详细的描述，如图3及图4a-4f所示，该方法包括如下步骤。
S201、如图4a所示，在形成有导通层20的基板表面(此外，该基板还包括在衬底基板01上依次形成有未示出的栅极101、半导体有源层103、像素电极104)形成光刻胶层30。
S202、如图4b所示，通过一次曝光显影工艺，形成第一光刻胶去除区域A和光刻胶保留区域B，第一光刻胶去除区域A对应预形成的隔断区域106，光刻胶保留区域B对应形成有导通层20的基板表面的其它区域，即光刻胶保留区域B对应除隔断区域外的基板表面的其他区域。
S203、如图4c所示，刻蚀第一光刻胶去除区域A的像素电极104的残留部分(导通层20)以及部分位于栅极101表面的部分栅极绝缘层102，形成用于避免相邻两个像素电极104电连接的隔断区域106；并如图4d所示， 对上述光刻胶保留区域B的光刻胶层30进行剥离。
S204、如图4e所示，在形成有上述结构的基板表面形成源漏金属层105(金属层)。
S205、如图4f所示，通过一次构图工艺(例如涂覆光刻胶后，进行一次掩膜曝光工艺，然后进行显影、刻蚀、剥离等工艺)在隔断区域106内，形成与相邻两个像素电极104非电连接的数据线11的(金属线)。
可以看出上述隔断区域106内的导通层20(像素电极104的残留部分)被完全去除。并且位于隔断区域106内的数据线11和位于其两侧的像素电极104均不会电连接。这样一来，可以保证数据线11能够正常接收数据信号，以使得阵列基板能够正常工作，并且还可以通过隔断区域106避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。
需要说明的是，第一、上述步骤S203中在刻蚀第一光刻胶去除区域的导通层20时，还对部分栅极绝缘层102进行了刻蚀。这样一来，可以使得数据线11与位于其两侧的像素电极104之间具有一定的段差，增加了数据线11与像素电极104之间的距离，从而可以有效避免数据线11与像素电极104之间的信号串扰(Crosstalk)。当然，当上述金属层采用栅极金属层时，上述方案同样可以有效避免栅线10与像素电极104之间的信号串扰。此外，本领域技术人员可以根据实际需要对段差的高度进行控制。例如为了提高防止信号串扰的效果，可以将段差的高度设置为大于等于数据线11或栅线10的厚度。或者，为了减小显示面板的厚度，可以减小上述段差的高度。本发明对此不作限制。
第二、上述实施例是以导通层20由像素电极104的残留部分构成为例进行的说明。当导通层20由半导体有源层103的残留部分构成时同理可得。此处不再赘述。
实施例二
在上述通过一次曝光显影工艺，形成第一光刻胶去除区域A和光刻胶保留区域B的步骤之后，在上述刻蚀第一光刻胶去除区域A的导通层20的步骤之前，所述方法可以包括：
上述第一光刻胶去除区域A对应预形成的凹槽1061，光刻胶保留区域B对应形成有上述导通层20的基板表面的其它区域。即，光刻胶保留区域B 对应除了第一光刻胶去除区域A外的基板表面的其他区域。所述预形成的隔断区域106包括两个上述凹槽1061以及位于两个所述凹槽1061之间的绝缘部1062。
以下对形成有上述隔断区域106的阵列基板的制备方法进行详细的描述，如图5及图6a-6h所示，该方法包括如下步骤。
S301、如图6a所示，在形成有导通层20的基板表面(此外，该基板还包括在衬底基板01上依次形成有未示出的栅极101，以及栅线10、栅极绝缘层102、半导体有源层103、像素电极104)形成光刻胶层30。其中导通层20由半导体有源层103的残留部分构成。
S302、如图6b所示，通过一次曝光显影工艺，形成第一光刻胶去除区域A、光刻胶保留区域B以及第二光刻胶去除区域C，上述第一光刻胶去除区域A对应预形成的凹槽1061，第二光刻胶去除区域C对应预形成的引线过孔107，光刻胶保留区域B对应形成有上述导通层20的基板表面的其它区域。即光刻胶保留区域B对应除了第一光刻胶去除区域A及第二光刻胶去除区域C外的基板表面的其他区域。
所述预形成的隔断区域106包括两个上述凹槽1061以及位于两个所述凹槽1061之间的绝缘部1062，如图6c所示。
S303、如图6c所示，刻蚀第一光刻胶去除区域A的半导体有源层103的残留部分(导通层20)。形成用于避免相邻两个像素电极104电连接的隔断区域106。刻蚀第二光刻胶去除区域C的栅极绝缘层102，形成上述引线过孔107。并如图6d所示，对上述光刻胶保留区域B的光刻胶层30进行剥离。
S304、如图6e所示，在形成有上述结构的基板表面形成源漏金属层105(金属层)。
S305、如图6f所示，通过一次构图工艺(例如涂覆光刻胶后，进行一次掩膜曝光工艺，然后进行显影、刻蚀、剥离等工艺)在隔断区域106内，形成与相邻两个像素电极104非电连接的数据线11(金属线)。即在绝缘部1062的表面形成上述数据线11。此外，还可以在上述引线过孔107内形成引线108。通过上述引线过孔107，位于阵列基板引线区域的引线108与阵列基板上的栅线10电连接。
S306、如图6g所示，在形成有上述结构的基板表面，形成钝化层109。
S307、在钝化层109的表面通过构图工艺形成公共电极层110。
可以看出，通过上述隔断区域106的两个凹槽1061将部分导通层20完全去除，以使得相邻两个像素电极104处于非电连接的状态，并且数据线11位于隔断区域106的绝缘部1062的表面，并与其两侧的像素电极104均不会电连接。这样一来，可以保证数据线11能够正常接收数据信号，以使得阵列基板能够正常工作，并且还可以通过隔断区域106避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。
需要说明的是，第一、上述实施例的方案中，在形成凹槽1061的同时可以完成引线过孔107的制备，因此能够简化制作工艺。并且该方法同样适用于实施例一。
第二、实施例二提供的方案中，像素电极104与公共电极层110异层设置。位于阵列基板最上方的公共电极层110可以为狭缝状，而靠近衬底基板01的像素电极104可以为平面状。采用上述阵列基板构成的显示装置为AD-SDS(Advanced-Super Dimensional Switching，简称为ADS，高级超维场开关)型显示装置。AD-SDS技术通过同一平面内公共电极层110边缘所产生的平行电场以及像素电极104与公共电极层110间产生的纵向电场形成多维电场，使液晶盒内像素电极间、电极正上方所有取向液晶分子都能够产生旋转转换，从而提高了平面取向系液晶工作效率并增大了透光效率。同样，上述公共电极层110的制备方法，同样适用于实施例一。
此外，在实施例一和实施例二，当将公共电极层110制作于与阵列基板相对盒的彩膜基板上时，构成的显示装置为TN(Twist Nematic，扭曲向列)型显示装置。不同的是，TN型显示装置，采用垂直电场原理的液晶显示器，通过被相对布置在彩膜基板上的公共电极层110和在阵列基板上的像素电极104之间形成垂直电场来驱动向列模式的液晶。TN型显示装置具有大孔径比的优点，但是具有约90°的窄视角的缺点。本领域技术人员，可以根据实际需要对公共电极层110的设置进行选择。
第三、上述实施例是以导通层20由半导体有源层103的残留部分构成为例进行的说明。当导通层20由像素电极104的残留部分构成时同理可得。此处不再赘述。
第四、对比实施例一和实施例二中的隔断区域106，可以看出实施例一中，在制作隔断区域106时，需要对大部分导通层20进行刻蚀，刻蚀时间长，但刻蚀精度要求低，防止相邻两个像素电极104电连接的效果好。而实施例二中，在制作隔断区域106时，仅需要对一小部分导通层20进行刻蚀以形成凹槽1061，因此刻蚀速度快，但是对刻蚀的精度要求高，防止相邻两个像素电极104电连接的效果较低于实施例一。因此，本领域技术人员可以根据实际需要对制作隔断区域106的方案进行选择。
进一步的，上述隔断区域106的宽度范围可以为12μm～20μm。这样一来，能够保证金属线(数据线11或栅线10)有足够的布线空间，避免与位于其两侧的像素电极104发生信号串扰的不良现象。
本发明实施例提供一种阵列基板，如图1a所示包括多个呈矩阵形式排列的像素电极104，还包括：
用于避免相邻两个像素电极104电连接的隔断区域106；以及位于该隔断区域内，与相邻两个像素电极106非电连接的金属线。
本发明实施例提供一种阵列基板，包括多个呈矩阵形式排列的像素电极，还包括用于避免相邻两个像素电极电连接的隔断区域；以及位于该隔断区域内，与相邻两个像素电极非电连接的金属线。这样一来，即使由于制备工艺或者运输、储藏等因素，在进行像素电极进行制备的过程中，形成的将相邻两个像素电极电连接的导通层，导致相邻的两个像素电极对应的像素单元被电连接。当其中一个像素单元受控进行显示时，与其相邻并电连接的像素单元也被点亮，从而造成不受控的亮像素点(亮点缺陷)的产生，对显示效果和产品质量造成不利的影响。本发明实施例能够通过隔断区域对导通层进行切断处理，可避免两个相邻像素电极之间的电连接，减小亮点缺陷的产生。并且在金属线制备之前完成隔断区域的设置，因此对阵列基板通过后续制作工艺形成的薄膜层结构不会造成破坏和影响。从而能够避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。提高了亮点缺陷修复效果，以及产品的质量。
例如，所述隔断区域106可以如图4c所示，隔断区域106内的导通层20(像素电极的残留部分)被完全去除，隔断区域106内仅设置有金属线(例如数据线11)。并且位于隔断区域106内的数据线11和位于其两侧的像素 电极104均不会电连接。这样一来，可以保证数据线11能够正常接收数据信号，以使得阵列基板能够正常工作，并且还可以通过隔断区域106避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。
例如，隔断区域106也可以如图6d所示，隔断区域106包括两个凹槽1061，以及位于两个凹槽1061之间的绝缘部1062，金属线(例如数据线11)位于绝缘部1062的表面。可以看出，通过上述隔断区域106的两个凹槽1061将部分导通层20完全去除，以使得相邻两个像素电极104处于非电连接的状态，并且数据线11位于隔断区域106的绝缘部1062的表面，并与其两侧的像素电极104均不会电连接。这样一来，可以保证数据线11能够正常接收数据信号，以使得阵列基板能够正常工作，并且还可以通过隔断区域106避免在减少亮点缺陷的过程中，对阵列基板上过多薄膜层的破坏。
本发明实施例提供一种显示装置，包括如上所述的任意一种阵列基板。具有与前述实施例中的阵列基板相同的有益效果。由于阵列基板的详细结构以及有益效果已在前述实施例中做了详细的描述，此处不再赘述。
在本发明实施例中，显示装置可以包括液晶显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机、手表、平板电脑、笔记本电脑或导航仪等任何具有显示功能的产品或者部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所附权利要求的保护范围为准。
本专利申请要求于2014年9月16日递交的中国专利申请第201410472064.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种阵列基板的制备方法，包括形成多个呈矩阵形式排列的像素电极的方法，在形成所述像素电极时，形成有将相邻两个所述像素电极电连接的导通层，
    该方法还包括：
    在形成有所述导通层的基板表面形成光刻胶层；
    通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域，所述第一光刻胶去除区域对应所述导通层的位置，所述光刻胶保留区域对应形成有所述导通层的基板表面的其它区域；
    刻蚀所述第一光刻胶去除区域的所述导通层，形成用于避免相邻两个所述像素电极电连接的隔断区域；并对所述光刻胶保留区域的光刻胶层进行剥离；
    在形成有上述结构的基板表面形成金属层；
    通过一次构图工艺在所述隔断区域内，形成与相邻两个所述像素电极非电连接的金属线。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，在所述通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域的步骤之后，所述刻蚀所述第一光刻胶去除区域的所述导通层的步骤之前，所述方法包括：
    所述第一光刻胶去除区域对应预形成的所述隔断区域，所述光刻胶保留区域对应形成有所述导通层的基板表面的其它区域。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，在所述通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域的步骤之后，所述刻蚀所述第一光刻胶去除区域的所述导通层的步骤之前，所述方法包括：
    所述第一光刻胶去除区域对应预形成的凹槽，所述光刻胶保留区域对应形成有所述导通层的基板表面的其它区域；所述预形成的隔断区域包括两个所述凹槽以及位于两个所述凹槽之间的绝缘部。
  4. 根据权利要求1所述的阵列基板的制备方法，其中，所述金属层包括栅极金属层或源漏金属层。
  5. 根据权利要求1所述的阵列基板的制备方法，其中，在所述阵列基板 包括栅极绝缘层的情况下，在刻蚀所述第一光刻胶去除区域的所述导通层的同时，对部分所述栅极绝缘层进行刻蚀。
  6. 根据权利要求1所述的阵列基板的制备方法，在进行所述通过一次曝光显影工艺，形成第一光刻胶去除区域和光刻胶保留区域的步骤的同时，所述方法还包括：
    形成第二光刻胶去除区域，所述第二光刻胶去除区域对应预形成的引线过孔；
    对所述第二光刻胶去除区域的栅极绝缘层进行刻蚀，以形成所述引线过孔。
  7. 根据权利要求1-6任一项所述的阵列基板的制备方法，在所述通过构图工艺在对应所述隔断区域的位置处形成金属线的步骤之后，所述方法还包括：
    在形成有上述结构的基板表面，形成钝化层；
    在所述钝化层的表面形成公共电极层。
  8. 根据权利要求7所述的阵列基板的制备方法，其中，所述隔断区域的宽度范围为12μm～20μm。
  9. 一种阵列基板，包括多个呈矩阵形式排列的像素电极、用于避免相邻两个所述像素电极电连接的隔断区域、以及位于所述隔断区域内，与相邻两个所述像素电极非电连接的金属线。
  10. 根据权利要求9所述的阵列基板，其中，所述隔断区域内仅设置有所述金属线。
  11. 根据权利要求9所述的阵列基板，其中，所述隔断区域包括两个凹槽，以及位于两个所述凹槽之间的绝缘部，所述金属线位于所述绝缘部的表面。
  12. 一种显示装置，包括如权利要求9-11任一项所述的阵列基板。
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