CN103985671B - 阵列基板制备方法和阵列基板、显示装置 - Google Patents

阵列基板制备方法和阵列基板、显示装置 Download PDF

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CN103985671B
CN103985671B CN201410183494.1A CN201410183494A CN103985671B CN 103985671 B CN103985671 B CN 103985671B CN 201410183494 A CN201410183494 A CN 201410183494A CN 103985671 B CN103985671 B CN 103985671B
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active layer
array base
base palte
data wire
gate insulator
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CN103985671A (zh
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张文余
谢振宇
郭建
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明实施例公开了一种阵列基板制备方法和阵列基板、显示装置，涉及显示领域，能够解决因有源层残留导致的开口率降低的技术问题。本发明的阵列基板制备方法，包括：形成栅金属层的工序，所述栅金属层包括栅线；有源层的成膜工序和信号线金属层的成膜工序，所述信号线金属层包括数据线；以及，通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形的工序；在所述有源层的成膜工序之后，所述信号线金属层的成膜工序之前，还包括：通过构图工艺，将所述有源层的第一区域镂空，所述第一区域位于显示区域的数据线下方，且，所述数据线与所述栅线的交叠区域除外。

Description

阵列基板制备方法和阵列基板、显示装置
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板制备方法和阵列基板、显示装置。
背景技术
液晶显示器因其具有体积小、重量轻、低功耗、低电压以及无辐射等特点，已广泛替代了传统CRT显示装置，应用于在生活工作中。
液晶显示器由阵列基板和彩膜基板对盒而成，如图1和图2所示，图1为现有技术中一种阵列基板的平面结构，图2为沿B-B’的剖面结构示意图，在基板7上，顺序形成有栅金属层(包括栅极和图中的栅线8)、栅绝缘层4、有源层5、信号线金属层、像素电极层、钝化层2和公共电极层，信号线金属层包括薄膜晶体管的源极、漏极和图中的数据线6，像素电极层包括图中的像素电极1，公共电极层包括图中的公共电极3。其中，形成有源层5及信号线金属层的图形时可采用半色调掩膜工艺，此过程中因有源层5和信号线金属层材料不同，刻蚀难易程度也不同，结果往往会存在有源层残留(activetail)现象。例如图2所示，显示区域数据线6下方的有源层边缘存在残留，见图中的A区域，而一般而言为避免发生短路及信号干扰等原因，像素电极1需要远离数据线6一定距离，但因该有源层残留区域(即图中A区域)的存在，像素电极1与数据线6之间的距离设计时则需考虑该有源层残留区域的存在，结果导致像素的透光面积减小，开口率下降。
发明内容
本发明实施例提供一种阵列基板制备方法和阵列基板、显示装置，能够解决因有源层残留导致的开口率降低的技术问题。
为达到上述目的，本发明的实施例采用如下技术方案：
一种阵列基板的制备方法，包括：形成栅金属层的工序，所述栅金属层包括栅线；有源层的成膜工序和信号线金属层的成膜工序，所述信号线金属层包括数据线；以及，通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形的工序；在所述有源层的成膜工序之后，所述信号线金属层的成膜工序之前，还包括：通过构图工艺，将所述有源层的第一区域镂空，所述第一区域位于显示区域的数据线下方，且，所述数据线与所述栅线的交叠区域除外。
优选地，还包括在所述栅金属层上方且所述有源层下方形成栅极绝缘层的工序；通过所述构图工艺，除将所述有源层的所述第一区域镂空外，还将栅极绝缘层对应所述第一区域的位置镂空。
优选地，通过所述构图工艺还同步形成栅极绝缘层通孔，所述栅极绝缘层通孔设置在所述阵列基板的边缘，贯穿所述栅极绝缘层和所述有源层。
本发明实施例还提供一种阵列基板，包括：薄膜晶体管、交叠设计的数据线和栅线，所述数据线所在层的图形和所述薄膜晶体管的有源层图形通过半色调掩膜工艺同时形成，除所述数据线与所述栅线的交叠区域外，显示区域的数据线下方对应区域的所述有源层镂空。
优选地，所述薄膜晶体管还包括：栅绝缘层，所述栅极绝缘层位于所述有源层的下方，所述栅线所在层的上方；除所述数据线与所述栅线的交叠区域外，显示区域的数据线下方对应区域的所述栅绝缘层也镂空。
进一步地，上述阵列基板的边缘还设置有：贯穿所述栅极绝缘层和所述有源层的栅极绝缘层通孔。
本发明实施例还提供一种显示装置，包括：上述的任一阵列基板。
本发明实施例提供的阵列基板制备方法和阵列基板、显示装置，在信号线金属层的成膜工序之前，先通过构图工艺，将显示区域数据线下方对应区域(与栅线的交叠区域除外)的有源层镂空，这样后续采用半色调掩膜工艺同时形成有源层图形和信号线金属层图形时，可以避免数据线下方存在有源层残留，使像素电极与数据线之间的距离可进一步减小，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率；同时，数据线下方的有源层镂空，还可降低了数据线处的段差，减小了RubbingMura(因取向膜摩擦取向工艺在面板上形成的细条纹状不良)的发生几率，有利于提高良品率和画面品质。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为现有阵列基板的平面结构示意图；
图2为图1所示阵列基板沿B-B’的剖面结构示意图；
图3为本发明实施例一提供的TN模式阵列基板制备方法流程图；
图4为本发明实施例一提供的ADS模式阵列基板制备方法流程图；
图5为本发明实施例二提供的阵列基板的平面结构示意图；
图6为图5所示阵列基板沿B-B’的剖面结构示意图；
图7为图5所示阵列基板沿C-C’的剖面结构示意图。
附图标记
1-像素电极，2-钝化层，3-公共电极，4-栅绝缘层，5-有源层，6-数据线，7-基板，8-栅线，9-栅极绝缘层通孔，10-第一区域，11-信号线金属层，12-栅极金属层。
具体实施方式
本发明实施例提供一种阵列基板制备方法和阵列基板、显示装置，能够解决因有源层残留导致的开口率降低的技术问题。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
实施例一
本发明实施例提供一种阵列基板的制备方法，该制备方法包括：形成栅金属层的工序，所述栅金属层包括栅线；有源层的成膜工序和信号线金属层的成膜工序，所述信号线金属层包括数据线；以及，通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形的工序；在有源层的成膜工序之后，信号线金属层的成膜工序之前，还包括：通过构图工艺，将有源层的第一区域镂空，所述第一区域位于显示区域的数据线下方，且，所述数据线与栅线的交叠区域除外。
本实施例阵列基板制备方法，在信号线金属层的成膜工序之前，先通过构图工艺，将显示区域数据线下方对应区域(与栅线的交叠区域除外)的有源层镂空，这样后续采用半色调掩膜工艺同时形成有源层图形和信号线金属层图形时，即可避免数据线下方存在有源层残留，使像素电极与数据线之间的距离可进一步减小，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率；同时，数据线下方的有源层镂空，还可降低数据线处的段差，减小摩擦不良(RubbingMura)的发生几率，有利于提高良品率和画面品质。
本发明实施例对如何将有源层第一区域进行镂空的具体实现方式不做限定，可以是本领域技术人员所熟知的任意实现方式。为便于本领域技术人员的理解，下面对本实施例提供的阵列基板制备方法详细叙述如下。
以TN模式阵列基板为例，本实施例提供的阵列基板制备方法，如图3所示，具体包括：
101、形成栅极金属层的工序，所述栅金属层包括栅线；
本步骤在基板上通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第1次MASK)，形成包括栅极、栅线及其他功能图形的栅极金属层。
102、形成栅绝缘层的工序及有源层的成膜工序；
本步骤继续在基板上依次沉积栅极绝缘层和有源层的膜层。
103、通过构图工艺，将有源层的第一区域镂空，所述第一区域位于显示区域的数据线下方，且，所述数据线与栅线的交叠区域除外；
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第2次MASK)，在第一区域形成刻蚀槽，参照图5所示，所述第一区域10位于显示区域的数据线6下方，且，数据线6与栅线8的交叠区域除外。如图5中所示，虚线框区域对应区域即为第一区域10。此处所述的显示区域指最终形成显示装置时的有效观看部分对应的区域，不包括阵列基板边缘的非像素区域。
所述阵列基板的制备方法还包括在所述栅金属层上方且所述有源层下方形成栅极绝缘层的工序；优选地，除将所述有源层的所述第一区域镂空外，还将栅极绝缘层对应所述第一区域的位置镂空。
具体而言，有源层之下为栅绝缘层，为降低数据线处的段差，减小RubbingMura的发生几率，提高良品率和画面品质，优选地，本步骤所述构图工艺除将第一区域对应的有源层镂空外，还将第一区域对应的栅极绝缘层镂空；而且，本领域技术人员可以实际需要(主要是降低段差的需要)，既可以将第一区域对应的栅极绝缘层全部去除，也可以只将第一区域对应的栅极绝缘层的厚度减薄。
104、信号线金属层的成膜工序；本步骤沉积金属膜层用以形成信号线金属层。
105、通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形的工序，对应第3次MASK。
本步骤通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形，即一次曝光，通过各自的刻蚀方法形成信号线金属层图形和有源层图形，同时形成TFT(ThinFilmTransistor，薄膜场效应晶体管)沟道。此时，数据线6下方不存在有源层残留，如图6所示。图6中A-A’区域为第一区域10，因第一区域有源层和栅绝缘层均被镂空(此处栅极金属层也被刻蚀掉了)，该第一区域10内的数据线6直接设置在基板7上。
本步骤形成的信号线金属层图形包括薄膜晶体管的源极、漏极、数据线以及阵列基板边缘功能区(GOA单元)的功能引线，本步骤形成的有源层图形主要包括薄膜晶体管的沟道。
106、本步骤形成钝化层以覆盖以上图形，并通过涂胶曝光\显影\刻蚀\剥离(第4次MASK)，形成通孔。本步骤形成的通孔贯穿钝化层，位于薄膜晶体管的源极上方以及阵列基板各线外接连接区(bonding区)，通过该些通孔，用于将后续形成的像素电极连接至薄膜晶体管的源极以及用于将阵列基板各种线外接连接区(bonding区)。
107、形成像素电极，且像素电极与薄膜晶体管的源极电连接；本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离工序(第5次MASK)，形成像素电极，同时覆盖106步骤中提到的位于阵列基板bonding区的通孔，保护通孔下裸露的金属线。
ADS(Advanced-SuperDimensionalSwitching，高级超维场开关技术，简称：ADS)，通过同一平面内像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极间产生的纵向电场形成多维电场，使液晶盒内像素电极或公共电极之间、像素电极或公共电极正上方所有取向液晶分子都能够产生旋转转换，从而提高了平面取向系液晶工作效率并增大了透光效率。高级超维场开关技术可以提高TFT-LCD画面品质，具有高透过率、宽视角、高开口率、低色差、低响应时间、无挤压水波纹(pushMura)波纹等优点。
如图4所示，本实施例还提供一种ADS模式阵列基板的制备方法，步骤201-205与图3所述制备方法大致相同，其区别之处在于，先执行步骤206形成像素电极，再执行步骤207形成钝化层，最后还包括：步骤208形成公共电极。步骤208通过沉积\涂胶曝光\显影\刻蚀\剥离工序(第6次MASK)，形成公共电极。
ADS模式阵列基板的具体结构参照附图5、图6和图7。另外，因ADS模式和TN模式的结构区别，步骤205、206、步骤207和步骤208中使用的掩模板，形成的图形均不同，因该些区别与本发明无直接关系，此处不再详述。
上述阵列基板制备方法，通过5MASK形成TN模式阵列基板，或者，通过6MASK形成ADS模式阵列基板，在显示区域数据线6下方不存在有源层残留，像素电极与数据线之间的距离可进一步减小，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率；同时，数据线下方的有源层镂空，还可降低了数据线处的段差，减小了RubbingMura的发生几率，从而有利于提高良品率和画面品质以及降低成本。
另外，对于周边采用GOA(GateOnArray,集成在阵列基板上的栅极驱动器)单元的阵列基板，因在边缘的连接区域(Band区域)需要设计贯穿栅极绝缘层和有源层的栅极绝缘层通孔，以实现外围特殊需求(GOA单元内部设计需求，主要是与栅线的连接需求)的栅极金属层和信号电极层金属层导通，例如位于栅极金属层的各种引线与栅线的连接需求，以及GOA单元与栅线的连接需求。
现有技术中在有源层的成膜工序之后，信号线金属层的成膜工序之前，形成栅极绝缘层通孔。因此优选地，上述步骤103(或203)可与形成栅极绝缘层通孔的工序同步形成。具体而言，如图5、图6和图7所示，该方案中在显示区域将第一区域10对应的有源层和栅极绝缘层均镂空外，还同步在阵列基板的边缘(非显示区域)形成栅极绝缘层通孔9，换言之，即通过所述构图工艺还同步形成栅极绝缘层通孔9，所述栅极绝缘层通孔设置在所述阵列基板的边缘，贯穿栅极绝缘层和有源层。其中，图5为阵列基板的平面结构图，图6为图5中B-B’处阵列基板的剖面结构图，显示出数据线6下方第一区域10处存在的各膜层结构。第一区域10的有源层和栅绝缘层4均被镂空(此区域的栅极金属层在步骤101或201中也被刻蚀掉了)，第一区域10处的数据线6直接设置在基板7上。图7为图5中C-C’处阵列基板的剖面结构图，显示出位于阵列基板边缘的栅极绝缘层通孔9处存在的各膜层结构，其中栅极金属层12和信号电极线金属层11连接，此位置处的栅极金属层12和信号电极线金属层11可分别用作栅线引线与栅线，此处通过栅极绝缘层通孔9将二者连接。
上述阵列基板制备方法，形成栅极绝缘层通孔的同时将数据线下方(第一区域处)的栅极绝缘层和有源层去除，不需要额外增加工序，但形成的阵列基板数据线下方不再存在有源层残留，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率，同时降低了数据线处的段差，减小了RubbingMura的发生几率，从而有利于提高良品率和画面品质以及降低成本。
实施例二
本发明实施例还提供一种阵列基板，如图5、图6和图7所示，包括：薄膜晶体管、交叠设计的数据线6和栅线8，数据线6所在层的图形和薄膜晶体管的有源层5图形通过半色调掩膜工艺同时形成，除数据线6与栅线8的交叠区域外，显示区域的数据线6下方对应区域的有源层5镂空，即将第一区域10内的有源层5镂空
本实施例提供的阵列基板，数据线下方不再存在有源层残留，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率，同时降低了数据线处的段差，减小了RubbingMura的发生几率，从而有利于提高良品率和画面品质以及降低成本。
上述薄膜晶体管还包括：还包括：栅绝缘层4，栅极绝缘层4位于有源层5的下方，栅线8所在层(即栅极金属层12)的上方；本实施例优选地，除数据线6与栅线8的交叠区域外，显示区域的数据线6下方对应区域的栅绝缘层4也镂空，即将第一区域10对应位置的栅绝缘层4也镂空。
这样阵列基板制备时，形成栅极绝缘层通孔的同时即可将数据线下方(第一区域处)的栅极绝缘层和有源层去除，不需要额外增加工序，但形成的阵列基板数据线下方不再存在有源层残留。
本发明实施例提供的阵列基板，显示区域的数据线下方对应区域的有源层(与栅线的交叠区域除外)镂空，数据线下方不会存在有源层残留，像素电极与数据线之间的距离可进一步减小，从而解决因有源层残留导致的开口率降低的问题，实现更高开口率；同时，数据线下方的有源层镂空，还可降低了数据线处的段差，减小了RubbingMura的发生几率，从而有利于提高良品率和画面品质以及降低成本。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。所述显示装置，可以实现更高开口率，同时良品率和画面品质获得低声，所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (7)

1.一种阵列基板制备方法，包括：形成栅金属层的工序，所述栅金属层包括栅线；有源层的成膜工序和信号线金属层的成膜工序，所述信号线金属层包括数据线；以及，通过半色调掩膜工艺同时形成有源层图形和信号线金属层图形的工序；其特征在于，在所述有源层的成膜工序之后，所述信号线金属层的成膜工序之前，还包括：
通过构图工艺，将所述有源层的第一区域镂空，
所述第一区域位于显示区域的数据线下方，且，所述数据线与所述栅线的交叠区域除外。
2.根据权利要求1所述的制备方法，其特征在于，还包括在所述栅金属层上方且所述有源层下方形成栅极绝缘层的工序；
通过所述构图工艺，除将所述有源层的所述第一区域镂空外，还将栅极绝缘层对应所述第一区域的位置镂空。
3.根据权利要求2所述的制备方法，其特征在于，通过所述构图工艺还同步形成栅极绝缘层通孔，所述栅极绝缘层通孔设置在所述阵列基板的边缘，贯穿所述栅极绝缘层和所述有源层。
4.一种阵列基板，包括：薄膜晶体管、交叠设计的数据线和栅线，所述数据线所在层的图形和所述薄膜晶体管的有源层图形通过半色调掩膜工艺同时形成，其特征在于，
除所述数据线与所述栅线的交叠区域外，显示区域的数据线下方对应区域的所述有源层镂空。
5.根据权利要求4所述的阵列基板，其特征在于，所述薄膜晶体管还包括：栅极绝缘层，所述栅极绝缘层位于所述有源层的下方，所述栅线所在层的上方；
除所述数据线与所述栅线的交叠区域外，显示区域的数据线下方对应区域的所述栅极绝缘层也镂空。
6.根据权利要求5所述的阵列基板，其特征在于，所述阵列基板的边缘还设置有：贯穿所述栅极绝缘层和所述有源层的栅极绝缘层通孔。
7.一种显示装置，其特征在于，包括：权利要求4-6任一项所述的阵列基板。
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