US20150318310A1 - Array Substrate and Method for Manufacturing the Same, and Display Device - Google Patents

Array Substrate and Method for Manufacturing the Same, and Display Device Download PDF

Info

Publication number
US20150318310A1
US20150318310A1 US14/498,066 US201414498066A US2015318310A1 US 20150318310 A1 US20150318310 A1 US 20150318310A1 US 201414498066 A US201414498066 A US 201414498066A US 2015318310 A1 US2015318310 A1 US 2015318310A1
Authority
US
United States
Prior art keywords
gate
layer
array substrate
active layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/498,066
Other versions
US9196631B1 (en
Inventor
Wenyu ZHANG
Zhenyu XIE
Jian Guo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Assigned to BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUO, JIAN, XIE, ZHENYU, ZHANG, WENYU
Publication of US20150318310A1 publication Critical patent/US20150318310A1/en
Application granted granted Critical
Publication of US9196631B1 publication Critical patent/US9196631B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to the field of display technology, in particular, to an array substrate and a method for manufacturing the same, and a display device.
  • Liquid crystal displays have widely replaced the traditional CRT display devices because of its small volume, light weight, low power consumption, low voltage and no radiation and the like, and have been used in life and work.
  • FIG. 1 shows a plane structure of an array substrate in the prior art
  • FIG. 2 is a cross-sectional diagram of the structure of the array substrate in FIG. 1 taken along line B-B′.
  • a gate metal layer including a gate and gate line 8 in FIG.
  • a gate insulation layer 4 an active layer 5 , a signal line metal layer, a pixel electrode layer, a passivation layer 2 and a common electrode layer are sequentially formed, wherein the signal line metal layer comprises a source and a drain of a thin film transistor, and data line 6 in the drawings, the pixel electrode layer comprises a pixel electrode 1 in FIG. 1 , and the common electrode layer comprises a common electrode 3 in FIG. 2 .
  • Patterns of the active layer 5 and the signal line metal layer may be formed by using a half-tone mask process, as difference in difficulties in etching the active layer 5 and the signal line metal layer due to their difference in material, active tail phenomenon often occurs. For example, as shown in FIG.
  • active tail phenomenon occurs at edges of the active layer below the data line 6 in the display area (see the region A in FIG. 2 ).
  • the pixel electrode 1 is required to be away from data line 6 as far as possible, however, as the existence of active tail (i.e., region A in FIG. 2 ), the existence of active tail must be taken into account during designing the distance between the pixel electrode 1 and the data line 6 , which results in that the transmittance area of the pixel is decreased, and the aperture ratio is decreased.
  • Embodiments of the invention provide an array substrate and a method for manufacturing the same, and a display device, which can solve the problem that the aperture ratio is decreased due to the active tail.
  • a method for manufacturing an array substrate comprises: a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines; a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after the step of film-forming the active layer and before the step of film-forming the signal line metal layer, the method further comprises a step of:
  • the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • the method further comprises steps of:
  • the method further comprises a step of:
  • gate-insulation-layer through holes simultaneously by using the patterning process, wherein the gate-insulation-layer through holes are provided at edges of the array substrate and penetrate through the gate insulation layer and the active layer.
  • Embodiments of the invention provide an array substrate comprising thin film transistors, and data lines and gate lines provided crossly, a pattern of a layer where the data lines are located and a pattern of an active layer of the thin film transistors are formed simultaneously by using a half-tone mask process, wherein
  • portions of the active layer provided below the data lines in a display area are hollowed out, except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • the thin film transistor further comprises: a gate insulation layer, which is provided below the active layer and above a layer where the gate lines are located, wherein
  • portions of the gate insulation layer provided below the data lines in a display area are hollowed out, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines.
  • the array substrate is further provided with a plurality of gate-insulation-layer through holes penetrating through the gate insulation layer and the active layer at edges thereof.
  • Embodiments of the invention further provide a display device, which comprises any one of the above array substrates.
  • corresponding portions of the active layer provided below the data lines in a display area are hollowed out (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) by using the patterning process firstly, thus active tail below the data lines can be avoided when forming the pattern of the active layer and the pattern of the signal line metal layer simultaneously using a half-tone mask process, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ratio due to the active tail can be solved so as to obtain a high aperture ratio.
  • FIG. 1 is a plane structural diagram of an array substrate in the prior art.
  • FIG. 2 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 1 taken along line B-B′.
  • FIG. 3 is a flowchart of a method for manufacturing a TN-mode array substrate in embodiment 1 of the invention.
  • FIG. 4 is a flowchart of a method for manufacturing an ADS-mode array substrate in embodiment 1 of the invention.
  • FIG. 5 is a plane structural diagram of an array substrate in embodiment 2 of the invention.
  • FIG. 6 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 5 taken along line B-B′.
  • FIG. 7 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 5 taken along line C-C′.
  • Embodiments of the invention provide an array substrate and a method for manufacturing the same, and a display device, which can solve the problem of the decreased aperture ratio due to the active tail.
  • the embodiment provides a method for manufacturing an array substrate, which comprises: a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines; a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after the step of film-forming the active layer and before the step of film-forming the signal line metal layer, the method further comprises a step of:
  • the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • corresponding portions of the active layer provided below the data lines in a display area are hollowed out (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) by using the patterning process firstly, thus active tail below the data lines can be avoided when forming the pattern of the active layer and the pattern of the signal line metal layer simultaneously using a half-tone mask process, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ratio due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as the portions of the active layer below the data lines are hollowed out, the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image.
  • the manner in which the first region of the active layer is hollowed out is not limited, and may be any manner well known to a person skilled in the art. To facilitate a person skilled in the art to understand, a method for manufacturing an array substrate in the embodiment will be described in detail below.
  • the method for manufacturing an array substrate in the embodiment will be described by taking a TN-mode array substrate as an example, as shown in FIG. 3 , the method specifically comprises:
  • Step 101 forming a gate metal layer on a substrate, wherein the gate metal layer comprises gate lines.
  • the gate metal layer including gates, gate lines and other functional pattern is formed on the substrate through depositing, coating photoresist, exposure, development, etching, peeling off and the like (i.e., the first MASK).
  • Step 102 forming a gate insulation layer and film-forming an active layer.
  • the gate insulation layer and the active layer are sequentially deposited on the substrate.
  • a first region of the active layer is hollowed out through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • an etching groove is formed at the first region, as shown in FIG. 5 , the first region 10 is below the data lines 6 in the display area, and the first region 10 does not include portions of the active layer corresponding to overlapping regions of the data lines 6 and the gate lines 8 . As shown in FIG. 5 , the first region 10 is indicated by frames of dotted lines.
  • the display area refers to the effective viewing portion of a display, and does not include the non-pixel regions at edges of the array substrate.
  • the method further comprises a step of forming a gate insulation layer above the gate metal layer and under the active layer, wherein portions of the gate insulation layer corresponding to the first region is hollowed out through the patterning process, in addition to hollowing out the first region of the active layer.
  • the gate insulation layer is under the active layer, and in order to reduce the segment difference at the data lines, reduce the chance of occurrence of Rubbing Mura, and improve the yield and quality of image, preferably, in this step, in addition to hollowing out the first region of the active layer, portions of the gate insulation layer corresponding to the first region are also hollowed out; also, depending on actual requirements (mainly to reduce the segment difference), persons skilled in the art can determine portions of the gate insulation layer corresponding to the first region are removed completely or just thinned.
  • Step 104 film-forming a signal line metal layer, in the step, a metal film layer is first deposited so as to form the signal line metal layer.
  • Step 105 a pattern of the active layer and a pattern of the signal line metal layer are simultaneously formed through a half-tone mask process, and this step corresponds to a third MASK.
  • the pattern of the active layer and the pattern of the signal line metal layer are simultaneously formed through the half-tone mask process, that is, through a single exposure, the pattern of the active layer and the pattern of the signal line metal layer are formed by respective etching methods, and meanwhile, a channel of a thin film transistor (TFT) is formed.
  • TFT thin film transistor
  • region A-A′ denotes the first region 10 , as portions of the active layer and the gate insulation layer corresponding to the first region are hollowed out (the gate metal layer is also removed here), the data line 6 at the first region 10 is directly formed on the substrate 7 .
  • the pattern of the signal line metal layer formed in the step comprises a source and a drain of the TFT, the data line and functional leads for function regions at edges of the array substrate (GOA unit), and the pattern of the active layer formed in this step mainly comprises the channel of the TFT.
  • Step 106 forming a passivation layer to cover above mentioned patterns, and forming a plurality of through holes by coating photoresist, exposure, etching and peeling off (the fourth MASK).
  • the formed through holes penetrate through the passivation layer, and are arranged above the source of the TFT and in the bonding areas of the array substrate for various leads, and through these through holes the subsequently formed pixel electrode is connected to the source of the TFT and the various leads of the array substrate are connected to the bonding areas for connecting with the outside.
  • Step 107 forming a pixel electrode which is connected to the source of the TFT.
  • the pixel electrode is formed through depositing, coating photoresist, exposure, etching and peeling off (the fifth MASK); and covering the through holes formed in the bonding areas of the array substrate in the step 106 to protect exposed wires below the through holes.
  • ADS Advanced-Super Dimensional Switching
  • a multi-dimensional electric field is formed by a parallel electric field generated at edges of slit electrodes (one of the pixel electrode and the common electrode is a slit electrode, and the other thereof is a plate-like electrode) which are in the same plane and a vertical electric field generated between a slit electrodes and a plate-like electrodes, so that liquid crystal molecules at all orientations which are located between the slit electrodes or directly above the electrodes in a liquid crystal cell can be rotated, thus the efficiency of the plane orientation system liquid crystal is improved and the transmittance is increased.
  • ADS technology can improve the image quality of the TFT-LCD, and can bring out advantages of high transmittance, wide viewing angle, high aperture ratio, small chromatic aberration, high response speed, and free of push Mura and the like.
  • the embodiment also provides a method for manufacturing an ADS-mode array substrate, wherein the steps 201 to 205 are substantially the same as steps 101 to 105 in FIG. 3 , and differences therebetween are in that, in the method for manufacturing an ADS-mode array substrate, a step 206 is performed firstly to form a pixel electrode, and then a step 207 is performed to form a passivation layer, and finally a common electrode is formed in a step 208 .
  • the common electrode is formed through depositing, coating photoresist, exposure, development, etching and peeling off (the sixth MASK).
  • FIGS. 5 , 6 and 7 A specific structure of the ADS-mode array substrate is shown in FIGS. 5 , 6 and 7 . Furthermore, as the ADS-mode display panel and the TN-mode display panel are different in structure, the mask plate used in the steps 205 , 206 , 207 and 208 are different and thus the formed patterns are also different, and these differences do not directly relate to the invention, so the description thereof will be omitted.
  • the TN-mode array substrate is manufactured through 5 MASKs, or the ADS-mode array substrate is manufactured through 6 MASKs, and there is no active tail below the data line 6 in the display area, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio.
  • the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • an array substrate provided with a GOA (Gate On Array, i.e. a gate driver integrated on the array substrate) unit at edges thereof it is required to provide gate-insulation-layer through holes penetrating through the gate insulation layer and the active layer at bonding areas at edges so as to obtain conduction between the gate metal layer and the signal line metal layer for meeting special peripheral requirements (requirements for interior design of the GOA unit, which mainly refer to requirements for connecting with the gate lines), for example, connecting various leads in the gate metal layer with the gate lines, and connecting the GOA unit with the gate lines.
  • GOA Gate On Array
  • the gate-insulation-layer through holes are formed.
  • the step 103 (or the step 203 ) and the step of forming the gate-insulation-layer through holes may be performed simultaneously. Specifically, in the solution, as shown in FIGS.
  • FIG. 5 is a plane structure diagram of the array substrate
  • FIG. 6 is a cross-sectional diagram of the structure of the array substrate in FIG. 5 taken along line B-B′, to illustrate the structure of layers at the first region 10 below the data line 6 .
  • FIG. 7 is a cross-sectional diagram of the structure of the array substrate in FIG. 5 taken along line C-C′, to illustrate the structure of layers at the gate-insulation-layer through hole 9 provided at the edge of the array substrate, wherein the gate metal layer 12 is connected to the signal line metal layer 11 , and the gate metal layer 12 and the signal line metal layer 11 at this position may function as a gate lead and a gate line respectively, and they are connected to each other through the gate-insulation-layer through hole 9 .
  • the portions of the gate insulation layer and the active layer below the data line (at the first region) are removed while the gate-insulation-layer through holes are formed, without adding an extra process, and there is no active tail below the formed data line in the array substrate, therefore, the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • the embodiment of the invention provides an array substrate, as shown in FIGS. 5 , 6 and 7 , which comprises thin film transistors, and data lines 6 and gate lines 8 provided crossly, a pattern of a layer where the data lines 6 are located and a pattern of an active layer 5 of the thin film transistors are formed simultaneously by using a half-tone mask process, wherein corresponding portions of the active layer 5 provided below the data lines 6 in a display area, except portions of the active layer 5 corresponding to overlapping regions of the data lines 6 and the gate lines 8 , are hollowed out, that is, the portions of the active layer 5 at the first region 10 are removed.
  • the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio.
  • the segment difference at the data lines can be decreased, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • the above thin film transistor further comprises: a gate insulation layer 4 , which is provided below the active layer 5 and above a layer where the gate lines 8 are located (i.e., the gate metal layer 12 ), preferably, in the embodiment, corresponding portions of the gate insulation layer provided below the data lines 6 in a display area, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines, are also hollowed out, that is, the portions of the gate insulation layer 4 at the first region 10 are removed.
  • a gate insulation layer 4 which is provided below the active layer 5 and above a layer where the gate lines 8 are located (i.e., the gate metal layer 12 ), preferably, in the embodiment, corresponding portions of the gate insulation layer provided below the data lines 6 in a display area, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines, are also hollowed out, that is, the portions of the gate insulation layer 4 at the first region 10 are removed.
  • the portions of the gate insulation layer and the active layer below the data lines (at the first region) are removed while the gate-insulation-layer through holes are formed, without adding an extra process, and there is no active tail below the formed data line in the array substrate,
  • the array substrate in the invention In the array substrate in the invention, corresponding portions of the active layer below the data lines in a display area (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) are removed, thus there is no active tail below the data line, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as a portion of the active layer below the data line is hollowed out, the segment difference at the data line can be decreased, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • the embodiment further provides a display device, which comprises any one of above array substrates.
  • a display device which comprises any one of above array substrates.
  • the display device may be a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a pad, a TV, a display, a notebook computer, a digital frame, a navigator and any product or part which is provided with display function.
  • each is described in a progressive manner, like or similar parts between the embodiments may be referred to each other, and each embodiment mainly describes the difference from others.
  • the device embodiment as it is substantially similar to the method embodiment, thus it is described briefly, corresponding parts may referred to those of the method embodiment.

Abstract

Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.

Description

    FIELD OF THE INVENTION
  • The invention relates to the field of display technology, in particular, to an array substrate and a method for manufacturing the same, and a display device.
    • BACKGROUND OF THE INVENTION
  • Liquid crystal displays have widely replaced the traditional CRT display devices because of its small volume, light weight, low power consumption, low voltage and no radiation and the like, and have been used in life and work.
  • A liquid crystal display is formed by aligning and assembling an array substrate and a color filter substrate, as shown in FIG. 1 and FIG. 2. FIG. 1 shows a plane structure of an array substrate in the prior art, and FIG. 2 is a cross-sectional diagram of the structure of the array substrate in FIG. 1 taken along line B-B′. As shown in FIG. 1 and FIG. 2, on a substrate 7, a gate metal layer (including a gate and gate line 8 in FIG. 1), a gate insulation layer 4, an active layer 5, a signal line metal layer, a pixel electrode layer, a passivation layer 2 and a common electrode layer are sequentially formed, wherein the signal line metal layer comprises a source and a drain of a thin film transistor, and data line 6 in the drawings, the pixel electrode layer comprises a pixel electrode 1 in FIG. 1, and the common electrode layer comprises a common electrode 3 in FIG. 2. Patterns of the active layer 5 and the signal line metal layer may be formed by using a half-tone mask process, as difference in difficulties in etching the active layer 5 and the signal line metal layer due to their difference in material, active tail phenomenon often occurs. For example, as shown in FIG. 2, active tail phenomenon occurs at edges of the active layer below the data line 6 in the display area (see the region A in FIG. 2). Usually, in order to avoid the occurrence of short circuit and signal interference, the pixel electrode 1 is required to be away from data line 6 as far as possible, however, as the existence of active tail (i.e., region A in FIG. 2), the existence of active tail must be taken into account during designing the distance between the pixel electrode 1 and the data line 6, which results in that the transmittance area of the pixel is decreased, and the aperture ratio is decreased.
    • SUMMARY OF THE INVENTION
  • Embodiments of the invention provide an array substrate and a method for manufacturing the same, and a display device, which can solve the problem that the aperture ratio is decreased due to the active tail.
  • In order to achieve the above object, embodiments of the invention adopt following solutions:
  • A method for manufacturing an array substrate comprises: a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines; a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after the step of film-forming the active layer and before the step of film-forming the signal line metal layer, the method further comprises a step of:
  • hollowing out a first region of the active layer through a patterning process,
  • wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • the method further comprises steps of:
  • forming a gate insulation layer above the gate metal layer and under the active layer; and
  • hollowing out portions of the gate insulation layer corresponding to the first region through the patterning process.
  • Preferably, the method further comprises a step of:
  • forming a plurality of gate-insulation-layer through holes simultaneously by using the patterning process, wherein the gate-insulation-layer through holes are provided at edges of the array substrate and penetrate through the gate insulation layer and the active layer.
  • Embodiments of the invention provide an array substrate comprising thin film transistors, and data lines and gate lines provided crossly, a pattern of a layer where the data lines are located and a pattern of an active layer of the thin film transistors are formed simultaneously by using a half-tone mask process, wherein
  • portions of the active layer provided below the data lines in a display area are hollowed out, except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • Preferably, the thin film transistor further comprises: a gate insulation layer, which is provided below the active layer and above a layer where the gate lines are located, wherein
  • portions of the gate insulation layer provided below the data lines in a display area are hollowed out, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines.
  • Furthermore, the array substrate is further provided with a plurality of gate-insulation-layer through holes penetrating through the gate insulation layer and the active layer at edges thereof.
  • Embodiments of the invention further provide a display device, which comprises any one of the above array substrates.
  • In the array substrate and the method for manufacturing the same, and the display device, before film-forming the signal line metal layer, corresponding portions of the active layer provided below the data lines in a display area are hollowed out (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) by using the patterning process firstly, thus active tail below the data lines can be avoided when forming the pattern of the active layer and the pattern of the signal line metal layer simultaneously using a half-tone mask process, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ratio due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as the portions of the active layer below the data lines are hollowed out, the segment difference at the data lines can be reduced, thus the chance of Rubbing Mura (thin stripe-like defects formed on the panel due to the rubbing alignment process performed on an alignment film) is reduced, which can help to improve the yield and quality of image.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • To clearly describe embodiments of the invention, hereinafter, drawings used for describing the embodiments will be briefly introduced, apparently, the following drawings are just some embodiments of the invention, the persons skilled in the art can obtain other drawings from these drawings without creative efforts.
  • FIG. 1 is a plane structural diagram of an array substrate in the prior art.
  • FIG. 2 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 1 taken along line B-B′.
  • FIG. 3 is a flowchart of a method for manufacturing a TN-mode array substrate in embodiment 1 of the invention.
  • FIG. 4 is a flowchart of a method for manufacturing an ADS-mode array substrate in embodiment 1 of the invention.
  • FIG. 5 is a plane structural diagram of an array substrate in embodiment 2 of the invention.
  • FIG. 6 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 5 taken along line B-B′.
  • FIG. 7 is a cross-sectional diagram of the structure of the array substrate shown in FIG. 5 taken along line C-C′.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Embodiments of the invention provide an array substrate and a method for manufacturing the same, and a display device, which can solve the problem of the decreased aperture ratio due to the active tail.
  • Solutions in the invention will be described thoroughly and completely below in conjunction with the drawings in the embodiments of the invention.
    • Embodiment 1
  • The embodiment provides a method for manufacturing an array substrate, which comprises: a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines; a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after the step of film-forming the active layer and before the step of film-forming the signal line metal layer, the method further comprises a step of:
  • hollowing out a first region of the active layer through a patterning process,
  • wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • In the method for manufacturing the array substrate, after film-forming the active layer and before film-forming the signal line metal layer, corresponding portions of the active layer provided below the data lines in a display area are hollowed out (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) by using the patterning process firstly, thus active tail below the data lines can be avoided when forming the pattern of the active layer and the pattern of the signal line metal layer simultaneously using a half-tone mask process, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ratio due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as the portions of the active layer below the data lines are hollowed out, the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image.
  • In the embodiment, the manner in which the first region of the active layer is hollowed out is not limited, and may be any manner well known to a person skilled in the art. To facilitate a person skilled in the art to understand, a method for manufacturing an array substrate in the embodiment will be described in detail below.
  • The method for manufacturing an array substrate in the embodiment will be described by taking a TN-mode array substrate as an example, as shown in FIG. 3, the method specifically comprises:
  • Step 101, forming a gate metal layer on a substrate, wherein the gate metal layer comprises gate lines.
  • In the step, the gate metal layer including gates, gate lines and other functional pattern is formed on the substrate through depositing, coating photoresist, exposure, development, etching, peeling off and the like (i.e., the first MASK).
  • Step 102, forming a gate insulation layer and film-forming an active layer.
  • In the step, the gate insulation layer and the active layer are sequentially deposited on the substrate.
  • step 103, a first region of the active layer is hollowed out through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
  • In the step, through depositing, coating photoresist, exposure, development, etching, peeling off and the like (i.e., the second MASK), an etching groove is formed at the first region, as shown in FIG. 5, the first region 10 is below the data lines 6 in the display area, and the first region 10 does not include portions of the active layer corresponding to overlapping regions of the data lines 6 and the gate lines 8. As shown in FIG. 5, the first region 10 is indicated by frames of dotted lines. Herein, the display area refers to the effective viewing portion of a display, and does not include the non-pixel regions at edges of the array substrate.
  • The method further comprises a step of forming a gate insulation layer above the gate metal layer and under the active layer, wherein portions of the gate insulation layer corresponding to the first region is hollowed out through the patterning process, in addition to hollowing out the first region of the active layer.
  • Specifically, the gate insulation layer is under the active layer, and in order to reduce the segment difference at the data lines, reduce the chance of occurrence of Rubbing Mura, and improve the yield and quality of image, preferably, in this step, in addition to hollowing out the first region of the active layer, portions of the gate insulation layer corresponding to the first region are also hollowed out; also, depending on actual requirements (mainly to reduce the segment difference), persons skilled in the art can determine portions of the gate insulation layer corresponding to the first region are removed completely or just thinned.
  • Step 104, film-forming a signal line metal layer, in the step, a metal film layer is first deposited so as to form the signal line metal layer.
  • Step 105, a pattern of the active layer and a pattern of the signal line metal layer are simultaneously formed through a half-tone mask process, and this step corresponds to a third MASK.
  • In the step, the pattern of the active layer and the pattern of the signal line metal layer are simultaneously formed through the half-tone mask process, that is, through a single exposure, the pattern of the active layer and the pattern of the signal line metal layer are formed by respective etching methods, and meanwhile, a channel of a thin film transistor (TFT) is formed. At this time, there is no active tail under the data line 6, as shown in FIG. 6. With reference to FIG. 6, region A-A′ denotes the first region 10, as portions of the active layer and the gate insulation layer corresponding to the first region are hollowed out (the gate metal layer is also removed here), the data line 6 at the first region 10 is directly formed on the substrate 7.
  • The pattern of the signal line metal layer formed in the step comprises a source and a drain of the TFT, the data line and functional leads for function regions at edges of the array substrate (GOA unit), and the pattern of the active layer formed in this step mainly comprises the channel of the TFT.
  • Step 106, forming a passivation layer to cover above mentioned patterns, and forming a plurality of through holes by coating photoresist, exposure, etching and peeling off (the fourth MASK). The formed through holes penetrate through the passivation layer, and are arranged above the source of the TFT and in the bonding areas of the array substrate for various leads, and through these through holes the subsequently formed pixel electrode is connected to the source of the TFT and the various leads of the array substrate are connected to the bonding areas for connecting with the outside.
  • Step 107, forming a pixel electrode which is connected to the source of the TFT. In this step, the pixel electrode is formed through depositing, coating photoresist, exposure, etching and peeling off (the fifth MASK); and covering the through holes formed in the bonding areas of the array substrate in the step 106 to protect exposed wires below the through holes.
  • The above embodiment of the invention has been described by taking a TN-mode liquid crystal display panel as an example. There is also an ADS (Advanced-Super Dimensional Switching)-mode liquid crystal display panel, wherein a multi-dimensional electric field is formed by a parallel electric field generated at edges of slit electrodes (one of the pixel electrode and the common electrode is a slit electrode, and the other thereof is a plate-like electrode) which are in the same plane and a vertical electric field generated between a slit electrodes and a plate-like electrodes, so that liquid crystal molecules at all orientations which are located between the slit electrodes or directly above the electrodes in a liquid crystal cell can be rotated, thus the efficiency of the plane orientation system liquid crystal is improved and the transmittance is increased. ADS technology can improve the image quality of the TFT-LCD, and can bring out advantages of high transmittance, wide viewing angle, high aperture ratio, small chromatic aberration, high response speed, and free of push Mura and the like.
  • As shown in FIG. 4, the embodiment also provides a method for manufacturing an ADS-mode array substrate, wherein the steps 201 to 205 are substantially the same as steps 101 to 105 in FIG. 3, and differences therebetween are in that, in the method for manufacturing an ADS-mode array substrate, a step 206 is performed firstly to form a pixel electrode, and then a step 207 is performed to form a passivation layer, and finally a common electrode is formed in a step 208. In the step 208, the common electrode is formed through depositing, coating photoresist, exposure, development, etching and peeling off (the sixth MASK).
  • A specific structure of the ADS-mode array substrate is shown in FIGS. 5, 6 and 7. Furthermore, as the ADS-mode display panel and the TN-mode display panel are different in structure, the mask plate used in the steps 205, 206, 207 and 208 are different and thus the formed patterns are also different, and these differences do not directly relate to the invention, so the description thereof will be omitted.
  • It can seen from above, in the method for manufacturing the array substrate described in the embodiment, the TN-mode array substrate is manufactured through 5 MASKs, or the ADS-mode array substrate is manufactured through 6 MASKs, and there is no active tail below the data line 6 in the display area, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as portions of the active layer below the data lines are hollowed out, the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • In addition, as to an array substrate provided with a GOA (Gate On Array, i.e. a gate driver integrated on the array substrate) unit at edges thereof, it is required to provide gate-insulation-layer through holes penetrating through the gate insulation layer and the active layer at bonding areas at edges so as to obtain conduction between the gate metal layer and the signal line metal layer for meeting special peripheral requirements (requirements for interior design of the GOA unit, which mainly refer to requirements for connecting with the gate lines), for example, connecting various leads in the gate metal layer with the gate lines, and connecting the GOA unit with the gate lines.
  • In the prior art, after the step of film-forming the active layer and before the step of film-forming the signal line metal layer, the gate-insulation-layer through holes are formed. Preferably, the step 103 (or the step 203) and the step of forming the gate-insulation-layer through holes may be performed simultaneously. Specifically, in the solution, as shown in FIGS. 5, 6 and 7, in the display area, portions of the active layer and the gate insulation layer corresponding to the first region 10 are hollowed out, while a plurality of gate-insulation-layer through holes 9 are formed at edges (non-display area) of the array substrate, in other words, through the above single patterning process, the gate-insulation-layer through holes 9 are formed at edges of the array substrate to penetrate through the gate insulation layer and the active layer. For example, FIG. 5 is a plane structure diagram of the array substrate, and FIG. 6 is a cross-sectional diagram of the structure of the array substrate in FIG. 5 taken along line B-B′, to illustrate the structure of layers at the first region 10 below the data line 6. The portions of the active layer and the gate insulation layer 4 at the first region 10 are hollowed out (the portions of the gate metal layer here are also removed in the step 101 or step 201), so that the data line 6 at the first region 10 is directly provided on the substrate 7. FIG. 7 is a cross-sectional diagram of the structure of the array substrate in FIG. 5 taken along line C-C′, to illustrate the structure of layers at the gate-insulation-layer through hole 9 provided at the edge of the array substrate, wherein the gate metal layer 12 is connected to the signal line metal layer 11, and the gate metal layer 12 and the signal line metal layer 11 at this position may function as a gate lead and a gate line respectively, and they are connected to each other through the gate-insulation-layer through hole 9.
  • In the above method for manufacturing an array substrate, the portions of the gate insulation layer and the active layer below the data line (at the first region) are removed while the gate-insulation-layer through holes are formed, without adding an extra process, and there is no active tail below the formed data line in the array substrate, therefore, the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, the segment difference at the data lines can be reduced, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
    • Embodiment 2
  • The embodiment of the invention provides an array substrate, as shown in FIGS. 5, 6 and 7, which comprises thin film transistors, and data lines 6 and gate lines 8 provided crossly, a pattern of a layer where the data lines 6 are located and a pattern of an active layer 5 of the thin film transistors are formed simultaneously by using a half-tone mask process, wherein corresponding portions of the active layer 5 provided below the data lines 6 in a display area, except portions of the active layer 5 corresponding to overlapping regions of the data lines 6 and the gate lines 8, are hollowed out, that is, the portions of the active layer 5 at the first region 10 are removed.
  • In the array substrate in the embodiment, there is no active tail below the formed data line in the array substrate, therefore, the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, the segment difference at the data lines can be decreased, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • The above thin film transistor further comprises: a gate insulation layer 4, which is provided below the active layer 5 and above a layer where the gate lines 8 are located (i.e., the gate metal layer 12), preferably, in the embodiment, corresponding portions of the gate insulation layer provided below the data lines 6 in a display area, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines, are also hollowed out, that is, the portions of the gate insulation layer 4 at the first region 10 are removed.
  • Thus, in manufacturing the above array substrate, the portions of the gate insulation layer and the active layer below the data lines (at the first region) are removed while the gate-insulation-layer through holes are formed, without adding an extra process, and there is no active tail below the formed data line in the array substrate,
  • In the array substrate in the invention, corresponding portions of the active layer below the data lines in a display area (except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines) are removed, thus there is no active tail below the data line, therefore, the distance between the pixel electrode and the data line may be further reduced, and hence the problem of decreased aperture ration due to the active tail can be solved so as to obtain a high aperture ratio. Meanwhile, as a portion of the active layer below the data line is hollowed out, the segment difference at the data line can be decreased, thus the chance of occurrence of Rubbing Mura is reduced, which can help to improve the yield and quality of image and reduce cost.
  • The embodiment further provides a display device, which comprises any one of above array substrates. With the display device, a higher aperture ratio can be obtained, and the yield and quality of image can be improved. The display device may be a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a pad, a TV, a display, a notebook computer, a digital frame, a navigator and any product or part which is provided with display function.
  • The embodiments of the invention each is described in a progressive manner, like or similar parts between the embodiments may be referred to each other, and each embodiment mainly describes the difference from others. Especially, as to the device embodiment, as it is substantially similar to the method embodiment, thus it is described briefly, corresponding parts may referred to those of the method embodiment.
  • The above are only specific embodiments of the present invention, but the protection scope of the invention is not limited thereto, and persons skilled in the art will readily conceive various modifications or substitutes within the technical range disclosed in the invention, which should fall within the protection scope of the invention. Therefore, the protection scope of the invention should be defined by the claims.

Claims (9)

1. A method for manufacturing an array substrate comprising: a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines; a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after the step of film-forming an active layer and before the step of film-forming a signal line metal layer, the method further comprises a step of:
hollowing out a first region of the active layer through a patterning process,
wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
2. The method of claim 1, wherein further comprising steps of:
forming a gate insulation layer above the gate metal layer and under the active layer; and
hollowing out portions of the gate insulation layer corresponding to the first region through the patterning process.
3. The method of claim 2, wherein further comprising a step of:
forming a plurality of gate-insulation-layer through holes simultaneously by using the patterning process, wherein the gate-insulation-layer through holes are provided at edges of the array substrate and penetrate through the gate insulation layer and the active layer.
4. An array substrate comprising thin film transistors, and data lines and gate lines provided crossly, a pattern of a layer where the data lines are located and a pattern of an active layer of the thin film transistors are formed simultaneously by using a half-tone mask process, wherein
portions of the active layer provided below the data lines in a display area are hollowed out, except portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.
5. The array substrate of claim 4, wherein the thin film transistor further comprises: a gate insulation layer, which is provided below the active layer and above a layer where the gate lines are located, wherein
portions of the gate insulation layer provided below the data lines in a display area are hollowed out, except portions of the gate insulation layer corresponding to overlapping regions of the data lines and the gate lines.
6. The array substrate of claim 5, wherein the array substrate is further provide with a plurality of gate-insulation-layer through holes penetrating through the gate insulation layer and the active layer at edges thereof.
7. A display device comprising the array substrate of claim 4.
8. A display device comprising the array substrate of claim 5.
9. A display device comprising the array substrate of claim 6.
US14/498,066 2014-04-30 2014-09-26 Array substrate and method for manufacturing the same, and display device Expired - Fee Related US9196631B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201410183494 2014-04-30
CN201410183494.1A CN103985671B (en) 2014-04-30 2014-04-30 Array base palte preparation method and array base palte, display device
CN201410183494.1 2014-04-30

Publications (2)

Publication Number Publication Date
US20150318310A1 true US20150318310A1 (en) 2015-11-05
US9196631B1 US9196631B1 (en) 2015-11-24

Family

ID=51277588

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/498,066 Expired - Fee Related US9196631B1 (en) 2014-04-30 2014-09-26 Array substrate and method for manufacturing the same, and display device

Country Status (2)

Country Link
US (1) US9196631B1 (en)
CN (1) CN103985671B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870008A (en) * 2016-04-18 2016-08-17 武汉华星光电技术有限公司 Etching equipment and etching method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362152B (en) * 2014-09-16 2017-08-01 京东方科技集团股份有限公司 A kind of preparation method of array base palte
CN109541885A (en) * 2019-01-14 2019-03-29 京东方科技集团股份有限公司 Joining method, nano impression plate, grating and the production method of nano-pattern

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW478014B (en) * 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
TWI287132B (en) * 2001-11-23 2007-09-21 Chi Mei Optoelectronics Corp A liquid crystal display having reduced flicker
KR101107981B1 (en) * 2004-09-03 2012-01-25 삼성전자주식회사 Substrate for Diaplay Apparatus, Liquid Crystal Display Apparatus And Method of Manufacturing The Same
CN100466266C (en) * 2006-04-21 2009-03-04 北京京东方光电科技有限公司 A TFT LCD array base plate and manufacture method
JP4740203B2 (en) * 2006-08-04 2011-08-03 北京京東方光電科技有限公司 Thin film transistor LCD pixel unit and manufacturing method thereof
CN101630098B (en) * 2008-07-18 2010-12-08 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacturing method thereof
CN102456620B (en) * 2010-10-22 2015-04-15 北京京东方光电科技有限公司 Array substrate and manufacturing method thereof
KR101258903B1 (en) * 2012-02-24 2013-04-29 엘지디스플레이 주식회사 Liquid crystal display device and the method of fabricating thereof
CN103066017A (en) * 2012-12-28 2013-04-24 北京京东方光电科技有限公司 Preparing method of array substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870008A (en) * 2016-04-18 2016-08-17 武汉华星光电技术有限公司 Etching equipment and etching method

Also Published As

Publication number Publication date
CN103985671A (en) 2014-08-13
CN103985671B (en) 2016-06-15
US9196631B1 (en) 2015-11-24

Similar Documents

Publication Publication Date Title
US9368520B2 (en) Array substrate, manufacturing method thereof and display device
US9437619B2 (en) Array substrate, manufacturing method thereof and display device
US8643799B2 (en) TFT-LCD array substrate and manufacturing method thereof
US9716110B2 (en) Array substrate, method for manufacturing the same, and display device
US9653492B2 (en) Array substrate, manufacturing method of array substrate and display device
US20190051667A1 (en) An array substrate and a manufacturing method thereof, a display panel, as well as a display device
US9893091B2 (en) Array substrate and fabricating method thereof, display panel and display apparatus
US10192894B2 (en) Thin film transistor and method of manufacturing the same, array substrate and display panel
US20150333182A1 (en) Method of fabricating array substrate, array substrate, and display device
US9905593B2 (en) Mask plate and method for manufacturing array substrate
US20160148954A1 (en) Manufacturing method of array substrate, array substrate and display device
US9798192B2 (en) Display substrate and manufacturing method thereof, display panel and display device
WO2015000255A1 (en) Array substrate, display device, and method for manufacturing array substrate
US9305945B2 (en) TFT array substrate, manufacturing method of the same and display device
US9791755B2 (en) Color filter-on-array substrate, display device, and method for manufacturing the color filter-on-array substrate
US9490266B2 (en) Array substrate and method for producing the same and display apparatus
US9690146B2 (en) Array substrate, its manufacturing method, and display device
US20140071553A1 (en) Color filter substrate, tft array substrate, manufacturing method of the same, and liquid crystal display panel
US9799683B2 (en) Array substrate, preparation method thereof and display device
US9196631B1 (en) Array substrate and method for manufacturing the same, and display device
US20170373099A1 (en) Array substrate, manufacturing method thereof and display device
US9653608B2 (en) Array substrate and manufacturing method thereof, display device and thin film transistor
US20180149934A1 (en) Array substrate and liquid crystal display panel
US9366932B2 (en) TFT-LCD array substrate manufacturing method and LCD panel/device produced by the same
KR102494509B1 (en) Display device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: BOE TECHNOLOGY GROUP CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHANG, WENYU;XIE, ZHENYU;GUO, JIAN;REEL/FRAME:033853/0036

Effective date: 20140912

Owner name: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHANG, WENYU;XIE, ZHENYU;GUO, JIAN;REEL/FRAME:033853/0036

Effective date: 20140912

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20231124