CN100466266C - A TFT LCD array base plate and manufacture method - Google Patents

A TFT LCD array base plate and manufacture method Download PDF

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CN100466266C
CN100466266C CNB2006100744587A CN200610074458A CN100466266C CN 100466266 C CN100466266 C CN 100466266C CN B2006100744587 A CNB2006100744587 A CN B2006100744587A CN 200610074458 A CN200610074458 A CN 200610074458A CN 100466266 C CN100466266 C CN 100466266C
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data wire
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CN101060124A (en
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邓朝勇
林承武
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Abstract

The related TFT LCD array substrate comprises: a glass substrate with grid wire and grid electrode, an insulation medium layer on the electrode, a semi-conductor layer, an ohmic contact layer, a transparent pixel electrode, a source/drain electrode, a sectional data line including the primary and connection parts, and a passive layer, wherein the primary part of data line is formed in the same photo etching as the grid line and electrode. Compared with 5Mask technique, this invention can reduce data line resistance, and eliminates the data signal RC-delay effect.

Description

A kind of TFT LCD array base palte and manufacture method
Technical field
The present invention relates to a kind of TFT LCD array base palte and manufacture method thereof, relate in particular to and a kind ofly can effectively reduce the TFT LCD array base palte of data wire resistance and the manufacture method of this substrate.
Background technology
Tft liquid crystal shows that (Thin Film Transistor Liquid CrystalDisplay is called for short TFT LCD) become a kind of important flat panel display mode for the liquid crystal display of representative.
The manufacturing technology of TFT LCD array base palte has experienced from the evolution of 7 photoetching techniques (7Mask), 5 photoetching techniques (5Mask) up till now, the 5Mask technology becomes the main manufacture methods of present TFT LCD array base palte, comprise gate electrode photoetching (Gate Mask), active layer photoetching (ActiveMask), source-drain electrode photoetching (S/D Mask), via hole photoetching (Via Hole Mask) and pixel electrode layer photoetching (Pixel Mask).In each Mask processing step, comprise one or many thin film deposition (Thin Film Deposition) technology and etching technics (comprising dry etching Dry Etch and wet etching Wet Etch) technology again respectively, formed the cyclic process of 5 thin film deposition → photoetching → etchings.
Gray tone photoetching (Gray Tone Mask) technology is to use the figure that has strip (Slit) on Mask, by the interference and the diffraction effect of light, forms translucent graphics field on Mask.In exposure process, light can only partly see through translucent area.By the control exposure, shine on the photoresist after can making light by the Gray Tone zone on the Mask, photoresist can only partly be exposed, and other parts can fully be exposed.After the development, complete exposure area does not have photoresist, and fully the thickness of exposed areas photoresist will be less than complete unexposed zone, thereby forms 3-D solid structure on photoresist.By the transmitance in control Gray Tone zone, i.e. " duty ratio " of lines zone and white space can be controlled the thickness of photoresist.Thereby thisly be collectively referred to as Gray Tone Mask technology in the method for using translucent graphic on photoresist, to form the different three-D pattern of thickness on the mask blank.The typical pixel cells of the resulting TFT LCD of the 5Mask technological process array base palte that process is above as shown in Figure 2.
In above-mentioned technology, the grid metal under the common situation all is to adopt the AlNd composite film layer by layer, and the source-drain electrode layer generally all adopts single Mo (or Cr) metal film.Along with the progress of society, people become more and more stronger to the demand of large-screen TFT LCD display, and this just requires TFT LCD manufacturer that increasing large-screen TFT LCD array base palte is provided.Because the continuous increase of substrate, grid line (Gate) and data wire (Data) will become more and more longer, and Gate line and Data line resistance will be increasing, and the quality problem of displaying that causes owing to reasons such as signal delays will manifest.The problem that solves the line resistance increase can adopt composite membrane to increase methods such as thickness or live width and be resolved by adopting the lower metal of resistivity usually.But the employing composite membrane, the method that increases thickness and live width often can bring cost to increase drawbacks such as aperture opening ratio reduction again.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, a kind of TFT LCD array base palte and manufacture method are provided.The major part of Data line and Gate line and Gate electrode are to form under the GateMask at same Mask, and promptly the major part of Data line adopts Gate layer metal; The Data line adopts segmented to make, and connects at S/D Mask by via hole, and this method is compared with common 5Mask technology, can effectively reduce the Data line resistance, alleviates or eliminates the adverse effect that Data signal RC delay brings.
To achieve these goals, the invention provides a kind of TFT LCD array base palte, comprise glass substrate, be formed at grid line and gate electrode on the glass substrate, be formed at insulating medium layer, semiconductor layer and ohmic contact layer on the gate electrode, the transparent pixels electrode, source-drain electrode and data wire, passivation layer, described data wire is segmentation structure, be divided into data wire major part and data wire coupling part, the data wire major part is the data wire part between adjacent grid line; The data wire coupling part is to stride across the data wire part that grid line connects adjacent data wire major part, and wherein, described Data line coupling part can be structure as a whole with the source electrode of source-drain electrode.
Described grid line, gate electrode and data wire major part can be the monofilm by AlNd, Al, Cu, Mo, MoW or Cr deposition, perhaps by the composite membrane that sedimentary deposit constituted of AlNd, Al, Cu, Mo, MoW and Cr combination in any.Described insulating medium layer can be the monofilm by SiNx, SiOx or SiOxNy deposition, perhaps by the composite membrane that sedimentary deposit constituted of SiNx, SiOx and SiOxNy combination in any.Described source-drain electrode, data wire coupling part are the monofilm by Mo, MoW or Cr deposition; Perhaps by the composite membrane that sedimentary deposit constituted of Mo, MoW and Cr combination in any.
The present invention also provides a kind of manufacture method of TFT LCD array base palte, may further comprise the steps:
Step 1, employing magnetron sputtering technique deposit a gate metal layer on substrate, carry out mask and etching then, obtain grid line, gate electrode and data wire major part;
Step 2, employing chemical vapour deposition technique deposit an insulating medium layer, an active layer and an ohmic contact layer successively on the substrate of completing steps one, adopt the gray tone mask plate to carry out mask and etching then, form the via hole part on film crystal tube portion and the data wire major part;
Step 3, employing magnetron sputtering technique deposit a source and leak metal level on the substrate of completing steps two, carry out source-drain layer mask and etching, and carry out the ohmic contact layer etching, form source-drain electrode, film crystal tube portion channel part and with the data wire coupling part of source electrode one; And the data wire coupling part is connected with the data wire major part by the via hole that step 2 forms;
Step 4, employing chemical vapour deposition technique deposit a passivation layer on the substrate of completing steps three, carry out passivation layer and mask and etching, form passivation layer via hole and raceway groove is formed protection;
Step 5, employing magnetron sputtering method deposit a transparent pixels electrode layer on the substrate of completing steps four, carry out transparent pixels electrode layer mask and etching, form the transparent pixels electrode.
Wherein, when adopting the gray tone mask plate to carry out the active layer mask in the described step 2, making via hole part mask plate is complete light transmission part, and active layer part mask plate is complete lightproof part, and the other parts mask plate is semi-transparent part.Gate metal layer described in the step 1 adopts AlNd, Al, Cu, Mo, MoW or Cr to deposit; Perhaps adopt AlNd, Al, Cu, Mo, MoW and Cr combination in any layer to deposit.Insulating barrier of deposition described in the step 2 can be specially: the monofilm of deposition SiNx, SiOx or SiOxNy; Perhaps for depositing the composite membrane of SiNx, SiOx and SiOxNy combination in any.Source described in the step 3 is leaked metal level and is adopted Mo, MoW or Cr to deposit; Perhaps adopt Mo, MoW and Cr combination in any layer to deposit.
The major part of the Data line of TFT LCD array base palte of the present invention and Gate line and Gate electrode are to form under the Gate Mask at same Mask, and promptly the major part of Data line adopts Gate layer metal; The Data line adopts segmented to make, and connects at S/D Mask by via hole, and this method is compared with common 5Mask technology, can effectively reduce the Data line resistance, alleviates or eliminates the adverse effect that Data signal RC delay brings.
Description of drawings
Fig. 1 is five photoetching manufacturing method flow charts of existing TFT LCD array base palte;
Fig. 2 is the typical pixel cells plane graph of TFT LCD array base palte;
Fig. 3 is a TFT LCD manufacturing method of array base plate flow chart of the present invention;
Fig. 4 is the plane graph through the substrate that obtains behind the Gate Mask;
Fig. 5 is the A-A sectional view of Fig. 4;
Fig. 6 is the plane graph through the substrate that obtains behind the Act.Mask;
Fig. 7 is the A-A sectional view of Fig. 6;
Fig. 8 is the plane graph through obtaining behind the S/D Mask;
Fig. 9 is the A-A sectional view of Fig. 8;
Figure 10 is through resulting plane graph behind the Via Hole Mask
Figure 11 is through resulting plane graph behind the ITO Mask
Figure 12 is the A-A sectional view of Figure 11;
Figure 13 is the B-B sectional view of Figure 11.
Description of reference numerals:
1 substrate, 2 gate metal electrodes, 3 data wire major parts
31 data wire major part via holes, 32 data wire coupling parts
Metal electrode is leaked in 4 insulating medium layers, 5 active layers, 6 sources
7 passivation layers, 8 pixel electrodes
Embodiment
As shown in Figure 3, comprise the steps: for flow chart of the present invention
Step 1, at first last by sputtering method deposition Gate metal at clean glass substrate (Bare Glass), the Gate metal is the composite membrane that sedimentary deposit constituted by one of AlNd, Al, Cu, Mo, MoW or Cr or combination in any, for example: Mo/AlNd/Mo composite membrane, AlNd/Mo composite membrane; Then, carry out the Gate photoetching,, obtain structure as shown in Figure 4, along the A-A cross section as shown in Figure 5, promptly obtain grid line and gate electrode 2 through etching technics, and data wire major part 3.
Step 2, adopt chemical gaseous phase (PECVD) deposit multilayer (MultiLayer) on the substrate that step 1 forms, comprise one or more layers SiNx successively, SiOx, insulating medium layers such as SiOxNy, and a-Si active layer and ohmic contact layer, adopt gray tone (Gray Tone) technology to carry out gray tone active layer mask (G/T Act.Mask), the active layer of TFT partly blocks fully for panchromatic accent (Full Tone), the via portion of Data line major part is divided into exposure fully, remainder is the exposure of gray tone (Gray Tone) part, pass through etching technics then, obtain structure as shown in Figure 6 and Figure 7, promptly obtain the via hole 31 on thin film transistor active layer 5 and the Data line major part;
Step 3, on the basis of step 2, adopt magnetron sputtering technique deposition S/D metal (as by Mo, the monofilm that deposition such as MoW or Cr forms, or the composite membrane that constitutes of the sedimentary deposit of combination in any wherein), carry out the photoetching of S/D electrode, through etching technics, form source-drain electrode 6, film crystal tube portion channel part and with the Data line coupling part 32 of source electrode one; The S/D metal is connected with Data line major part by via hole, forms complete Data line and S/D electrode, and finishes the ohmic contact layer etching, obtains structure such as Fig. 8 and shown in Figure 9, and ohmic contact layer is expressed among the figure;
Step 4, on the substrate that step 3 forms, deposit passivation (Passivation) protective layer, carry out via hole (Via Hole) photoetching, and finish via hole (Via Hole) etching, and for being connected with the ITO pixel electrode, the S/D electrode prepares, and the structure that obtains is as shown in figure 10;
Step 5, pixel electrode (ITO) deposition of on the basis of step 4, carrying out, and, finally form the Pixel electrode, and be connected by via hole with the S/D metal electrode by ITO photoetching and ITO etching technics, form complete TFT pixel cell, as Figure 11, Figure 12 and Figure 13.
Because the major part 3 of Gate line 2 and Data line forms at same Mask, the major part 3 of the Data line that obtains so the Data line is is just connected and composed by two parts, is respectively Data line major part 3 and Data line coupling part 32 among the figure for the Gate metal.Adopt metals such as Mo or Cr to compare fully with traditional Data line, resulting Data line adopts mainly based on the Gate metal, can just can reduce the line resistance of Data line so greatly, reduces or eliminates the adverse effect that signal RC delay causes display quality.
The Gate line of TFT LCD array base palte of the present invention and the major part of Data line form at same Mask, make the major part of Data line adopt metal identical with the Gate line.Because the Gate line adopts the composite construction of AlNd usually, resistivity is far smaller than Mo or Cr, so this segmented Data line can reduce the resistance of Data line greatly; The manufacture method of TFT LCD array base palte of the present invention provides more choices for TFT LCD makes.
Below, describe a specific embodiment of the present invention in detail with reference to accompanying drawing.
1. employing magnetically controlled sputter method, sputtering sedimentation metal level Mo/AlNd/Mo successively, thickness is respectively 400/4000/
Figure C200610074458D00091
, carry out Gate Mask then, and carry out wet etching, form the major part 3 of Gate line and Gate electrode 2 and Data line, as shown in Figure 4 and Figure 5;
2. use the PECVD method, deposit SiNx/a-Si/n+a-Si successively, thickness is respectively
Figure C200610074458D00092
/
Figure C200610074458D00093
/
Figure C200610074458D00094
Adopt Gray Tone technology to carry out G/T Act.Mask, the layer segment of having chance with of TFT is that Full Tone blocks fully, the Data line connects via portion and is divided into exposure fully, remainder is that Gray Tone partly exposes, pass through etching technics then, and form the TFT part of SiNx/a-Si/n+a-Si and the via hole part 31 of Data line major part 3 with the method for reactive ion etching technology (RIE) dry etching, as Fig. 6 and Fig. 7;
3. employing magnetically controlled sputter method, plated metal Mo or Cr, thickness is
Figure C200610074458D00101
, and carry out S/D Mask and wet etching and ohmic contact layer etching, form Data line coupling part 32, and form S/D electrode and the TFT raceway groove of TFT; Data line coupling part 32 cross-over connection Data line major parts 3 are connected with Data line major part 3 by via hole, as Fig. 8 and Fig. 9 (ohmic contact layer of channel part is not expressed among the figure);
4. adopt PECVD to carry out passivation layer deposition, deposition SiNx, thickness is , and carry out Via Hole Mask and via hole dry etching, form via hole and raceway groove is formed protection, as shown in figure 10;
5. pass through magnetically controlled sputter method, deposition of transparent conductive film ITO, thickness
Figure C200610074458D00103
, and carry out ITOMask and ITO Etch, finally form the Pixel electrode, as Figure 11, Figure 12 and shown in Figure 13.
By the above manufacture method that is different from existing 5Mask technology, obtained complete tft array substrate, when reducing the Data line resistance, also provide a kind of TFT LCD manufacturing method of array base plate that is different from existing 5Mask technology.
Should be noted that at last: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit; Although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the field should be appreciated that still and can make amendment or the part technical characterictic is equal to replacement the specific embodiment of the present invention; And not breaking away from the spirit of technical solution of the present invention, it all should be encompassed in the middle of the technical scheme scope that the present invention asks for protection.

Claims (9)

1. TFT LCD array base palte, comprise glass substrate, be formed at grid line and gate electrode on the glass substrate, be formed at insulating medium layer, semiconductor layer and ohmic contact layer on the gate electrode, transparent pixels electrode, source-drain electrode and data wire, passivation layer, described data wire is segmentation structure, is divided into data wire major part and data wire coupling part, and the data wire major part is the data wire part between adjacent grid line; The data wire coupling part is to stride across the data wire part that grid line connects adjacent data wire major part, it is characterized in that the source electrode of described data wire coupling part and source-drain electrode is structure as a whole.
2. substrate according to claim 1, it is characterized in that, described grid line, gate electrode and data wire major part are the monofilm by AlNd, Al, Cu, Mo, MoW or Cr deposition, perhaps by the composite membrane that sedimentary deposit constituted of AlNd, Al, Cu, Mo, MoW and Cr combination in any.
3. substrate according to claim 1 is characterized in that, described insulating medium layer is the monofilm by SiNx, SiOx or SiOxNy deposition, perhaps by the composite membrane that sedimentary deposit constituted of SiNx, SiOx and SiOxNy combination in any.
4. substrate according to claim 1 is characterized in that, described source-drain electrode, data wire coupling part are the monofilm by Mo, MoW or Cr deposition; Perhaps by the composite membrane that sedimentary deposit constituted of Mo, MoW and Cr combination in any.
5. the manufacture method of a TFT LCD array base palte is characterized in that, this manufacture method may further comprise the steps:
Step 1, employing magnetron sputtering technique deposit a gate metal layer on substrate, carry out mask and etching then, obtain grid line, gate electrode and data wire major part;
Step 2, employing chemical vapour deposition technique deposit an insulating medium layer, an active layer and an ohmic contact layer successively on the substrate of completing steps one, adopt the gray tone mask plate to carry out mask and etching then, form the via hole part on film crystal tube portion and the data wire major part;
Step 3, employing magnetron sputtering technique deposit a source and leak metal level on the substrate of completing steps two, carry out source-drain layer mask and etching, and carry out the ohmic contact layer etching, form source-drain electrode, film crystal tube portion channel part and with the data wire coupling part of source electrode one; And the data wire coupling part is connected with the data wire major part by the via hole that step 2 forms;
Step 4, employing chemical vapour deposition technique deposit a passivation layer on the substrate of completing steps three, carry out passivation layer and mask and etching, form passivation layer via hole and raceway groove is formed protection;
Step 5, employing magnetron sputtering method deposit a transparent pixels electrode layer on the substrate of completing steps four, carry out transparent pixels electrode layer mask and etching, form the transparent pixels electrode.
6. manufacture method according to claim 5, it is characterized in that: adopt the gray tone mask plate to carry out the active layer mask in the described step 2 and be specially, making via hole part mask plate is complete light transmission part, active layer part mask plate is complete lightproof part, and the other parts mask plate is semi-transparent part.
7. according to claim 5 or 6 described manufacture methods, it is characterized in that: the gate metal layer described in the step 1 adopts AlNd, Al, Cu, Mo, MoW or Cr to deposit; Perhaps adopt Al Nd, Al, Cu, Mo, MoW and Cr combination in any layer to deposit.
8. according to claim 5 or 6 described manufacture methods, it is characterized in that: insulating barrier of the deposition in the described step 2 is specially: the monofilm of deposition SiNx, SiOx or SiOxNy; Perhaps for depositing the composite membrane of SiNx, SiOx and SiOxNy combination in any.
9. according to claim 5 or 6 described manufacture methods, it is characterized in that: the source described in the step 3 is leaked metal level and is adopted Mo, MoW or Cr to deposit; Perhaps adopt Mo, MoW and Cr combination in any layer to deposit.
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