CN101013709A - TFT array structure and manufacturing method thereof - Google Patents
TFT array structure and manufacturing method thereof Download PDFInfo
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- CN101013709A CN101013709A CN 200710063656 CN200710063656A CN101013709A CN 101013709 A CN101013709 A CN 101013709A CN 200710063656 CN200710063656 CN 200710063656 CN 200710063656 A CN200710063656 A CN 200710063656A CN 101013709 A CN101013709 A CN 101013709A
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Abstract
The invention discloses one TFT array structure, which comprises the following parts: one baseboard; one grating wire and electrode formed on baseboard covered with grating insulation layer; one source layer and Ohm contact layer; one data line and its source metal electrode formed on ohm contact layer; one leakage metal electrode formed on contact layer; one passive layer formed on data line, source metal and leakage electrode; one pass hole formed on source metal electrode; one pixel electrode on passive layer connected to leak metal electrode.
Description
Technical field
The present invention relates to a kind of active driving TFT (thin-film transistor) array structure and manufacture method thereof, particularly a kind of tft array structure and manufacture method thereof that reduces pixel electrode generation broken string.
Background technology
For price and its rate of finished products of raising of reducing Thin Film Transistor-LCD (TFT LCD) effectively, the manufacturing process of active driving TFT array progressively obtains simplifying, from seven times or six photoetching generally five photoetching of employing till now of beginning.Five times photoetching process has obtained large-scale application in different TFT LCD factory commercial cities, and its specific embodiment at first, forms grid line and gate electrode by the photoetching first time as shown in Figure 1; Follow successive sedimentation one deck gate insulation layer, active layer, ohmic contact layer on grid line and gate electrode, and form active layer and ohmic contact layer pattern by the photoetching second time; Then deposit one deck source again and leak metal level, form the source, leak metal electrode and data wire by photoetching for the third time; Deposit one deck passivation layer then, on passivation layer, form connecting hole by the 4th photoetching; Deposit the layer of transparent conductive layer at last and form pixel electrode by the 5th photoetching.
Figure 2 shows that the floor map of a pixel cell of tft array structure, on transparent glass substrate 11, be followed successively by gate electrode 12a and grid line 12b, gate insulation layer 13 and semiconductor layer 14.Source, leakage metal electrode 15b, 15a and data wire 15C are respectively formed on the semiconductor layer 14.Wherein passivation layer 17 is respectively formed at the source, leaks on metal electrode 15b, the 15a.Pixel electrode 18a is deposited on the passivation layer 17 and by via hole 17a and links to each other with leakage metal electrode 15a.
Though this five photoetching processes have developed very ripely at present, also there is certain defective in it.Leak metal level in the source through behind the wet etching, its cross section, edge may be for falling trapezoidal corner 15d, therefore be deposited on the pixel electrode on the passivation layer subsequently, around via hole 17a, locate to be very easy to break, the cross section at its A-A position in Fig. 2 as shown in Figure 3, cause generation of defects, influenced the rate of finished products of tft array.
Summary of the invention
The objective of the invention is the defective at prior art, tft array structure of a kind of improvement and preparation method thereof is provided, the trapezoid cross section of falling of metal level is leaked in the elimination source up hill and dale, reduces the generation of pixel electrode broken string in the tft array effectively.
To achieve these goals, the invention provides a kind of TFT matrix structure, comprising:
One substrate;
One grid line and with the gate electrode of its one, be formed on the described substrate, the top of grid line and gate electrode is coated with gate insulation layer;
One active layer and ohmic contact layer are formed on the gate insulation layer top;
One data wire reaches the source metal electrode with its one, is formed on the top of described ohmic contact layer;
One leaks metal electrode, is formed on the top of described ohmic contact layer;
One passivation layer, the top that is formed on described data wire, source metal electrode and leaks metal electrode;
One via hole is formed on the Lou top of metal electrode;
One pixel electrode is formed on the described passivation layer, and is connected with described leakage metal electrode by via hole;
Wherein, data wire and with the source metal electrode of its one, and the corner of leaking metal electrode be trapezoidal corner.
In the such scheme, described grid line, gate electrode, source metal electrode, data wire or to leak metal electrode be the monofilm of Cr, W, Ti, Ta, Mo, Al or Cu perhaps are one of Cr, W, Ti, Ta, Mo, Al or Cu or composite membrane that combination in any constituted.Described insulating barrier or passivation layer are oxide, nitride or oxynitrides.
To achieve these goals, the present invention also provides a kind of manufacture method of TFT matrix structure, comprising:
Step 2 deposits gate insulation layer, active layer and ohmic contact layer on completing steps 1 substrate, adopts second mask, carry out mask, exposure and etching after, form active layer and ohmic contact layer pattern;
Step 3, sedimentary origin leaks metal level on the substrate of completing steps 2, adopts the 3rd mask, carries out formation source after mask, exposure and the etching, leaks metal electrode and data wire figure; Then carry out the cineration technics of photoresist, source, leakage metal electrode and data wire are partly come out; The source that will expose by dry etching, leakage metal electrode and data wire etch away subsequently, thus the trapezoidal corner of formation source, leakage metal electrode and data wire; Carry out the etching of ohmic contact layer at last, form raceway groove;
Step 4, deposit passivation layer on completing steps 3 substrates adopts the 4th mask, carries out forming via pattern after mask, exposure and the etching;
Step 5, pixel deposition electrode layer on the substrate of completing steps 4 adopts the 5th mask, carries out forming the pixel electrode figure after mask, exposure and the etching, and pixel electrode links to each other with the leakage metal electrode by via hole.
In the such scheme, in the described step 3 the used gas of the cineration technics of photoresist be 02, gas such as SF6/02, C12/02 or CF4/02.The etching gas that dry etching adopts in the described step 3 is gases such as C12/02, SF6/02, CF4/02, CF4/C12/02 or SF6/C12/02.The dry etch process of photoresist ashing technology in the described step 3 and source, leakage metal electrode can be carried out continuously or substep carries out.
With respect to prior art, in the tft array manufacturing process that the present invention provides, leak in the source between the dry etching of the wet etching of metal level and ohmic contact layer, the cineration technics of photoresist and the dry etching that metal level is leaked in the source have been added, eliminate the trapezoid cross section of falling that metal level is leaked in the source up hill and dale, reduced the generation of pixel electrode broken string in the tft array effectively.
Tft array manufacturing process proposed by the invention is compared with 5 times traditional photoetching processes, only the dry etch process of metal level is leaked in cineration technics by having increased photoresist and source, just the trapezoidal sectional shape that metal level may form is leaked in the elimination source behind wet etching fully, and technology that this two step increases can carry out in same reative cell with the etching technics of ohmic contact layer, therefore can not bring any adverse influence to the production cycle of tft array.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 is 5 photolithography process figure of prior art;
Fig. 2 is the floor map of a pixel cell of tft array structure;
Fig. 3 is the sectional view at A-A position among Fig. 2;
Fig. 4 is 5 photolithography process figure of the present invention;
Fig. 5 is the sectional view at tft array structure A-A position in Fig. 2 among the present invention;
Fig. 6 is the sectional view that gate electrode among the present invention, gate insulation layer and active layer figure form A-A position in Fig. 2, back;
Fig. 7 is the sectional view that A-A position in Fig. 2 is leaked behind the metal level wet etching in the source among the present invention;
Fig. 8 be among the present invention after the photoresist ashing technology in Fig. 2 the sectional view at A-A position;
Fig. 9 is the sectional view that A-A position in Fig. 2 is leaked behind the metal level dry etching in the source among the present invention;
Figure 10 is the sectional view that ohmic contact layer carries out behind the dry etching A-A position in Fig. 2 among the present invention;
Figure 11 is the sectional view that via hole forms A-A position in Fig. 2, back among the present invention.
Mark among the figure: 11, transparent glass substrate; 12, grid metal level; 12a, grid metal electrode; 12b, grid line; 13, gate insulation layer; 14, semiconductor layer; 15a, leakage metal electrode; 15b, source metal electrode; 15c, data wire; 15d, fall trapezoidal corner; 15e, trapezoidal corner; 16, photoresist; 17, passivation layer; 17a, via hole; 18a, pixel electrode.
Embodiment
Fig. 4 is 5 photolithography process figure of the present invention.As shown in Figure 4, the concrete implementation procedure of five photoetching processes that the present invention proposes is: at first, form grid line and gate electrode by the photoetching first time and etching process, follow successive sedimentation one deck gate insulation layer on grid line and gate electrode, active layer, ohmic contact layer, and form active layer and ohmic contact layer pattern by the photoetching second time and etching technics, then deposit one deck source again and leak metal level, form the source by photoetching for the third time and etching process, leak metal electrode and data wire, and subsequently continuously or substep carry out the cineration technics of photoresist, the dry etch process of metal level and ohmic contact layer is leaked in the source, deposit one deck passivation layer then, on passivation layer, form connecting hole by the 4th photoetching, deposit the layer of transparent conductive layer at last and form pixel electrode by the 5th photoetching.
Above-mentioned technological process finish the tft array structure of the present invention that the back forms a pixel cell floor map as shown in Figure 2, Fig. 5 is the sectional view at tft array structure A-A position in Fig. 2 among the present invention.As Fig. 2 and shown in Figure 5, array structure of the present invention comprises: transparent glass substrate 11 forms gate electrode 12a and grid line 12b, gate insulation layer 13 and semiconductor layer 14 (comprising active layer and ohmic contact layer) successively on transparent glass substrate 11; Source, leakage metal electrode 15b, 15a and data wire 15c are respectively formed on the semiconductor layer 14; Grid line 12b and pixel region of data wire 15c intersection definition; Passivation layer 17 is respectively formed at the source, leaks on metal electrode 15b, the 15a; Pixel electrode 18a is deposited on the passivation layer 17 and by via hole 17a and links to each other with leakage metal electrode 15a.Said structure and tft array structure of the prior art similar, the present invention is different from prior art and is characterised in that: the corner of source, leakage metal electrode 15b, 15a is trapezoidal corner 15e, deposit superincumbent pixel electrode layer 18 and therefore can not break, therefore the rate of finished products of tft array significantly improves.
Preparation technology's method of 5 photolithographic fabrication tft array of the present invention's proposition is described in detail in detail below.
On transparent glass substrate or quartzy 11, it is the grid metal level 12 of 500～4000 that the method deposition of employing sputter or thermal evaporation goes up thickness.The grid metal can be selected metal and alloys such as Cr, W, Ti, Ta, Mo, Al, Cu for use, also can be satisfied the demand by the grid metal level that multiple layer metal is formed.Form needed gate electrode 12a and grid line 12b by the photoetching first time and etching process.On grid metal level 12, be the gate insulation layer 13 of 1000～4000 , the semiconductor layer 14 (comprising ohmic contact layer) that thickness is 1300～3000 then by PECVD method successive sedimentation thickness, gate insulation layer 13 can be selected oxide, nitride or oxynitrides for use, corresponding reacting gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2.The reacting gas of semiconductor layer 14 correspondences can be SiH4, H2 or SiH2Cl2, H2, form needed semiconductor layer figure by the photoetching second time and dry etch process again, this moment, the etching gas of semiconductor layer 14 can be selected gases such as SF6/Cl2 or SF6/HCl for use along the cross sectional shape at A-A position as shown in Figure 6.
After the figure of semiconductor layer 14 formed, sedimentary origin leaked metal level, and the method deposition of metal level by sputter or thermal evaporation leaked in the source, and thickness is about 500～2500 , can select metal and alloys such as Cr, W, Ti, Ta, Mo, Al, Cu for use.After layer metal deposition is leaked in the source, formed the source, leaked metal electrode 15b, 15a and data wire 15c by photoetching for the third time and etching technics, it along its cross sectional shape of A-A direction as shown in Figure 7.After source, leakage metal electrode 15b, 15a form, then carry out the cineration technics of photoresist 16, the gases used gases such as O2, SF6/O2, Cl2/O2 or CF4/O2 that can be of cineration technics, it is along its cross sectional shape of A-A direction as shown in Figure 8.After cineration technics is finished, the source that method by dry etching will expose is leaked metal level and is etched away, thereby the dihedral of falling the trapezoidal side of removal source leakage metal level is corner 15e in echelon, its along its cross sectional shape of A-A direction as shown in Figure 9, etching gas can be gases such as Cl2/O2, SF6/O2, CF4/O2, CF4/Cl2/O2 or SF6/Cl2/O2.After the dry etching of source leakage metal level is finished, carry out the etching of ohmic contact layer, be used for cutting off the source, leaked the connection between metal electrode 15b, the 15a, its along its cross sectional shape of A-A direction as shown in figure 10, etching gas can be selected gases such as SF6/Cl2 or SF6/HCl for use.
After the etching of ohmic contact layer is finished, be about the passivation layer 17 of 700～2000 by PECVD method deposit thickness.Passivation layer 17 can be selected oxide, nitride or oxynitrides for use, corresponding reacting gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2 forms via hole 17a by the 4th photoetching and etching technics then, it is along its cross sectional shape of A-A direction such as Figure 11, and etching gas can be selected SF6/O2, Cl2/O2 or HCl/O2 for use.
After via hole formed, the method deposition by sputter or thermal evaporation went up the transparency conducting layer that thickness is about 300～600 , is generally ITO or IZO, forms pixel electrode 18a by the 5th photoetching and etching technics at last, and it is along its cross sectional shape of A-A direction such as Fig. 2.Be removed because the trapezoidal corner of falling of metal level is leaked in the source, deposit superincumbent pixel electrode layer and therefore can not break, therefore the rate of finished products of tft array significantly improves.
The above embodiment that proposes is best implementation method, and not exclusive implementation method.Can use different materials and equipment to realize it as required.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that and can uses different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (8)
1, a kind of TFT matrix structure is characterized in that, comprising:
One substrate;
One grid line and with the gate electrode of its one, be formed on the described substrate, the top of grid line and gate electrode is coated with gate insulation layer;
One active layer and ohmic contact layer are formed on the gate insulation layer top;
One data wire reaches the source metal electrode with its one, is formed on the top of described ohmic contact layer;
One leaks metal electrode, is formed on the top of described ohmic contact layer;
One passivation layer, the top that is formed on described data wire, source metal electrode and leaks metal electrode;
One via hole is formed on the Lou top of metal electrode;
One pixel electrode is formed on the described passivation layer, and is connected with described leakage metal electrode by via hole;
Wherein, data wire and with the source metal electrode of its one, and the corner of leaking metal electrode be trapezoidal corner.
2, matrix structure according to claim 1, it is characterized in that: described grid line, gate electrode, source metal electrode, data wire or to leak metal electrode be the monofilm of Cr, W, Ti, Ta, Mo, Al or Cu perhaps are one of Cr, W, Ti, Ta, Mo, Al or Cu or composite membrane that combination in any constituted.
3, matrix structure according to claim 1 is characterized in that: described insulating barrier or passivation layer are oxide, nitride or oxynitrides.
4, a kind of manufacture method of TFT matrix structure is characterized in that, comprising:
Step 1, on substrate, deposition grid metal level adopts first mask, carries out mask, exposure and etching, forms grid line and gate electrode;
Step 2 deposits gate insulation layer, active layer and ohmic contact layer on completing steps 1 substrate, adopts second mask, carry out mask, exposure and etching after, form active layer and ohmic contact layer pattern;
Step 3, sedimentary origin leaks metal level on the substrate of completing steps 2, adopts the 3rd mask, carries out formation source after mask, exposure and the etching, leaks metal electrode and data wire figure; Then carry out the cineration technics of photoresist, source, leakage metal electrode and data wire are partly come out; The source that will expose by dry etching, leakage metal electrode and data wire etch away subsequently, thus the trapezoidal corner of formation source, leakage metal electrode and data wire; Carry out the etching of ohmic contact layer at last, form raceway groove;
Step 4, deposit passivation layer on completing steps 3 substrates adopts the 4th mask, carries out forming via pattern after mask, exposure and the etching;
Step 5, pixel deposition electrode layer on the substrate of completing steps 4 adopts the 5th mask, carries out forming the pixel electrode figure after mask, exposure and the etching, and pixel electrode links to each other with the leakage metal electrode by via hole.
5, manufacture method according to claim 4 is characterized in that: the used gas of the cineration technics of photoresist is O2, SF6/O2, Cl2/O2 or CF4/O2 in the described step 3.
6, manufacture method according to claim 4 is characterized in that: the etching gas that dry etching adopted in the described step 3 is Cl2/O2, SF6/O2, CF4/O2, CF4/Cl2/O2 or SF6/Cl2/O2.
7, manufacture method according to claim 4 is characterized in that: the dry etch process of photoresist ashing technology in the described step 3 and source, leakage metal electrode is carried out continuously.
8, manufacture method according to claim 4 is characterized in that: the dry etch process of photoresist ashing technology in the described step 3 and source, leakage metal electrode is that substep carries out.
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| CN101435962B (en) * | 2007-11-15 | 2010-09-22 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN105679707A (en) * | 2016-04-20 | 2016-06-15 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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| WO2017071405A1 (en) * | 2015-10-29 | 2017-05-04 | 京东方科技集团股份有限公司 | Thin film transistor manufacturing method, array substrate manufacturing method, display panel and display device |
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| CN101435962B (en) * | 2007-11-15 | 2010-09-22 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN104091807B (en) * | 2014-06-19 | 2016-09-07 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| US10475906B2 (en) | 2015-10-29 | 2019-11-12 | Boe Technology Group Co., Ltd. | Fabrication method of thin film transistor, fabrication method of array substrate, display panel, and display device |
| WO2017071405A1 (en) * | 2015-10-29 | 2017-05-04 | 京东方科技集团股份有限公司 | Thin film transistor manufacturing method, array substrate manufacturing method, display panel and display device |
| CN105679707A (en) * | 2016-04-20 | 2016-06-15 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN106771726A (en) * | 2016-12-02 | 2017-05-31 | 深圳市华星光电技术有限公司 | Method, the display panel of test suite and its monitoring display panel electric characteristics |
| CN107195638A (en) * | 2017-05-19 | 2017-09-22 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, display panel and array base palte |
| WO2018209754A1 (en) * | 2017-05-19 | 2018-11-22 | 深圳市华星光电技术有限公司 | Array substrate, display panel, and manufacturing method for array substrate |
| CN107579103A (en) * | 2017-08-31 | 2018-01-12 | 京东方科技集团股份有限公司 | A kind of array base palte, display panel, display device and preparation method thereof |
| CN109037348A (en) * | 2018-07-19 | 2018-12-18 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate |
| CN109037348B (en) * | 2018-07-19 | 2021-11-09 | Tcl华星光电技术有限公司 | Thin film transistor, preparation method thereof and array substrate |
| CN111048592A (en) * | 2019-11-19 | 2020-04-21 | 福建华佳彩有限公司 | Thin film field effect transistor structure and manufacturing method |
| CN111048592B (en) * | 2019-11-19 | 2022-10-25 | 福建华佳彩有限公司 | Thin film field effect transistor structure and manufacturing method |
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