WO2018032670A1 - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

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Publication number
WO2018032670A1
WO2018032670A1 PCT/CN2016/110072 CN2016110072W WO2018032670A1 WO 2018032670 A1 WO2018032670 A1 WO 2018032670A1 CN 2016110072 W CN2016110072 W CN 2016110072W WO 2018032670 A1 WO2018032670 A1 WO 2018032670A1
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Prior art keywords
layer
photoresist
drain
region
passivation layer
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PCT/CN2016/110072
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English (en)
French (fr)
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甘启明
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深圳市华星光电技术有限公司
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Priority to US15/326,648 priority Critical patent/US20180337202A1/en
Publication of WO2018032670A1 publication Critical patent/WO2018032670A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • a liquid crystal display panel consists of a color filter substrate (CF), a thin film transistor substrate (TFT, Thin Film Transistor), a liquid crystal (LC) sandwiched between a color filter substrate and a thin film transistor substrate, and a sealant frame ( Sealant), the molding process generally includes: front array (Array) process (film, yellow, etching and stripping), middle cell (Cell) process (TFT substrate and CF substrate bonding) and rear module assembly Process (drive IC and printed circuit board is pressed).
  • Array array
  • Cell middle cell
  • rear module assembly Process drive IC and printed circuit board is pressed.
  • the front Array process mainly forms a TFT substrate to control the movement of liquid crystal molecules; the middle Cell process mainly adds liquid crystal between the TFT substrate and the CF substrate; the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • the existing TFT substrate fabrication method has been gradually developed from the original 7-mask technology (4Mask) technology to four masks (4Mask) technology, and four masks are respectively used to form: patterned gate, patterned The active layer and the source/drain, the pixel electrode via, and the patterned pixel electrode, at the same time, in order to further reduce the fabrication process of the TFT substrate, shorten the production time, and improve the production efficiency, 3 mask technology (3Mask) It has also begun to be used on some products. Compared with the 4 reticle technology, the 3 reticle technology can save another reticle. The process time is shorter and the advantages are obvious. However, the current 3 reticle technology is better than 4 The process of mask technology is difficult, because the process of ITO Lift Off technology widely used in 3 mask technology is very difficult, which makes the process of 3 mask technology difficult.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can reduce the number of masks in the process of fabricating a TFT substrate and improve the fabrication efficiency of the TFT substrate.
  • the present invention provides a method of fabricating a TFT substrate, including the following step:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate and patterning the first metal layer through a photomask to form a gate and a gate line electrically connected to the gate;
  • Step 2 depositing a gate insulating layer on the substrate, the gate, and the gate line;
  • Step 3 depositing a semiconductor layer and a second metal layer on the gate insulating layer and simultaneously patterning the semiconductor layer and the second metal layer through a photomask to form a gate insulating layer on the gate An active layer, a source and a drain respectively contacting the both ends of the active layer, and a data line electrically connected to the source;
  • Step 4 depositing a passivation layer on the source, the drain, the data line, the active layer, and the gate insulating layer;
  • Step 5 coating a photoresist on the passivation layer to form a photoresist layer, patterning the photoresist layer through a photomask, and completely removing light corresponding to a portion of the drain and a region of the region where the pixel electrode is to be formed.
  • a resist layer exposing the passivation layer above the portion of the drain and the edge of the region where the pixel electrode is to be formed, while thinning the thickness of a portion of the photoresist layer in the region where the pixel electrode is to be formed, forming a photoresist trench extending in a plurality of different directions groove;
  • Step 6 Perform a first etching by using the remaining photoresist layer as a occlusion, completely removing the passivation layer not blocked by the photoresist layer above the drain, exposing a part of the drain, and partially removing the pixel electrode to be formed. a passivation layer at the edge of the region, thinning the thickness of a portion of the passivation layer at the edge of the region where the pixel electrode is to be formed, and then performing the first photoresist ashing to completely remove the photoresist layer in each photoresist trench, and thinning The thickness of the photoresist layer on both sides of each photoresist trench;
  • Step 7 Perform a second etching by using the remaining photoresist layer as a occlusion, and thin the thickness of the passivation layer in each photoresist trench to form a passivation layer trench extending in a plurality of different directions, and partially remove or Completely removing the remaining passivation layer at the edge of the region where the pixel electrode is to be formed, forming a pixel spacer groove at the edge of the region where the pixel electrode is to be formed;
  • Step 8 completely removing the remaining photoresist layer, depositing a transparent conductive layer on the passivation layer and the exposed drain, the transparent conductive layer being disconnected at the pixel spacing groove during deposition, forming a structure
  • a pixel electrode that is in contact with the drain, and the pixel electrode is formed with a pattern of irregularities along the trench of the passivation layer.
  • the step 3 specifically includes:
  • Step 31 Apply a photoresist on the second metal layer to provide a gray scale mask or a halftone mask to pattern the photoresist to remove the channel region of the thin film transistor to be formed. Part of the photoresist, removing all photoresist except the region where the thin film transistor and the data line are to be formed, and retaining all the photoresist of the region where the source and the drain of the thin film transistor are to be formed, and the data line;
  • Step 32 performing a first etching to remove the second metal layer and the semiconductor without photoresist Floor
  • Step 33 ashing the photoresist on the channel region of the thin film transistor to be removed to remove all photoresist on the channel region of the thin film transistor to be formed;
  • Step 34 followed by performing a second etching to remove the second metal layer on the channel region of the thin film transistor to be formed, forming an active layer, a source and a drain respectively contacting the both ends of the active layer, and a data line electrically connected to the source.
  • the reticle for exposing the photoresist layer in the step 5 is a gray scale reticle or a halftone reticle.
  • the material of the active layer is amorphous silicon, polycrystalline silicon, or an oxide semiconductor.
  • a taper angle of a passivation layer on a side closer to the drain of the pixel spacer in the pixel spacer is greater than 90 degrees, and a taper angle of the passivation layer on a side far from the source is less than 90 degrees;
  • the passivation layer of the grooves on both sides of the portion other than the drain has a taper angle greater than 90 degrees.
  • the material of the transparent conductive layer in the step 8 is ITO.
  • the material of the first metal layer and the second metal layer is a combination of one or more of aluminum, molybdenum, and copper.
  • the material of the gate insulating layer and the passivation layer is a combination of one or more of silicon oxide and silicon nitride.
  • the substrate is a transparent glass substrate or a transparent plastic substrate.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate and patterning the first metal layer through a photomask to form a gate and a gate line electrically connected to the gate;
  • Step 2 depositing a gate insulating layer on the substrate, the gate, and the gate line;
  • Step 3 depositing a semiconductor layer and a second metal layer on the gate insulating layer and simultaneously patterning the semiconductor layer and the second metal layer through a photomask to form a gate insulating layer on the gate An active layer, a source and a drain respectively contacting the both ends of the active layer, and a data line electrically connected to the source;
  • Step 4 depositing a passivation layer on the source, the drain, the data line, the active layer, and the gate insulating layer;
  • Step 5 coating a photoresist on the passivation layer to form a photoresist layer, patterning the photoresist layer through a photomask, and completely removing light corresponding to a portion of the drain and a region of the region where the pixel electrode is to be formed.
  • a resist layer exposing the passivation layer above the portion of the drain and the edge of the region where the pixel electrode is to be formed, while thinning the thickness of a portion of the photoresist layer in the region where the pixel electrode is to be formed, forming a photoresist trench extending in a plurality of different directions groove;
  • Step 6 Perform a first etching by using the remaining photoresist layer as a occlusion, completely removing the passivation layer not blocked by the photoresist layer above the drain, exposing a part of the drain, and partially removing the Forming a passivation layer at the edge of the region of the pixel electrode, thinning the thickness of a portion of the passivation layer at the edge of the region where the pixel electrode is to be formed, and then performing the first photoresist ashing to completely remove the photoresist layer in each photoresist trench Thinning the thickness of the photoresist layer on both sides of each photoresist trench;
  • Step 7 Perform a second etching by using the remaining photoresist layer as a occlusion, and thin the thickness of the passivation layer in each photoresist trench to form a passivation layer trench extending in a plurality of different directions, and partially remove or Completely removing the remaining passivation layer at the edge of the region where the pixel electrode is to be formed, forming a pixel spacer groove at the edge of the region where the pixel electrode is to be formed;
  • Step 8 completely removing the remaining photoresist layer, depositing a transparent conductive layer on the passivation layer and the exposed drain, the transparent conductive layer being disconnected at the pixel spacing groove during deposition, forming a structure a pixel electrode of the drain contact, wherein the pixel electrode is formed with a pattern of irregularities along the trench of the passivation layer;
  • the reticle for exposing the photoresist layer in the step 5 is a gray scale reticle or a halftone reticle;
  • the material of the active layer is amorphous silicon, polycrystalline silicon, or an oxide semiconductor.
  • the present invention provides a method of fabricating a TFT substrate by patterning a passivation layer by a halftone mask or a gray scale mask, and thereby forming a pixel electrode via hole through a mask A trench patterned passivation layer is then directly deposited on the trench patterned passivation layer to form a pixel electrode.
  • the pixel electrode is patterned without a mask, and the entire TFT substrate is fabricated only. It requires three masks to complete, and does not need to use indium tin oxide stripping technology, which is difficult to manufacture and high in efficiency.
  • FIG. 1 is a cross-sectional view showing a step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 2 is a cross-sectional view showing a step 2 of a method of fabricating a TFT substrate of the present invention
  • FIG. 3 is a cross-sectional view showing a step 3 of a method of fabricating a TFT substrate of the present invention
  • FIG. 4 is a cross-sectional view showing the step 4 of the method for fabricating the TFT substrate of the present invention
  • Figure 5 is a cross-sectional view showing the fifth step of the method for fabricating the TFT substrate of the present invention.
  • Figure 6 is a cross-sectional view showing the sixth step of the method of fabricating the TFT substrate of the present invention.
  • FIG. 7 is a plan view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a plan view showing a step 8 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a plan view showing a step 1 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a plan view showing a step 3 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 11 is a plan view showing a step 8 of a method of fabricating a TFT substrate of the present invention.
  • Fig. 12 is a flow chart showing a method of fabricating a TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 please refer to FIG. 1 and FIG. 9, providing a substrate 1 on which a first metal layer is deposited and patterned by a reticle to form a gate 21 and the gate The gate 21 is electrically connected to the gate line 22.
  • the number of the gate electrode 21 and the gate line 22 are multiple, and the plurality of gate electrodes 21 are distributed in an array, and the plurality of gate lines 22 all extend in a horizontal direction and are spaced apart from each other.
  • Each of the gate lines 22 is electrically connected to a row of gate electrodes 21.
  • the material of the first metal layer is one of metal materials such as aluminum (Al), molybdenum (Mo), and copper (Cu). Or a combination of multiples.
  • the substrate 1 is a transparent glass substrate or a transparent plastic substrate.
  • Step 2 a gate insulating layer 3 is deposited on the substrate 1, the gate 21, and the gate line 22.
  • the material of the gate insulating layer 3 is a combination of one or more of silicon oxide (SiOx) and silicon nitride (SiNx).
  • Step 3 referring to FIG. 3 and FIG. 10, depositing a semiconductor layer and a second metal layer on the gate insulating layer 3 and simultaneously patterning the semiconductor layer and the second metal layer through a photomask to form the An active layer 4 on the gate insulating layer 3 on the gate electrode 21, a source electrode 51 and a drain electrode 52 respectively contacting the both ends of the active layer 4, and data electrically connected to the source electrode 51 Line 53.
  • the step 3 includes:
  • Step 31 applying a photoresist on the second metal layer, providing a Gray Tone Mask (GTM) or a Half Tone Mask (HTM) to pattern the photoresist. Removing a portion of the photoresist at a position of the channel region of the thin film transistor to be formed, removing all photoresists other than the region where the thin film transistor and the data line are to be formed, and retaining the source and drain of the thin film transistor to be formed, and the data line The total resistance of the area;
  • GTM Gray Tone Mask
  • HTM Half Tone Mask
  • Step 32 performing a first etching to remove the second metal layer and the semiconductor layer without photoresist blocking
  • Step 33 The photoresist on the channel region of the thin film transistor to be formed is subjected to ashing treatment to be removed. Forming all the photoresist on the channel region of the thin film transistor;
  • Step 34 followed by performing a second etching to remove the second metal layer on the channel region of the thin film transistor to be formed, forming the active layer 4, the source 51 and the drain respectively contacting the both ends of the active layer 4 a pole 52 and a data line 53 electrically connected to the source 51.
  • the number of the source 51 and the drain 52 is in one-to-one correspondence with the number of the gates 21, and is also distributed in an array.
  • the number of the data lines 53 is also multiple, and the plurality of data lines 53 are along Each of the data lines 53 is electrically connected to a row of source electrodes 51.
  • the material of the active layer 4 is amorphous silicon, polysilicon, or an oxide semiconductor.
  • the material of the two metal layers is a combination of one or more of aluminum, molybdenum, and metallic materials such as copper.
  • Step 4 please refer to FIG. 4, depositing a passivation layer 6 on the source 51, the drain 52, the data line 53, the active layer 4, and the gate insulating layer 3;
  • the material of the passivation layer 6 is a combination of one or more of silicon oxide and silicon nitride.
  • Step 5 referring to FIG. 5, coating a photoresist on the passivation layer 6 to form a photoresist layer 7, patterning the photoresist layer 7 through a photomask, completely removing a portion corresponding to a portion of the drain electrode 52 and The photoresist layer 7 at the edge of the region where the pixel electrode is to be formed exposes the passivation layer 6 above the portion of the drain electrode 52 and the edge of the region where the pixel electrode is to be formed, while thinning the portion of the photoresist layer 7 in the region where the pixel electrode is to be formed Thickness, forming a photoresist trench 71 extending in a plurality of different directions;
  • the photoresist layer 7 is exposed by using a halftone mask or a gray scale mask
  • the halftone mask or gray scale mask includes: a semi-transmissive region, an opaque region, and a semi-transmissive region corresponding to a region of the photoresist layer 7 on which the photoresist trench 71 is to be formed, the fully transparent region corresponding to a portion of the drain 52 and a photoresist at an edge of the region where the pixel electrode is to be formed
  • the layer 7 is disposed, and the regions other than the semi-transmissive region and the completely transparent region are opaque regions, and the thickness of the photoresist layer 7 corresponding to the position is thinned by the semi-transmissive region, and the corresponding position is completely removed by using the completely transparent region.
  • the photoresist layer 7 and the photoresist layer 7 corresponding to the position of the opaque region will be completely retained. It can be understood that the positions corresponding to the opaque region and the completely transparent region can be interchanged depending on the positive and negative properties of the photoresist.
  • the photoresist trenches 71 extending in a plurality of different directions have a "m"-shaped distribution, and include a plurality of lights respectively extending in opposite directions of 45°, 135°, 225°, and 315° in the horizontal direction.
  • the barrier groove 71 is a "m"-shaped distribution, and include a plurality of lights respectively extending in opposite directions of 45°, 135°, 225°, and 315° in the horizontal direction.
  • Step 6 please refer to FIG. 6, using the remaining photoresist layer 7 as a occlusion for the first etching, completely removing the passivation layer 6 above the drain 52 that is not blocked by the photoresist layer 7, exposing the drain 52. a portion of the passivation layer 6 at the same time partially removing the edge of the region where the pixel electrode is to be formed, thinning the thickness of the portion of the passivation layer 6 at the edge of the region where the pixel electrode is to be formed, and then performing the first photoresist ashing, The photoresist layer 7 in each of the photoresist trenches 71 is completely removed, and the thickness of the photoresist layer 7 on both sides of each of the photoresist trenches 71 is thinned.
  • Step 7 referring to FIG. 7, the second etching is performed by using the remaining photoresist layer 7 as a mask, and the thickness of the passivation layer 6 in each photoresist trench 71 is thinned to form a passivation extending in a plurality of different directions.
  • the layer trench 61 simultaneously partially removes or completely removes the remaining passivation layer 6 at the edge of the region where the pixel electrode is to be formed, forming a pixel spacer groove 62 at the edge of the region where the pixel electrode is to be formed.
  • the pattern of the passivation layer trench 61 corresponds to the pattern of the photoresist trench 71, and is also in a "meter"-shaped distribution, including respectively deflecting 45°, 135°, 225° in a relative horizontal direction, and a passivation layer trench 61 extending in a 315° direction, and a taper angle of the passivation layer 6 on a portion of the pixel spacer trench 62 located near the drain electrode 52 near the source 51 side is greater than 90 degrees.
  • the passivation layer 6 on the side far from the source 51 has a taper angle of less than 90 degrees; the passivation layer on both sides of the portion of the pixel spacer 62 located above the drain 52 has a taper angle greater than 90 degrees.
  • the amount of the remaining passivation layer 6 at the edge of the region of the pixel electrode to be formed removed by the second etching is correspondingly changed according to the designed depth of the passivation layer trench 61, and can be completely removed at the time of complete removal.
  • the depth of the passivation layer trench 61 is greater than or equal to the thickness of the remaining passivation layer 6 of the edge of the region where the pixel electrode is to be formed, of course, if the depth of the passivation layer trench 61 is smaller than the pixel electrode to be formed The thickness of the remaining passivation layer 6 at the edge of the region is not completely removed by the remaining passivation layer 6 at the edge of the region where the pixel electrode is to be formed.
  • Step 8 referring to FIG. 8 and FIG. 11, completely removing the remaining photoresist layer 7, depositing a transparent conductive layer on the passivation layer 6, and the exposed drain 52, the transparent conductive layer being deposited at the time of deposition
  • the pixel spacer groove 62 is turned off to form a pixel electrode 81 that is in contact with the drain electrode 52, and the pixel electrode 81 is formed with a pattern of unevenness along the passivation layer trench 61.
  • the pixel electrode 81 is formed along the passivation layer trench 61, which is a full-face pixel electrode, and has a surface having the same "m"-shaped uneven pattern as the passivation layer trench 61.
  • the same control effect can be achieved as in the multi-domain vertical alignment (VA) type liquid crystal display panel using the "meter” type slit (Silt) pixel electrode, and at least one side of the pixel spacer groove 62 is blunt.
  • the Taper angle of the layer is large, and the transparent conductive layer is naturally disconnected at the position of the pixel spacer 62 when deposited, so that the transparent conductive layer is located above the data line 53, the gate line 22, the gate 21, and the source 51.
  • the layer is spaced apart from the pixel electrode 81 to avoid affecting the normal operation of the pixel electrode 81.
  • the pixel electrode 81 does not need to be patterned by the mask when forming, and the material ITO Lift Off technology is not needed, which saves a mask and avoids the difficulty of the process, and ensures the obtained pixel.
  • the display effect of the electrode 81 is the same as that of the pixel electrode obtained by exposure.
  • the material of the transparent conductive layer in the step 8 is Indium Tin Oxides (ITO).
  • ITO Indium Tin Oxides
  • the present invention provides a method for fabricating a TFT substrate by patterning a passivation layer through a halftone mask or a gray scale mask, and thereby forming a pixel electrode via and a trench through a mask.
  • the grooved patterned passivation layer is then directly deposited on the trench patterned passivation layer to form a pixel electrode.
  • the pixel electrode is patterned without a mask, and the entire TFT substrate is only required to be fabricated. Three masks can be completed without using indium tin oxide stripping technology, which is difficult to manufacture and high in efficiency.

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Abstract

一种TFT基板的制作方法，该方法通过半色调光罩或灰阶光罩图案化钝化层，进而通过一道光罩就可以制得像素电极过孔和沟槽图案化的钝化层，接着在沟槽图案化的钝化层上直接顺势沉积透明导电材料，即可制得像素电极，该像素电极无需光罩进行图案化，整个TFT基板的制作只需要3道光罩即可完成，且不需要采用氧化铟锡剥离技术，制作难度低，效率高。

Description

TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
通常液晶显示面板由彩膜基板(CF，Color Filter)、薄膜晶体管基板(TFT，Thin Film Transistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
现有的TFT基板的制作方法已从最初的7光罩(7Mask)技术发展逐渐发展到的4光罩(4Mask)技术，4个光罩分别用于形成：图案化的栅极、图案化的有源层和源/漏极、像素电极过孔、及图案化的像素电极，与此同时，为了进一步减化TFT基板的制作工艺，缩短生产时间，提升生产效率，3光罩技术(3Mask)也已经开始在部分产品上开始使用，相比于4光罩技术，3光罩技术能够再节省一道光罩，制程时间较短，优势明显，然而，目前所采用的3光罩技术较于4光罩技术制程难度较大，因为目前在3光罩技术中广泛采用的氧化铟锡剥离(ITO Lift Off)技术的制程难度很大，进而导致了3光罩技术制程难度也很大。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能够减少TFT基板制作过程中的光罩数目，提升TFT基板的制作效率。
为实现上述目的，本发明提供了一种TFT基板的制作方法，包括如下 步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层并通过一道光罩图案化所述第一金属层，形成栅极以及与所述栅极电性连接的栅极线；
步骤2、在所述基板、栅极、及栅极线上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积半导体层及第二金属层并通过一道光罩同时图案化所述半导体层及第二金属层，形成位于所述栅极上的栅极绝缘层上的有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线；
步骤4、在所述源极、漏极、数据线、有源层、以及栅极绝缘层上沉积钝化层；
步骤5、在所述钝化层上涂布光阻，形成光阻层，通过一道光罩图案化所述光阻层，完全去除对应于一部分漏极上方以及待形成像素电极的区域边缘的光阻层，暴露出该部分漏极上方以及待形成像素电极的区域边缘的钝化层，同时减薄待形成像素电极的区域内部分光阻层的厚度，形成向多个不同方向延伸的光阻沟槽；
步骤6、利用剩余的光阻层做遮挡进行第一次蚀刻，完全去除所述漏极上方的未被光阻层遮挡的钝化层，暴露出漏极的一部分，同时部分去除待形成像素电极的区域边缘的钝化层，减薄待形成像素电极的区域边缘的部分钝化层的厚度，接着进行第一次光阻灰化，完全去除各个光阻沟槽内的光阻层，减薄各个光阻沟槽两侧的光阻层的厚度；
步骤7、利用剩余的光阻层做遮挡进行第二次蚀刻，减薄各个光阻沟槽内的钝化层的厚度，形成向多个不同方向延伸的钝化层沟槽，同时部分去除或完全去除待形成像素电极的区域边缘的剩余的钝化层，形成位于待形成像素电极的区域边缘的像素间隔槽；
步骤8、完全去除剩余的光阻层，在所述钝化层、以及暴露的漏极上沉积透明导电层，所述透明导电层在沉积时在所述像素间隔槽处断开，形成与所述漏极接触的像素电极，所述像素电极顺着所述钝化层沟槽形成有凹凸不平的图案。
所述步骤3具体包括：
步骤31、在所述第二金属层上涂布光阻，提供一灰阶光罩或半色调光罩对所述光阻进行图案化，去除所述待形成薄膜晶体管的沟道区的位置上的部分光阻，去除待形成薄膜晶体管和数据线的区域以外的全部光阻，保留待形成薄膜晶体管源极及漏极、以及数据线的区域的全部光阻；
步骤32、进行第一次蚀刻，去除没有光阻覆盖的第二金属层和半导体 层；
步骤33、对待形成薄膜晶体管的沟道区上的光阻进行灰化处理去除待形成薄膜晶体管的沟道区上的全部光阻；
步骤34、接着进行第二次蚀刻，去除待形成薄膜晶体管的沟道区上的第二金属层，形成有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线。
所述步骤5中对光阻层进行曝光的光罩为灰阶光罩或半色调光罩。
所述有源层的材料为非晶硅、多晶硅、或氧化物半导体。
所述像素间隔槽中位于所述漏极上方的部分靠近源极一侧的钝化层的锥度角大于90度，远离源极一侧的钝化层的锥度角小于90度；所述像素间隔槽位于所述漏极上方的以外的部分两侧的钝化层的锥度角大于90度。
所述步骤8中的透明导电层的材料为ITO。
所述第一金属层与第二金属层的材料为铝、钼、与铜中的一种或多种的组合。
所述栅极绝缘层与钝化层的材料为氧化硅与氮化硅中的一种或多种的组合。
所述基板为透明的玻璃基板、或透明的塑料基板。
本发明还提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层并通过一道光罩图案化所述第一金属层，形成栅极以及与所述栅极电性连接的栅极线；
步骤2、在所述基板、栅极、及栅极线上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积半导体层及第二金属层并通过一道光罩同时图案化所述半导体层及第二金属层，形成位于所述栅极上的栅极绝缘层上的有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线；
步骤4、在所述源极、漏极、数据线、有源层、以及栅极绝缘层上沉积钝化层；
步骤5、在所述钝化层上涂布光阻，形成光阻层，通过一道光罩图案化所述光阻层，完全去除对应于一部分漏极上方以及待形成像素电极的区域边缘的光阻层，暴露出该部分漏极上方以及待形成像素电极的区域边缘的钝化层，同时减薄待形成像素电极的区域内部分光阻层的厚度，形成向多个不同方向延伸的光阻沟槽；
步骤6、利用剩余的光阻层做遮挡进行第一次蚀刻，完全去除所述漏极上方的未被光阻层遮挡的钝化层，暴露出漏极的一部分，同时部分去除待 形成像素电极的区域边缘的钝化层，减薄待形成像素电极的区域边缘的部分钝化层的厚度，接着进行第一次光阻灰化，完全去除各个光阻沟槽内的光阻层，减薄各个光阻沟槽两侧的光阻层的厚度；
步骤7、利用剩余的光阻层做遮挡进行第二次蚀刻，减薄各个光阻沟槽内的钝化层的厚度，形成向多个不同方向延伸的钝化层沟槽，同时部分去除或完全去除待形成像素电极的区域边缘的剩余的钝化层，形成位于待形成像素电极的区域边缘的像素间隔槽；
步骤8、完全去除剩余的光阻层，在所述钝化层、以及暴露的漏极上沉积透明导电层，所述透明导电层在沉积时在所述像素间隔槽处断开，形成与所述漏极接触的像素电极，所述像素电极顺着所述钝化层沟槽形成有凹凸不平的图案；
其中，所述步骤5中对光阻层进行曝光的光罩为灰阶光罩或半色调光罩；
其中，所述有源层的材料为非晶硅、多晶硅、或氧化物半导体。
本发明的有益效果：本发明提供了一种TFT基板的制作方法，该方法通过半色调光罩或灰阶光罩图案化钝化层，进而通过一道光罩就可以制得像素电极过孔和沟槽图案化的钝化层，接着在沟槽图案化的钝化层上直接顺势沉积透明导电材料，即可制得像素电极，该像素电极无需光罩进行图案化，整个TFT基板的制作只需要3道光罩即可完成，且不需要采用氧化铟锡剥离技术，制作难度低，效率高。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的TFT基板的制作方法的步骤1的剖视图；
图2为本发明的TFT基板的制作方法的步骤2的剖视图；
图3为本发明的TFT基板的制作方法的步骤3的剖视图；
图4为本发明的TFT基板的制作方法的步骤4的剖视图；
图5为本发明的TFT基板的制作方法的步骤5的剖视图；
图6为本发明的TFT基板的制作方法的步骤6的剖视图；
图7为本发明的TFT基板的制作方法的步骤7的俯视图；
图8为本发明的TFT基板的制作方法的步骤8的俯视图；
图9为本发明的TFT基板的制作方法的步骤1的俯视图；
图10为本发明的TFT基板的制作方法的步骤3的俯视图；
图11为本发明的TFT基板的制作方法的步骤8的俯视图；
图12为本发明的TFT基板的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图12，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、请参阅图1及图9，提供一基板1，在所述基板1上沉积第一金属层并通过一道光罩图案化所述第一金属层，形成栅极21以及与所述栅极21电性连接的栅极线22。
具体地，所述栅极21和栅极线22的数量均为多个，所述多个栅极21呈阵列式分布，所述多条栅极线22均沿水平方向延伸并且相互平行间隔分布，每一条栅极线22对应电性连接一行栅极21，优选地，所述第一金属层的材料为铝(Al)、钼(Mo)、与铜(Cu)等金属材料中的一种或多种的组合。优选地，所述基板1为透明的玻璃基板、或透明的塑料基板。
步骤2、请参阅图2，在所述基板1、栅极21、及栅极线22上沉积栅极绝缘层3。
具体地，所述栅极绝缘层3的材料为氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种的组合。
步骤3、请参阅图3及图10，在所述栅极绝缘层3上沉积半导体层及第二金属层并通过一道光罩同时图案化所述半导体层及第二金属层，形成位于所述栅极21上的栅极绝缘层3上的有源层4、分别与所述有源层4的两端接触的源极51和漏极52、以及与所述源极51电性连接的数据线53。
具体地，所述步骤3包括：
步骤31、在所述第二金属层上涂布光阻，提供一灰阶光罩(Gray Tone Mask，GTM)或半色调光罩(Half Tone Mask，HTM)对所述光阻进行图案化，去除所述待形成薄膜晶体管的沟道区的位置上的部分光阻，去除待形成薄膜晶体管和数据线的区域以外的全部光阻，保留待形成薄膜晶体管源极及漏极、以及数据线的区域的全部光阻；
步骤32、进行第一次蚀刻，去除没有光阻覆盖的第二金属层和半导体层；
步骤33、对待形成薄膜晶体管的沟道区上的光阻进行灰化处理去除待 形成薄膜晶体管的沟道区上的全部光阻；
步骤34、接着进行第二次蚀刻，去除待形成薄膜晶体管的沟道区上的第二金属层，形成有源层4、分别与所述有源层4的两端接触的源极51和漏极52、以及与所述源极51电性连接的数据线53。
具体地，所述源极51和漏极52的数量与栅极21的数量一一对应，也呈阵列式分布，所述数据线53的数量也为多条，所述多条数据线53沿均竖直方向延伸且相互平行间隔分布，每一条数据线53电性连接一列源极51，优选地，所述有源层4的材料为非晶硅、多晶硅、或氧化物半导体，所述第二金属层的材料为铝、钼、与铜等金属材料中的一种或多种的组合。
步骤4、请参阅图4，在所述源极51、漏极52、数据线53、有源层4、以及栅极绝缘层3上沉积钝化层6；
具体地，所述钝化层6的材料为氧化硅与氮化硅中的一种或多种的组合。
步骤5、请参阅图5，在所述钝化层6上涂布光阻，形成光阻层7，通过一道光罩图案化所述光阻层7，完全去除对应于一部分漏极52上方以及待形成像素电极的区域边缘的光阻层7，暴露出该部分漏极52上方以及待形成像素电极的区域边缘的钝化层6，同时减薄待形成像素电极的区域内部分光阻层7的厚度，形成向多个不同方向延伸的光阻沟槽71；
具体地，所述步骤5中采用半色调光罩或灰阶光罩对光阻层7进行曝光，所述半色调光罩或灰阶光罩包括：半透光区域、不透光区域、以及完全透光区域，所述半透光区域对应光阻层7上待形成光阻沟槽71的区域，所述完全透光区域对应一部分漏极52上方以及待形成像素电极的区域边缘的光阻层7设置，除了半透光区域和完全透光区域以外的区域都是不透光区域，利用半透光区域减薄对应位置的光阻层7的厚度，利用完全透光区域完全去除对应位置光阻层7，而不透光区域对应位置的光阻层7将被全部保留下来。可以理解的是，根据光阻的正负性质的不同，不透光区域和完全透光区域对应的位置可以互换。
优选地，所述向多个不同方向延伸的光阻沟槽71呈“米”字型分布，包括分别向相对水平方向偏转45°、135°、225°、及315°方向延伸的多个光阻沟槽71。
步骤6、请参阅图6，利用剩余的光阻层7做遮挡进行第一次蚀刻，完全去除所述漏极52上方的未被光阻层7遮挡的钝化层6，暴露出漏极52的一部分，同时部分去除待形成像素电极的区域边缘的钝化层6，减薄待形成像素电极的区域边缘的部分钝化层6的厚度，接着进行第一次光阻灰化， 完全去除各个光阻沟槽71内的光阻层7，减薄各个光阻沟槽71两侧的光阻层7的厚度。
步骤7、请参阅图7，利用剩余的光阻层7做遮挡进行第二次蚀刻，减薄各个光阻沟槽71内的钝化层6的厚度，形成向多个不同方向延伸的钝化层沟槽61，同时部分去除或完全去除待形成像素电极的区域边缘的剩余的钝化层6，形成位于待形成像素电极的区域边缘的像素间隔槽62。
具体地，所述钝化层沟槽61的图案对应所述光阻沟槽71的图案，也呈“米”字型分布，包括分别向相对水平方向偏转45°、135°、225°、及315°方向延伸的钝化层沟槽61，并且所述像素间隔槽62中位于所述漏极52上方的部分靠近源极51一侧的钝化层6的锥度(Taper)角大于90度，远离源极51一侧的钝化层6的锥度角小于90度；所述像素间隔槽62位于所述漏极52上方的以外的部分两侧的钝化层的锥度角大于90度。
进一步地，所述第二次蚀刻去除的待形成像素电极的区域边缘的剩余的钝化层6的多少根据所设计的钝化层沟槽61深度相应变化，最多可以完全去除，完全去除时所述钝化层沟槽61的深度大于或等于所述待形成像素电极的区域边缘的剩余的钝化层6的厚度，当然若所述钝化层沟槽61的深度小于所述待形成像素电极的区域边缘的剩余的钝化层6的厚度，所述待形成像素电极的区域边缘的剩余的钝化层6也就不会被完全去除。
步骤8、请参阅图8及图11，完全去除剩余的光阻层7，在所述钝化层6、以及暴露的漏极52上沉积透明导电层，所述透明导电层在沉积时在所述像素间隔槽62处断开，形成与所述漏极52接触的像素电极81，所述像素电极81顺着所述钝化层沟槽61形成有凹凸不平的图案。
具体地，所述像素电极81沿着钝化层沟槽61顺势形成，其为一个整面的像素电极，并且其表面具有与钝化层沟槽61相同的“米”字型分布的凹凸图案，可以达成与多畴垂直配向(vertical alignment，VA)型液晶显示面板中采用“米”字型狭缝(Silt)像素电极相同的控制效果，而由于所述像素间隔槽62至少一侧的钝化层的Taper角较大，透明导电层在沉积时会在像素间隔槽62的位置自然断开，从而使得位于数据线53、栅极线22、栅极21、以及源极51上方的透明导电层与像素电极81分隔开，避免对像素电极81的正常工作产生影响。
进一步地，在步骤8中像素电极81在形成时不需要光罩进行图案化，也不需要材料ITO Lift Off技术，节省一道光罩的同时，避免了制程难度的增加，同时保证制得的像素电极81的显示效果与曝光制得的像素电极的显示效果相同。
优选地，所述步骤8中的透明导电层的材料为氧化铟锡(Indium Tin Oxides，ITO)。
综上所述，本发明提供了一种TFT基板的制作方法，该方法通过半色调光罩或灰阶光罩图案化钝化层，进而通过一道光罩就可以制得像素电极过孔和沟槽图案化的钝化层，接着在沟槽图案化的钝化层上直接顺势沉积透明导电材料，即可制得像素电极，该像素电极无需光罩进行图案化，整个TFT基板的制作只需要3道光罩即可完成，且不需要采用氧化铟锡剥离技术，制作难度低，效率高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层并通过一道光罩图案化所述第一金属层，形成栅极以及与所述栅极电性连接的栅极线；
    步骤2、在所述基板、栅极、及栅极线上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积半导体层及第二金属层并通过一道光罩同时图案化所述半导体层及第二金属层，形成位于所述栅极上的栅极绝缘层上的有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线；
    步骤4、在所述源极、漏极、数据线、有源层、以及栅极绝缘层上沉积钝化层；
    步骤5、在所述钝化层上涂布光阻，形成光阻层，通过一道光罩图案化所述光阻层，完全去除对应于一部分漏极上方以及待形成像素电极的区域边缘的光阻层，暴露出该部分漏极上方以及待形成像素电极的区域边缘的钝化层，同时减薄待形成像素电极的区域内部分光阻层的厚度，形成向多个不同方向延伸的光阻沟槽；
    步骤6、利用剩余的光阻层做遮挡进行第一次蚀刻，完全去除所述漏极上方的未被光阻层遮挡的钝化层，暴露出漏极的一部分，同时部分去除待形成像素电极的区域边缘的钝化层，减薄待形成像素电极的区域边缘的部分钝化层的厚度，接着进行第一次光阻灰化，完全去除各个光阻沟槽内的光阻层，减薄各个光阻沟槽两侧的光阻层的厚度；
    步骤7、利用剩余的光阻层做遮挡进行第二次蚀刻，减薄各个光阻沟槽内的钝化层的厚度，形成向多个不同方向延伸的钝化层沟槽，同时部分去除或完全去除待形成像素电极的区域边缘的剩余的钝化层，形成位于待形成像素电极的区域边缘的像素间隔槽；
    步骤8、完全去除剩余的光阻层，在所述钝化层、以及暴露的漏极上沉积透明导电层，所述透明导电层在沉积时在所述像素间隔槽处断开，形成与所述漏极接触的像素电极，所述像素电极顺着所述钝化层沟槽形成有凹凸不平的图案。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述第二金属层上涂布光阻，提供一灰阶光罩或半色调光 罩对所述光阻进行图案化，去除所述待形成薄膜晶体管的沟道区的位置上的部分光阻，去除待形成薄膜晶体管和数据线的区域以外的全部光阻，保留待形成薄膜晶体管源极及漏极、以及数据线的区域的全部光阻；
    步骤32、进行第一次蚀刻，去除没有光阻覆盖的第二金属层和半导体层；
    步骤33、对待形成薄膜晶体管的沟道区上的光阻进行灰化处理去除待形成薄膜晶体管的沟道区上的全部光阻；
    步骤34、接着进行第二次蚀刻，去除待形成薄膜晶体管的沟道区上的第二金属层，形成有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤5中对光阻层进行曝光的光罩为灰阶光罩或半色调光罩。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述有源层的材料为非晶硅、多晶硅、或氧化物半导体。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述像素间隔槽中位于所述漏极上方的部分靠近源极一侧的钝化层的锥度角大于90度，远离源极一侧的钝化层的锥度角小于90度；所述像素间隔槽位于所述漏极上方的以外的部分两侧的钝化层的锥度角大于90度。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤8中的透明导电层的材料为ITO。
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述第一金属层与第二金属层的材料为铝、钼、与铜中的一种或多种的组合。
  8. 如权利要求1所述的TFT基板的制作方法，其中，所述栅极绝缘层与钝化层的材料为氧化硅与氮化硅中的一种或多种的组合。
  9. 如权利要求1所述的TFT基板的制作方法，其中，所述基板为透明的玻璃基板、或透明的塑料基板。
  10. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层并通过一道光罩图案化所述第一金属层，形成栅极以及与所述栅极电性连接的栅极线；
    步骤2、在所述基板、栅极、及栅极线上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积半导体层及第二金属层并通过一道光罩同时图案化所述半导体层及第二金属层，形成位于所述栅极上的栅极绝缘层上的有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线；
    步骤4、在所述源极、漏极、数据线、有源层、以及栅极绝缘层上沉积钝化层；
    步骤5、在所述钝化层上涂布光阻，形成光阻层，通过一道光罩图案化所述光阻层，完全去除对应于一部分漏极上方以及待形成像素电极的区域边缘的光阻层，暴露出该部分漏极上方以及待形成像素电极的区域边缘的钝化层，同时减薄待形成像素电极的区域内部分光阻层的厚度，形成向多个不同方向延伸的光阻沟槽；
    步骤6、利用剩余的光阻层做遮挡进行第一次蚀刻，完全去除所述漏极上方的未被光阻层遮挡的钝化层，暴露出漏极的一部分，同时部分去除待形成像素电极的区域边缘的钝化层，减薄待形成像素电极的区域边缘的部分钝化层的厚度，接着进行第一次光阻灰化，完全去除各个光阻沟槽内的光阻层，减薄各个光阻沟槽两侧的光阻层的厚度；
    步骤7、利用剩余的光阻层做遮挡进行第二次蚀刻，减薄各个光阻沟槽内的钝化层的厚度，形成向多个不同方向延伸的钝化层沟槽，同时部分去除或完全去除待形成像素电极的区域边缘的剩余的钝化层，形成位于待形成像素电极的区域边缘的像素间隔槽；
    步骤8、完全去除剩余的光阻层，在所述钝化层、以及暴露的漏极上沉积透明导电层，所述透明导电层在沉积时在所述像素间隔槽处断开，形成与所述漏极接触的像素电极，所述像素电极顺着所述钝化层沟槽形成有凹凸不平的图案；
    其中，所述步骤5中对光阻层进行曝光的光罩为灰阶光罩或半色调光罩；
    其中，所述有源层的材料为非晶硅、多晶硅、或氧化物半导体。
  11. 如权利要求10所述的TFT基板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述第二金属层上涂布光阻，提供一灰阶光罩或半色调光罩对所述光阻进行图案化，去除所述待形成薄膜晶体管的沟道区的位置上的部分光阻，去除待形成薄膜晶体管和数据线的区域以外的全部光阻，保留待形成薄膜晶体管源极及漏极、以及数据线的区域的全部光阻；
    步骤32、进行第一次蚀刻，去除没有光阻覆盖的第二金属层和半导体层；
    步骤33、对待形成薄膜晶体管的沟道区上的光阻进行灰化处理去除待形成薄膜晶体管的沟道区上的全部光阻；
    步骤34、接着进行第二次蚀刻，去除待形成薄膜晶体管的沟道区上的 第二金属层，形成有源层、分别与所述有源层的两端接触的源极和漏极、以及与所述源极电性连接的数据线。
  12. 如权利要求10所述的TFT基板的制作方法，其中，所述像素间隔槽中位于所述漏极上方的部分靠近源极一侧的钝化层的锥度角大于90度，远离源极一侧的钝化层的锥度角小于90度；所述像素间隔槽位于所述漏极上方的以外的部分两侧的钝化层的锥度角大于90度。
  13. 如权利要求10所述的TFT基板的制作方法，其中，所述步骤8中的透明导电层的材料为ITO。
  14. 如权利要求10所述的TFT基板的制作方法，其中，所述第一金属层与第二金属层的材料为铝、钼、与铜中的一种或多种的组合。
  15. 如权利要求10所述的TFT基板的制作方法，其中，所述栅极绝缘层与钝化层的材料为氧化硅与氮化硅中的一种或多种的组合。
  16. 如权利要求10所述的TFT基板的制作方法，其中，所述基板为透明的玻璃基板、或透明的塑料基板。
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