WO2017133097A1 - 阵列基板及其制造方法以及显示面板 - Google Patents

阵列基板及其制造方法以及显示面板 Download PDF

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Publication number
WO2017133097A1
WO2017133097A1 PCT/CN2016/081146 CN2016081146W WO2017133097A1 WO 2017133097 A1 WO2017133097 A1 WO 2017133097A1 CN 2016081146 W CN2016081146 W CN 2016081146W WO 2017133097 A1 WO2017133097 A1 WO 2017133097A1
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region
insulating layer
conductive layer
layer
semi
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PCT/CN2016/081146
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English (en)
French (fr)
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陈程
李纪龙
徐德智
吕艳明
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/501,424 priority Critical patent/US20180046045A1/en
Publication of WO2017133097A1 publication Critical patent/WO2017133097A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display panel.
  • the organic insulating film layer is easy to form a thick film layer, the signal interference in the array substrate can be reduced, and the parasitic capacitance can be reduced.
  • the organic insulating film layer is widely used because of the advantages of reducing the substrate load and reducing power consumption.
  • an organic insulating film layer is disposed between two conductive film layers, for example, between a source/drain electrode layer and a pixel electrode layer. In order to electrically connect the pixel electrode to the drain of the thin film transistor, it is necessary to form a via hole in the organic insulating film layer.
  • FIG. 1a is a schematic view showing the application structure of an organic insulating film layer in the prior art.
  • Fig. 1b is a schematic cross-sectional view of Fig. 1a taken along the line A-A'.
  • Figure 1c is a schematic cross-sectional view of Figure 1a taken along line B-B'.
  • a substrate transistor 10 is provided with a thin film transistor composed of an active layer 11, a gate (not shown), a source (not shown), and a drain 12, data. Line 13, gate line 14, and pixel electrode 15.
  • An organic insulating film layer 16 is provided between the pixel electrode 15 and the drain electrode 12.
  • the pixel electrode 15 is electrically connected to the drain electrode 12 through a via hole V penetrating the organic insulating film layer 16.
  • the data line 13, the source and the drain 12 are arranged in the same layer.
  • the organic insulating film layer 16 is thick, the parasitic capacitance between the data line 13 and the pixel electrode 15 is small, and thus the picture quality is good.
  • the via hole V is deep (for example, up to 2 ⁇ m), so that the pixel electrode 15 overlapping the side of the via hole V is easily broken and due to the organic insulating film layer.
  • a large difference in the length difference of 16 causes a problem such as uneven orientation of the subsequent alignment film.
  • Embodiments of the present invention provide an array substrate including a substrate substrate, a first conductive layer, an insulating layer, and a second conductive layer sequentially disposed on the substrate, the insulating layer including a via area, a semi-reserved area outside the via area, and a completely reserved area surrounding the semi-reserved area and the area where the via area is located;
  • the via region includes a via hole penetrating the insulating layer, and the second conductive layer is electrically connected to the first conductive layer through the via hole;
  • a vertical distance between an upper surface of the semi-retained region of the insulating layer and an upper surface of the first conductive layer is less than an upper surface of the completely remaining region of the insulating layer and an upper surface of the first conductive layer The vertical distance.
  • the semi-reserved region completely surrounds the via region.
  • the material of the insulating layer is an organic material.
  • the material of the insulating layer is a photosensitive organic material.
  • the semi-reserved region has a width of from 1 ⁇ m to 6 ⁇ m.
  • a vertical distance between an upper surface of the semi-retained region of the insulating layer and an upper surface of the first conductive layer is less than or equal to an upper surface of the completely remaining region of the insulating layer and an upper surface of the first conductive layer Half of the vertical distance.
  • the insulating layer has a thickness in the completely remaining region of 2 ⁇ m to 3 ⁇ m.
  • the first conductive layer is the drain of the thin film transistor on the array substrate and the second conductive layer is the pixel electrode.
  • the embodiment of the present invention further provides a display panel, including any of the above array substrates provided by the embodiments of the present invention.
  • an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
  • the insulating layer including a via region, a semi-retained region outside the via region, and surrounding the semi-reserved region and the a completely reserved area of the area where the hole area is located, the via area including a via penetrating the insulating layer, a vertical surface between the upper surface of the semi-retained area of the insulating layer and the upper surface of the first conductive layer a distance that is less than a vertical distance between an upper surface of the completely remaining region of the insulating layer and an upper surface of the first conductive layer;
  • a second conductive layer is formed on the base substrate on which the insulating layer is formed, and the second conductive layer is electrically connected to the first conductive layer through the via.
  • forming the insulating layer on the base substrate on which the first conductive layer is formed includes forming an insulating layer on the base substrate on which the first conductive layer is formed by one patterning process.
  • the material of the insulating layer is a photosensitive organic material.
  • forming the insulating layer on the base substrate on which the first conductive layer is formed by one patterning process includes:
  • Forming the insulating layer film layer with the first mask forming a completely remaining region of the insulating layer at a region of the insulating layer film layer corresponding to the first region of the first mask, in the second with the first mask
  • a semi-retained region of the insulating layer is formed at a region of the insulating layer film layer corresponding to the region, and a via region of the insulating layer is formed at a region of the insulating layer film layer corresponding to the third region of the first mask.
  • the first mask is a halftone mask or a gray tone mask.
  • the photosensitive organic material is a positive photosensitive material
  • the first region of the first mask is a light-shielding region
  • the second region of the first mask is a partially transparent region
  • the third of the first mask The area is a completely transparent area.
  • the photosensitive organic material is a negative photosensitive material
  • the first region of the first mask is a completely transparent region
  • the second region of the first mask is a partially transparent region
  • the first mask The third area is a light-shielding area.
  • the semi-retained region outside the via region can reduce the thickness of the insulating layer around the via hole, not only the probability of the second conductive layer being broken at the edge of the via hole but also the probability of the second conductive layer being broken at the edge of the via hole can be reduced. It is also possible to avoid residual insulating layer material at the edge of the via.
  • the vertical distance between the upper surface of the semi-retained region and the upper surface of the first conductive layer is smaller than the vertical distance between the upper surface of the completely reserved region and the upper surface of the first conductive layer, the height difference of the insulating layer is made It is divided into two sections, which can reduce the influence of the step caused by the overall thickness of the insulation layer.
  • the semi-reserved region is disposed only outside the via region of the insulating layer, the other regions are still completely reserved regions, and thus the parasitic capacitance between the first conductive layer and the second conductive layer in the other regions is not increased.
  • 1a is a schematic view showing the application structure of a conventional organic insulating film layer
  • Figure 1b is a schematic cross-sectional view of the Figure 1a along the A-A' direction;
  • Figure 1c is a schematic cross-sectional view of Figure 1a along the B-B' direction;
  • FIGS. 2a and 2b are schematic top plan views of an array substrate according to an embodiment of the present invention.
  • FIG. 3a is a schematic cross-sectional view of the array substrate shown in FIG. 2a along the A-A' direction;
  • 3b is a schematic cross-sectional view of the array substrate shown in FIG. 2b along the A-A' direction;
  • FIG. 4a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4b is a schematic cross-sectional view of the array substrate shown in FIG. 4a along the A-A' direction;
  • FIG. 4c is a schematic cross-sectional view of the array substrate shown in FIG. 4a along the B-B' direction;
  • FIG. 5 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention.
  • the array substrate provided by the embodiment of the present invention is shown in Figures 2a, 2b, 3a and 3b.
  • the array substrate includes a base substrate 100, and a first conductive layer 101, an insulating layer 102, and a second conductive layer 103 which are sequentially disposed on the base substrate 100.
  • the insulating layer 102 includes a via region I, a semi-reserved region M located outside the via region I, and a completely reserved region O surrounding the region where the semi-reserved region M and the via region I are located.
  • the via region I includes a via hole penetrating the insulating layer 102, and the second conductive layer 103 is electrically connected to the first conductive layer 101 through the via hole.
  • the vertical distance h1 between the upper surface of the semi-retained region M of the insulating layer 102 and the upper surface of the first conductive layer 101 is smaller than the upper surface of the completely reserved region O of the insulating layer 102 and the first The vertical distance h2 between the upper surfaces of the conductive layers 101. That is, the thickness of the insulating layer 102 in the semi-retained region M is smaller than the thickness of the completely remaining region O.
  • the semi-reserved region M of the insulating layer 102 includes a land region and a ramp region adjacent the platform region.
  • the vertical distance between the upper surface of the land area and the upper surface of the first conductive layer 101 is less than the vertical distance between the upper surface of the completely reserved area O and the upper surface of the first conductive layer 101, and any of the upper surfaces of the sloped area
  • the vertical distance between the point and the upper surface of the first conductive layer 101 is smaller than the vertical distance between the upper surface of the completely remaining region O and the upper surface of the first conductive layer 101.
  • the specific shape of the semi-reserved area M is not limited to the shape shown in FIGS. 3a and 3b, and other shapes may be employed as long as the semi-reserved area can be reduced around the via hole.
  • the thickness of the edge layer can be.
  • the semi-retained region outside the via region can reduce the thickness of the insulating layer around the via hole, not only the probability of the second conductive layer being broken at the edge of the via hole but also the probability of the second conductive layer being broken at the edge of the via hole can be reduced. Residual insulation material can be avoided at the edge of the via.
  • the vertical distance between the upper surface of the semi-retained region and the upper surface of the first conductive layer is smaller than the vertical distance between the upper surface of the completely reserved region and the upper surface of the first conductive layer, the height difference of the insulating layer is made It is divided into two sections, which can reduce the influence of the step caused by the overall thickness of the insulation layer.
  • the semi-reserved region is disposed only outside the via region of the insulating layer, the other regions are still completely reserved regions, and thus the parasitic capacitance between the first conductive layer and the second conductive layer in the other regions is not increased.
  • the semi-reserved region M may completely surround the via region I.
  • the semi-reserved area M may partially surround the via-area I.
  • the size of the semi-reserved region may be traded off according to the aperture ratio required in the actual situation and the probability that the second conductive layer is broken at the edge of the via hole.
  • the width of the semi-retained region can be controlled between 1 ⁇ m and 6 ⁇ m. This is because when the width of the semi-reserved area is too wide, the range of black matrix occlusion in the existing array substrate may be exceeded, thereby reducing the aperture ratio of the array substrate. When the width of the semi-reserved area is too narrow, the current manufacturing process may not be realized, and the effect of reducing the step difference may be affected.
  • the material of the insulating layer is an organic material. This is because the insulating layer formed of the organic material is easy to achieve a thicker thickness in the process.
  • the material of the insulating layer may also be an inorganic material, which is not limited herein.
  • the material of the insulating layer is a photosensitive organic material.
  • the material of the insulating layer is a photosensitive organic material.
  • a vertical distance between an upper surface of the semi-retained region of the insulating layer and an upper surface of the first conductive layer is less than or equal to an upper surface of the completely remaining region of the insulating layer and an upper surface of the first conductive layer Half the vertical distance between.
  • the thickness of the insulating layer in the completely remaining region is generally 2 ⁇ m to 3 ⁇ m, which is not limited herein.
  • the above array substrate provided by the embodiment of the present invention is suitable for a structure in which any two conductive layers need to be electrically connected through via holes of an insulating layer between the two conductive layers, but the structure effect of the thicker insulating layer is particularly remarkable.
  • the first conductive layer is a drain of the thin film transistor on the array substrate
  • the second conductive layer is a pixel electrode, which is not limited herein.
  • the array substrate provided by the embodiment of the present invention may further include a data line, a gate line, a source, a gate, an active layer, a gate insulating layer, a passivation layer, a common electrode, and the like. structure. Since these layers and structures are known to those skilled in the art, they will not be described in detail herein.
  • the common electrode may be located above the pixel electrode or below the pixel electrode, which is not limited herein.
  • the base substrate 100 is sequentially provided with a gate line 110 and a gate electrode 111 disposed in the same layer, a gate insulating layer 112, an active layer 113, and a source disposed in the same layer (not shown in the figure). Shown), drain 114 and data line 115, insulating layer 102, and pixel electrode 116.
  • the insulating layer 102 includes a via region I, an annular semi-retained region M surrounding the via region I, and a completely reserved region O surrounding the semi-reserved region M.
  • the via region I includes a via hole penetrating the insulating layer 102.
  • FIG. 4b is a schematic cross-sectional view of Figure 4a taken along the line A-A'. As shown in FIG.
  • Figure 4c is a schematic cross-sectional view of Figure 4a taken along line B-B'. As shown in FIG. 4c, although the insulating layer 102 is thick, since the periphery of the via region I is a semi-retained region M, the thickness of the insulating layer 102 around the via hole is lowered, so that not only the pixel electrode 116 can be reduced at the edge of the via hole.
  • the probability of fracture, and also the material of the insulating layer 102 remaining at the edge of the via can be avoided.
  • the semi-reserved area M is provided between the via area I and the completely reserved area O, and the thickness of the semi-reserved area M is smaller than the thickness of the completely reserved area O,
  • the height section of the insulating layer 102 is made to be divided into two sections, so that the influence of the step caused by the overall thickness of the insulating layer 102 can be reduced.
  • a semi-retained region is provided outside the via region of the insulating layer.
  • the semi-reserved area reduces the probability of breakage of the pixel electrode, if the semi-reserved area is located in the liquid crystal pixel area, the flipping of the liquid crystal molecules is affected at the time of display. Therefore, in order to avoid affecting the inversion of the liquid crystal molecules, the semi-retained region may be set to a semi-surrounding via region, and the semi-retained region may be located on a side of the via region away from the pixel region.
  • the black matrix will exceed the edge of the via region by 3 ⁇ m. Therefore, in order to ensure that the semi-reserved area does not exceed the coverage of the black matrix, the width of the semi-reserved area does not exceed 3 ⁇ m.
  • the present invention is not limited thereto.
  • An array substrate in which a common electrode is disposed between the pixel electrode and the insulating layer may also be employed.
  • a common electrode 117 is provided between the insulating layer 102 and the pixel electrode 116.
  • a passivation layer 118 is disposed between the common electrode 117 and the pixel electrode 116.
  • the common electrode 117 and the passivation layer 118 are each provided with a via hole at a region corresponding to the via region I of the insulating layer 102.
  • the pixel electrode 116 and the drain electrode 114 are electrically connected by via holes penetrating the passivation layer 118, the common electrode 117, and the insulating layer 102.
  • the common electrode 117 in order to prevent the common electrode 117 from being short-circuited with the pixel electrode 116, the common electrode 117 generally needs a distance of 3 ⁇ m from the outer side of the via region I of the insulating layer 102. At this time, there is a process range of 3 ⁇ m between the black matrix and the edge of the common electrode 117 on the process. That is, the black matrix should cover at least the width of the common electrode 117 of 3 ⁇ m. Therefore, in this case, in order to ensure that the semi-reserved area does not exceed the coverage of the black matrix, the width of the semi-reserved area does not exceed 6 ⁇ m.
  • an embodiment of the present invention further provides a display panel, including any of the above array substrates provided by the embodiments of the present invention.
  • the principle of the display panel is similar to that of any of the foregoing array substrates. Therefore, the implementation of the display panel can be referred to the implementation of the foregoing array substrate, and the repeated description is omitted.
  • an embodiment of the present invention further provides a method of fabricating an array substrate. As shown in FIG. 6, the method may include the following steps:
  • the via region includes a via hole penetrating the insulating layer, and a vertical distance between an upper surface of the semi-retained region of the insulating layer and an upper surface of the first conductive layer is smaller than an upper surface of the completely remaining region of the insulating layer and the first conductive region The vertical distance between the upper surfaces of the layers;
  • the semi-retained area outside the via area can reduce the thickness of the insulating layer around the via hole, not only the probability of the second conductive layer being broken at the edge of the via hole but also the residual insulating layer material at the edge of the via hole can be avoided.
  • the vertical distance between the upper surface of the semi-retained region and the upper surface of the first conductive layer is smaller than the vertical distance between the upper surface of the completely reserved region and the upper surface of the first conductive layer, the height difference of the insulating layer is made It is divided into two sections, which can reduce the influence of the step caused by the overall thickness of the insulation layer.
  • the semi-reserved region is disposed only outside the via region of the insulating layer, the other regions are still completely reserved regions, and thus the parasitic capacitance between the first conductive layer and the second conductive layer in the other regions is not increased.
  • forming the insulating layer on the substrate formed with the first conductive layer may include:
  • An insulating layer is formed on the base substrate on which the first conductive layer is formed by one patterning process.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may further include printing, inkjet, etc.
  • Other processes for forming a predetermined pattern refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • a corresponding patterning process can be selected according to the structure to be formed.
  • forming the insulating layer on the substrate formed with the first conductive layer by one patterning process may include:
  • the first mask may be, for example, a halftone mask or a gray tone mask.
  • the first region of the first mask is a light-shielding region
  • the second region is a partially transparent region
  • the third region is a completely transparent region.
  • the material of the photoresist layer is a negative photoresist
  • the first region of the first mask is a completely transparent region
  • the second region is a partially transparent region
  • the third region is a light shielding region.
  • the insulating layer can be formed by one patterning process, whereby the number of masks can be reduced, thereby reducing the cost.
  • the insulating layer may also be formed by two patterning processes, which is not limited herein.
  • forming the insulating layer on the substrate substrate on which the first conductive layer is formed may include:
  • the insulating layer film layer is secondarily patterned by the third mask, and a semi-retained region and a completely reserved region of the insulating layer are formed in the first remaining region of the insulating layer.
  • the insulating layer is a photosensitive organic material
  • the insulating layer since the insulating layer itself has a photosensitive property, the insulating layer can be multiplexed into a photoresist layer, so that not only the photoresist can be avoided when patterning the insulating layer. Use, and can simplify the process.
  • the material of the insulating layer is a photosensitive organic material.
  • Forming the insulating layer on the base substrate on which the first conductive layer is formed by one patterning process may include:
  • Forming the insulating layer film layer with the first mask forming a completely remaining region of the insulating layer at a region of the insulating layer film layer corresponding to the first region of the first mask, in the second with the first mask
  • the first mask may be, for example, a halftone mask or a gray tone mask.
  • Patterning the insulating layer film layer with the first mask may include, for example, patterning the insulating layer film by exposure and development using the first mask.
  • the first region of the first mask is a light-shielding region
  • the second region is a partially light-transmitting region
  • the third region is a completely light-transmitting region.
  • the first region of the first mask is a completely transparent region
  • the second region is a partially transparent region
  • the third region is a light shielding region
  • the method of fabricating the array substrate may further include the steps of forming a data line, a gate line, a source, a gate, an active layer, a gate insulating layer, a passivation layer, a common electrode, and the like. Since these steps are known to those skilled in the art, they are not described in detail herein.
  • the manufacturing process of the above array substrate provided by the embodiment of the present invention is specifically described below by taking the array substrate shown in FIG. 4a as an example.
  • the manufacturing process may specifically include the following steps:
  • the material of the gate insulating layer may be, for example, SiNx;
  • the insulating layer includes a via region, an annular semi-retained region surrounding the via region, and a completely reserved region surrounding the semi-retained region, the via region including a via hole penetrating the insulating layer, and a semi-reserved region of the insulating layer a vertical distance between the upper surface and the upper surface of the first conductive layer is less than a vertical distance between the upper surface of the completely remaining region of the insulating layer and the upper surface of the first conductive layer;
  • the pixel electrode is formed by one patterning process, and the pixel electrode is electrically connected to the drain through a via hole in the insulating layer.
  • forming the insulating layer by one patterning process may include: first forming an insulating layer, and then patterning the insulating layer by using a first mask such as a halftone mask or a gray tone mask, A completely remaining region of the insulating layer is formed at a region of the insulating layer film layer corresponding to the first region of the first mask, and a half of the insulating layer is formed at a region of the insulating layer film corresponding to the second region of the first mask Reserved area; in the first cover A via region of the insulating layer is formed at a region of the insulating layer film layer corresponding to the third region of the template.
  • a first mask such as a halftone mask or a gray tone mask
  • the first region of the first mask is a light-shielding region
  • the second region is a partially light-transmitting region
  • the third region is a completely light-transmitting region.
  • the photosensitive organic material is a negative photosensitive material
  • the first region of the first mask is a completely transparent region
  • the second region is a partially transparent region
  • the third region is a light shielding region.
  • the thickness of the insulating layer of the completely remaining region is controlled to about 2 ⁇ m, and the thickness of the insulating layer of the semi-retained region is controlled to be less than or equal to 1 ⁇ m.
  • the width and thickness of the insulating layer of the semi-retained region can be controlled by the light transmittance and the total exposure amount of the second region of the first mask.
  • the method may further include a step of forming a passivation layer over the pixel electrode, and forming a common electrode on the passivation layer, which is not limited herein.
  • the manufacturing method thereof and the display panel provided by the embodiments of the present invention since the semi-retained region outside the via region can reduce the thickness of the insulating layer around the via hole, the second conductive layer can be reduced not only at the edge of the via hole. The probability of breakage occurs, and the insulation material remains at the edge of the via.
  • the vertical distance between the upper surface of the semi-retained region and the upper surface of the first conductive layer is smaller than the vertical distance between the upper surface of the completely reserved region and the upper surface of the first conductive layer, the height difference of the insulating layer is made It is divided into two sections, which can reduce the influence of the step caused by the overall thickness of the insulation layer.
  • the semi-reserved region is disposed only outside the via region of the insulating layer, the other regions are still completely reserved regions, and thus the parasitic capacitance between the first conductive layer and the second conductive layer in the other regions is not increased.

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Abstract

一种阵列基板及其制造方法以及显示面板，所述阵列基板包括衬底基板（100），依次位于所述衬底基板（100）上的第一导电层（101）、绝缘层（102）和第二导电层（103），绝缘层（102）包括过孔区域（I）、位于过孔区域（I）外侧的半保留区域（M）、以及包围半保留区域（M）和过孔区域（I）所在的区域的完全保留区域（O）。由于过孔区域（I）周围是半保留区域（M），降低了过孔周围绝缘层（102）的厚度，因此能够降低过孔边缘残留绝缘层材料的影响。另外，由于绝缘层（102）的高度段差分为两段，因此可以降低绝缘层（102）整体厚度造成的段差影响。

Description

阵列基板及其制造方法以及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、其制造方法以及显示面板。
背景技术
在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)生产工艺中，由于有机绝缘膜层容易形成较厚的膜层而具有可以减小阵列基板中的信号干扰、减小寄生电容、降低基板负载从而降低功耗等优点，因此有机绝缘膜层被广泛应用。通常，有机绝缘膜层设置于两个导电膜层之间，例如设置于源漏电极层和像素电极层之间。为了使像素电极与薄膜晶体管的漏极电连接，需要在有机绝缘膜层中形成过孔(Via Hole)。
图1a为现有技术中有机绝缘膜层的应用结构示意图。图1b为图1a沿A-A’方向的剖面结构示意图。图1c为图1a沿B-B’方向的剖面结构示意图。如图1a-1c所示，衬底基板10上设置有由有源层11、栅极(图中未示出)、源极(图中未示出)和漏极12组成的薄膜晶体管，数据线13、栅线14和像素电极15。像素电极15与漏极12之间设置有有机绝缘膜层16。像素电极15通过贯穿有机绝缘膜层16的过孔V与漏极12电连接。数据线13、源极以及漏极12同层设置。如图1b所示，由于有机绝缘膜层16较厚，数据线13和像素电极15之间的寄生电容较小，因此画面品质好。如图1c所示，由于有机绝缘膜层16较厚，导致过孔V较深(例如可达2μm)，因此容易发生使过孔V侧面搭接的像素电极15发生断裂以及由于有机绝缘膜层16的段差大导致的后续取向膜摩擦取向不均匀等不良问题。
发明内容
因此，所期望的是能够改善由于现有阵列基板中绝缘层的过孔深所产生的不良问题。
本发明实施例提供了一种阵列基板，包括衬底基板，依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层，所述绝缘层包括 过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域；其中，
所述过孔区域包括贯穿所述绝缘层的过孔，且所述第二导电层通过所述过孔与所述第一导电层电连接；
所述绝缘层的半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离。
根据另一实施例，半保留区域完全包围过孔区域。
根据另一实施例，绝缘层的材料为有机材料。
根据另一实施例，绝缘层的材料为感光性有机材料。
根据另一实施例，半保留区域的宽度为1μm～6μm。
根据另一实施例，绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于或等于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离的一半。
根据另一实施例，绝缘层在完全保留区域的厚度为2μm～3μm。
根据另一实施例，第一导电层为阵列基板上的薄膜晶体管的漏极，第二导电层为像素电极。
相应地，本发明实施例还提供了一种显示面板，包括本发明实施例提供的上述任一种阵列基板。
相应地，本发明实施例还提供了一种阵列基板的制造方法，包括：
在衬底基板上形成第一导电层；
在形成有所述第一导电层的衬底基板上形成绝缘层，所述绝缘层包括过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域，所述过孔区域包括贯穿所述绝缘层的过孔，所述绝缘层的半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离；
在形成有所述绝缘层的衬底基板上形成第二导电层，所述第二导电层通过所述过孔与所述第一导电层电连接。
根据另一实施例，在形成有第一导电层的衬底基板上形成绝缘层包括：通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层。
根据另一实施例，绝缘层的材料为感光性有机材料。
根据另一实施例，通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层包括：
在形成有第一导电层的衬底基板上形成绝缘层膜层；
利用第一掩膜板对绝缘层膜层进行构图，在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域，在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域，在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域。
根据另一实施例，第一掩膜板为半色调掩模板或灰色调掩模板。
根据另一实施例，感光性有机材料为正性感光材料，并且第一掩模板的第一区域为遮光区域，第一掩模板的第二区域为部分透光区域，第一掩模板的第三区域为完全透光区域。
根据另一实施例，感光性有机材料为负性感光材料，并且第一掩模板的第一区域为完全透光区域，第一掩模板的第二区域为部分透光区域，第一掩模板的第三区域为遮光区域。
在本发明实施例提供的上述阵列基板中，由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度，因此，不仅可以降低第二导电层在过孔边缘发生断裂的概率，而且还可以避免过孔边缘残留绝缘层材料。另外，由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离，因此使得绝缘层的高度段差分为两段，从而可以降低绝缘层整体厚度造成的段差影响。并且，由于半保留区域仅是设置在绝缘层的过孔区域外侧，其它区域仍为完全保留区域，因此不会增加其它区域第一导电层与第二导电层之间的寄生电容。
附图说明
图1a为现有的有机绝缘膜层的应用结构示意图；
图1b为图1a沿A-A’方向的剖面结构示意图；
图1c为图1a沿B-B’方向的剖面结构示意图；
图2a和图2b分别为本发明实施例提供的阵列基板的俯视结构示意图；
图3a为图2a所示阵列基板沿A-A’方向的剖面结构示意图；
图3b为图2b所示阵列基板沿A-A’方向的剖面结构示意图；
图4a为本发明实施例提供的阵列基板的具体结构示意图；
图4b为图4a所示阵列基板沿A-A’方向的剖面结构示意图；
图4c为图4a所示阵列基板沿B-B’方向的剖面结构示意图；
图5为本发明实施例提供的阵列基板的剖面结构示意图；
图6为本发明实施例提供的阵列基板的制造方法的流程图。
具体实施方式
为了使本发明的目的，技术方案和优点更加清楚，下面结合附图，对本发明实施例提供的阵列基板、其制造方法及显示面板的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。
本发明实施例提供的阵列基板如图2a、2b、3a和3b所示。阵列基板包括衬底基板100，依次位于衬底基板100上的第一导电层101、绝缘层102和第二导电层103。绝缘层102包括过孔区域I、位于过孔区域I外侧的半保留区域M、以及包围半保留区域M和过孔区域I所在的区域的完全保留区域O。过孔区域I包括贯穿绝缘层102的过孔，且第二导电层103通过该过孔与第一导电层101电连接。
如图3a和图3b所示，绝缘层102的半保留区域M的上表面与第一导电层101的上表面之间的垂直距离h1小于绝缘层102的完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离h2。即，绝缘层102在半保留区域M的厚度小于完全保留区域O的厚度。
更具体而言，在图3a和图3b所示的实施例中，绝缘层102的半保留区域M包括平台区域以及与该平台区域邻接的斜坡区域。平台区域的上表面与第一导电层101的上表面之间的垂直距离小于完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离，并且斜坡区域的上表面的任何一点与第一导电层101的上表面之间的垂直距离小于完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离。当然，半保留区域M的具体形状并不限于图3a和3b所示的形状，也可以采用其它形状，只要该半保留区域可以降低过孔周围绝 缘层的厚度即可。
在本发明实施例提供的上述阵列基板中，由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度，因此不仅可以降低第二导电层在过孔边缘发生断裂的概率，而且还可以避免过孔边缘残留绝缘层材料。另外，由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离，因此使得绝缘层的高度段差分为两段，从而可以降低绝缘层整体厚度造成的段差影响。并且，由于半保留区域仅是设置在绝缘层的过孔区域外侧，其它区域仍为完全保留区域，因此不会增加其它区域第一导电层与第二导电层之间的寄生电容。
在具体实施时，为了最大限度的降低第二导电层在过孔边缘发生断裂的概率，如图2b所示，半保留区域M可以完全包围过孔区域I。但是，由于设置半保留区域可能会降低阵列基板的开口率，因此，从开口率的角度考虑，如图2a所示，半保留区域M可以半包围过孔区域I。在具体实施时，可以根据实际情况中所需的开口率和第二导电层在过孔边缘发生断裂的概率来折衷确定半保留区域的大小。
在具体实施时，半保留区域的宽度可以控制在1μm～6μm之间。这是因为，当半保留区域的宽度太宽时，可能会超出现有阵列基板中黑矩阵遮挡的范围，从而降低阵列基板的开口率。而当半保留区域的宽度太窄时，目前的制作工艺可能不能实现，并且会影响减小段差的效果。
根据另一实施例，绝缘层的材料为有机材料。这是因为有机材料形成的绝缘层在工艺上容易实现较厚的厚度。当然，在具体实施时，绝缘层的材料也可以为无机材料，在此不作限定。
进一步地，绝缘层的材料为感光性有机材料。这样，在制造绝缘层的图形时，不需要单独再涂覆光刻胶层。利用绝缘层自身的感光性复用光刻胶层，可以降低制造成本。
在具体实施时，在半保留区域面积固定的情况下，半保留区域的厚度越小，第二导电层在过孔边缘发生断裂的概率也就越小。因此，根据另一实施例，绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于或等于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离的一半。
根据另一实施例，绝缘层在完全保留区域的厚度一般为2μm～3μm，在此不作限定。
本发明实施例提供的上述阵列基板适用于任何两导电层之间需要通过位于该两导电层之间的绝缘层的过孔电连接的结构，但是针对绝缘层厚度较厚的结构效果尤为显著。
在具体实施时，第一导电层为阵列基板上的薄膜晶体管的漏极，第二导电层为像素电极，在此不作限定。
一般地，在具体实施时，本发明实施例提供的阵列基板还可以包括数据线、栅线、源极、栅极、有源层、栅极绝缘层、钝化层、公共电极等膜层和结构。由于这些膜层和结构均为本领域技术人员所知，因此在此不作详述。
在具体实施时，公共电极可以位于像素电极上方，也可以位于像素电极的下方，在此不作限定。
下面通过一个具体实施例说明本发明实施例提供的上述阵列基板。如图4a至图4c所示，衬底基板100上依次设置有同层设置的栅线110和栅极111，栅极绝缘层112，有源层113，同层设置的源极(图中未示出)、漏极114和数据线115，绝缘层102，以及像素电极116。绝缘层102包括过孔区域I、包围过孔区域I的环状的半保留区域M、以及包围半保留区域M的完全保留区域O。过孔区域I包括贯穿绝缘层102的过孔。绝缘层102的半保留区域M的上表面与第一导电层101的上表面之间的垂直距离小于绝缘层102的完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离。即，绝缘层102在半保留区域M的厚度小于完全保留区域O的厚度。像素电极116通过过孔与漏极114电连接。图4b为图4a沿A-A’方向的剖面结构示意图。如图4b所示，由于绝缘层102较厚，因此位于绝缘层102两侧的导电层(例如数据线115与像素电极116)之间的寄生电容较小，从而使得画面品质好。图4c为图4a沿B-B’方向的剖面结构示意图。如图4c所示，虽然绝缘层102较厚，但由于过孔区域I周围是半保留区域M，降低了过孔周围绝缘层102的厚度，因此，不仅可以降低像素电极116在过孔边缘发生断裂的概率，而且还可以避免过孔边缘残留绝缘层102的材料。另外，由于在过孔区域I与完全保留区域O之间设置有半保留区域M，且半保留区域M的厚度小于完全保留区域O的厚度，因此 使得绝缘层102的高度段差分为两段，从而可以降低绝缘层102整体厚度造成的段差影响。
在上述阵列基板中，在绝缘层的过孔区域外侧设置了半保留区域。虽然半保留区域会降低像素电极发生断裂的概率，但是如果半保留区域位于液晶像素区域，则会在显示时影响液晶分子的翻转。因此，为了避免影响液晶分子的翻转，可以将半保留区域设置为半包围过孔区域，且半保留区域位于过孔区域的远离像素区域的一侧。
进一步地，在上述阵列基板中，在工艺上黑矩阵一般与过孔区域边缘之间有3μm的工艺范围。即，黑矩阵会超出过孔区域边缘3μm。因此，为了保证半保留区域不超出黑矩阵的覆盖范围，半保留区域的宽度不超过3μm。
尽管上述阵列基板是以像素电极直接通过绝缘层与漏极电连接为例进行说明的，但是本发明不限于此。也可以采用将公共电极设置于像素电极与绝缘层之间的阵列基板。
具体地，如图5所示，在绝缘层102与像素电极116之间设置有公共电极117。在公共电极117与像素电极116之间设置有钝化层118。公共电极117和钝化层118在与绝缘层102的过孔区域I对应的区域处均设置有过孔。像素电极116与漏极114通过贯穿钝化层118、公共电极117和绝缘层102的过孔实现电连接。
进一步地，在上述阵列基板中，为了避免公共电极117与像素电极116发生短路，公共电极117距绝缘层102的过孔区域I的外侧一般需要有3μm的距离。这时，在工艺上黑矩阵一般与公共电极117边缘之间有3μm的工艺范围。即，黑矩阵要至少覆盖公共电极117的宽度为3μm。因此，在这种情况下，为了保证半保留区域不超出黑矩阵的覆盖范围，半保留区域的宽度不超过6μm。
基于同一发明构思，本发明实施例还提供了一种显示面板，包括本发明实施例提供的上述任一种阵列基板。由于该显示面板解决问题的原理与前述任一种阵列基板相似，因此该显示面板的实施可以参见前述阵列基板的实施，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种阵列基板的制造方法。如图6所示，该方法可以包括以下步骤：
S601、在衬底基板上形成第一导电层；
S602、在形成有第一导电层的衬底基板上形成绝缘层，绝缘层包括过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域，过孔区域包括贯穿绝缘层的过孔，且绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离；
S603、在形成有绝缘层的衬底基板上形成第二导电层，第二导电层通过过孔与第一导电层电连接。
由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度，因此不仅可以降低第二导电层在过孔边缘发生断裂的概率，而且还可以避免过孔边缘残留绝缘层材料。另外，由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离，因此使得绝缘层的高度段差分为两段，从而可以降低绝缘层整体厚度造成的段差影响。并且，由于半保留区域仅是设置在绝缘层的过孔区域外侧，其它区域仍为完全保留区域，因此不会增加其它区域第一导电层与第二导电层之间的寄生电容。
在具体实施时，在形成有第一导电层的衬底基板上形成绝缘层可以包括：
通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层。
需要说明的是，在本发明实施例提供的上述阵列基板的制造方法中，构图工艺可以只包括光刻工艺，或者，可以包括光刻工艺以及刻蚀步骤，并且还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。在具体实施时，可根据所要形成的结构选择相应的构图工艺。
在具体实施时，通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层可以包括：
在形成有第一导电层的衬底基板上形成绝缘层膜层；
在绝缘层膜层上形成光刻胶层；
利用第一掩膜板对光刻胶层进行曝光显影以在光刻胶层上定义出 绝缘层的图形，以该具有绝缘层的图形的光刻胶层为掩膜，对绝缘层进行刻蚀，在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域，在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域；在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域。
第一掩模板例如可以为半色调掩模板或灰色调掩模板。
当光刻胶层的材料为正性光刻胶时，第一掩模板的第一区域为遮光区域，第二区域为部分透光区域，第三区域为完全透光区域。当光刻胶层的材料为负性光刻胶时，第一掩模板的第一区域为完全透光区域，第二区域为部分透光区域，第三区域为遮光区域。
这样，通过一次构图工艺就能够形成绝缘层，由此可以减少掩膜板(Mask)的数目，从而降低成本。当然，在具体实施时，也可以通过两次构图工艺形成绝缘层，在此不作限定。
具体地，当通过两次构图工艺形成绝缘层时，在形成有第一导电层的衬底基板上形成绝缘层可以包括：
在形成有第一导电层的衬底基板上形成绝缘层膜层；
利用第二掩膜板对绝缘层膜层进行一次构图，形成绝缘层的过孔区域和绝缘层的第一保留区域；
利用第三掩膜板对绝缘层膜层进行二次构图，在绝缘层的第一保留区域中形成绝缘层的半保留区域和完全保留区域。
在具体实施时，不管是采用一次掩膜板，还是采用两次掩膜板，一般均需要利用光刻胶进行构图。但是，当绝缘层的材料为感光性有机材料时，由于绝缘层自身具有感光性能，因此可以将绝缘层复用为光刻胶层，从而不仅可以在对绝缘层进行构图时避免光刻胶的使用，而且可以简化工艺。
因此，根据另一实施例，绝缘层的材料为感光性有机材料。通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层可以包括：
在形成有第一导电层的衬底基板上形成绝缘层膜层；
利用第一掩膜板对绝缘层膜层进行构图，在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域，在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留 区域；在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域。
第一掩模板例如可以为半色调掩模板或灰色调掩模板。利用第一掩膜板对绝缘层膜层进行构图例如可以包括利用第一掩膜板通过曝光和显影对绝缘层膜层进行构图。
当感光性有机材料为正性感光材料时，第一掩模板的第一区域为遮光区域，第二区域为部分透光区域，第三区域为完全透光区域。
当感光性有机材料为负性感光材料时，第一掩模板的第一区域为完全透光区域，第二区域为部分透光区域，第三区域为遮光区域。
一般地，在具体实施时，阵列基板的制造方法还可以包括形成数据线、栅线、源极、栅极、有源层、栅极绝缘层、钝化层、公共电极等的步骤。由于这些步骤为本领域技术人员所知，因此在此不作详述。
下面通过以图4a所示阵列基板为例具体说明本发明实施例提供的上述阵列基板的制造过程。该制造过程具体可以包括以下步骤：
(1)在衬底基板上通过一次构图工艺形成栅极和栅线；
(2)沉积栅极绝缘层，栅极绝缘层的材料例如可以为SiNx；
(3)通过一次构图工艺形成有源层；
(4)通过一次构图工艺形成数据线、源极和漏极；
(5)通过一次构图工艺形成绝缘层，该绝缘层的材料为感光性有机材料，
绝缘层包括过孔区域、包围该过孔区域的环状的半保留区域、以及包围该半保留区域的完全保留区域，过孔区域包括贯穿绝缘层的过孔，且绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离；
(6)通过一次构图工艺形成像素电极，像素电极通过绝缘层中的过孔与漏极电连接。
在具体实施时，通过一次构图工艺形成绝缘层可以包括：先形成绝缘层膜层，再利用例如为半色调掩模板或灰色调掩模板的第一掩膜板对绝缘层膜层进行构图，在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域，在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域；在与第一掩 模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域。
当感光性有机材料为正性感光材料时，第一掩模板的第一区域为遮光区域，第二区域为部分透光区域，第三区域为完全透光区域。当感光性有机材料为负性感光材料时，第一掩模板的第一区域为完全透光区域，第二区域为部分透光区域，第三区域为遮光区域。
进一步地，完全保留区域的绝缘层的厚度控制在2μm左右，半保留区域的绝缘层的厚度控制在小于或等于1μm。
具体地，半保留区域的绝缘层的宽度和厚度都可以通过第一掩膜板的第二区域的透光率和总曝光量进行控制。
当然，在具体实施时，在步骤(6)之后，该方法还可以包括在像素电极上方形成钝化层，以及在钝化层上形成公共电极等步骤，在此不作限定。
在本发明实施例提供的上述阵列基板、其制造方法以及显示面板中，由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度，因此不仅可以降低第二导电层在过孔边缘发生断裂的概率，而且还可以避免过孔边缘残留绝缘层材料。另外，由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离，因此使得绝缘层的高度段差分为两段，从而可以降低绝缘层整体厚度造成的段差影响。并且，由于半保留区域仅是设置在绝缘层的过孔区域外侧，其它区域仍为完全保留区域，因此不会增加其它区域第一导电层与第二导电层之间的寄生电容。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

  1. 一种阵列基板，包括衬底基板，依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层，其中，所述绝缘层包括过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域；其中，
    所述过孔区域包括贯穿所述绝缘层的过孔，且所述第二导电层通过所述过孔与所述第一导电层电连接；
    所述绝缘层的半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离。
  2. 如权利要求1所述的阵列基板，其中，所述半保留区域完全包围所述过孔区域。
  3. 如权利要求1所述的阵列基板，其中，所述绝缘层的材料为有机材料。
  4. 如权利要求3所述的阵列基板，其中，所述绝缘层的材料为感光性有机材料。
  5. 如权利要求1所述的阵列基板，其中，所述半保留区域的宽度为1μm～6μm。
  6. 如权利要求1所述的阵列基板，其中，所述绝缘层的半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于或等于所述绝缘层的完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离的一半。
  7. 如权利要求1所述的阵列基板，其中，所述绝缘层在所述完全保留区域的厚度为2μm～3μm。
  8. 如权利要求1-7中任一项所述的阵列基板，其中，所述第一导电层为所述阵列基板上的薄膜晶体管的漏极，所述第二导电层为像素电极。
  9. 一种显示面板，包括如权利要求1-8中任一项所述的阵列基板。
  10. 一种阵列基板的制造方法，包括：
    在衬底基板上形成第一导电层；
    在形成有所述第一导电层的衬底基板上形成绝缘层，所述绝缘层 包括过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域，所述过孔区域包括贯穿所述绝缘层的过孔，所述绝缘层的半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离；
    在形成有所述绝缘层的衬底基板上形成第二导电层，所述第二导电层通过所述过孔与所述第一导电层电连接。
  11. 如权利要求10所述的制造方法，其中，在形成有所述第一导电层的衬底基板上形成绝缘层包括：
    通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层。
  12. 如权利要求11所述的制造方法，其中，所述绝缘层的材料为感光性有机材料。
  13. 如权利要求12所述的制造方法，其中，通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层包括：
    在形成有所述第一导电层的衬底基板上形成绝缘层膜层；
    利用第一掩膜板对所述绝缘层膜层进行构图，在与所述第一掩模板的第一区域对应的所述绝缘层膜层的区域处形成所述绝缘层的完全保留区域，在与所述第一掩模板的第二区域对应的所述绝缘层膜层的区域处形成所述绝缘层的半保留区域，在与所述第一掩模板的第三区域对应的所述绝缘层膜层的区域处形成所述绝缘层的过孔区域。
  14. 如权利要求13所述的制造方法，其中，所述第一掩膜板为半色调掩模板或灰色调掩模板。
  15. 如权利要求13所述的制造方法，其中，所述感光性有机材料为正性感光材料，并且所述第一掩模板的第一区域为遮光区域，所述第一掩模板的第二区域为部分透光区域，所述第一掩模板的第三区域为完全透光区域。
  16. 如权利要求13所述的制造方法，其中，所述感光性有机材料为负性感光材料，并且所述第一掩模板的第一区域为完全透光区域，所述第一掩模板的第二区域为部分透光区域，所述第一掩模板的第三区域为遮光区域。
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