WO2014205998A1 - Coa基板及其制造方法、显示装置 - Google Patents

Coa基板及其制造方法、显示装置 Download PDF

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Publication number
WO2014205998A1
WO2014205998A1 PCT/CN2013/087973 CN2013087973W WO2014205998A1 WO 2014205998 A1 WO2014205998 A1 WO 2014205998A1 CN 2013087973 W CN2013087973 W CN 2013087973W WO 2014205998 A1 WO2014205998 A1 WO 2014205998A1
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Prior art keywords
color film
layer
substrate
photoresist
forming
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PCT/CN2013/087973
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English (en)
French (fr)
Inventor
惠官宝
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京东方科技集团股份有限公司
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Priority to US14/385,273 priority Critical patent/US9274368B2/en
Publication of WO2014205998A1 publication Critical patent/WO2014205998A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G02F1/133516—Methods for their manufacture, e.g. printing, electro-deposition or photolithography
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to a COA substrate, a manufacturing method thereof, and a display device. Background technique
  • the thin film transistor liquid crystal display comprises a thin film transistor array substrate, a color filter substrate and a liquid crystal layer, wherein the color film substrate is a main component of the liquid crystal display and is used for realizing display of a color picture.
  • a color film layer and a thin film transistor as a driving switch are formed on different substrates and located on both sides of the liquid crystal layer.
  • this arrangement causes a decrease in the aperture ratio of the display panel, thereby affecting the display.
  • the brightness and picture quality of the panel In recent years, the market demand for the aperture ratio and brightness of the display panel has increased, and the industry has developed a color film layer directly formed on the array substrate (Color Filter On Array, called "COA").
  • the technology that is, the color film layer and the thin film transistor are formed on one substrate, so that not only the aperture ratio of the display panel can be increased, the brightness of the display panel is increased, but also the problem of forming the color film layer and the thin film transistor on different substrates is avoided. .
  • the COA substrate includes a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines, each of the pixel units including a thin film transistor ("Thin Film Transistor"), a color film layer 6, and a pixel electrode 7,
  • the color film layer 6 is generally formed of three color organic resin layers of red, green, and blue (R, G, B), and a resin flat layer (not shown) is formed on the surface of the organic resin layer.
  • the pixel electrode 7 is electrically connected to the drain electrode 12 of the TFT through the color filter via 5'.
  • the size of pixel units of display panels is getting smaller and smaller.
  • the size of pixel units is generally around 25 ⁇ 25 ⁇ .
  • the aperture size of the color filter via 5' formed by the conventional mask exposure and development process is large, and the maximum aperture size is also large, wherein the aperture size is changed by about 8 ⁇ m, and the maximum aperture is
  • the embodiment of the invention provides a method for manufacturing a OLED substrate, which is used to solve the problem that the maximum aperture size of the color filter via hole formed by the conventional process is large, and the aperture size variation is also large, which seriously affects the aperture ratio of the pixel unit.
  • a method for fabricating a color filter array substrate includes: forming a thin film transistor on a substrate substrate;
  • a COA substrate manufactured by the manufacturing method as described above.
  • a display device comprising the COA substrate as described above.
  • FIG. 1 is a schematic structural view of a COA substrate in the prior art
  • FIG. 2 is a schematic structural view 1 of a COA substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view 2 of a COA substrate according to an embodiment of the present invention.
  • 4 to 11 are schematic views showing a manufacturing process of the COA substrate in FIG. 2;
  • 1 village substrate; 2: gate electrode; 3: gate insulating layer; 4: active layer pattern; 5, 5': color film via; 6: color film layer; 7: pixel electrode; 9: common electrode; 10: thin film transistor; 11: source electrode; 12: drain electrode; 13: photoresist; 14: transparent protective layer; 15: protective layer via.
  • Embodiments of the present invention provide a method of fabricating a color filter array substrate that can reduce the amount of change in aperture size and the maximum aperture size of a color filter via.
  • the method for manufacturing a COA substrate in the embodiment of the present invention includes the following steps:
  • a thin film transistor 10 is first formed on a substrate 1 on a substrate.
  • the substrate substrate 1 is made of a light-transmitting material and has good light transmittance, and is usually a glass substrate, a quartz substrate or a transparent resin substrate.
  • the COA substrate includes a substrate 1 on which a plurality of matrix-arranged pixel cells are formed, each of the pixel cells including at least one thin film transistor.
  • the thin film transistor may be a thin film transistor of a top gate structure or a thin film transistor of a bottom gate structure.
  • the thin film transistor of the bottom gate structure is taken as an example to specifically describe the formation process of the thin film transistor:
  • a pattern including the gate electrode 2 is formed on the substrate substrate 1.
  • a gate metal layer film (not shown) may be formed on the substrate 1 by a process such as vapor deposition, sputtering, or the like, and a pattern of the gate electrode 2 is formed on the gate metal film by a patterning process.
  • the patterning process includes, for example, a process of coating a photoresist on a gate metal layer film, exposing, developing, etching, stripping, or the like using a common mask, wherein etching is preferably performed by wet etching;
  • a gate insulating film 3 and an active layer film are sequentially formed on the pattern including the gate electrode 2 (Fig. And a source/drain metal layer film (not shown), wherein the active layer film comprises a semiconductor layer film and a doped semiconductor layer film, and the doped semiconductor layer film is located above the semiconductor layer film.
  • a pattern including the source electrode 11 and the drain electrode 12 may be separately formed by a plurality of patterning processes, or a pattern including the source electrode 11 and the drain electrode 12 may be simultaneously formed by one patterning process. Forming the patterns of the source electrode 11 and the drain electrode 12 by a plurality of patterning processes includes, for example:
  • a gate insulating layer film 3 and an active layer film are formed on the pattern of the gate electrode 2 by deposition, coating or sputtering, and the active layer pattern 4 is formed by a patterning process using a common mask; then vapor deposition is employed.
  • a process such as sputtering is performed to form a source/drain metal layer film on the pattern including the active layer 4, and a pattern including the source electrode 11 and the drain electrode 12 is formed by a patterning process using a common mask.
  • the patterning process may include, for example, coating a photoresist on the source/drain metal layer film, exposing, developing, etching, stripping, or the like using a common mask, wherein etching is preferably performed by wet etching, including forming
  • etching is preferably performed by wet etching, including forming
  • forming the pattern of the source electrode 11 and the drain electrode 12 by one patterning process includes: firstly forming a gate insulating layer film 3, an active layer film, and a source on the gate electrode pattern 2 by a process such as vapor deposition, coating, or sputtering. The metal layer film is leaked, and then the pattern of the source electrode 11 and the drain electrode 12 is formed by one patterning process using a halftone or gray tone mask.
  • the patterning process can include, for example:
  • a layer of photoresist (not shown) is coated on the source/drain metal layer film;
  • the halftone or gray tone mask is used for exposure, so that the photoresist forms a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to The region where the source electrode pattern 11 and the drain electrode pattern 12 are located, the photoresist semi-retained region corresponds to the region where the channel pattern between the source electrode pattern 11 and the drain electrode pattern 12 is located, and the photoresist completely removed region corresponds to the above pattern Outside the area; after the development process, the thickness of the photoresist in the completely remaining area of the photoresist is not changed, the photoresist in the completely removed area of the photoresist is completely removed, and the light scale of the semi-reserved area of the photoresist is reduced; And an active layer film.
  • the dry etching method completely retains the photoresist and the photoresist is semi-reserved.
  • the photoresist in the region acts as a thinning process
  • the photoresist in the semi-reserved region of the photoresist is removed by an ashing process, and the source/drain metal layer film of the region is exposed;
  • the source/drain metal layer film, the doped semiconductor layer film and the semiconductor layer film of a certain thickness under the semi-reserved region of the photoresist are completely etched by the second etching process, and the semiconductor layer film of the region is exposed, and the film is formed.
  • the source-drain metal layer film under the semi-reserved region of the photoresist may be etched away by wet etching, and then the underlying semiconductor layer film and the semiconductor layer film of a certain thickness are etched away by dry etching to form a semiconductor layer film. Channel pattern; Finally, the remaining photoresist is stripped to form a pattern including the source electrode 11 and the drain electrode 12.
  • the color film layer 6 may be composed of red pixels (not shown) and green pixels (not shown in the drawing) And a blue pixel (not shown), the red pixel pattern, the green pixel pattern, and the blue pixel pattern are respectively formed by one patterning process.
  • red pixel resin layer (not shown) is coated on the whole substrate substrate 1, wherein the pixel resin layer is usually an acrylic photosensitive resin or other carboxylic acid type pigment pigment resin;
  • the stencil forms a red pixel pattern by one patterning process.
  • the steps include, for example:
  • the color filter layer 6 is exposed by using a mask to form a color film layer retention area and a color film layer non-retention area, wherein the color film layer does not retain the area including the color film via 5; and then is removed by an ashing process.
  • the color film layer 6 does not retain the color film layer 6 of the region, and a pattern including the color film via 5 is formed.
  • the size of the formed color filter via 5 can be changed to 2 to 3 ⁇ m, and the maximum aperture is smaller than ⁇ , while the pixel electrode and the drain are connected.
  • the problem that the aperture ratio of the pixel unit is lowered due to the excessive size of the color filter via 5 is effectively solved.
  • the ashing process power range can be 4500 ⁇ 7500W
  • the gas pressure range can be 13.3 ⁇ 40Pa
  • the ashing gas flow rate range can be 2000 ⁇ 2500mL/min.
  • the color film layer 6 is preferably exposed by a projection exposure machine, due to projection exposure.
  • the resolution of the optical machine is high, and the dimensional error is small, and the color film via 5 having a smaller aperture size can be formed later.
  • a transparent protective layer may be formed on the color filter layer 6 by a process such as vapor deposition, coating or sputtering.
  • the patterning process for forming the color filter via 5 includes coating photoresist, exposure and development of the photoresist, etching of the transparent protective layer, and ashing of the color filter layer, since no direct color layer is required.
  • the patterning process includes, for example:
  • a layer of photoresist 13 is first applied to the substrate 1 on the substrate.
  • the substrate 1 on the substrate For example, in the color layer
  • the mask 13 is used, and the photoresist 13 is preferably exposed by a projection type exposure machine. Since the resolution of the projection type exposure machine is high, the dimensional error is small, and a color film via hole 5 having a smaller aperture size can be formed subsequently;
  • the photoresist 13 is developed to form the photoresist 13 to form a photoresist retention region and a photoresist non-retention region, wherein the photoresist non-retention region includes a color film via region, and the photoresist retention region corresponds to In the area of other patterns, as shown in Figure 8;
  • the transparent protective layer 14 of the photoresist non-retained region is etched away, as shown in FIG. 9, a pattern including the protective layer via 15 is formed, and the protective layer via 15 corresponds to the position of the color filter via 5, thereby the pixel
  • the electrode 7 can be electrically connected to the drain electrode 12 of the thin film transistor 10 through the protective layer via 15 and the color filter via 5, as shown in FIG.
  • the transparent protective layer 14 may be a transparent insulating layer material, such as one or two of SiN x , SiO x , and SiON x , or may be a transparent metal oxide material, such as: indium tin oxide or indium oxide. ;
  • the color film layer 6 of the photoresist non-retained region is removed by an ashing process to form a pattern including the color film via 5, as shown in FIG.
  • forming a pattern including the pixel electrode 7 on the substrate 1 includes, for example, first forming a transparent conductive layer film on the color filter via 5 by a process such as coating, vapor deposition, or sputtering (not shown). show). Then coating a photoresist (not shown) on the transparent conductive layer, exposing the photoresist to a photoresist using a mask, and forming a photoresist retention region and a photoresist non-reserved region, wherein the light
  • the glue-retained area includes a region where the pixel electrode 7 is formed.
  • the transparent conductive metal layer under the non-retained area of the photoresist is etched away to form the pixel electrode 7. Finally, the remaining photoresist is stripped.
  • the pixel electrode 7 is electrically connected to the drain electrode 12 of the thin film transistor 10 through the color filter via 5, and the color film layer 6 corresponds to the position of the pixel electrode 7.
  • the common electrode 9 when the common electrode 9 is located above the pixel electrode 7, after forming the pattern of the pixel electrode 7, it is also required to process the pixel by a process such as coating, vapor deposition or sputtering.
  • a passivation layer 8 covering the entire substrate substrate 1 is formed on the electrode 7.
  • a pattern including the common electrode 9 is then formed on the passivation layer 8.
  • a transparent conductive layer film (not shown) is first formed on the passivation layer 8 by a process such as coating, vapor deposition or sputtering, and then a photoresist is coated on the transparent conductive layer (not shown) And exposing and developing the photoresist to form a photoresist retention region and a photoresist non-retention region, wherein the photoresist retention region includes a region forming the common electrode 9, and then preferably by wet etching The transparent conductive layer of the photoresist non-retained region is etched away to form the common electrode 9. Finally, the remaining photoresist is stripped.
  • the common electrode 9 is a slit electrode, and the pixel electrode 7 may be a block electrode or a slit electrode. If the pixel electrode 7 is a slit electrode, the pixel electrode 7 corresponds to the slit position of the common electrode 9. When the common electrode 9 is located below the pixel electrode 7, the pixel electrode 7 is a slit electrode, and the common electrode 9 may be a block electrode or a slit electrode. If the common electrode 9 is a slit electrode, the common electrode 9 is The slit positions of the pixel electrodes 7 correspond.
  • Embodiment 2 Embodiment 2
  • a COA substrate is provided which is manufactured by the manufacturing method of the first embodiment. Since the aperture size of the color filter via hole formed by the manufacturing method is small and the amount of change in the aperture size is small, the problem that the aperture ratio of the pixel unit of the COA substrate is affected by the color filter via hole is effectively solved.
  • Embodiment 3
  • a display device which adopts the COA substrate in the second embodiment, which greatly improves the display quality of the display device.
  • the method for manufacturing a COA substrate provided by the embodiments of the present invention The color film layer of the color film through-hole region is removed by an ashing process to form a color film via hole, so that the aperture size variation of the color film via hole is reduced, and the maximum aperture diameter is also reduced, thereby effectively solving the size of the color film via hole.
  • the problem that the aperture ratio of the pixel unit is reduced is large, and the problem that the aperture ratio of the pixel unit of the COA substrate is affected by the color filter via hole is solved, and the display quality of the display device is improved.

Abstract

提供一种COA基板及其制造方法、显示装置。所述方法包括：在一衬底基板（1）上形成薄膜晶体管（10）；在形成有薄膜晶体管（10）的衬底基板（1）上形成有彩膜层（6）图案；通过构图工艺在彩膜层（6）上形成包括彩膜过孔（5）的图案，构图工艺中包括灰化工艺；在衬底基板（1）上形成包括像素电极（7）的图案；像素电极（7）通过彩膜过孔（5）与薄膜晶体管（10）的漏电极（12）电性连接。

Description

COA基板及其制造方法、 显示装置 技术领域
本发明实施例涉及显示技术领域， 特别涉及一种 COA基板及其制造方 法、 显示装置。 背景技术
薄膜晶体管液晶显示器包括薄膜晶体管阵列基板、 彩膜基板和液晶层， 其中， 彩膜基板是液晶显示器的主要组成部分， 用于实现彩色画面的显示。 早期制造薄膜晶体管液晶显示器的技术中， 彩膜层与作为驱动开关的薄膜晶 体管形成在不同基板上， 并位于液晶层两侧， 然而这种配置方式会造成显示 面板的开口率降低， 进而影响显示面板的亮度与画面品质。 由于近年来， 市 场上对显示面板的开口率及亮度的要求提高， 业界为应市场需求进而开发出 一种彩膜层直接形成在阵列基板上（Color filter On Array, 筒称 "COA" ) 的 技术， 即将彩膜层和薄膜晶体管形成在一块基板上， 如此不仅可以提升显示 面板的开口率， 增加显示面板的亮度， 而且避免了将彩膜层和薄膜晶体管形 成在不同基板上所衍生的问题。
如图 1所示， 现有技术中通过 COA技术形成的彩色滤光阵列基板（即
COA基板）包括由多条栅线和多条数据线限定的多个像素单元，每个像素单 元包括薄膜晶体管 （Thin Film Transistor, 筒称 "TFT" ) 10、 彩膜层 6和像 素电极 7, 彩膜层 6—般由红、 绿、 蓝（R、 G、 B )三种彩色有机树脂层形 成， 并在有机树脂层表面形成有树脂平坦层（图中未示出）。像素电极 7通过 彩膜过孔 5' 与 TFT的漏电极 12电性连接。
随着液晶显示器的分辨率不断提高，显示面板的像素单元尺寸越来越小， 例如： 分辨率为 400ppi的显示器， 像素单元的尺寸一般在 25 χ 25μιη左右。 而通过传统的掩膜曝光和显影工艺形成的彩膜过孔 5' 的孔径尺寸变化量 大， 最大孔径尺寸也大， 其中， 孔径尺寸的变化量为 8μιη左右， 最大孔径为
25μιη左右， 严重影响了像素单元的开口率。 发明内容 本发明实施例提供一种 C0A基板的制造方法， 用以解决通过传统工艺 形成的彩膜过孔的最大孔径尺寸大， 孔径尺寸变化量也大， 严重影响了像素 单元的开口率的问题。
根据本发明的第一方面，提供一种彩色滤光阵列基板的制造方法， 包括： 在一村底基板上形成薄膜晶体管；
在形成有薄膜晶体管的所述村底基板上形成彩膜层图案；
通过构图工艺在所述彩膜层上形成包括彩膜过孔的图案， 所述构图工艺 中包括灰化工艺；
在所述村底基板上形成包括像素电极的图案； 所述像素电极通过所述彩 膜过孔与所述薄膜晶体管的漏电极电性连接。
根据本发明的第二方面， 提供一种 COA基板， 其采用如上所述的制造 方法制造。
根据本发明的第三方面，还提供一种显示装置， 其包括如上所述的 COA 基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中 COA基板的结构示意图；
图 2为本发明实施例中 COA基板的结构示意图一；
图 3为本发明实施例中 COA基板的结构示意图二；
图 4~图 11为图 2中 COA基板的制造过程示意图；
其中， 1 : 村底基板； 2: 栅电极； 3: 栅绝缘层； 4: 有源层图案； 5,5' ： 彩膜过孔； 6: 彩膜层； 7: 像素电极； 8: 钝化层； 9: 公共电极； 10: 薄膜 晶体管； 11 : 源电极； 12: 漏电极； 13: 光刻胶； 14: 透明保护层； 15: 保 护层过孔。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 实施例一
在 COA基板的生产过程中， 形成彩膜过孔的传统工艺包括掩膜曝光和 显影工艺。 显影工艺的原理是利用一定浓度的显影液将彩膜层溶解掉， 从而 形成彩膜过孔的图案。 为了保证显影的效果， 需要控制显影液的浓度、 显影 时间和显影温度等， 如条件控制不好， 4艮容易造成形成的彩膜过孔的孔径尺 寸变化量（即彩膜过孔两端的孔径尺寸的差值） 大， 最大孔径尺寸也大， 从 而严重影响了像素单元的开口率。 本发明的实施例提供一种彩色滤光阵列基 板的制造方法， 可以减小彩膜过孔的孔径尺寸变化量和最大孔径尺寸。
结合图 2~图 11所示，本发明实施例中的 COA基板的制造方法包括以下 步骤：
在一村底基板上形成薄膜晶体管；
结合图 4所示， 首先在一村底基板 1上形成薄膜晶体管 10。 其中， 村底 基板 1由透光材料制成， 具有良好的透光性， 通常为玻璃基板、 石英基板或 透明树脂基板。
在一个实施例中， COA基板包括村底基板 1 , 村底基板 1上形成有多个 矩阵排列的像素单元， 每个像素单元包括至少一个薄膜晶体管。
该薄膜晶体管可以为顶栅结构的薄膜晶体管， 也可以为底栅结构的薄膜 晶体管。 下面以底栅结构的薄膜晶体管为例来具体说明薄膜晶体管的形成过 程：
首先在村底基板 1上形成包括栅电极 2的图案。 例如， 可以采用气相沉 积、 溅射等工艺在村底基板 1上形成栅金属层薄膜（图中未示出）， 并通过构 图工艺在该栅金属层薄膜上形成栅电极 2的图案。 该构图工艺例如包括在栅 金属层薄膜上涂覆光刻胶、 采用普通掩膜版曝光、 显影、 刻蚀、 剥离光刻胶 等工艺， 其中优选采用湿刻法进行刻蚀；
然后在包括栅电极 2的图案上依次形成栅绝缘层薄膜 3、有源层薄膜（图 中未示出）和源漏金属层薄膜（图中未示出）， 其中， 有源层薄膜包括半导体 层薄膜和掺杂半导体层薄膜， 且掺杂半导体层薄膜位于半导体层薄膜上方。 本实施例中可以通过多次构图工艺分别形成包括源电极 11和漏电极 12的图 案， 或通过一次构图工艺同时形成包括源电极 11和漏电极 12的图案。 通过 多次构图工艺形成源电极 11和漏电极 12的图案例如包括：
首先在栅电极 2的图案上采用沉积、 涂敷或溅射等工艺形成栅绝缘层薄 膜 3、 有源层薄膜， 采用普通掩膜版通过一次构图工艺形成有源层图案 4; 然后采用气相沉积、 溅射等工艺在包括有源层 4的图案上形成源漏金属 层薄膜， 采用普通掩膜版通过一次构图工艺形成包括源电极 11和漏电极 12 的图案。 该构图工艺例如可以包括在源漏金属层薄膜上涂覆光刻胶、 采用普 通掩膜版曝光、 显影、 刻蚀、 剥离光刻胶等工艺， 其中优选采用湿刻法进行 刻蚀， 形成包括源电极 11和漏电极 12的图案， 然后可以采用干刻法刻蚀掉 源电极 11和漏电极 12之间的全部掺杂半导体层和部分半导体层。
例如， 通过一次构图工艺形成源电极 11和漏电极 12的图案包括： 首先采用气相沉积、 涂敷或溅射等工艺在栅电极图案 2上依次形成栅绝 缘层薄膜 3、 有源层薄膜和源漏金属层薄膜， 然后采用半色调或灰色调掩膜 版通过一次构图工艺形成源电极 11和漏电极 12的图案。 该构图工艺例如可 以包括：
首先， 在源漏金属层薄膜上涂覆一层光刻胶（图中未示出）；
接着， 采用半色调或灰色调掩膜版进行曝光， 使光刻胶形成光刻胶完全 去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其中， 光刻胶完全保 留区域对应于源电极图案 11和漏电极图案 12所在的区域， 光刻胶半保留区 域对应于源电极图案 11和漏电极图案 12之间的沟道图案所在的区域， 光刻 胶完全去除区域对应于上述图案以外的区域； 显影处理后， 光刻胶完全保留 区域的光刻胶厚度没有变化， 光刻胶完全去除区域的光刻胶被完全去除， 光 刻胶半保留区域的光刻 度减少； 金属层薄膜和有源层薄膜。 例如， 优选通过湿刻法先刻蚀掉光刻胶完全去除 区域下方的源漏金属层薄膜， 再通过干刻法刻蚀掉其下的有源层薄膜， 形成 包括有源层 4的图案。 同时， 干刻法对光刻胶完全保留区域和光刻胶半保留 区域的光刻胶起到一个减薄过程；
之后， 通过灰化工艺去除光刻胶半保留区域的光刻胶， 暴露出该区域的 源漏金属层薄膜；
再通过第二次刻蚀工艺完全刻蚀掉光刻胶半保留区域下方的源漏金属层 薄膜、 掺杂半导体层薄膜和一定厚度的半导体层薄膜， 暴露出该区域的半导 体层薄膜， 形成位于源电极 11和漏电极 12之间的沟道图案。 例如， 可以先 通过湿刻法刻蚀掉光刻胶半保留区域下方的源漏金属层薄膜， 再通过干刻法 刻蚀掉其下的掺杂半导体层薄膜和一定厚度的半导体层薄膜，形成沟道图案； 最后， 剥离剩余的光刻胶， 形成包括源电极 11和漏电极 12的图案。 在形成包括源电极和漏电极图案的村底基板上形成彩膜层图案； 结合图 5所示， 彩膜层 6可以由红色像素（图中未示出）、 绿色像素（图 中未示出）和蓝色像素 （图中未示出）组成， 红色像素图案、 绿色像素图案 和蓝色像素图案分别通过一次构图工艺形成。 下面以红色像素为例来具体说 明像素图案的形成过程：
首先在整块村底基板 1上涂覆一层红色像素树脂层（图中未示出）,其中， 像素树脂层通常是丙烯酸类感光性树脂或其他羧酸型色素颜料树脂； 然后采 用普通掩膜版通过一次构图工艺形成红色像素图案。
通过构图工艺在所述彩膜层上形成包括彩膜过孔的图案， 所述构图工艺 包括灰化工艺；
结合图 3所示， 该步骤例如包括：
首先利用掩膜版对彩膜层 6进行曝光， 形成彩膜层保留区域和彩膜层不 保留区域， 其中， 彩膜层不保留区域包括彩膜过孔 5的区域； 然后通过灰化 工艺去除彩膜层不保留区域的彩膜层 6, 形成包括彩膜过孔 5的图案。
由于通过控制灰化工艺的功率、 气压和灰化气体的流量， 可以使得形成 的彩膜过孔 5的尺寸变化量为 2~3μιη, 最大孔径小于 ΙΟμιη, 在实现像素电 极与漏极连接的同时， 有效解决了由于彩膜过孔 5的尺寸过大， 而导致的像 素单元开口率降低的问题。 其中， 灰化工艺的功率范围可以为 4500~7500W, 气压的范围可以为 13.3~40Pa, 灰化气体的流量范围可以为 2000~2500mL/分 钟。
本实施例中优选通过投影式曝光机对彩膜层 6进行曝光， 由于投影式曝 光机的分辨率高， 尺寸误差较小， 后续可以形成孔径尺寸更小的彩膜过孔 5。 进一步地， 在通过构图工艺在彩膜层 6上形成包括彩膜过孔 5的图案之 前， 还可以通过气相沉积、 涂覆或溅射等工艺在彩膜层 6上形成透明保护层
14, 如图 6所示。 则形成彩膜过孔 5的构图工艺包括涂覆光刻胶、 光刻胶的 曝光和显影、 透明保护层的刻蚀和彩膜层的灰化， 由于不需要直接对彩膜层
6进行曝光， 因此减小了由于曝光量控制不好对彩膜过孔 5最大孔径尺寸的 影响。 结合图 7~图 10所示， 该构图工艺例如包括：
如图 7所示， 首先在村底基板 1上涂覆一层光刻胶 13。 例如， 在彩膜层
6上涂覆覆盖整块村底基板 1的光刻胶 13;
然后采用掩膜版，优选通过投影式曝光机对光刻胶 13进行曝光， 由于投 影式曝光机的分辨率高， 尺寸误差较小， 后续可以形成孔径尺寸更小的彩膜 过孔 5;
之后对光刻胶 13进行显影， 使光刻胶 13形成光刻胶保留区域和光刻胶 不保留区域， 其中， 光刻胶不保留区域包括彩膜过孔的区域， 光刻胶保留区 域对应于其他图案的区域， 如图 8所示；
然后刻蚀掉光刻胶不保留区域的透明保护层 14, 如图 9所示， 形成包括 保护层过孔 15的图案， 且保护层过孔 15与彩膜过孔 5的位置对应， 从而像 素电极 7可以通过保护层过孔 15和彩膜过孔 5与薄膜晶体管 10的漏电极 12 电性连接，结合图 2所示。其中，透明保护层 14可以为透明绝缘层材料，如： SiNx、 SiOx、 SiONx中的一种或两种复合， 也可以为透明金属氧化物材料， 如： 氧化铟锡或氧化铟辞；
最后采用灰化工艺去除光刻胶不保留区域的彩膜层 6, 形成包括彩膜过 孔 5的图案， 如图 10所示。
在所述村底基板上形成包括像素电极的图案； 所述像素电极通过所述彩 膜过孔与所述薄膜晶体管的漏电极电性连接。
结合图 11所示， 在村底基板 1上形成包括像素电极 7的图案例如包括： 首先通过涂覆、 气相沉积或溅射等工艺在彩膜过孔 5上形成透明导电层 薄膜（图中未示出）。 然后在该透明导电层上涂覆光刻胶（图中未示出）， 采 用掩膜版对光刻胶进行曝光， 显影， 形成光刻胶保留区域和光刻胶不保留区 域， 其中， 光刻胶保留区域包括形成像素电极 7的区域。 之后优选通过湿刻 法刻蚀掉光刻胶不保留区域下方的透明导电金属层， 形成像素电极 7。 最后 剥离剩余的光刻胶。
其中， 像素电极 7通过彩膜过孔 5与薄膜晶体管 10的漏电极 12电性连 接， 且彩膜层 6与像素电极 7的位置对应。
结合图 2和图 3所示， 对于 ADS型液晶显示器， 当公共电极 9位于像 素电极 7上方时， 在形成像素电极 7的图案之后， 还需要通过涂覆、 气相沉 积或溅射等工艺在像素电极 7上形成覆盖整个村底基板 1的钝化层 8。 然后 在钝化层 8上形成包括公共电极 9的图案。 例如， 首先通过涂覆、 气相沉积 或溅射等工艺在钝化层 8上形成透明导电层薄膜（图中未示出），然后在该透 明导电层上涂覆光刻胶（图中未示出），采用掩膜版对光刻胶进行曝光，显影， 形成光刻胶保留区域和光刻胶不保留区域， 其中， 光刻胶保留区域包括形成 公共电极 9的区域， 之后优选通过湿刻法刻蚀掉光刻胶不保留区域的透明导 电层， 形成公共电极 9。 最后剥离剩余的光刻胶。 其中， 公共电极 9为狭缝 电极， 像素电极 7可以为块状电极也可以为狭缝电极， 如像素电极 7为狭缝 电极， 则像素电极 7与公共电极 9的狭缝位置对应。 而当公共电极 9位于像 素电极 7的下方时， 像素电极 7为狭缝电极， 公共电极 9可以为块状电极也 可以为狭缝电极， 如公共电极 9为狭缝电极， 则公共电极 9与像素电极 7的 狭缝位置对应。 实施例二
基于同一发明构思， 本实施例中提供一种 COA基板， 其采用实施例一 中的制造方法制造。 由于通过该制造方法形成的彩膜过孔的孔径尺寸小， 且 孔径尺寸的变化量也小， 有效解决了 COA基板的像素单元的开口率受彩膜 过孔影响的问题。 实施例三
本实施例中提供一种显示装置， 其采用实施例二中的 COA基板， 大大 改善了显示装置的显示质量。 由以上实施例可以看出， 本发明实施例所提供的 COA基板的制造方法, 通过灰化工艺去除彩膜过孔区域的彩膜层来形成彩膜过孔， 使得彩膜过孔的 孔径尺寸变化量减小，最大孔径也减小，有效解决了由于彩膜过孔尺寸过大, 而导致的像素单元开口率降低的问题， 解决了 COA基板的像素单元的开口 率受彩膜过孔影响的问题， 提高了显示装置的显示质量。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种 COA基板的制造方法， 包括：
在一村底基板上形成薄膜晶体管；
在形成有薄膜晶体管的所述村底基板上形成彩膜层图案；
通过构图工艺在所述彩膜层上形成包括彩膜过孔的图案， 所述构图工艺 中包括灰化工艺；
在所述村底基板上形成包括像素电极的图案； 所述像素电极通过所述彩 膜过孔与所述薄膜晶体管的漏电极电性连接。
2、 根据权利要求 1所述的 COA基板的制造方法， 其中在通过构图工艺 在所述彩膜层上形成包括彩膜过孔的图案之前， 还包括： 在所述彩膜层上形 成透明保护层。
3、 根据权利要求 2所述的 COA基板的制造方法， 其中所述通过构图工 艺在所述彩膜层上形成包括像素电极过孔的图案， 包括以下步骤：
在所述透明保护层上涂覆光刻胶， 对所述光刻胶进行曝光、 显影， 形成 光刻胶保留区域和光刻胶不保留区域， 所述光刻胶不保留区域包括彩膜过孔 的区域；
刻蚀掉光刻胶不保留区域的透明保护层， 形成包括保护层过孔的图案， 所述保护层过孔与所述彩膜过孔的位置对应；
采用灰化工艺去除光刻胶不保留区域的彩膜层， 形成包括彩膜过孔的图 案。
4、 根据权利要求 2或 3所述的 COA基板的制造方法， 其中所述透明保 护层为透明绝缘材料或透明金属氧化物材料。
5、 根据权利要求 1所述的 COA基板的制造方法， 其中所述通过构图工 艺在所述彩膜层上形成包括像素电极过孔的图案， 包括以下步骤：
对所述彩膜层进行曝光， 形成彩膜层保留区域和彩膜层不保留区域， 所 述彩膜层不保留区域包括彩膜过孔的区域；
采用灰化工艺去除所述彩膜层不保留区域的彩膜层， 形成包括彩膜过孔 的图案。
6、 根据权利要求 5所述的 COA基板的制造方法， 其中采用投影式曝光 机对所述彩膜层进行曝光。
7、 根据权利要求 1所述的 COA基板的制造方法， 其中在所述村底基板 上形成包括像素电极的图案之后， 还包括：
在所述像素电极上形成钝化层。
8、 根据权利要求 7所述的 COA基板的制造方法， 其中在所述像素电极 上形成钝化层之后， 还包括：
在所述钝化层上形成包括公共电极的图案。
9、 一种 COA基板， 采用权利要求 1~8任一所述的制造方法制造。
10、 一种显示装置， 包括权利要求 9所述的 COA基板。
PCT/CN2013/087973 2013-06-28 2013-11-27 Coa基板及其制造方法、显示装置 WO2014205998A1 (zh)

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