WO2014015631A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2014015631A1
WO2014015631A1 PCT/CN2012/087124 CN2012087124W WO2014015631A1 WO 2014015631 A1 WO2014015631 A1 WO 2014015631A1 CN 2012087124 W CN2012087124 W CN 2012087124W WO 2014015631 A1 WO2014015631 A1 WO 2014015631A1
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Prior art keywords
photoresist
layer
color filter
area
semiconductor active
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PCT/CN2012/087124
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English (en)
French (fr)
Inventor
曹占锋
童晓阳
姚琪
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/126,941 priority Critical patent/US9804463B2/en
Publication of WO2014015631A1 publication Critical patent/WO2014015631A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • a conventional TFT-LCD (Thin Film Transistor-Liquid Crystal Display) substrate is formed by pairing a TFT array substrate with another color filter substrate.
  • the new type of color filter integrates a thin film transistor array substrate (COA) technology, which is a color filter manufacturing process on the array substrate after the TFT array manufacturing process is completed.
  • COA thin film transistor array substrate
  • the film is formed on a TFT array substrate. Since the wiring is precise, it is not necessary to increase the width of the light shielding layer by the process of the box, so that the transmittance can be improved.
  • the COA technology that integrates color filters on an array substrate has been valued and studied for its low manufacturing cost and lighter weight.
  • Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display device, which can reduce the number of MASK processes in the COA manufacturing technology, simplify the process steps, and thereby ensure the production quality.
  • An embodiment of the present invention provides a method for fabricating an array substrate, the method comprising: forming a semiconductor active layer, a gate insulating layer, and a gate on a substrate; forming a light shielding layer; forming a first color filter layer, and second a color filter layer; forming a third color filter layer and via holes penetrating through the first, second and third color filter layers respectively; forming a pixel electrode and a source/drain electrode.
  • forming the semiconductor active layer, the gate insulating layer, and the gate on the substrate comprises: sequentially forming a semiconductor active layer film, a gate insulating layer film, and a gate metal layer film on the substrate; coating the photoresist, And forming a first photoresist completely reserved region by exposure and development by using a mask, first a photoresist partially reserved region and a first photoresist completely removed region, wherein the first photoresist completely reserved region corresponds to a region where a gate electrode is to be formed, and the first photoresist portion remaining region corresponds to a semiconductor to be formed a region of the source layer, wherein the first photoresist completely removed region corresponds to a region other than the gate electrode and the semiconductor active layer; and the first photoresist is completely removed by an etching process
  • the gate metal layer film, the gate insulating layer film and the semiconductor active layer film ashing the photoresist to remove the photoresist of the first photoresist portion remaining region;
  • the method of fabricating the array substrate further includes: forming a first protective layer on the substrate on which the semiconductor active layer, the gate insulating layer, and the gate are formed, wherein the via hole penetrates the The first protective layer.
  • forming the first protective layer and forming the light shielding layer include: forming a first protective layer film on the substrate on which the semiconductor active layer, the gate insulating layer, and the gate are formed; forming a black light blocking a photoresist is coated with a mask to form a second photoresist completely remaining region and a second photoresist completely removed region by exposure and development, and the second photoresist completely remaining region corresponds to the gate a region of the second photoresist completely removed from the region completely adjacent to the second photoresist; the black light blocking material in the completely removed region of the second photoresist is removed by an etching process; And stripping the photoresist.
  • forming the via hole includes: coating a photoresist on the third color filter layer, and performing exposure and development using the mask to form a third photoresist completely reserved region and the third light
  • the photoresist is completely removed, and the third photoresist completely removes regions corresponding to both sides of the gate and over the semiconductor active layer to form via holes; the third photoresist is completely retained
  • the region correspondingly removes the third color filter layer, the first color filter layer, the second color filter layer and the first protective layer in the third photoresist completely removed region; gum.
  • forming the pixel electrode and the source/drain electrodes includes: depositing a pixel electrode layer; depositing a source/drain metal layer; coating the photoresist, exposing through a two-tone mask, developing to form a fourth photolithography a completely complete area of the glue, a fourth photoresist partially reserved area, and a fourth photoresist completely removed area, wherein the fourth photoresist completely reserved area corresponds to the via hole, and the fourth photoresist part reserved area corresponds to a portion of the first, second, and third color filter layers not forming the semiconductor active layer a region of the square, the fourth photoresist completely removed region corresponding to another portion of the first, second, and third color filter layers not forming the semiconductor active layer and forming the gate a region above the color filter layer of the gate insulating layer; removing the pixel electrode layer and the source/drain metal in the completely removed region of the fourth photoresist by etching; The glue is subjected to ashing treatment to remove the
  • the array substrate includes: a substrate; a semiconductor active layer, a gate insulating layer, and a gate formed on the substrate; and the semiconductor active layer, the a gate insulating layer and a light shielding layer on the gate, a first color filter layer, a second color filter layer, and a third color filter layer, wherein the first, second, and third color filters are penetrated
  • the light layer is formed with via holes; pixel electrodes and source/drain electrodes formed on the first color filter layer, the second color filter layer, and the third color filter layer;
  • a pole is electrically connected to the semiconductor active layer through the via.
  • a gate is disposed over the gate insulating layer and the gate is coincident with the gate insulating layer pattern.
  • the light shielding layer is located above the gate.
  • the source electrode and the drain electrode are electrically connected to the semiconductor active layer through a pixel electrode layer and a via, respectively.
  • the array substrate further includes: a first protective layer formed on the semiconductor active layer, the gate insulating layer, and the gate.
  • Another aspect of an embodiment of the present invention provides a display device including the array substrate manufactured according to the above-described method of fabricating an array substrate.
  • the preparation method according to the embodiment of the present invention reduces the use of the patterning process and simplifies the process steps, thereby ensuring the display of the array substrate and the array substrate, while ensuring the function of the TFT array substrate.
  • the quality of the production of the unit is improved in COA technology.
  • FIG. 13 are schematic diagrams showing a process of fabricating an array substrate according to an embodiment of the invention
  • FIG. 14 is a schematic structural view of an array substrate according to an embodiment of the invention
  • FIG. 16 is a schematic structural view of an array substrate according to another embodiment of the present invention. detailed description
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and A pixel electrode that controls the arrangement of liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the embodiment of the present invention provides a method for fabricating the array substrate 1. As shown in FIG. 15, the method includes:
  • Al, an active layer 20, a gate insulating layer 30, and a gate electrode 40 are formed on the substrate 10.
  • a semiconductor active layer film 201, a gate insulating film 301, and a gate metal film 401 are formed on the substrate 10 by, for example, chemical vapor deposition or thermal evaporation.
  • a semiconductor active layer film 201 is deposited first; and one of silicon nitride, silicon oxide, silicon oxynitride or the like is deposited to form a gate insulating film 301; and one of a metal material such as molybdenum or copper is deposited.
  • a gate metal layer film 401 is formed of a gate line and a gate material.
  • a photoresist 501 is then coated on the gate metal layer film 401.
  • the exposure is performed by a two-tone mask, wherein the two-tone mask comprises: a gray tone mask and a halftone mask, such as photolithography.
  • the glue 501 is exposed by a halftone mask, and is formed to form a first photoresist completely remaining region 101, a first photoresist portion remaining region 102 and a first photoresist completely removed region 103, and the first photoresist is completely retained.
  • the region 101 corresponds to a region where the gate electrode 40 is to be formed
  • the first photoresist portion remaining region 102 corresponds to a region where the semiconductor active layer 20 is to be formed
  • the first photoresist completely removed region 103 corresponds to the gate electrode 40 and the semiconductor active layer 20 Outside the area.
  • the first photoresist completely removed region 103 is then etched to remove the gate metal layer film, the gate insulating layer film, and the semiconductor active layer film in the region.
  • the photoresist 501 is further subjected to ashing treatment to remove the photoresist of the first photoresist portion remaining region 102, and the photoresist of the first photoresist completely remaining region 101 is thinned. This is because the photoresist completely remaining region 101 is also affected by the ashing treatment, and the applied photoresist is thinned.
  • a portion of the gate metal layer film 401 and a portion of the gate insulating film 301 are removed by an etching process, and then the photoresist 501 of the first photoresist completely remaining region 101 is stripped, thereby forming a semiconductor active.
  • Layer 20, gate insulating layer 30, and gate electrode 40 are removed by an etching process, and then the photoresist 501 of the first photoresist completely remaining region 101 is stripped, thereby forming a semiconductor active.
  • a light shielding layer 70 is formed on the substrate on which the semiconductor active layer 20, the gate insulating layer 30, and the gate electrode 40 are formed.
  • first protective layer and the light shielding layer may be formed on the substrate on which the semiconductor active layer 20, the gate insulating layer 30, and the gate electrode 40 are formed.
  • This embodiment is described by taking the first protective layer and the light shielding layer as an example.
  • the array substrate manufacturing method in which the first protective layer is not formed is also within the scope of protection.
  • a first protective layer 60 is formed on the semiconductor active layer 20, the gate insulating layer 30, and the gate electrode 40.
  • a first protective layer 60 is formed over the gate electrode 40, and then a black light blocking material is formed on the substrate on which the first protective layer 60 is formed, and a photoresist is coated on the black light blocking material.
  • a second photoresist completely remaining region 201 and a second photoresist completely removed region 202 are formed, and the second photoresist completely remaining region 201 corresponds to a region where the gate electrode 40 is formed, and the second photoresist The region other than the completely reserved region 201 corresponds to the second photoresist completely removed region 202.
  • the black light blocking material is etched by the coated photoresist to remove the black light blocking material in the second photoresist completely removed region 202, and finally the photoresist is stripped, thereby forming a black matrix over the gate 40. That is, the light shielding layer 70 is formed over the gate electrode 40.
  • a first color filter layer and a second color filter layer are formed on the substrate on which the light shielding layer 70 is formed.
  • a third color filter layer 80 and a via 90 extending through each of the color filter layers are formed on the substrate on which the first color filter layer and the second color filter layer are formed.
  • the color of the first color filter layer, the second color filter layer, and the third color filter layer 80 is not limited, and the first color filter layer may be red, and the second color filter layer may be The green color, the third color filter layer 80 is blue, or may be arranged in other order, or may be other primary colors, each color filter layer corresponding to one pixel area, and each set of color filter layers includes a first color.
  • each color filter layer is exemplified by red
  • the pixel region corresponding to the red filter layer may be referred to as a red pixel region.
  • the analogy also includes a green pixel area and a blue pixel area. The order of arrangement of each color filter layer is not limited, and is not limited by the example of the embodiment.
  • a blue filter layer 80 is formed on a substrate on which a red filter layer and a green filter layer are formed, and then a via hole 90 is formed over the semiconductor active layer 20.
  • a photoresist (not shown) is coated on the blue filter layer 80, and after exposure and development by using a mask, the third photoresist completely remaining region 301 and the third photoresist are completely formed.
  • the region 302 is removed, the third photoresist completely removed region 302 corresponds to both sides of the gate 40, a region above the semiconductor active layer 20 where the via 90 is to be formed, and the third photoresist completely reserved region 301 corresponds to the third light.
  • the engraving completely removes all areas except the area 302.
  • the third photoresist completely removed region 302 is etched to remove the blue filter layer, the red filter layer, and the green filter layer in the third photoresist completely removed region 302. Via holes 90 are formed through the red filter layer, the green filter layer, and the blue filter layer, respectively. Further, if the first protective layer 60 is prepared in A2, the red filter layer, the green filter layer and the blue filter layer 80, and the first protective layer 60 in the third photoresist completely removed region 302 are removed. To form a via 90 extending through the red filter layer, the green filter layer and the blue filter layer 80, and the first protective layer 60.
  • the first color filter layer and the second color green layer are sequentially prepared according to the above method, and a third color filter layer is formed on the substrate on which the first color filter layer and the second color filter layer are formed, and Through holes penetrating the respective color filter layers.
  • the color filter layer may be directly formed by using a color photosensitive resin material, so that when the first color filter layer, the second color filter layer, and the third color green layer are formed, only the exposure and development processes are required.
  • the via holes penetrating through the respective color filter layers can be directly formed, and the etching process can be saved.
  • the first protective layer is prepared in step A2
  • the blue filter layer, the red filter layer, and the green filter layer in the third photoresist complete removal region 302 are removed by development, and the etching process is performed.
  • the first protective layer is removed to form vias 90 that extend through the respective filter layers.
  • the first protective layer 60 is prepared in the above process step, the first color filter layer, the second color filter layer, the third color filter layer 80, and the color filter layers are penetrated A pixel electrode layer 101 and a source/drain metal layer 111 are formed on the substrate of the via 90 of a protective layer 60.
  • a substrate having a first color filter layer, a second color filter layer, a third color filter layer 80, and a via 90 penetrating the color filter layer and the first protective layer 60 is formed.
  • a pixel electrode layer 101 is deposited thereon, and a source/drain metal layer 111 is deposited on the pixel electrode layer 101, and then a photoresist 150 is coated on the source/drain metal layer 111 through a two-tone mask, such as The half-tone mask is subjected to one exposure and development to form a fourth photoresist completely remaining region 401, a fourth photoresist portion remaining region 402, and a fourth photoresist completely removed region 403, wherein the fourth photoresist is completely
  • the reserved area 401 corresponds to the via 90, and the fourth photoresist portion retains the area of the portion corresponding to the color filter layer of the semiconductor active layer 20 that is not formed (such as the color of the right side of the right via in FIG.
  • the fourth photoresist completely removed region 403 corresponds to the channel region of the thin film transistor and the remaining region (such as above the region where the gate electrode 40 is formed and to the left of the via hole on the left side in FIG. 10) The area above the color filter layer), The fourth photoresist completely removed region 403 Corresponding to another portion of the region above the first, second, and third color filter layers where the semiconductor active layer 20 is not formed and a region above the color filter layer where the gate and gate insulating layers are formed, as shown in FIG. Show.
  • the fourth photoresist completely removed region 403 is etched to remove a portion of the pixel electrode layer 101 and the source/drain metal layer 111.
  • the photoresist is ashed, and the photoresist 150 of the fourth photoresist partially remaining region 402 is removed, and the photoresist of the fourth photoresist completely retaining region 401 is reduced. Thin, the pixel electrode layer 101 and the source/drain metal layer 111 outside the fourth photoresist completely remaining region 401 are removed by an etching process, and the photoresist 150 is stripped, thereby forming the pixel electrode 100 and the source/drain electrodes 110. .
  • the embodiment of the invention provides a method for preparing an array substrate.
  • the semiconductor active layer, the gate insulating layer, and the gate line can be obtained by one patterning process; and then each color filter layer is prepared by one patterning process;
  • the pixel electrode and the source and drain electrodes are formed by a patterning process.
  • the preparation method reduces the number of patterning processes and simplifies the process steps, thereby ensuring the process steps.
  • the array substrate and the display device including the array substrate have improved production quality in terms of COA technology.
  • the array substrate 1 includes: a substrate 10; a semiconductor active layer 20, a gate insulating layer 30, and a gate electrode 40 formed on the substrate 10; a semiconductor active layer 20, a gate insulating layer 30, and a light shielding layer 70 on the gate 40, a first color filter layer or a second color filter layer or a third color filter layer 80, wherein the color filter layers are penetrated A via hole 90 is formed; a pixel electrode 100 and source/drain electrodes 110 formed on the first color filter layer, the second color filter layer, and the third color filter layer 80, wherein the source/drain electrodes 110 pass through
  • the vias 90 of the respective color filter layers are electrically connected to the semiconductor active layer 20, such as the source and the drain, and the semiconductor active layer 20 through the source/drain electrodes 110 and the vias 90, respectively.
  • the color filter layer 80 is one of the first color filter layer, the second color filter layer, and the third color filter layer, and each color filter layer corresponds to one pixel region, each group.
  • the color filter layer includes a first color filter layer, a second color filter layer and a third color filter layer, each set of color filter layers corresponding to three adjacent pixel regions, and the array substrate includes a plurality of a color filter layer, a plurality of second color filter layers, and a plurality of third color filter layers.
  • the first color filter layer is exemplified by red
  • the red filter layer is corresponding to the pixel region.
  • red pixel area It is called a red pixel area, and so on, and includes a green pixel area and a blue pixel area, and the red pixel area, the green pixel area, and the blue pixel area are sequentially arranged adjacent to each other.
  • the gate electrode 40 is placed over the gate insulating layer 30, and the gate electrode 40 is in conformity with the pattern of the gate insulating layer 30.
  • the light shielding layer 70 is located above the gate 40.
  • the array substrate 1 may further include a first protective layer 60 formed on the semiconductor active layer 20 , the gate insulating layer 30 , and the gate electrode 40 .
  • the array substrate 1 provided by the embodiment of the invention can integrate the color filter on the thin film transistor array substrate, has the COA technology wiring precision, does not need to increase the width of the light shielding layer due to the box process, and has high transmittance.
  • the advantages also simplify the process steps of the existing COA technology, thereby ensuring the production quality of the array substrate 1.
  • an embodiment of the present invention provides a display device, which includes the array substrate prepared by the method for manufacturing the array substrate 1 described above, and the color filter may be integrated on the array substrate 1.
  • the integrated display of the array substrate 1 and the transparent glass substrate may also be a liquid crystal display, an OLED display, an active electronic paper display, and other display devices using the above array substrate 1.
  • the display device provided by the embodiment of the invention comprises an array substrate 10 on which a color filter is integrated on a thin film transistor array substrate, which has the COA technology wiring precision, and does not need to increase the width of the light shielding layer by the box process, and
  • the advantage of high rate simplifies the process steps of the existing COA technology, thereby ensuring the production quality of the display device.

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Abstract

本发明实施例提供一种阵列基板及其制备方法和显示装置，其能够减少COA制造技术中MASK工艺次数，简化工艺步骤，进而保证生产质量。阵列基板的制作方法包括：在基板上形成半导体有源层、栅绝缘层和栅极；形成遮光层；形成第一彩色滤光层、第二彩色滤光层和第三彩色滤光层；形成分别贯穿第一、第二和第三彩色滤光层的过孔；以及形成像素电极和源/漏电极。

Description

阵列基板及其制备方法和显示装置 技术领域
本发明的实施例涉及阵列基板及其制备方法和显示装置。 背景技术
传统的 TFT-LCD ( Thin Film Transistor-Liquid Crystal Display, 薄膜晶体 管液晶显示器）基板是由一片 TFT阵列基板与另一片彩膜（ Color Filter )基 板对盒而成。
而新型的彩色滤光片整合薄膜晶体管阵列基板 ( Color Filter On Array, 简称 COA )技术， 是在 TFT阵列制造工艺完成之后， 再在阵列基板上进行 彩色滤光片的制造工艺， 也就是将彩膜制于 TFT阵列基板上。 由于其布线精 确， 无需因对盒工艺而增加遮光层的宽幅， 从而可以提高透过率。 将彩色滤 光片集成于阵列基板上的 COA技术因制造成本较低、 更利于轻薄化等优点 而被人所重视和研究。
但现有的 COA制造技术中需要进行多次掩模 ( MASK )工艺处理， 不 仅工艺复杂， 成本较高， 而且繁杂的工艺步骤致使质量难以保证。 发明内容
本发明的实施例提供一种阵列基板及其制备方法和显示装置， 能够减少 COA制造技术中 MASK工艺次数， 简化工艺步骤， 进而保证生产质量。
为达到上述目的， 本发明的实施例釆用如下技术方案：
本发明实施例的一方面提供一种阵列基板的制作方法， 该方法包括： 在 基板上形成半导体有源层、 栅绝缘层和栅极； 形成遮光层； 形成第一彩色滤 光层、 第二彩色滤光层； 形成第三彩色滤光层及分别贯穿第一、 第二和第三 彩色滤光层的过孔； 形成像素电极和源 /漏电极。
在一示例中， 在基板上形成半导体有源层、 栅绝缘层和栅极包括： 在基 板上依次形成半导体有源层薄膜、 栅绝缘层薄膜、 栅极金属层薄膜； 涂覆光 刻胶， 并利用掩膜版通过曝光、 显影而形成第一光刻胶完全保留区域、 第一 光刻胶部分保留区域及第一光刻胶完全去除区域， 其中所述第一光刻胶完全 保留区域对应将形成栅极的区域， 所述第一光刻胶部分保留区域对应将形成 半导体有源层的区域， 所述第一光刻胶完全去除区域对应将形成所述栅极和 所述半导体有源层以外的区域； 通过刻蚀工艺去除所述第一光刻胶完全去除 区域内的所述栅极金属层薄膜、所述栅绝缘层薄膜和所述半导体有源层薄膜； 对光刻胶进行灰化处理， 去除所述第一光刻胶部分保留区域的光刻胶； 通过 刻蚀工艺去除半导体有源层上的所述栅极金属层薄膜和所述栅绝缘层薄膜的 一部分； 以及剥离光刻胶。
在一示例中，阵列基板的制造方法还包括：在形成有所述半导体有源层、 所述栅绝缘层和所述栅极的基板上形成第一保护层， 其中所述过孔贯穿所述 第一保护层。
在一示例中， 形成第一保护层以及形成遮光层包括： 在形成有所述半导 体有源层、 所述栅绝缘层和所述栅极的基板上形成第一保护层薄膜； 形成黑 色挡光材料； 涂覆光刻胶， 利用掩膜版通过曝光、 显影而形成第二光刻胶完 全保留区域和第二光刻胶完全去除区域， 所述第二光刻胶完全保留区域对应 所述栅极上方， 所述第二光刻胶完全保留区域以外的区域对应所述第二光刻 胶完全去除区域； 通过刻蚀工艺去除所述第二光刻胶完全去除区域内的黑色 挡光材料； 以及剥离光刻胶。
在一示例中， 形成过孔包括： 在所述第三彩色滤光层上涂覆光刻胶， 并 利用掩膜版进行曝光、 显影后而形成第三光刻胶完全保留区域和第三光刻胶 完全去除区域， 所述第三光刻胶完全去除区域对应所述栅极的两侧且在所述 半导体有源层上方的将形成过孔的区域； 所述第三光刻胶完全保留区域对应 去除第三光刻胶完全去除区域内的所述第三彩色滤光层、 所述第一彩色滤光 层、 所述第二彩色滤光层和所述第一保护层； 剥离光刻胶。
在一示例中， 形成像素电极和源 /漏电极包括： 沉积像素电极层； 沉积源 /漏极金属层； 涂覆光刻胶， 通过双色调掩膜版进行曝光、 显影后形成第四光 刻胶完全保留区域、 第四光刻胶部分保留区域及第四光刻胶完全去除区域， 所述第四光刻胶完全保留区域对应所述过孔， 所述第四光刻胶部分保留区域 对应部分的未形成所述半导体有源层的所述第一、 第二和第三彩色滤光层上 方的区域， 所述第四光刻胶完全去除区域对应另一部分的未形成所述半导体 有源层的所述第一、 第二和第三彩色滤光层上方的区域和形成所述栅极、 所 述栅绝缘层的所述彩色滤光层上方的区域； 通过蚀刻去除所述第四光刻胶完 全去除区域内的所述像素电极层和所述源 /漏极金属；再对光刻胶进行灰化处 理， 去除所述第四光刻胶部分保留区域的光刻胶； 通过刻蚀工艺去除在所述 部分的未形成所述半导体有源层的所述第一、 第二和第三彩色滤光层上方的 区域的所述源 /漏极金属； 以及剥离光刻胶。
本发明实施例的另一方面提供一种阵列基板， 该阵列基板包括： 基板； 形成于所述基板上的半导体有源层、 栅绝缘层、 栅极； 形成于所述半导体有 源层、 所述栅绝缘层和所述栅极上的遮光层、 第一彩色滤光层、 第二彩色滤 光层和第三彩色滤光层， 其中， 贯穿所述第一、 第二和第三彩色滤光层形成 有过孔； 形成于所述第一彩色滤光层、 所述第二彩色滤光层和所述第三彩色 滤光层上的像素电极和源 /漏电极； 所述源 /漏电极通过所述过孔与所述半导 体有源层电连接。
在一示例中， 栅极置于所述栅绝缘层上方， 且所述栅极与所述栅绝缘层 图形一致。
在一示例中， 所述遮光层位于所述栅极上方。
在一示例中， 源电极和漏电极分别通过像素电极层和过孔与所述半导体 有源层电连接。
在一示例中， 阵列基板还包括： 形成于所述半导体有源层、 所述栅绝缘 层和所述栅极上的第一保护层。
本发明实施例的另一方面提供一种显示装置， 该显示装置包括根据上述 所述阵列基板的制造方法制得的所述阵列基板。
根据本发明实施例的制备方法在保证 TFT阵列基板功能的前提下，相对 现有技术而言， 减少了构图工艺的使用数量， 简化工艺步骤， 进而保证了阵 列基板和包含有该阵列基板的显示装置的在 COA技术上， 生产质量得以提 高。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例, 而非对本发明的限制。
图 1至图 13为根据本发明实施例的阵列基板的制作过程示意图； 图 14为根据本发明实施例的阵列基板的结构示意图；
图 15为根据本发明实施例的制作阵列基板的流程图； 以及
图 16为根据本发明另一实施例的阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个像素的薄 膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线电连 接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述主要 针对单个或多个像素单元进行， 但是其他像素单元可以相同地形成。 本发明实施例提供了阵列基板 1的制作方法，如图 15所示，该方法包括：
Al、 在基板 10上形成有源层 20、 栅绝缘层 30和栅极 40。
如图 1所示，在基板 10上依次釆用例如化学气相沉积或热蒸发的方法形 成半导体有源层薄膜 201、栅绝缘层薄膜 301和栅极金属层薄膜 401。例如先 沉积半导体有源层薄膜 201 ; 再沉积氮化硅、 氧化硅、 氮氧化硅等材料中的 一种， 形成栅绝缘层薄膜 301 ; 再沉积钼、 铜等金属材料中的一种（制作栅 线、 栅极的材料） ， 形成栅极金属层薄膜 401。
然后在栅极金属层薄膜 401上涂布光刻胶 501。
如图 2所示，涂覆一层光刻胶 501后，通过双色调掩膜版进行一次曝光， 其中， 双色调掩膜版包括： 灰色调掩膜版和半色调掩膜版， 例如光刻胶 501 通过半色调掩膜版曝光、 显影后形成第一光刻胶完全保留区域 101 , 第一光 刻胶部分保留区域 102及第一光刻胶完全去除区域 103 , 第一光刻胶完全保 留区域 101对应将形成栅极 40的区域，第一光刻胶部分保留区域 102对应将 形成半导体有源层 20的区域， 第一光刻胶完全去除区域 103对应栅极 40和 半导体有源层 20以外的区域。然后对第一光刻胶完全去除区域 103进行刻蚀， 去除在该区域内的栅极金属层薄膜、 栅绝缘层薄膜和半导体有源层薄膜。
如图 3所示， 再对光刻胶 501进行灰化处理， 将第一光刻胶部分保留区 域 102的光刻胶去除掉， 同时第一光刻胶完全保留区域 101的光刻胶减薄， 这是由于光刻胶完全保留区域 101也会受到灰化处理的影响， 涂覆的光刻胶 会被减薄。
如图 4所示， 再通过刻蚀工艺去除部分栅极金属层薄膜 401和部分栅绝 缘层薄膜 301 ,然后剥离第一光刻胶完全保留区域 101的光刻胶 501 , 由此形 成半导体有源层 20、 栅绝缘层 30、 栅极 40。
A2、在形成有半导体有源层 20、栅绝缘层 30和栅极 40的基板上形成遮 光层 70。
进一步地， 也可以在形成有半导体有源层 20、 栅绝缘层 30和栅极 40的 基板上形成第一保护层和遮光层， 本实施例以形成第一保护层和遮光层为例 进行说明， 但是不形成第一保护层的阵列基板制造方法也在保护范围之内。
例如， 如图 5所示， 在所述半导体有源层 20、 栅绝缘层 30、 栅极 40上 形成第一保护层 60。 如图 6所示， 在栅极 40上方形成第一保护层 60, 然后在形成有第一保 护层 60的基板上形成黑色挡光材料，在黑色挡光材料上涂覆光刻胶，利用掩 膜版进行曝光、 显影后形成第二光刻胶完全保留区域 201和第二光刻胶完全 去除区域 202, 第二光刻胶完全保留区域 201对应形成栅极 40的区域， 第二 光刻胶完全保留区域 201以外的区域对应第二光刻胶完全去除区域 202。 通 过涂覆的光刻胶对黑色挡光材料进行刻蚀， 将第二光刻胶完全去除区域 202 内的黑色挡光材料去除， 最后剥离光刻胶， 由此在栅极 40上方形成黑矩阵， 即在栅极 40上方形成遮光层 70。
A3、 在形成有遮光层 70的基板上形成第一彩色滤光层、 第二彩色滤光 层（未示出 ) 。
A4、 在形成有第一彩色滤光层、 第二彩色滤光层的基板上形成第三彩色 滤光层 80及贯穿各彩色滤光层的过孔 90。
需要说明的是， 第一彩色滤光层、 第二彩色滤光层和第三彩色滤光层 80 的颜色不做限制， 可以是第一彩色滤光层为红色、 第二彩色滤光层为绿色、 第三彩色滤光层 80为蓝色，也可以是其他顺序排列，或者也可以是其他的基 色， 每个彩色滤光层对应一个像素区域， 每组彩色滤光层包括一个第一彩色 滤光层、 一个第二彩色滤光层和一个第三彩色滤光层， 每组彩色滤光层对应 三个相邻的像素区域， 阵列基板包括多个第一彩色滤光层、 多个第二彩色滤 光层和多个第三彩色滤光层， 例如， 在阵列基板上， 第一彩色滤光层以红色 为例， 红色滤光层对应的像素区域可以称为红色像素区域， 以此类推还包括 绿色像素区域和蓝色像素区域， 每组彩色滤光层的排列顺序也不受限制， 不 以本实施例的举例为限制。
例如， 如图 7、 图 8所示， 在形成有红色滤光层和绿色滤光层的基板上 形成蓝色滤光层 80, 然后在半导体有源层 20上方形成过孔 90。 具体地， 在 蓝色滤光层 80上涂覆光刻胶（未示出） ， 再利用掩膜版进行曝光、 显影后， 形成第三光刻胶完全保留区域 301和第三光刻胶完全去除区域 302, 第三光 刻胶完全去除区域 302对应栅极 40的两侧、 半导体有源层 20上方的将形成 过孔 90的区域，而第三光刻胶完全保留区域 301对应第三光刻胶完全去除区 域 302以外的所有区域。 对第三光刻胶完全去除区域 302进行刻蚀， 将第三 光刻胶完全去除区域 302内的蓝色滤光层、 红色滤光层、 绿色滤光层去除以 形成分别贯穿红色滤光层、 绿色滤光层和蓝色滤光层的过孔 90。 进一步地， 若 A2中制备有第一保护层 60, 则将第三光刻胶完全去除区域 302内的红色 滤光层、 绿色滤光层和蓝色滤光层 80以及第一保护层 60去除， 以形成贯穿 红色滤光层、 绿色滤光层和蓝色滤光层 80以及第一保护层 60的过孔 90。
由此， 依照上述方法依次制备第一彩色滤光层、 第二彩色绿光层， 并在 形成有第一彩色滤光层和第二彩色滤光层的基板上形成第三彩色滤光层以及 贯穿各彩色滤光层的过孔。
进一步地， 彩色滤光层也可以直接釆用彩色感光树脂材料形成， 这样在 形成第一彩色滤光层、 第二彩色滤光层和第三彩色绿光层时， 仅需要曝光、 显影工序即可直接形成贯穿各彩色滤光层的过孔， 节省刻蚀工序。 当然， 如 果步骤 A2中制备有第一保护层， 则将第三光刻胶完全去除区域 302内的蓝 色滤光层、 红色滤光层、 绿色滤光层通过显影去除， 并通过刻蚀工序去除第 一保护层， 以形成贯穿各滤光层的过孔 90。
A5、 在形成有第一彩色滤光层、 第二彩色滤光层、 第三彩色滤光层 80 和贯穿各彩色滤光层的过孔 90的基板上形成像素电极层 101和源 /漏金属层 111。
进一步地， 如果上述工艺步骤中制备了第一保护层 60, 则在形成有第一 彩色滤光层、第二彩色滤光层、第三彩色滤光层 80以及贯穿各彩色滤光层和 第一保护层 60的过孔 90的基板上形成像素电极层 101和源 /漏金属层 111。
例如， 如图 9所示， 在形成有第一彩色滤光层、 第二彩色滤光层、 第三 彩色滤光层 80以及贯穿彩色滤光层和第一保护层 60的过孔 90的基板上沉积 像素电极层 101 , 再在像素电极层 101上沉积源 /漏极金属层 111 , 之后在源 / 漏极金属层 111上涂覆一层光刻胶 150, 通过双色调掩膜版， 如半色调掩膜 版进行一次曝光、 显影后形成第四光刻胶完全保留区域 401、 第四光刻胶部 分保留区域 402及第四光刻胶完全去除区域 403 , 其中， 第四光刻胶完全保 留区域 401对应过孔 90 ,第四光刻胶部分保留区域 402对应部分的未形成半 导体有源层 20的各彩色滤光层上方的区域（如图 10中右侧过孔的右侧的彩 色滤光层上方的区域） ， 第四光刻胶完全去除区域 403对应薄膜晶体管的沟 道区域以及剩余的区域（如形成有栅极 40的区域的上方以及与图 10中左侧 过孔的左边的彩色滤光层上方的区域） ， 即， 第四光刻胶完全去除区域 403 对应另一部分的未形成半导体有源层 20的所述第一、第二和第三彩色滤光层 上方的区域和形成栅极、 栅绝缘层的彩色滤光层上方的区域， 如图 10所示。
如图 10所示，对第四光刻胶完全去除区域 403进行刻蚀，去除部分像素 电极层 101和源 /漏极金属层 111。
如图 11-14所示， 再对光刻胶进行灰化处理， 将第四光刻胶部分保留区 域 402的光刻胶 150去除掉， 第四光刻胶完全保留区域 401的光刻胶减薄， 通过刻蚀工艺去除第四光刻胶完全保留区域 401之外的像素电极层 101和源 / 漏极金属层 111 , 剥离光刻胶 150, 由此形成像素电极 100和源 /漏电极 110。
本发明实施例提供了阵列基板的制备方法， 制备阵列基板时， 可以通过 一次构图工艺制得半导体有源层、 栅绝缘层、 及栅线； 再通过一次构图工艺 制得各彩色滤光层； 并再通过一次构图工艺制得像素电极、 源漏极， 这种制 备方法在保证 TFT阵列基板功能的前提下， 相对现有技术而言， 减少了构图 工艺的使用数量， 简化工艺步骤， 进而保证了阵列基板和包含有该阵列基板 的显示装置在 COA技术方面生产质量得以提高。
本发明另一实施例提供的阵列基板 1 ,如图 16所示，该阵列基板 1包括： 基板 10; 形成于基板 10上的半导体有源层 20、 栅绝缘层 30和栅极 40; 形成于半导体有源层 20、栅绝缘层 30和栅极 40上的遮光层 70、第一彩色滤 光层或第二彩色滤光层或第三彩色滤光层 80, 其中， 贯穿各彩色滤光层形成 有过孔 90; 形成于第一彩色滤光层、 第二彩色滤光层和第三彩色滤光层 80 上的像素电极 100和源 /漏电极 110, 其中， 源 /漏电极 110通过贯穿各彩色滤 光层的过孔 90与半导体有源层 20电连接，如源极和漏极分别通过源 /漏电极 110和过孔 90与半导体有源层 20电连接。
需要说明的是，彩色滤光层 80为第一彩色滤光层、 第二彩色滤光层、第 三彩色滤光层中的其中一种， 每个彩色滤光层对应一个像素区域， 每组彩色 滤光层包括一个第一彩色滤光层、 一个第二彩色滤光层和一个第三彩色滤光 层， 每组彩色滤光层对应三个相邻的像素区域， 阵列基板包括多个第一彩色 滤光层、 多个第二彩色滤光层和多个第三彩色滤光层， 例如， 在阵列基板上， 第一彩色滤光层以红色为例， 红色滤光层对应像素区域可以称为红色像素区 域， 以此类推还包括绿色像素区域和蓝色像素区域， 红色像素区域、 绿色像 素区域和蓝色像素区域依次相邻排列。 进一步地， 栅极 40置于栅绝缘层 30上方， 且栅极 40与栅绝缘层 30的 图形一致。 而遮光层 70位于栅极 40的上方。
需要说明的是， 阵列基板 1 , 如图 14所示， 还可以包括形成于半导体有 源层 20、 栅绝缘层 30和栅极 40上的第一保护层 60。
本发明实施例提供的阵列基板 1 , 可以将彩色滤光片整合于薄膜晶体管 阵列基板上， 既拥有 COA技术布线精确， 无需因对盒工艺而增加遮光层的 宽幅， 以及透过率高的优点， 又简化现有的 COA技术的工艺步骤， 进而保 证了阵列基板 1的生产质量。
同时， 本发明的实施例提供一种显示装置， 该显示装置包含以上所述的 阵列基板 1的制造方法制得的阵列基板， 可以将彩色滤光片整合在阵列基板 1上， 具体可以为将整合的阵列基板 1与透明玻璃基板对盒而成的显示器， 也可以为液晶显示器、 OLED显示器、 有源电子纸显示器及其它使用上述阵 列基板 1的显示装置。
本发明实施例提供的显示装置， 包含将彩色滤光片整合于薄膜晶体管阵 列基板上的阵列基板 10, 既拥有 COA技术布线精确， 无需因对盒工艺而增 加遮光层的宽幅， 以及透过率高的优点， 又简化现有的 COA技术的工艺步 骤， 进而保证了显示装置的生产质量。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的形成方法， 包括：
在基板上形成半导体有源层、 栅绝缘层和栅极；
形成遮光层；
形成第一彩色滤光层、 第二彩色滤光层；
形成第三彩色滤光层及分别贯穿第一、 第二和第三彩色滤光层的过孔； 形成像素电极和源 /漏电极。
2、根据权利要求 1所述的阵列基板的形成方法， 其中， 所述在基板上形 成半导体有源层、 栅绝缘层和栅极包括：
在基板上依次形成半导体有源层薄膜、栅绝缘层薄膜、栅极金属层薄膜； 涂覆光刻胶， 并利用掩膜版通过曝光、 显影而形成第一光刻胶完全保留 区域、 第一光刻胶部分保留区域及第一光刻胶完全去除区域， 其中所述第一 光刻胶完全保留区域对应将形成栅极的区域， 所述第一光刻胶部分保留区域 对应将形成半导体有源层的区域， 所述第一光刻胶完全去除区域对应将形成 所述栅极和所述半导体有源层以外的区域；
通过刻蚀工艺去除所述第一光刻胶完全去除区域内的所述栅极金属层薄 膜、 所述栅绝缘层薄膜和所述半导体有源层薄膜；
对光刻胶进行灰化处理， 去除所述第一光刻胶部分保留区域的光刻胶； 通过刻蚀工艺去除半导体有源层上的所述栅极金属层薄膜和所述栅绝缘 层薄膜的一部分； 以及
剥离光刻胶。
3、 根据权利要求 1或 2所述的阵列基板的制造方法， 还包括： 在形成有所述半导体有源层、 所述栅绝缘层和所述栅极的基板上形成第 一保护层，
所述过孔贯穿所述第一保护层。
4、根据权利要求 3所述的阵列基板的制造方法， 其中， 形成第一保护层 以及形成遮光层包括：
在形成有所述半导体有源层、 所述栅绝缘层和所述栅极的基板上形成第 一保护层薄膜； 形成黑色挡光材料；
涂覆光刻胶， 利用掩膜版通过曝光、 显影而形成第二光刻胶完全保留区 域和第二光刻胶完全去除区域， 所述第二光刻胶完全保留区域对应所述栅极 上方， 所述第二光刻胶完全保留区域以外的区域对应所述第二光刻胶完全去 除区域；
通过刻蚀工艺去除所述第二光刻胶完全去除区域内的黑色挡光材料； 剥离光刻胶。
5、根据权利要求 1至 4的任一项所述的阵列基板的制造方法， 其中， 所 述形成过孔包括：
在所述第三彩色滤光层上涂覆光刻胶， 并利用掩膜版进行曝光、 显影后 而形成第三光刻胶完全保留区域和第三光刻胶完全去除区域， 所述第三光刻 孔的区域； 所述第三光刻胶完全保留区域对应所述第三彩色滤光层上方的除 了将形成所述过孔以外的区域；
通过刻蚀工艺去除第三光刻胶完全去除区域内的所述第三彩色滤光层、 所述第一彩色滤光层、 所述第二彩色滤光层和所述第一保护层；
剥离光刻胶。
6、根据权利要求 3所述的阵列基板的制造方法，其中形成像素电极和源 /漏电极包括：
沉积像素电极层；
沉积源 /漏极金属层；
涂覆光刻胶， 通过双色调掩膜版进行曝光、 显影后形成第四光刻胶完全 保留区域、 第四光刻胶部分保留区域及第四光刻胶完全去除区域， 所述第四 光刻胶完全保留区域对应所述过孔， 所述第四光刻胶部分保留区域对应部分 的未形成所述半导体有源层的所述第一、第二和第三彩色滤光层上方的区域， 所述第四光刻胶完全去除区域对应另一部分的未形成所述半导体有源层的所 述第一、 第二和第三彩色滤光层上方的区域和形成所述栅极、 所述栅绝缘层 的所述彩色滤光层上方的区域；
通过蝕刻去除所述第四光刻胶完全去除区域内的所述像素电极层和所述 源 /漏极金属； 再对光刻胶进行灰化处理，去除所述第四光刻胶部分保留区域的光刻胶； 通过刻蚀工艺去除在所述部分的未形成所述半导体有源层的所述第一、 第二和第三彩色滤光层上方的区域的所述源 /漏极金属； 以及
剥离光刻胶。
7、 一种阵列基板， 包括：
基板；
形成于所述基板上的半导体有源层、 栅绝缘层、 栅极；
形成于所述半导体有源层、 所述栅绝缘层和所述栅极上的遮光层、 第一 彩色滤光层、 第二彩色滤光层和第三彩色滤光层， 其中， 贯穿所述第一、 第 二和第三彩色滤光层形成有过孔；
形成于所述第一彩色滤光层、 所述第二彩色滤光层和所述第三彩色滤光 层上的像素电极和源 /漏电极；
8、根据权利要求 7所述的阵列基板， 其中， 所述栅极置于所述栅绝缘层 上方， 且所述栅极与所述栅绝缘层图形一致。
9、根据权利要求 7或 8所述的阵列基板， 其中， 所述遮光层位于所述栅 极上方。
10、 根据权利要求 7至 9的任一项所述的阵列基板， 其中， 源电极和漏 电极分别通过像素电极层和过孔与所述半导体有源层电连接。
11、 根据权利要求 7至 10任一项所述阵列基板， 还包括：
形成于所述半导体有源层、 所述栅绝缘层和所述栅极上的第一保护层。
12、 一种显示装置， 包括权利要求 1-6中任意一项所述阵列基板的制造 方法制得的所述阵列基板。
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