TWI351764B - Pixel structure and method for forming the same - Google Patents

Pixel structure and method for forming the same Download PDF

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TWI351764B
TWI351764B TW096111888A TW96111888A TWI351764B TW I351764 B TWI351764 B TW I351764B TW 096111888 A TW096111888 A TW 096111888A TW 96111888 A TW96111888 A TW 96111888A TW I351764 B TWI351764 B TW I351764B
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conductive layer
layer
transistor
conductive
electrically connected
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TW096111888A
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TW200841471A (en
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Yu Hsin Ting
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Au Optronics Corp
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Priority to TW096111888A priority Critical patent/TWI351764B/en
Priority to US11/902,229 priority patent/US7745825B2/en
Publication of TW200841471A publication Critical patent/TW200841471A/en
Priority to US12/652,169 priority patent/US8263445B2/en
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

13517641351764

三達編號:TW3530PA ► 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種晝素結構及其之形成方法,且特 • 別是有關於一種具有儲存電容之晝素結構。 【先前技術】 請參照第1圖,其繪示傳統之晝素結構之剖面圖。晝 素結構100具有一基板109。基板109上形成一半導體層 φ 120。半導體層120及基板109上覆蓋有一絕緣層150。絕 緣層150上形成一閘極116,並覆蓋有一内層介電層190 於閘極116上。絕緣層150及内層介電層190具有兩個開 口 162,以暴露出半導體層120。一源極114、一汲極112 及一電容電極101形成於内層介電層190上。源極114及 汲極112是經由開口 162與半導體層120電性連接。 一保護層102形成於内層介電層190上,且覆蓋源極 114、汲極112及電容電極101,並具有一接觸洞(contact • hole)163,以暴露出源極114。晝素電極103形成於保護層 102上,並經由接觸洞163與源極114電性連接。 晝素結構100之電容電極101為導電材料,且保護層 102為介電材料。儲存電容Csl會形成於電容電極101及 晝素電極103之間。然而,因保護層102之覆蓋方式,晝 素電極103及電容電極101之間會因製程問題易產生短 路。雖然可增加保護層102之厚度以解決上述所提之問 題,儲存電容Csl卻因此而相對的減少。 6 1351764Sanda number: TW3530PA ► Nine, invention description: [Technical field of invention] The present invention relates to a halogen structure and a method for forming the same, and particularly relates to a halogen structure having a storage capacitor. [Prior Art] Please refer to Fig. 1, which shows a cross-sectional view of a conventional halogen structure. The pixel structure 100 has a substrate 109. A semiconductor layer φ 120 is formed on the substrate 109. The semiconductor layer 120 and the substrate 109 are covered with an insulating layer 150. A gate 116 is formed on the insulating layer 150 and is covered with an inner dielectric layer 190 on the gate 116. The insulating layer 150 and the inner dielectric layer 190 have two openings 162 to expose the semiconductor layer 120. A source 114, a drain 112, and a capacitor electrode 101 are formed on the inner dielectric layer 190. The source 114 and the drain 112 are electrically connected to the semiconductor layer 120 via the opening 162. A protective layer 102 is formed on the inner dielectric layer 190 and covers the source 114, the drain 112 and the capacitor electrode 101, and has a contact hole 163 to expose the source 114. The halogen electrode 103 is formed on the protective layer 102 and electrically connected to the source 114 via the contact hole 163. The capacitor electrode 101 of the halogen structure 100 is a conductive material, and the protective layer 102 is a dielectric material. The storage capacitor Cs1 is formed between the capacitor electrode 101 and the halogen electrode 103. However, due to the coverage of the protective layer 102, short circuits may occur between the germanium electrode 103 and the capacitor electrode 101 due to process problems. Although the thickness of the protective layer 102 can be increased to solve the above-mentioned problems, the storage capacitor Csl is relatively reduced. 6 1351764

三達編號:TW3530PA 此外,電容電極101 —般採用不透光之材質,且位於 ' : 晝素結構100之可視區域内(未圖示),因此,就算晝素電 極103採用透光之材質。然而,此設計方式往往會使畫素 - 結構100之開口率(aperture ratio),隨著儲存電容Csl之儲 存容量(如:儲存電容Csl於可視區域内之面積)增加而減 少。如此一來,即會使得面板之顯示亮度降低。除此之外, 此問題更顯見於同尺寸且具較高解析度之面板。 φ 【發明内容】 本發明是有關於一種畫素結構及其形成方法,可於不 變更電容值之情況下增加開口率。 根據本發明之第一方面,提出一種晝素結構。此晝素 結構包含至少一電晶體、一第一儲存電容、一第一導電 層、一内層介電層、一第二導電層、一保護層及一第三導 電層。第一儲存電容電性連接於電晶體。内層介電層覆蓋 於第一導電層上,且其具有至少一第一開口。第二導電層 • 形成於部份内層介電層上,且經由第一開口電性連接於第 .一導電層。保護層覆蓋於電晶體及第二導電層上,且其具 有至少一第二開口。第三導電層形成部份保護層上,且經 由第二開口電性連接於電晶體。第一儲存電容由第三導電 層、保護層及第二導電層所構成。 根據本發明之第二方面,提出一種晝素結構之形成方 法。畫素結構具有至少一電晶體及一第一儲存電容。第一 儲存電容電性連接於電晶體。此形成方法包含以下之步 7 1351764Sanda number: TW3530PA In addition, the capacitor electrode 101 is generally made of an opaque material and is located in the visible region of the : : 昼 结构 structure 100 (not shown), so that the halogen element 103 is made of a light transmissive material. However, this design approach tends to reduce the aperture ratio of the pixel-structure 100 as the storage capacity of the storage capacitor Cs1 (e.g., the area of the storage capacitor Cs1 in the visible area) increases. As a result, the display brightness of the panel is lowered. In addition, this problem is more apparent in panels of the same size and higher resolution. φ [Summary of the Invention] The present invention relates to a pixel structure and a method of forming the same, which can increase the aperture ratio without changing the capacitance value. According to a first aspect of the invention, a halogen structure is proposed. The halogen structure comprises at least one transistor, a first storage capacitor, a first conductive layer, an inner dielectric layer, a second conductive layer, a protective layer and a third conductive layer. The first storage capacitor is electrically connected to the transistor. The inner dielectric layer covers the first conductive layer and has at least one first opening. The second conductive layer is formed on the portion of the inner dielectric layer and electrically connected to the first conductive layer via the first opening. The protective layer covers the transistor and the second conductive layer and has at least one second opening. The third conductive layer is formed on the partial protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. According to a second aspect of the present invention, a method of forming a halogen structure is proposed. The pixel structure has at least one transistor and a first storage capacitor. The first storage capacitor is electrically connected to the transistor. This formation method includes the following steps 7 1351764

三麵號·· TW3530PA » 驟:首先,形成一第一導電層。接著,覆蓋一内層介電層 V : 於第一導電層上,且其具有一第一開口。然後,形成一第 '; 二導電層於部份内層介電層上,且經由第一開口電性連接 * 於第一導電層。接著,覆蓋一保護層於電晶體及第二導電 層上,且其具有一第二開口。最後,形成一第三導電層於 部份保護層上,且經由第二開口電性連接於電晶體。第一 儲存電容由第三導電層、保護層及第二導電層所構成。 為讓本發明之上述内容能更明顯易懂,下文特舉較佳 φ 實施例,並配合所附圖式,作詳細說明如下: 【實施方式】 本發明是提出具有至少一儲存電容於導電材料間之 畫素結構。導電材料包括透光材質、反射材質、或上述之 組合。本發明之實施例是以一光電裝置中顯示面板之晝素 結構作為範例來詳細說明。再者,實施例之圖示是省略某 些元件,以利清楚顯示本發明之技術特點。 第一實施例 請參第2A圖,其繪示本發明第一實施例之晝素結構 之上視示意圖。本實施例是以一光電裝置中顯示面板之晝 素結構200舉例說明。如第2A圖所示,資料線DT2及掃 描線SC2為分別與畫素結構200電性連接。請參照第2B 圖,其繪示第2A圖之晝素結構之剖面圖。第2B圖為沿著 第2A圖中之2B_2B’剖面線之剖面圖。晝素結構200包含Three-faced ·· TW3530PA » Step: First, form a first conductive layer. Next, an inner dielectric layer V is covered: on the first conductive layer, and has a first opening. Then, a second conductive layer is formed on the portion of the inner dielectric layer, and is electrically connected to the first conductive layer via the first opening. Next, a protective layer is covered on the transistor and the second conductive layer, and has a second opening. Finally, a third conductive layer is formed on the portion of the protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. In order to make the above description of the present invention more comprehensible, the following is a preferred embodiment of the invention, and is described in detail below with reference to the accompanying drawings: [Embodiment] The present invention is directed to having at least one storage capacitor for a conductive material. The structure of the pixel. The conductive material includes a light transmissive material, a reflective material, or a combination thereof. Embodiments of the present invention are described in detail by taking a pixel structure of a display panel in an optoelectronic device as an example. Further, the illustration of the embodiments is to omit certain elements in order to clearly show the technical features of the present invention. First Embodiment Referring to Figure 2A, there is shown a top plan view of a halogen structure of a first embodiment of the present invention. This embodiment is exemplified by a pixel structure 200 of a display panel in an optoelectronic device. As shown in Fig. 2A, the data line DT2 and the scan line SC2 are electrically connected to the pixel structure 200, respectively. Please refer to FIG. 2B, which is a cross-sectional view showing the structure of the halogen in FIG. 2A. Fig. 2B is a cross-sectional view taken along line 2B_2B' of Fig. 2A. Alizarin structure 200 contains

三達編號:TW3530PA 一電晶體(未標註)、〜 ,-内層介電層29。弟:=:^、-第-導電層 及一第三導電層243。較佳f :層犯、一保㈣280 包含一遮光圖案層(夫晝素結構200可選擇性地 掃描線SC2之至^少一繪示)’位於且平行於資料線DT2及 描線SC2之至少二:者之側邊,以防止資料線DT2及掃 第一儲存電容C之邊緣產生漏光現象。 290覆蓋於第一導⑵電性連接於電晶體。内層介電層 二導電層242形成於i二具有一開口 292。第 292電性連接於第一 J :内層介電層290上’且經由開口 體及第二導電層242電層241。保護層280覆蓋於電晶 層如形成部“護具有=開口心第三導電 於電晶體。第一健六 且經由開口 282電性連接 280及第二導電居子電容〜由第三導電層243、保護層 守私層242所構成。 晴參昭篦q Δ。tSanda number: TW3530PA A transistor (not labeled), ~, - inner dielectric layer 29. Dimensions: =: ^, - a first conductive layer and a third conductive layer 243. Preferably, f: layer constitutive, and one (four) 280 includes a light-shielding pattern layer (the sputum structure 200 can selectively scan the line SC2 to a lesser one), and is located at least two parallel to the data line DT2 and the line SC2. The side of the person is to prevent light leakage from the edge of the data line DT2 and the first storage capacitor C. 290 is electrically connected to the transistor by covering the first guide (2). Inner Dielectric Layer The second conductive layer 242 is formed on i and has an opening 292. The second electrode 292 is electrically connected to the first J: inner dielectric layer 290 and passes through the opening body and the second conductive layer 242. The protective layer 280 is covered on the electro-crystalline layer, such as the forming portion, and has a third conductive layer. The first sixth is electrically connected via the opening 282 and the second conductive capacitor is used. And the protective layer smuggling layer 242. Qingshen Zhaoqian q Δ.t

成方法之流程圖。書素^其繪示第2B圖之晝素結構之形 圖所示,於基板、、°冓200之形成方法如下:如第3A 一絕緣層250於半導=::H220,且接著覆蓋 二個摻雜區。+導體層220包含至少 區功是位於/祕及一本徵區222。—般而言,本徵 疋位於二個摻雜區22 个似 :明之實施例,可選擇性地 ;車二佳地’本 區從及二個摻雜區224a、224bq^卜摻雜區於本徵 另外捧雜區之摻雜濃度實f上小二者之間,且 之至少〜者、太舛「貝上J於一個摻雜區224a、224b 者本徵區222可摻雜或不摻雜,若摻雜時,本A flow chart of the method. The book is shown in the shape diagram of the halogen structure of FIG. 2B, and the method of forming the substrate, the temperature 200 is as follows: as the 3A, the insulating layer 250 is at the semi-conducting =::H220, and then covering the second Doped regions. The +conductor layer 220 includes at least a region where the function is located/secret and an intrinsic region 222. In general, the intrinsic enthalpy is located in two doped regions: 22, which may be selectively; the second region of the vehicle and the two doped regions 224a, 224bq^ The intrinsic doping concentration of the heterogeneous region is between f and small, and at least ~, too, "Beast J in a doped region 224a, 224b of the intrinsic region 222 may or may not be doped Miscellaneous, if doped, this

三達編號·· TW3530PA ^區222之極性較佳地與二個摻雜區224a、224b及另外 之極性實質上不同。另外,二個摻雜區勝展、 :222及/或另外摻雜區,亦可選擇 導體層220中或不同時形成於半導體層220中。再 之材f包括單晶之含石靖質、微晶之含石夕材 頻質、非晶之含讀f、含錯材質、或^ 它材質、或上述之組合。 &昇 戶25〇Τ:ΓΓ所示’形成第—導電層241於絕緣 = 250上。此時,電晶體之一 _216亦同時形成。 貫施例中,第—導電層241之材f是以反射材質(如、 銀、銅、鐵、錫、鉛、鎘、鉬、鎢、鉞、鈦、鈕、铪 其,材質、或上述之氧化物、或上述之氡化物、或丄述^ 兔氧化物、或上述之合金、或上述之級合)為實施範例,值 不限於此,亦可選擇性地使用透明材質(如:銦錫氧化物: 銘鋅氧化物、紹錫氧化物、銦鋅氧化物、鎘錫氧化物、或 其它材質、或上述之組合)或透明材質與反射材質之組人 此外,第一導電層241連接於一具有位準之電極線,例 共用電極線Vcom2,或亦可選擇性地使用部份具有位準’ 電極線,例如:共用電極線VCQm2當作第一導電層24ι(如 第2A圖所示)。其中,於本實施例中,電極線,例如 用電極線Vccln2之材質是以反射材質(如:金、銀、鋼、鐵^ 錫、錯、録、翻、鶴、敛、欽、组、給、戋其它材質 、 上述之氧化物、或上述之氮化物、或上述之氮^化物^ 上述之合金、或上述之組合)為貫施範例,但不限於此, 1351764The polarity of the ternary number TW3530PA ^ region 222 is preferably substantially different from the polarity of the two doped regions 224a, 224b and the other. In addition, the two doped regions, 222 and/or additional doped regions, may also be selected in the conductive layer 220 or not simultaneously formed in the semiconductor layer 220. The material f includes a quartz crystal containing a single crystal, a quartz crystal containing a microcrystal, an amorphous f-containing material, a mis-containing material, or a material thereof, or a combination thereof. & upgrade 25 〇Τ: ΓΓ shown 'formed the first conductive layer 241 on the insulation = 250. At this time, one of the transistors _216 is also formed at the same time. In the embodiment, the material f of the first conductive layer 241 is a reflective material (for example, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, button, bismuth, material, or the like) The oxide, or the above-mentioned telluride, or the description of the rabbit oxide, or the above-mentioned alloy, or the above-mentioned alloy, is an example, and the value is not limited thereto, and a transparent material (for example, indium tin) may be selectively used. Oxide: Ming zinc oxide, Shaoxi oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Further, the first conductive layer 241 is connected to An electrode line having a level, for example, a common electrode line Vcom2, or alternatively a portion having a level electrode line, for example, a common electrode line VCQm2 as the first conductive layer 24 (as shown in FIG. 2A) ). In the present embodiment, the electrode wire, for example, the material of the electrode wire Vccln2 is made of a reflective material (eg, gold, silver, steel, iron, tin, wrong, recorded, turned, crane, condensed, chin, group, given) And other materials, the above-mentioned oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen compounds, or the above-mentioned alloys, or a combination thereof, are examples, but are not limited thereto, 1351764

三達編號:TW3530PA 可選擇性地使用透明材質(如:銦錫氧化物 銘錫氧化物、銦鋅氧化物、麵氧化物、^鋅氡化物、 上述之組合)、或透明#質及反射材質之組合、^質、或 -導電層241連接於電極線,例如:共用矣言<,第 材質實質上相同或不同,較佳地,二者實Μ 低製程複雜性。 、上相同,以滅 接著,如第3C圖所示,覆蓋内層介電 曰50上,且分別形成開口 於内層介電:0於絕緣 開口 23U、册於内層介電層290及絕緣層\及兩個 然後,如第3D圖所示,形成第二^ | 。 之内層介電層290上,且經由開口 292、23ι^2於部份 =性連接於第一導電層241及半導體層22〇。复=分别 開口 231a、231b兩祕$ ^办 共中’經由 〇zl〇 B 生連接於半導體層220的第_ Γ中體之,212及-源極叫。= 銅、鐵=層ΓΓ質是以反射材質(如:金、銀、 材質'或:丄 鶴、敛、鈦、麵、給、或其它 化物、ί上述之2物、或上述之氮化物、或上述之氮氧 於此,介"口金、或上述之組合)為實施範例,但不限 氧亦可選擇性地使用透明材質(如:錮錫氧化物、 ::物^化物、銦辞氧化物,錫氧化物、或其它 者,^上述之組合)、或透明材質與反射材質之組合。再 日日體之源極214及汲極212之1中一者雷性逵拄# 貧料線dT2(如第2Α __、 L、干者電性連接於 連接於播> θ斤不)’且電晶體之閘極216電性 、田4 SC2(如第2Α圖所示)。必需說明的是,本實 11 1351764Sanda number: TW3530PA can selectively use transparent materials (such as: indium tin oxide, tin oxide, indium zinc oxide, surface oxide, zinc oxide, combination of the above), or transparent #质 and reflective materials The combination, the quality, or the conductive layer 241 is connected to the electrode lines, for example, the common vocabulary <the first material is substantially the same or different, and preferably, both of them have low process complexity. And the same as above, and then, as shown in FIG. 3C, covering the inner dielectric layer 50, and respectively forming openings in the inner layer dielectric: 0 in the insulating opening 23U, in the inner dielectric layer 290 and the insulating layer and Two then, as shown in Fig. 3D, form a second ^|. The inner dielectric layer 290 is connected to the first conductive layer 241 and the semiconductor layer 22 by a portion 292, 23 ι^2. The respective openings 231a and 231b are connected to the first body of the semiconductor layer 220 via the 〇zl〇B, and the 212 and the source are called. = copper, iron = layer enamel is a reflective material (such as: gold, silver, material 'or: 丄 crane, condensed, titanium, surface, give, or other compounds, 上述 the above two, or the above nitride, Or the above-mentioned nitrogen oxides, the combination of "mouth gold, or a combination of the above" is an example, but an oxygen-free material may also be selectively used (for example, antimony tin oxide, :: substance, indium) Oxide, tin oxide, or others, combinations of the above, or a combination of a transparent material and a reflective material. One of the source of the Japanese body 214 and the first of the 212 poles of the thunderstorm 逵拄# poor material line dT2 (such as the second Α __, L, the dry connection is connected to the broadcast > θ kg not) And the gate 216 of the transistor is electrically, and the field 4 SC2 (as shown in Figure 2). It must be stated that this real 11 1351764

三顯號:TW3530PA 施例之開口 231a、231b及292於非同一時間下所形成的, ' : 但不限於此,亦可選擇性地使用具有不同透光度光罩(如: *; 半調光罩、繞射光罩、柵狀圖案光罩、或其它光罩、或上 • 述之組合)之黃光製程,於同一時間下,形成開口 231a、 231b 及 292。 接著,如第3E圖所示,覆蓋保護層280於電晶體及 第二導電層242上,且保護層280具有一開口 282。 最後,如第3F圖所示,形成第三導電層243(亦稱晝 φ 素電極)於部份之保護層280上,且經由開口 282電性連接 於電晶體。其中,開口 282可選擇性地實質上對準或不對 準開口 231b。如此一來,整體之晝素結構200即如同第 3F圖所示。於本實施例中,第三導電層243之材質是以透 光材質(如:銦錫氧化物、鋁鋅氧化物、鋁錫氧化物、銦鋅 氧化物、鎘錫氧化物、或其它材質、或上述之組合)為實施 範例,但不限於此,亦可選擇性地使用反射材質(如:金、 銀、銅、鐵、錫、船、編、翻、鎢、歛、欽、组、給、或 • 其它材質、或上述之氧化物、或上述之氮化物、或上述之 氮氧化物、或上述之合金、或上述之組合)、或透明材質與 反射材質之組合。Three signs: TW3530PA The openings 231a, 231b and 292 of the example are formed at different times, ' : but not limited to this, optionally using different transmittance masks (eg: *; halftone Openings 231a, 231b, and 292 are formed at the same time by a yellow light process of a reticle, a diffractive reticle, a grid pattern mask, or other reticle, or a combination thereof. Next, as shown in FIG. 3E, the protective layer 280 is covered on the transistor and the second conductive layer 242, and the protective layer 280 has an opening 282. Finally, as shown in Fig. 3F, a third conductive layer 243 (also referred to as a φφ-element electrode) is formed on a portion of the protective layer 280, and is electrically connected to the transistor via the opening 282. Therein, the opening 282 can selectively substantially align or misalign the opening 231b. As a result, the overall pixel structure 200 is as shown in Fig. 3F. In this embodiment, the material of the third conductive layer 243 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, Or a combination of the above), but is not limited thereto, and may also selectively use a reflective material (eg, gold, silver, copper, iron, tin, boat, braid, turn, tungsten, condensed, chin, group, give Or other materials, or the above oxides, or the above-described nitrides, or the above-described nitrogen oxides, or the above-described alloys, or a combination thereof, or a combination of a transparent material and a reflective material.

於本實施例中,由於第一導電層241及第二導電層 242為共電位之電阻,也就是並聯設計,因此可降低電極 線,例如:共用電極線V com2 之負載阻抗。如此一來,即 可避免光電裝置中顯示面板於顯示晝面時產生串音現象 (cross-talk) ° 12 1351764In the present embodiment, since the first conductive layer 241 and the second conductive layer 242 have a common potential resistance, that is, a parallel design, the electrode lines, for example, the load impedance of the common electrode line V com2 can be reduced. In this way, cross-talk can be avoided when the display panel in the optoelectronic device displays the kneading surface. ° 12 1351764

: TW3530PA . 再者,絕緣層250、内層介電層290及保護層280之 ; 至少一者之材質,包含無機材質(如:氧化矽、氮化矽、氮 : 氧化矽、氧化铪、氮化铪、碳化矽、或其它材質、或上述 之組合)、有機材質(如:光阻、聚丙酿鍵(P〇lyarylene ether ; PAE)、聚醯類、聚酯類、聚醇類、聚烯類、苯並環丁烯 (benzocyclclobutene ; BCB) 、 HSQ (hydrogen silsesquioxane)、MSQ(methyl silesquioxane)、石夕氧碳氫化 物(SiOC-H)、或其它材質、或上述之組合)、或上述之組合。 • 本實施例之第二導電層242可選擇性地採用反射材 質、透光材質、或上述之組合。第圖之第二導電層242 是以反射材質為實施範例。請參照第4圖,其繪示第一實 施例之另-晝素結構之剖面圖。晝素結構3〇〇包含一電晶 體(未標註)、一第一儲存電交 ^ 〇^ 1 电合Cs3丨、一第一導電層341、一 内層介電層390、一第-增泰β。 乐一導電層342、一保護層380及一 第三導電層343。第二導艰 等电層342形成於部份内層介電層 390上’且經由開口 392铯k、圭& 電性連接於第一導電層341。第 • 2Β圖之第二導電層M2夕从陆θ 之材質是以反射材質為實施範 例,而第4圖之第二導雷思 €層342之材質是以透光材質為實 施範例,但不限於此。上诎咖—曰 上34内容是以晝素結構200為範例 說明其之形成方法,晝素鮏 、、、《構300之形成方法與晝素結構 200之形成方法相同,因孙τ —去、— 匕不在重複敘述。但值得注意的 是,晝素結構200之第二道# & a 一導電層242與畫素結構300之第 導電層342之材料是以y n ,, 地,晝 亦具有上述所提之方式。且由於晝素結 乂不同之材質作為實施範例。同樣 13 1351764 ?: TW3530PA. Further, the insulating layer 250, the inner dielectric layer 290 and the protective layer 280; at least one of the materials, including inorganic materials (such as: yttrium oxide, tantalum nitride, nitrogen: yttrium oxide, yttrium oxide, nitriding铪, tantalum carbide, or other materials, or a combination of the above), organic materials (such as: photoresist, polypropylene powder (PAE), polyfluorenes, polyesters, polyesters, polyolefins , benzocycl Clobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen hydrocarbon (SiOC-H), or other materials, or a combination thereof, or a combination thereof . • The second conductive layer 242 of this embodiment can be selectively made of a reflective material, a light transmissive material, or a combination thereof. The second conductive layer 242 of the figure is an embodiment of the reflective material. Referring to Figure 4, there is shown a cross-sectional view of the other-alkaline structure of the first embodiment. The halogen structure 3〇〇 comprises a transistor (not labeled), a first storage electrical connection, a first conductive layer 341, an inner dielectric layer 390, and a first-enhanced beta. . A conductive layer 342, a protective layer 380 and a third conductive layer 343. The second conductive layer 342 is formed on the portion of the inner dielectric layer 390 and electrically connected to the first conductive layer 341 via the openings 392 铯 k, 圭 & The material of the second conductive layer M2 of the second image is the reflection material as an example, and the material of the second layer of the third layer of the fourth layer of the fourth layer is a light-transmitting material, but not Limited to this. The content of the upper 诎 曰 曰 曰 34 昼 昼 昼 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 — 匕 Do not repeat the narrative. It should be noted, however, that the second material of the halogen structure 200, a conductive layer 242 and the first conductive layer 342 of the pixel structure 300, is y n , , and 昼 also has the above-mentioned manner. And because of the different materials of the element, the material is used as an example. Same 13 1351764 ?

^ 三_號:TW3530PA • 構300之第二導電層342是以透光材質為實施範例,因此 ; 晝素結構300可用於配合不同之運用實施方式。 第二實施例 請參第5A圖,其繪示本發明第二實施例之晝素結構 之上視示意圖。本實施例是以一光電裝置中顯示面板之晝 素結構400舉例說明。如第5A圖所示,資料線DT4i: DT42及掃描線SC4為分別與晝素結構4〇〇電性連接。請 參照第5B圖’其繪示第5A圖之晝素結構之剖。^ 5B圖為沿著第5A圖中之5Β·5Β,剖面線之剖面圖。 構400包含-電晶體(未標註)、一第一儲存 ° 第一導電層441、一内層介電層490、一第二二一 保捕、-第二導電層⑷及—第四 較佳地,晝*結構_可性地包含—遮^ 於且平行於資料線DT41、DT42及掃描線sc4^ =二 之側邊,以防止資料線的4卜DT42及掃描線=^ 一者之邊緣產生漏光現象。 之至乂 第-儲存電容Cs41電性連接於電日日日體 490覆蓋於第-導電層441上,且苴且有内層"電層 二導電層442形成於部份内層介電層490上:::2。第 492,連接於第—導電層441。保護層 體及第二導電層442上,且其具有-開口 482 ;= 層443形成部份保護層48〇上,且經由開 於電晶體。篦ra邋雪思h 電性連接 4四導電層444覆蓋於第二導電層442與部份 1351764^三_: TW3530PA • The second conductive layer 342 of the structure 300 is an example of a light-transmitting material, and therefore, the halogen structure 300 can be used to match different application embodiments. SECOND EMBODIMENT Referring to Figure 5A, there is shown a top plan view of a halogen structure of a second embodiment of the present invention. This embodiment is exemplified by a pixel structure 400 of a display panel in an optoelectronic device. As shown in FIG. 5A, the data lines DT4i: DT42 and the scan lines SC4 are electrically connected to the pixel structure 4A, respectively. Please refer to Fig. 5B' for a section showing the structure of the halogen in Fig. 5A. ^ 5B is a cross-sectional view taken along line 5Β·5Β in Figure 5A. The structure 400 includes a transistor (not labeled), a first storage layer, a first conductive layer 441, an inner dielectric layer 490, a second two-dimensional arrest, a second conductive layer (4), and a fourth preferred , 昼 * structure _ can be included - and parallel to the side of the data lines DT41, DT42 and scan line sc4 ^ = two, to prevent the edge of the data line 4 DT42 and scan line = ^ Light leakage. The first storage capacitor Cs41 is electrically connected to the electric solar cell 490 over the first conductive layer 441, and has an inner layer " an electric layer two conductive layer 442 formed on a portion of the inner dielectric layer 490. :::2. No. 492 is connected to the first conductive layer 441. The protective layer and the second conductive layer 442 have an opening 482; the layer 443 forms a partial protective layer 48 and is opened via a transistor.篦ra邋雪思h Electrical connection 4 four conductive layer 444 covering the second conductive layer 442 and part 1351764

一達編號:TW3530PA 内層介電層490上,以使得第一儲存電容 卜一 層443、保護層480、第四導電層444⑷由第三導電 所構成。 及名二導電層442 請參照第6A〜6G圖,其繪示第5b圖 成方法之流程圖。晝素結構400之形成 里素結構之形 圖所示,於基板409上形成一半導體層42〇如下:如第兮 —絕緣層45〇於半導體層42〇上。丰 ,且接著覆盍 二個摻雜區424a、雛及—本徵;伽包含至少 區422是位於二個摻雜區42如、似 般而言,本徵 發明之實施例,可選擇性地加入至少曰。較佳地,本 區422及二個摻雜區424a、424b之至,丨1 卜捧雜區於本徵 外摻雜區之_濃度實質 者之間,且另 之黾Ψ ^ , ^ 個擦雜區424a、424b 之至〆-者、本徵區422可推 424b 徵區422之極性鱼-彻哎雜,右摻雜時,本 之極性較佳騎質上—不個π接雜區424a、424b及另外摻雜區 本徵區 或另 tmi#sii£ 424a、424b、 _中42。或不同時形成;:==時形成於半 導體層420之材質包層420中。再者,半 質、多晶之含石夕材暂 含石夕材質、微晶之含石夕材 、 材質、非晶之含矽材質、会鍺材皙七甘 它材質、或上述之組合。 7材質3鍺材貝、或其 然後,如第犯圖所+ 層彻上。此時,成第—導電層441於絕緣 實施例中,第-導電層Θ4=θ416亦同時形成。於本 銀、銅、鐵、錫、錯、鑛、:材:疋以反射材質(如:金、 ’ 鉬嫣、敍、鈦、组、給、或 15 1351764One of the TW3530PA inner dielectric layers 490 is such that the first storage capacitor layer 443, the protective layer 480, and the fourth conductive layer 444 (4) are formed of a third conductive layer. Referring to Figures 6A to 6G, a flow chart of the method of Figure 5b is shown. Formation of the Alizarin Structure 400 As shown in the figure, a semiconductor layer 42 is formed on the substrate 409 as follows: for example, the insulating layer 45 is on the semiconductor layer 42. Abundantly, and then covering the two doped regions 424a, smear and intrinsic; gamma comprising at least region 422 is located in the two doped regions 42 as, in general, an embodiment of the intrinsic invention, optionally Join at least 曰. Preferably, the region 422 and the two doped regions 424a, 424b are between 丨1 and the nucleus region of the intrinsic outer doped region, and the other is 黾Ψ ^ , ^ The heterogeneous regions 424a, 424b to the 〆-, the intrinsic region 422 can push 424b the polar fish of the zoning region 422 - the complete impurity, the right doping, the polarity is better on the ride - no π junction region 424a , 424b and another doped area intrinsic area or another tmi#sii£ 424a, 424b, _42. Or not formed at the same time;: == is formed in the material cladding 420 of the semiconductor layer 420. In addition, the semi-mass and polycrystalline stone-containing materials contain Shishi material, microcrystalline stone material, material, amorphous yttrium material, material 皙 甘 甘 它, its material, or a combination of the above. 7 material 3 coffin shell, or its, then, as the first line of the map + layer. At this time, the first conductive layer 441 is formed in the insulating embodiment, and the first conductive layer Θ4 = θ416 is also formed at the same time. In this silver, copper, iron, tin, wrong, ore, material: 疋 with reflective material (such as: gold, 'molybdenum bismuth, Syria, titanium, group, give, or 15 1351764

三達編號:TW3530PA 其它材質、或上述之氧化物、或上述之氮化物、或上述之 : 氮氧化物、或上述之合金、或上述之組合)為實施範例,但 *- 不限於此,亦可選擇性地使用透明材質(如:銦錫氧化物、 • 銘鋅氧化物、铭錫氧化物、銦鋅氧化物、錢錫氧化物、或 其它材質、或上述之組合)、或透明材質與反射材質之組 合。此外,第一導電層441連接於一具有位準之電極線, 例如:共用電極線Vcom4(如第5A圖所示),但不限於此, 亦可選擇性地使用部份具有位準之電極線,例如:共用電 φ 極線Vcom4當作第一導電層441。其中,於本實施例中,電 極線,例如:共用電極線Vcom4之材質是以反射材質(如: 金、銀、銅、鐵、錫、錯、錫、錮、鶴、敍、鈦、组、給、 或其它材質、或上述之氧化物、或上述之氣化物、或上述 之氮氧化物、或上述之合金、或上述之組合)為實施範例, 但不限於此,亦可選擇性地使用透明材質(如:銦錫氧化 物、紹辞氧化物、铭錫氧化物、銦鋅氧化物、錫錫氧化物、 或其它材質、或上述之組合)、或透明材質及反射材質之組 • 合。換言之,第一導電層441連接於電極線,例如:共用 電極線Vcom4之材質實質上相同或不同,較佳地,二者實 質上相同,以減低製程複雜性。 接著,如第6C圖所示,覆蓋内層介電層490於絕緣 層450上,且分別形成開口 492於内層介電層490及兩個 開口 431a、431b於内層介電層490及絕緣層450。 然後,如第6D圖所示,形成第二導電層442於部份 之内層介電層490上,且經由開口 492、431a、431b分別 16 1351764Sanda number: TW3530PA Other materials, or the above oxides, or the above-mentioned nitrides, or the above: nitrogen oxides, or the above alloys, or a combination thereof, are examples, but *- are not limited thereto, Selectively use transparent materials (such as: indium tin oxide, • zinc oxide, tin oxide, indium zinc oxide, money tin oxide, or other materials, or a combination of the above), or transparent materials and A combination of reflective materials. In addition, the first conductive layer 441 is connected to a level electrode line, for example, the common electrode line Vcom4 (as shown in FIG. 5A), but is not limited thereto, and some partially-positioned electrodes may be selectively used. A line, for example, a common electric φ pole line Vcom4 is regarded as the first conductive layer 441. In this embodiment, the electrode line, for example, the material of the common electrode line Vcom4 is made of a reflective material (eg, gold, silver, copper, iron, tin, erroneous, tin, antimony, crane, sulphur, titanium, group, The application, or other materials, or the above oxides, or the above-mentioned vapors, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, are examples, but are not limited thereto, and may be selectively used. Transparent material (such as: indium tin oxide, rheumatism oxide, tin oxide, indium zinc oxide, tin tin oxide, or other materials, or a combination of the above), or a combination of transparent materials and reflective materials . In other words, the first conductive layer 441 is connected to the electrode lines. For example, the materials of the common electrode lines Vcom4 are substantially the same or different, and preferably, the two are substantially the same to reduce the process complexity. Next, as shown in FIG. 6C, the inner dielectric layer 490 is covered on the insulating layer 450, and an opening 492 is formed in the inner dielectric layer 490 and the two openings 431a and 431b in the inner dielectric layer 490 and the insulating layer 450, respectively. Then, as shown in Fig. 6D, a second conductive layer 442 is formed on a portion of the inner dielectric layer 490, and via openings 492, 431a, 431b, respectively, 16 1351764

三達編號:TW3530PA 電性連接於第一導電層441及半導體層420。其中,經由 •: 開口 431a、431b電性連接於半導體層420的第二導電層 ;442是當作電晶體之一汲極412及一源極414。於本實施 • 例中,第二導電層442之材質是以反射材質(如:金、銀、 銅、鐵、錫、鉛、鎘、鉬、鎢、鉉、鈦、鈕、鈴、或其它 材質、或上述之氧化物、或上述之氮化物、或上述之氮氧 化物、或上述之合金、或上述之組合)為實施範例,但不限 於此,亦可選擇性地使用透明材質(如:銦錫氧化物、鋁鋅 • 氧化物、鋁錫氧化物、銦鋅氧化物、鎘錫氧化物、或其它 材質、或上述之組合)、或透明材質與反射材質之組合。再 者電阳體之及極412及源極414之其中一者電性連接於 育料線DT4卜DT42(如第5A圖所示),且電晶體之閘極 4a16電性連接於掃描線SC4(如第5A圖所示)。必需說明的 疋’本實施例之開口 431a、431b及492於非同一時間下 所形成的,但不限於此,亦可選擇性地使用具有不同透光 ^ 度光罩(如:半調光罩、繞射光罩、柵狀圖案光罩、或其它 光罩、或上述之組合)之黃光製程,於同一時間下,形成開 口 431a、431b 及 492。 接著’如第6E圖所示,覆蓋第四導電層444於第二 導電層442與部份之内層介電層490上。於本實施例中, 以第四導電層444之材質為透光材質作為實施範例,但不 限於此’亦可選擇性地使用反射材質或透光材質與反射材 質之組合。此外,由於第一導電層441、第二導電層442 及第四導電層444相互電性連接,因此第一導電層441、 17 1351764Sanda number: TW3530PA is electrically connected to the first conductive layer 441 and the semiconductor layer 420. The second conductive layer is electrically connected to the semiconductor layer 420 via the openings 431a and 431b; the 442 is a drain 412 and a source 414 of the transistor. In this embodiment, the second conductive layer 442 is made of a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, button, bell, or other material). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material may be selectively used (for example: Indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the pole 412 and the source 414 of the electric male body is electrically connected to the feed line DT4 DT42 (as shown in FIG. 5A), and the gate 4a16 of the transistor is electrically connected to the scan line SC4. (as shown in Figure 5A). It should be noted that the openings 431a, 431b, and 492 of the present embodiment are formed at different times, but are not limited thereto, and a mask having different light transmittances (for example, a half-tone mask) may be selectively used. The yellow light process of the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 431a, 431b, and 492 at the same time. Next, as shown in FIG. 6E, the fourth conductive layer 444 is covered on the second conductive layer 442 and a portion of the inner dielectric layer 490. In the present embodiment, the material of the fourth conductive layer 444 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto. A reflective material or a combination of a light-transmitting material and a reflective material may be selectively used. In addition, since the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 are electrically connected to each other, the first conductive layer 441, 17 1351764

三達編號:TW3530PA 第二導電層442及第四導電層444之位準為實質上相同。 : 且第一導電層441、第二導電層442及第四導電層444之 ; 位準包含,例如:共用位準。 • 另外,於本實施例中,汲極412與掃描線SC4之間 具有一第一寄生電容,且汲極412與資料線DT41、DT42 之間各具有之電容之總和實質上為一第二寄生電容。此 外,晝素結構400之晝素電極與共用電極(未繪示)之間具 有一液晶電容(未繪示)。畫素結構400之一晝素電容實質 • 上等於液晶電容與第一儲存電容Cs41之和。第四導電層 444之面積即是決定於第一寄生電容與晝素電容之比、第 二寄生電容與晝素電容之比及第一儲存電容Cs41與液晶電 容之比。於本實施例之第四導電層444之面積,較佳地, 實質上大於第二導電層442之面積,但不限於此,亦可視 設計上之要求,來選擇性地改變第四導電層444之面積, 如:其實質上比第二導電層442之面積小、其實質上相等 於第二導電層442之面積、或上述之組合。 • 然後,如第6F圖所示,覆蓋保護層480於電晶體及 第二導電層442上,且保護層480具有一開口 482。 最後,如第6G圖所示,形成第三導電層443(亦稱晝 素電極)於部份之保護層480上,且經由開口 482電性連接 於電晶體。其中,開口 482可選擇性地實質上對準或不對 準開口 431b。如此一來,整體之畫素結構400即如同第 6G圖所示。於本實施例中,第三導電層443之材質是以 透光材質(如:銦錫氧化物、鋁鋅氧化物、鋁錫氧化物、銦 18 丄乃1764Sanda number: TW3530PA The level of the second conductive layer 442 and the fourth conductive layer 444 are substantially the same. And the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444; the level includes, for example, a common level. In addition, in this embodiment, the first parasitic capacitance is between the drain 412 and the scan line SC4, and the sum of the capacitances between the drain 412 and the data lines DT41 and DT42 is substantially a second parasitic. capacitance. In addition, a liquid crystal capacitor (not shown) is disposed between the halogen electrode of the halogen structure 400 and the common electrode (not shown). One of the pixel structures 400 is substantially equal to the sum of the liquid crystal capacitor and the first storage capacitor Cs41. The area of the fourth conductive layer 444 is determined by the ratio of the first parasitic capacitance to the halogen capacitance, the ratio of the second parasitic capacitance to the halogen capacitance, and the ratio of the first storage capacitor Cs41 to the liquid crystal capacitance. The area of the fourth conductive layer 444 in the present embodiment is preferably substantially larger than the area of the second conductive layer 442, but is not limited thereto, and the fourth conductive layer 444 may be selectively changed according to design requirements. The area is, for example, substantially smaller than the area of the second conductive layer 442, substantially equal to the area of the second conductive layer 442, or a combination thereof. • Then, as shown in FIG. 6F, the protective layer 480 is overlaid on the transistor and the second conductive layer 442, and the protective layer 480 has an opening 482. Finally, as shown in Fig. 6G, a third conductive layer 443 (also referred to as a germanium electrode) is formed on a portion of the protective layer 480, and is electrically connected to the transistor via the opening 482. Therein, the opening 482 can selectively substantially align or misalign the opening 431b. As a result, the overall pixel structure 400 is as shown in Fig. 6G. In this embodiment, the material of the third conductive layer 443 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium 18 丄 is 1764).

• : TW3530PA ' . 鋅氡化物、鎘錫氧化物、或其它材質、或上述之組合)為 • 實施範例,但不限於此,亦可選擇性地使用反射材質(如: 金銀、銅、鐵、锡、錯、箱)、翻、鎮、欽、钦、短、給、 或其它材質、或上述之氧化物、或上述之氮化物、或上述 之氮氧化物、或上述之合金、或上述之組合)、或透明材質 與反射材質之組合。 於本實施例中,第四導電層444採用透光材質,因此 鲁 晝素結構400可於不變更電容值之情況下增加開口率,但 不限於此’亦可使用反射材質、或透光材質及反射材質之 組合。此外’第四導電層444可選擇性地不與任何閘極線 或資料線相互重疊’因此可減少閘極線或資料線上的負 载’但不限於此,亦可選擇性地部份重疊。 再者’第一導電層441、第二導電層442及第四導電 層444為共電位之電阻,也就是並聯設計’因此可降低電 極線’例如:共用電極線Vcotn4之負載阻抗。如此一來, 即可避免光電裝置中顯示面板於顯示晝面時產生串音現 象。 再者,絕緣層450、内層介電層490及保護層480之 至少一者之材質,包含無機材質(如:氧化矽、氮化矽、氮 氧化矽、氧化铪、氮化铪、碳化矽、或其它材質、或上述 之組合)、有機材質(如:光阻、聚丙醯醚(polvarylene ether ; PAE)、聚醯類、聚酯類、聚醇類、聚烯類、苯並環丁烯 (benzocyclclobutene ; BCB) 、 HSQ (hydrogen silsesquioxane)、MSQ(methyl silesquioxane)、妙氧碳氫化 19 1351764• : TW3530PA ' . Zinc telluride, cadmium tin oxide, or other materials, or combinations of the above) are • Examples, but not limited to, selective use of reflective materials (eg, gold, silver, copper, iron, Tin, wrong, box), turned, town, ching, ching, short, giving, or other materials, or the above oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above alloys, or the above Combination), or a combination of a transparent material and a reflective material. In the embodiment, the fourth conductive layer 444 is made of a light-transmitting material. Therefore, the ruthenium structure 400 can increase the aperture ratio without changing the capacitance value, but is not limited to the use of a reflective material or a light-transmitting material. And a combination of reflective materials. Further, the fourth conductive layer 444 can selectively overlap with any gate line or data line. Thus, the load on the gate line or the data line can be reduced, but is not limited thereto, and can be selectively partially overlapped. Further, the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 have a common potential resistance, that is, a parallel design. Therefore, the load impedance of the electrode line 'e.g., the common electrode line Vcotn4 can be lowered. In this way, it is possible to avoid the occurrence of crosstalk when the display panel in the optoelectronic device displays the kneading surface. Furthermore, at least one of the insulating layer 450, the inner dielectric layer 490 and the protective layer 480 is made of an inorganic material (eg, cerium oxide, cerium nitride, cerium oxynitride, cerium oxide, tantalum nitride, tantalum carbide, Or other materials, or a combination of the above, organic materials (such as: photoresist, polvarylene ether (PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclobutene ( Benzylcyclclobutene ; BCB) , HSQ (hydrogen silsesquioxane ) , MSQ ( methyl silesquioxane ) , oxy oxygenation 19 1351764

三達編號:TW3530PA 物(SiOC-H)、或其它材質、或上述之組合)、或上述之組合。 第三實施例 請參第7A圖,其繪示本發明第三實施例之晝素結構 之上視示意圖。本實施例是以一光電裝置中顯示面板之晝 素結構500舉例說明。如第7A圖所示,資料線DT5及掃 描線SC5為分別與晝素結構500電性連接。請參照第7B 圖’其繪示第7A圖之晝素結構之剖面圖。第7b圖為 > 著 第7A圖中之7B-7B’剖面線之剖面_。晝素結構5〇〇 ^人 一電晶體(未標註)、一第一儲存電容cs5l、一m 3 SM 矛—儲存番 谷CS52、一第三儲存電容CS53、一第一導電層5竹— 2介電層590、-第二導電層542、—絕緣層:二2 體層52〇、一保護層580及一第三導電戶 導 於且平行於資料線DT5及掃 ,、s 、,、e示),饮 τ5细硬SC5之至少〜土 邊,以防止資料線DT5及掃描 ^者之匈 線奶之至少-者之邊緣 晝素結構,可選擇性地包含一遮;父佳地, 且巫分你签―⑽m 口茶層(禾繪不),饮 防止資料線 產生漏光現象 第一儲存電容Cm電性 59〇覆蓋於第一導電層541上,;電晶體。内層介電層 二導電層542形成於部份内層介f其具有一開σ 592。第 592電性連接於第一導電層;::。包層590上,且經由開口 體及第二導電層542上,且其具保濩層580覆蓋於電晶 層543形成部份保護層58〇上了有—開口 582。第三導電 於電晶體。第-儲存電容c上%由開口 582電性連接 SS1由第三導雷声5 ^ 等电禮M3、保護層 20 x^1764Sanda number: TW3530PA (SiOC-H), or other materials, or a combination thereof, or a combination thereof. THIRD EMBODIMENT Referring to Fig. 7A, there is shown a top plan view of a halogen structure of a third embodiment of the present invention. This embodiment is exemplified by a pixel structure 500 of a display panel in an optoelectronic device. As shown in Fig. 7A, the data line DT5 and the scan line SC5 are electrically connected to the halogen structure 500, respectively. Please refer to FIG. 7B for a cross-sectional view showing the structure of the pixel in FIG. 7A. Fig. 7b is a section _ of the 7B-7B' hatching in Fig. 7A. Alizarin structure 5 〇〇 ^ person a transistor (not labeled), a first storage capacitor cs5l, a m 3 SM spear - storage fan CS52, a third storage capacitor CS53, a first conductive layer 5 bamboo - 2 The dielectric layer 590, the second conductive layer 542, the insulating layer: the two body layer 52A, a protective layer 580 and a third conductive household are guided and parallel to the data line DT5 and the sweep, s,, and e ), drink τ5 fine hard SC5 at least ~ soil edge, to prevent the data line DT5 and the scan of the Hungarian line of milk at least - the edge of the alizarin structure, optionally containing a cover; father good land, and witch Divide you to sign (10) m mouth tea layer (Wu draw no), drink to prevent light leakage from the data line. The first storage capacitor Cm is electrically overlaid on the first conductive layer 541; the transistor. Inner Dielectric Layer The two conductive layers 542 are formed in a portion of the inner layer f having an opening σ 592. The first 592 is electrically connected to the first conductive layer;::. The cladding layer 590 is over the opening body and the second conductive layer 542, and the protective layer 580 is covered on the electro-crystalline layer 543 to form a partial protective layer 58 with an opening 582. The third is electrically conductive to the transistor. The first-storage capacitor c is electrically connected by the opening 582. The SS1 is controlled by the third thunder. 5 ^ equals the electric ceremony M3, the protective layer 20 x^1764

二達編號:TW3530PA 58〇及第二導電層542所構成。第二儲存 導電層541、絕緣層550及部分半導體層52〇所構成。第 =儲存電容Cs53由第二導電層542、内層介電層59〇、°絕 緣層550及部分半導體層520所構成。 請參照第8A〜8F圖,其繪示第7B圖之晝素結構之形 战方法之流程圖。晝素結構500之形成方法如下: ,所示,於基板509上形成一半導體層52〇,且 絕緣層550於半導體層52〇上。半導體層52^含 及一本徵區办 之 範一金屬層541之下方來當作實施 之Π /而S徵區522是位於二個摻雜區似a、 少一另,本發^實财彳,可轉祕加入至 另==…二個摻雜區%、· 夕者之間’且另外摻雜區之摻雜嚿庳每讲 個捧雜區524a、524b之至少打又只貝上小於二 ,,若摻雜時,本徵區⑵之極性本= 524b及另外摻雜區之極性較 :-個‘雜區加、 穆雜區524a、524b、太^佳地只質上不同。另外,二個 選擇性地同時形成於半^或另外摻雜區,亦可 體層520 t。再者,半導二=不同時形成於半導 :質、微晶之含頻質、多b;之含包括單晶之切 質、含鍺材質、戍立它枯β 材質、非晶之含石夕材 妙尨“ 材質、或上述之組合。 “後,如第8Β圖所示 層550上。此時 f導電層541於絕緣 體之—閘極516亦同時形成。於本 21 1351764Erda number: TW3530PA 58〇 and second conductive layer 542. The second storage conductive layer 541, the insulating layer 550, and a portion of the semiconductor layer 52 are formed. The first storage capacitor Cs53 is composed of a second conductive layer 542, an inner dielectric layer 59A, an insulating layer 550, and a portion of the semiconductor layer 520. Please refer to Figures 8A-8F for a flow chart showing the method of modeling the pixel structure of Figure 7B. The method of forming the halogen structure 500 is as follows: As shown, a semiconductor layer 52 is formed on the substrate 509, and the insulating layer 550 is on the semiconductor layer 52. The semiconductor layer 52^ is included in the lower portion of the template-type metal layer 541 of the intrinsic region as the implementation layer / and the S-signal region 522 is located in the two doped regions, such as a, one less, and the other is彳, can be transferred to another ==...two doped regions%,· Between the eve and the doping of the additional doped region 至少 at least each of the 524a, 524b Less than two, if doped, the polarity of the intrinsic region (2) = 524b and the polarity of the other doped regions are: - a 'hybrid zone plus, Mu miscellaneous zone 524a, 524b, too good quality only qualitatively different. Alternatively, two selectively formed simultaneously in the half or additional doped regions may also be in the bulk layer 520 t. Furthermore, the semiconducting two = is not formed in the semiconducting: the quality of the crystal, the crystallite, and the b; the inclusion of the single crystal, the crucible, the beta, the amorphous Shi Xi Ti Miao 尨 "Material, or a combination of the above. "After, as shown in Figure 8 on layer 550. At this time, the f conductive layer 541 is also formed at the same time as the gate 516 of the insulator. Yu Ben 21 1351764

三達編號:TW3530PA . 實施例中,第一導電層541之材質是以反射材質(如:金、 ·' 銀、銅、鐵、錫、錯、錫、链、鎢、鈥、欽、I旦、給、或 - 其它材質、或上述之氧化物、或上述之Ιι化物、或上述之 iu氧化物、或上述之合金、或上述之組合)為實施範例,但 不限於此,亦可選擇性地使用透明材質(如:銦錫氧化物、 在呂鋅氧化物、铭錫氧化物、銦鋅氧化物、錫錫氧化物、或 其它材質、或上述之組合)或透明材質與反射材質之組合。 此外,第一導電層541連接於一具有位準之電極線,例如: • 共用電極線VC()m5(如第7A圖所示),但不限於此,亦可選 擇性地使用部份具有位準之電極線,例如:共用電極線 VC()m5當作第一導電層541。其中,於本實施例中,共用電 極線Sanda number: TW3530PA. In the embodiment, the material of the first conductive layer 541 is made of reflective material (such as: gold, · 'silver, copper, iron, tin, wrong, tin, chain, tungsten, bismuth, chin, Idan And, or other materials, or the above-mentioned oxides, or the above-mentioned cerium compounds, or the above-described iu oxides, or the above-mentioned alloys, or a combination thereof, are examples, but are not limited thereto, and may be optionally Use a transparent material (such as: indium tin oxide, luminal zinc oxide, tin oxide, indium zinc oxide, tin tin oxide, or other materials, or a combination of the above) or a combination of transparent and reflective materials . In addition, the first conductive layer 541 is connected to a level electrode line, for example: • a common electrode line VC() m5 (as shown in FIG. 7A), but is not limited thereto, and may also be selectively used. The electrode line of the level, for example, the common electrode line VC() m5 serves as the first conductive layer 541. Wherein, in this embodiment, the common electrode line

Vcom5 之材質是以反射材質(如:金、銀、銅、鐵、錫、 錯、編、钥、嫣、鈥、鈦、紐、給、或其它材質、或上述 之氧化物、或上述之氮化物、或上述之氮氧化物、或上述 之合金、或上述之組合)為實施範例,但不限於此,亦可選 擇性地使用透明材質(如:銦錫氧化物、铭鋅氧化物、紹錫 ® 氧化物、銦鋅氧化物、鎘錫氧化物、或其它材質、或上述 之組合)、或透明材質及反射材質之組合。換言之,第一導 電層541連接於電極線,例如:共用電極線VC()m5之材質 實質上相同或不同,較佳地,二者實質上相同,以減低製 程複雜性。如同前述,本實施例之半導體層520之摻雜區 524a延伸至第一金屬層541之下方為實施範例。因此,第 二儲存電容Cs52由第一導電層541、絕緣層550及部分半 導體層520所構成。必需注意是,延伸至第一金屬層541 22 1351764The material of Vcom5 is made of reflective material (such as gold, silver, copper, iron, tin, erroneous, braided, key, bismuth, antimony, titanium, neon, nitrile, or other materials, or the above oxides, or the above nitrogen The compound, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an example, but is not limited thereto, and a transparent material (eg, indium tin oxide, zinc oxide, etc.) may be selectively used. Tin® oxide, indium zinc oxide, cadmium tin oxide, or other materials, or combinations thereof, or a combination of transparent and reflective materials. In other words, the first conductive layer 541 is connected to the electrode lines. For example, the materials of the common electrode lines VC() m5 are substantially the same or different, and preferably, the two are substantially the same to reduce the process complexity. As described above, the doping region 524a of the semiconductor layer 520 of the present embodiment extends below the first metal layer 541 as an example. Therefore, the second storage capacitor Cs52 is composed of the first conductive layer 541, the insulating layer 550, and the partial semiconductor layer 520. It must be noted that it extends to the first metal layer 541 22 1351764

三達編號:TW3530PA 之下方之半導體層520亦可選擇性地為透過一連接層(未 : 繪示)連接閘極516下方之半導體層520。其中,延伸至第 : 一金屬層541之下方之半導體層520包含至少一摻雜區 • 524a/524b、至少一另一摻雜區、至少一本徵區522之其中 至少一者。其中,連接層之材質可使用第一導電層541、 第二導電層542、第三導電層543、半導體層520其中至 少一者。 接著,如第8C圖所示,覆蓋内層介電層590於絕緣 • 層550上,且分別形成開口 592於内層介電層590及兩個 開口 531a、531b於内層介電層290及絕緣層550。 然後,如第8D圖所示,形成第二導電層542於部份 之内層介電層590上’且經由開口 592、531a、531b分別 電性連接於第一導電層541及半導體層520。其中,經由 開口 531a、531b電性連接於半導體層520的第二導電層 542是作為電晶體之一汲極512及一源極514。於本實施 例中,第二導電層542之材質是以反射材質(如:金、銀、 籲 銅、鐵、錫、錯、鑛、钥、鶴、鈥、鈦、组、給、或其它 材質、或上述之氧化物、或上述之氮化物、或上述之氮氧 化物、或上述之合金、或上述之組合)為實施範例,但不限 於此,亦可選擇性地使用透明材質(如:銦錫氧化物、鋁鋅 氧化物、鋁錫氧化物、銦鋅氧化物、鎘錫氧化物、或其它 材質、或上述之組合)、或透明材質與反射材質之組合。再 者,電晶體之源極514及汲極512之其中一者電性連接於 資料線DT5(如第7A圖所示),且電晶體之閘極516電性 23 1351764The semiconductor layer 520 below the TW3530PA may also be selectively connected to the semiconductor layer 520 under the gate 516 through a connection layer (not shown). The semiconductor layer 520 extending below the first metal layer 541 includes at least one of at least one doped region 524a/524b, at least one other doped region, and at least one intrinsic region 522. The material of the connection layer may use at least one of the first conductive layer 541, the second conductive layer 542, the third conductive layer 543, and the semiconductor layer 520. Next, as shown in FIG. 8C, the inner dielectric layer 590 is covered on the insulating layer 550, and openings 592 are formed in the inner dielectric layer 590 and the two openings 531a and 531b in the inner dielectric layer 290 and the insulating layer 550, respectively. . Then, as shown in FIG. 8D, the second conductive layer 542 is formed on a portion of the inner dielectric layer 590 and electrically connected to the first conductive layer 541 and the semiconductor layer 520 via the openings 592, 531a, and 531b, respectively. The second conductive layer 542 electrically connected to the semiconductor layer 520 via the openings 531a, 531b serves as one of the gates 512 and a source 514 of the transistor. In this embodiment, the material of the second conductive layer 542 is made of a reflective material (eg, gold, silver, copper, iron, tin, writh, mine, key, crane, sputum, titanium, group, give, or other materials). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material may be selectively used (for example: Indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the source 514 and the drain 512 of the transistor is electrically connected to the data line DT5 (as shown in FIG. 7A), and the gate 516 of the transistor is electrically 23 1351764.

三達編號:TW3530PA 連接於掃描線SC5(如第7A圖所示)。必需說明的是,本實 : 施例之開口 531a、531b及592於非同一時間下所形成的, : 但不限於此,亦可選擇性地使用具有不同透光度光罩(如: ' 半調光罩、繞射光罩、栅狀圖案光罩、或其它光罩、或上 述之組合)之黃光製程,於同一時間下,形成開口 531a、 531b 及 592。 接著,如第8E圖所示,覆蓋保護層580於電晶體及 第二導電層542上,且保護層580具有一開口 582。 • 最後,如第8F圖所示,形成第三導電層543(亦稱晝 素電極)於部份之保護層580上,且經由開口 582電性連接 於電晶體。其中,開口 582可選擇性地實質上對準或不對 準開口 531b。第三儲存電容Cs53由第二導電層542、内層 介電層590、絕緣層550及部分半導體層520所構成。如 此一來,整體之晝素結構500即如同第8F圖所示。於本 實施例中,第三導電層543之材質是以透光材質(如:銦錫 氧化物、铭鋅氧化物、紹錫氧化物、銦鋅氧化物、錫錫氧 ® 化物、或其它材質、或上述之組合)為實施範例,但不限於 此,亦可選擇性地使用反射材質(如:金、銀、銅、鐵、錫、 錯、錫、铜、鶊、鈦、鈦、组、給、或其它材質、或上述 之氧化物、或上述之氮化物、或上述之氣氧化物、或上述 之合金、或上述之組合)、或透明材質與反射材質之組合。 於本實施例中,第一導電層541及第二導電層542為 共電位之電阻,也就是並聯設計,因此可降低電極線,例 如:共用電極線VCC)m5之負載阻抗。如此一來,即可避免 24Sanda number: TW3530PA is connected to scan line SC5 (as shown in Figure 7A). It should be noted that the present embodiment: the openings 531a, 531b and 592 of the embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances can be selectively used (eg: 'half The yellow light process of the dimmer cover, the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 531a, 531b, and 592 at the same time. Next, as shown in FIG. 8E, the protective layer 580 is covered on the transistor and the second conductive layer 542, and the protective layer 580 has an opening 582. • Finally, as shown in FIG. 8F, a third conductive layer 543 (also referred to as a germanium electrode) is formed on a portion of the protective layer 580 and electrically connected to the transistor via the opening 582. Therein, the opening 582 can selectively substantially align or misalign the opening 531b. The third storage capacitor Cs53 is composed of a second conductive layer 542, an inner dielectric layer 590, an insulating layer 550, and a portion of the semiconductor layer 520. As a result, the overall pixel structure 500 is as shown in Fig. 8F. In this embodiment, the material of the third conductive layer 543 is made of a transparent material (eg, indium tin oxide, zinc oxide, sulphur oxide, indium zinc oxide, tin oxy-oxide, or other materials). Or a combination of the above), but is not limited thereto, and may also selectively use a reflective material (eg, gold, silver, copper, iron, tin, erroneous, tin, copper, bismuth, titanium, titanium, group, A combination of a given or other material, or an oxide of the above, or a nitride of the above, or a gas oxide as described above, or an alloy of the above, or a combination thereof, or a transparent material and a reflective material. In the present embodiment, the first conductive layer 541 and the second conductive layer 542 have a common potential resistance, that is, a parallel design, thereby reducing the load impedance of the electrode lines, for example, the common electrode lines VCC)m5. In this way, you can avoid 24

二達編號:TW3530PA 光電裝置中顯示面板於顯示 本實施例之半導❹別』面時產W音現象。此外, 電層541之下方為雜區遍,以延伸至第-導 容k及第三餘存id。’以更進—步形成第二儲存電 ,1&緣層550、内層介電層590及保護層580之 ,/者?"材質’包含無機材質(如:氧化石夕、氮化石夕、氮 乳匕石夕、氧化給、氮化铪、碳化石夕、或其它材質、或上述Erda No.: TW3530PA The display panel in the optoelectronic device produces the W-tone phenomenon when the semi-conductive screen of this embodiment is displayed. In addition, the lower portion of the electric layer 541 is a sub-region extending to the first-conductance k and the third residual id. 'To further form a second storage power, 1 & edge layer 550, inner dielectric layer 590 and protective layer 580, / "material" contains inorganic materials (such as: oxidized stone eve, nitride eve, Nitrogen citrate, oxidative, cerium nitride, carbon carbide, or other materials, or

之組合)、有機材質(如:光阻、聚丙醯醚(polyarylene ether; PAE)、聚醯類、聚酯類、聚醇類、聚烯類、苯並環丁烯 (benzocyclclobutene ; BCB) 、HSQ (hydrogen silsesquioxane)、MSQ(methyl silesquioxane)、石夕氧碳氮化 物(SiOC-H)、或其它材質、或上述之組合)、或上述之組合。Combination), organic materials (such as: photoresist, polyarylene ether (PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen carbonitride (SiOC-H), or other materials, or a combination thereof, or a combination thereof.

本實施例之第二導電層542可選擇性地採用反射材 質、透光材質、或上述之組合。第7B圖之第二導電層542 是以反射材質為實施範例。請參照第9圖,其缘示第三實 施例之另一晝素結構之剖面圖。晝素結構6〇〇包含一電晶 體(未標註)、一第一儲存電容Cs01、一第二儲存電容q 2、 一第二儲存電容CS63、一第一導電層641、一内層介電層 690、一第二導電層642、一半導體層620、絕緣層65〇 : 一保護層680及一第三導電層643。第二導電層二2形成 於部份内層介電層690上,且經由開口 692電性連接於第 一導電層641。第7B圖之第二導電層542之材質是以反射 材質為實施範例,而第9圖之第二導電層642之材質是以 透光材質為實施範例,但不限於此。上述内容是以全素名士 25 1351764The second conductive layer 542 of this embodiment can be selectively made of a reflective material, a light transmissive material, or a combination thereof. The second conductive layer 542 of FIG. 7B is an embodiment of a reflective material. Referring to Figure 9, there is shown a cross-sectional view of another unitary structure of the third embodiment. The halogen structure 6A includes a transistor (not labeled), a first storage capacitor Cs01, a second storage capacitor q2, a second storage capacitor CS63, a first conductive layer 641, and an inner dielectric layer 690. A second conductive layer 642, a semiconductor layer 620, and an insulating layer 65A: a protective layer 680 and a third conductive layer 643. The second conductive layer 222 is formed on a portion of the inner dielectric layer 690 and is electrically connected to the first conductive layer 641 via the opening 692. The material of the second conductive layer 542 in FIG. 7B is a reflective material, and the material of the second conductive layer 642 in FIG. 9 is a light-transmitting material, but is not limited thereto. The above content is a vegan celebrity 25 1351764

三達編號:TW3530PA 構500為範例說明其之形成方法,晝素結構600之形成方 : 法與畫素結構500之形成方法相同,因此不在重複敘述。 : 但值得注意的是,晝素結構500之第二導電層542與晝素 ' 結構600之第二導電層642之材料是以不同之材質作為實 施範例。同樣地,晝素結構600亦具有上述所提之方式。 且由於晝素結構600之第二導電層642是以透光材質為實 施範例,因此晝素結構600可用於配合不同之運用實施方 式。 第四實施例 請參第10A圖,其繪示本發明第四實施例之晝素結 構之上視示意圖。本實施例是以一光電裝置中顯示面板之 晝素結構700舉例說明。如第10A圖所示,資料線DT7卜 DT72及掃描線SC7為分別與晝素結構700電性連接。請 參照第10B圖,其繪示第10A圖之晝素結構之剖面圖。第 10B圖為沿著第10A圖中之10B-10B’剖面線之剖面圖。晝 • 素結構700包含一電晶體(未標註)、一第一儲存電容Cs71、 一第二儲存電容Cs72、一第三儲存電容Cs73、一第一導電 層741、一内層介電層790、一第二導電層742、一半導體 層720、絕緣層750、一保護層780、一第三導電層743及 一第四導電層744。較佳地,晝素結構700可選擇性地包 含一遮光圖案層(未繪示),位於且平行於資料線DT71、 DT72及掃描線SC7之至少一者之側邊,以防止資料線 DT71、DT72及掃描線SC7之至少一者之邊緣產生漏光現 26 三達編號:TW3530pa 象0 罘一 儲存電容Csn電性連接於 7一9〇覆蓋於第’導電層%上,且二日:體門内層:5 -導電層742形成於部份内層介、$ ° °第 792電性連接於第一導電層741790上,且經由開口 體及第二導電層742上讲有保,層780覆蓋於電晶 屏7心…丄 八有—開口 782。第二暮恭 層7们形成部份保護層上,且 弟一導电 於電晶體。第四導電層7 4 4覆%由開口 7 8 2電性連接 内層介電声79η p 现於第二導電層742與部份 層w 得第1存電容h由第三導電 W、保護層780、第四導電屑7心 所構成。第二健产恭— -θ 744及第二導電層742 及部分半導體二。由7導電層74卜絕緣層750 電層%、第四導電層744、内層了二 由第二導 及部分半導體層720所構成。曰,1電層79〇、絕緣層750 之形,其一咖圖之晝素結構 第iC程圖。晝素結構700之形成方法如下:如 八圖所不,於基板7〇9上形 著覆蓋—絕緣層750於半導❹^半導縣⑽,且接 含至少二個摻雜區724a、724b ; —2:上。半導體層,包 ,摻雜區咖,以延伸至第—金屬^本徵區722。本實施例 例。一般而言,本徵區722是位^層/41之下方為實施範 $間。較佳地,本發明之實施例於=個摻雜區·、_ 少_者=於=:22及二個_ 之間,立另外換雜區之接雜濃度實質上小於二個換 27 1351764Sanda number: TW3530PA structure 500 is an example to illustrate its formation method. The formation of the halogen structure 600: The method is the same as the method of forming the pixel structure 500, and therefore is not repeated. However, it is worth noting that the material of the second conductive layer 542 of the halogen structure 500 and the second conductive layer 642 of the halogen structure 600 is a different example of the material. Similarly, the halogen structure 600 also has the above-described manner. Moreover, since the second conductive layer 642 of the halogen structure 600 is an example of a light transmissive material, the halogen structure 600 can be used to suit different application embodiments. Fourth Embodiment Referring to Fig. 10A, there is shown a top view of a pixel structure of a fourth embodiment of the present invention. This embodiment is exemplified by a pixel structure 700 of a display panel in an optoelectronic device. As shown in Fig. 10A, the data lines DT7, DT72, and the scan lines SC7 are electrically connected to the halogen structure 700, respectively. Please refer to FIG. 10B, which is a cross-sectional view showing the structure of the halogen in FIG. 10A. Fig. 10B is a cross-sectional view taken along line 10B-10B' of Fig. 10A. The structure 700 includes a transistor (not labeled), a first storage capacitor Cs71, a second storage capacitor Cs72, a third storage capacitor Cs73, a first conductive layer 741, an inner dielectric layer 790, and a a second conductive layer 742, a semiconductor layer 720, an insulating layer 750, a protective layer 780, a third conductive layer 743, and a fourth conductive layer 744. Preferably, the halogen structure 700 can selectively include a light shielding pattern layer (not shown) located at a side parallel to at least one of the data lines DT71, DT72 and the scan line SC7 to prevent the data line DT71, Light leakage occurs at the edge of at least one of DT72 and scan line SC7. 26 达号: TW3530pa 象0 储存 A storage capacitor Csn is electrically connected to the 7th 〇 layer on the 'conductive layer%, and the second day: inside the body door The layer: the conductive layer 742 is formed on a portion of the inner layer, and the 792 is electrically connected to the first conductive layer 741790, and the layer 780 is covered by the opening body and the second conductive layer 742. Crystal screen 7 heart... 丄 eight have - opening 782. The second layer 7 forms part of the protective layer, and the younger one is electrically conductive to the transistor. The fourth conductive layer 7 4 4 is electrically connected to the inner layer dielectric sound 79η p by the opening 782. The second conductive layer 742 and the partial layer w are obtained. The first storage capacitor h is provided by the third conductive layer W and the protective layer 780. The fourth conductive crucible 7 is composed of a heart. The second health production is - θ 744 and the second conductive layer 742 and part of the semiconductor two. The seventh conductive layer 74, the fourth conductive layer 744, and the inner layer are composed of a second conductive layer and a partial semiconductor layer 720.曰, 1 electrical layer 79 〇, the shape of the insulating layer 750, a 咖 结构 结构 第 i i i i i i i i i i i i i i i i i i i i i i i i i i i i The method for forming the halogen structure 700 is as follows: as shown in FIG. 8 , a covering-insulating layer 750 is formed on the substrate 7〇9 in the semi-conducting semi-conducting county (10), and at least two doping regions 724a and 724b are included. ; — 2: Up. The semiconductor layer, the package, and the doped region are extended to the first metal-intrinsic region 722. This embodiment is an example. In general, the intrinsic area 722 is below the level/41 and is the implementation cost. Preferably, in the embodiment of the present invention, the ratio of the impurity of the other impurity-changing region is substantially smaller than that of the two-doped region, _ less _ 者 = y = 22, and two _ 27 351 764

二達編號:TW3530PA 雜區724a、724b之至少一者、本徵區7 雜,若掺雜時,本徵區722之極性與二個:摻雜或不摻 及另外摻純之極性較佳地實f上不同咖、似b 區724a、724b、本徵區⑶及/或 ,—個摻雜 性地同時形成於半導體層72〇 ,亦可選擇 720中。再者,半導體層72〇之材質包^=成於半導體層 微晶之含矽材質:貝已括早晶之含矽材質、 鍺材二或其它村 實施例中,第—導:二極716亦同時形成。於本 銀、銅、鐵、錫::二材質是以反射材質(如:金、 其它材質、或上述之氧化物7、、敍―、鈦、麵、給、或 氮氧化物、或上述之合金、或、或上述之 不限於此,亦 边之組合)為貫施範例,但 紹鋅氧化物、㉝ =透明材質(如:銦錫氧化物、 其它材質、或上:之氧化物、崎㈣ 此外,第1電層=於透?質與反射材質之組合。 共用電極線V連接於—具有準位之電極線,例如: 擇性地使用部=有所示),但不限於此,亦可選 V-當作第—導::準二之電極線’例如:共用電極線 線,例如:共用雷= 其中’於本實施例中,電極 銀、銅、鐵、錫 _7之材質是以反射材質(如:金、Erda number: TW3530PA at least one of the hetero-regions 724a, 724b, the intrinsic region 7 is heterogeneous, if doped, the polarity of the intrinsic region 722 and two: doping or not doping with additional pure polarity is preferred In the real f, different areas, such as b regions 724a, 724b, intrinsic regions (3) and/or, doped simultaneously at the semiconductor layer 72, may also be selected 720. Furthermore, the material of the semiconductor layer 72 is composed of a germanium-containing material of the semiconductor layer microcrystals: a germanium containing an anthracene material, a coffin or another village embodiment, a first guide: a dipole 716 Also formed at the same time. In this silver, copper, iron, tin:: two materials are reflective materials (such as: gold, other materials, or the above oxides 7,, -, titanium, surface, give, or nitrogen oxides, or the above The alloy, or, or the above, is not limited to this, and the combination thereof is an example, but zinc oxide, 33 = transparent material (such as: indium tin oxide, other materials, or on: oxide, (4) In addition, the first electric layer = a combination of a transparent material and a reflective material. The common electrode line V is connected to an electrode line having a level, for example, an optional use portion = as shown, but is not limited thereto. V- can also be used as the first guide: the electrode line of the quasi-two: for example: common electrode line, for example: shared lightning = where 'in this embodiment, the material of the electrode silver, copper, iron, tin _7 is Reflective material (eg gold,

直它材t 4 、鉛、鎘、鉬、鎢、鈦、鈦、鈕H 4材H述找化物、或域之氮化物、或 28 1351764Straight to the material t 4 , lead, cadmium, molybdenum, tungsten, titanium, titanium, button H 4 material H to find the compound, or the nitride of the domain, or 28 1351764

三達編號_· TW3530PA 氮氧化物、或上述之合金、或上述之組合)為實施範例,但 : 不限於此,亦可選擇性地使用透明材質(如:銦錫氧化物、 : 銘辞氧化物、铭錫氧化物、銦鋅氧化物、録錫氧化物、或 • 其它材質、或上述之組合)、或透明材質及反射材質之組 合。換言之,第一導電層741連接於電極線,例如:共用 電極線Vcom7之材質實質上相同或不同,較佳地,二者實 質上相同,以減低製程複雜性。如同前述,本實施例之半 導體層720之摻雜區724a延伸至第一金屬層741之下方 • 為實施範例,因此,第二儲存電容Cs72由第一導電層74卜 絕緣層750及部分半導體層720所構成。必需注意是,延 伸至第一金屬層741之下方之半導體層720亦可選擇性地 為透過一連接層(未繪示)連接閘極716下方之半導體層 720。其中,延伸至第一金屬層741之下方之半導體層720 或區塊包含至少一摻雜區724a/724b、至少一另一摻雜區、 至少一本徵區722之其中至少一者。其中,連接層之材質 可使用第一導電層741、第二導電層742、第三導電層743、 • 半導體層720其中至少一者。 接著,如第11C圖所示,覆蓋内層介電層790於絕緣 層750上,且分別形成開口 792於内層介電層790及兩個 開口 731a、731b於内層介電層790及絕緣層750。 然後,如第11D圖所示,形成第二導電層742於部份 之内層介電層790上,且經由開口 792、731a、731b分別 電性連接於第一導電層741及半導體層720。其中,經由 開口 731a、731b電性連接於半導體層720的第二導電層 29 1351764Sanda number _· TW3530PA oxynitride, or the above alloy, or a combination thereof, is an example, but: not limited thereto, selective use of transparent materials (eg, indium tin oxide, : inscription oxidation A combination of a material, a tin oxide, an indium zinc oxide, a tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. In other words, the first conductive layer 741 is connected to the electrode lines. For example, the materials of the common electrode lines Vcom7 are substantially the same or different, and preferably, the two are substantially the same to reduce the process complexity. As described above, the doped region 724a of the semiconductor layer 720 of the present embodiment extends below the first metal layer 741. • For the sake of example, the second storage capacitor Cs72 is composed of the first conductive layer 74, the insulating layer 750, and a portion of the semiconductor layer. 720 is composed. It should be noted that the semiconductor layer 720 extending below the first metal layer 741 may also selectively connect the semiconductor layer 720 under the gate 716 through a connection layer (not shown). The semiconductor layer 720 or block extending below the first metal layer 741 includes at least one of at least one doped region 724a/724b, at least one other doped region, and at least one intrinsic region 722. The material of the connection layer may be at least one of the first conductive layer 741, the second conductive layer 742, the third conductive layer 743, and the semiconductor layer 720. Next, as shown in FIG. 11C, the inner dielectric layer 790 is covered on the insulating layer 750, and an opening 792 is formed in the inner dielectric layer 790 and the two openings 731a and 731b in the inner dielectric layer 790 and the insulating layer 750, respectively. Then, as shown in FIG. 11D, the second conductive layer 742 is formed on a portion of the inner dielectric layer 790, and electrically connected to the first conductive layer 741 and the semiconductor layer 720 via the openings 792, 731a, and 731b, respectively. Wherein, the second conductive layer electrically connected to the semiconductor layer 720 via the openings 731a, 731b 29 1351764

三達編號:TW3530PASanda number: TW3530PA

742是=為電晶體之1極712及一源極7…於本實施 例第二導電層742之材質是以反射材質(如:金、銀、 銅、鐵、錫、鉛、鎘、鉬、鎢、鉉、鈦、鈕、鈴、或其它 材質、或上述之氧化物、或上述之氮化物、或上述之氮氧 化物或上述之5金、或上述之組合)為實施範例,但不限 於此’亦可選擇性地使用透明材質(如:銦錫氧化物、銘鋅 氧化物:鋁錫氧化物、銦鋅氧化物、鎘錫氧化物、或其它 材質、或上述之組合)、錢明材質與反射材質之組合。電 晶體之一没極712及-源極714則利用開口 731&、咖 以與半導體層72。電性連接。再者,電晶體之源極714及 汲極712之其中一者電性連接於資料線DT7卜DT72(如第 10A圖所示)’且電晶體之閘極716電性連接於掃描線 SC7(如第10人圖所示)。必需說明的是,本實施例之開口 731a、731b及792於非同一時間下所形成的,但不限於此, 亦可選擇性地使用具有不同透光度光罩(如:半調光罩、繞 射光單、柵狀圖案光罩、或其它光罩、或上述之組合)之黃 光製释,於同一時間下,形成開口 73la、73lb及792。 接著’如第11E圖所示’覆蓋第四導電層744於第二 導電層742與部份之内層介電層790上。於本實施例中, 以第四導電層744之材質為透光材質作為實施範例,但不 限於此’亦可選擇性地使用反射材質或透光材質與反射材 質之餌合。此外,由於第—導電層741、第二導電層742 及第四導電層?44相互電性連接,因此第一導電層741、 第二導電層742及第四導電層744之位準為實質上相同。 30 1351764742 is = 1 pole 712 and a source 7 of the transistor. The material of the second conductive layer 742 in this embodiment is a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, Tungsten, tantalum, titanium, button, bell, or other material, or the above oxide, or the above nitride, or the above nitrogen oxide or the above 5 gold, or a combination thereof, is an embodiment, but is not limited thereto This can also optionally use transparent materials (such as: indium tin oxide, zinc oxide: aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination of the above), Qian Ming A combination of material and reflective material. One of the transistors, the pole 712 and the source 714, utilizes an opening 731 & Electrical connection. Furthermore, one of the source 714 and the drain 712 of the transistor is electrically connected to the data line DT7 DT72 (as shown in FIG. 10A) and the gate 716 of the transistor is electrically connected to the scan line SC7 ( As shown in the figure of the 10th person). It should be noted that the openings 731a, 731b, and 792 of the embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (eg, a half dimming cover, The yellow light of the diffracted light, the grid pattern mask, or other reticle, or a combination thereof, is released at the same time to form openings 73la, 73bb and 792. Next, the fourth conductive layer 744 is overlaid on the second conductive layer 742 and a portion of the inner dielectric layer 790 as shown in FIG. 11E. In the present embodiment, the material of the fourth conductive layer 744 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto. A reflective material or a light-transmitting material and a reflective material can be selectively used. In addition, due to the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer? 44 is electrically connected to each other, and thus the levels of the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 are substantially the same. 30 1351764

三達編號:TW3530PA . 且第一導電層741、第二導電層742及第四導電層744之 ' 位準包含,例如:共用位準。 ’‘ 另外,於本實施例中,汲極712與掃描線SC7之間具 ' 一第一寄生電容,且汲極712與資料線DT71、DT72之間 各具有之電容之總和實質上為一第二寄生電容。此外,晝 素結構700之晝素電極與共用電極(未繪示)之間具有一液 晶電容(未繪示)。晝素結構7〇〇之一晝素電容實質上等於 液晶電容與第一儲存電容Cs71之和。第四導電層744之面 • 積即是決定於第一寄生電容與晝素電容之比、第二寄生電 容與晝素電極之比及第一儲存電容Cs71與液晶電容之比。 於本實施例之第四導電層744之面積,較佳地,實質上大 於第二導電層742之面積,但不限於此,亦可視設計上之 要求,來選擇性地改變第四導電層744之面積,如:其實 質上比第二導電層742之面積小、其實質上相等於第二導 電層742之面積、或上述之組合。 然後,如第11F圖所示,覆蓋保護層780於電晶體及 鲁 第二導電層742上,且保護層780具有一開口 782。 最後,如第11G圖所示,形成第三導電層743(亦稱 晝素電極)於部份之保護層780上,且經由開口 782電性連 接於電晶體。其中,開口 782可選擇性地實質上對準或不 對準開口 731b。第三儲存電容Cs73由第二導電層742、内 層介電層790、絕緣層750及部分半導體層720所構成。 如此一來,整體之晝素結構700即如同第11G圖所示。於 本實施例中,第三導電層743之材質是以透光材質(如:銦 31 1351764The third level is TW3530PA. The 'levels of the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 include, for example, a common level. In addition, in the present embodiment, the first parasitic capacitance is between the drain 712 and the scan line SC7, and the sum of the capacitances between the drain 712 and the data lines DT71 and DT72 is substantially one. Two parasitic capacitances. In addition, there is a liquid crystal capacitor (not shown) between the halogen electrode of the germanium structure 700 and the common electrode (not shown). One of the pixel structures of the halogen structure is substantially equal to the sum of the liquid crystal capacitance and the first storage capacitor Cs71. The surface of the fourth conductive layer 744 is determined by the ratio of the first parasitic capacitance to the halogen capacitance, the ratio of the second parasitic capacitance to the halogen electrode, and the ratio of the first storage capacitor Cs71 to the liquid crystal capacitance. The area of the fourth conductive layer 744 in the present embodiment is preferably substantially larger than the area of the second conductive layer 742, but is not limited thereto, and the fourth conductive layer 744 may be selectively changed according to design requirements. The area is, for example, substantially smaller than the area of the second conductive layer 742, substantially equal to the area of the second conductive layer 742, or a combination thereof. Then, as shown in Fig. 11F, the protective layer 780 is overlaid on the transistor and the second conductive layer 742, and the protective layer 780 has an opening 782. Finally, as shown in Fig. 11G, a third conductive layer 743 (also referred to as a halogen electrode) is formed on a portion of the protective layer 780, and is electrically connected to the transistor via the opening 782. Therein, the opening 782 can be selectively aligned or not substantially aligned with the opening 731b. The third storage capacitor Cs73 is composed of a second conductive layer 742, an inner dielectric layer 790, an insulating layer 750, and a portion of the semiconductor layer 720. As a result, the overall pixel structure 700 is as shown in FIG. 11G. In this embodiment, the material of the third conductive layer 743 is made of a light transmissive material (eg, indium 31 1351764).

三達編號:TW3530PA . 錫氧化物、链鋅氧化物、紹錫氧化物、銦鋅氧化物、錯錫 :氧化物、或其它材質、或上述之組合)為實施耗例,但不 ···限於此,亦可選擇性地使用反射材質(如:金、銀、銅、鐵、 •錫、鉛、鎘、鉬、鎢、鈥、鈦、鋁、铪、或其它材質、或 上述之氧化物、或上述之氮化物、或上述之氮氧化物、或 上述之合金、或上述之組合)、或透明材質與反射材質之組 合0 於本實施例中,第四導電層744採用透光材質,因此 • 晝素結構700可於不變更電容值之情沉下增加開口率,但 不限於此,亦可使用反射材質、或透光材質及反射材質之 組合。此外,第四導電層744可選擇性地不與任何閘極線 或資料線相互重疊,因此可減少閘極線或資料線上的負 載,但不限於此,亦可選擇性地部分重疊。 再者,第一導電層741、第二導電層742及第四導電 層744為共電位之電阻,也就是並聯設計,因此可降低電 極線,例如:共用電極線Vcom7之負載阻抗。如此一來, 即可避免光電裝置中顯示面板於顯示晝面時產生串音現 象。 此外,本實施例之半導體層72〇之摻雜區724a,以 延伸至第—導電層741之下方為實施範例,以更進一步形 成第二儲存電容C.77及第三儲存電容CS73。 再者,絕緣層750、内層介電層790及保護層78〇之 至少一者之材質,包含無機材質(如:氧化矽、氮化矽、氮 氧化秒、氧化铪、氮化铪、碳化矽、或其它材質、或上述 32 1351764Sanda number: TW3530PA. Tin oxide, chain zinc oxide, Shaoxi oxide, indium zinc oxide, staggered tin: oxide, or other materials, or a combination of the above) is an implementation cost, but not ··· In addition, it is also possible to selectively use a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, aluminum, tantalum, or other materials, or oxides thereof). Or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, or a combination of a transparent material and a reflective material. In the present embodiment, the fourth conductive layer 744 is made of a light-transmitting material. Therefore, the halogen structure 700 can increase the aperture ratio without changing the capacitance value, but is not limited thereto, and a reflective material or a combination of a light-transmitting material and a reflective material can also be used. In addition, the fourth conductive layer 744 can selectively overlap with any gate lines or data lines, thereby reducing the load on the gate lines or data lines, but is not limited thereto, and can also be selectively partially overlapped. Furthermore, the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 have a common potential resistance, that is, a parallel design, thereby reducing the load impedance of the electrode line, for example, the common electrode line Vcom7. In this way, it is possible to avoid the occurrence of crosstalk when the display panel in the optoelectronic device displays the kneading surface. In addition, the doped region 724a of the semiconductor layer 72 of the present embodiment extends to the lower portion of the first conductive layer 741 as an embodiment to further form the second storage capacitor C.77 and the third storage capacitor CS73. Furthermore, at least one of the insulating layer 750, the inner dielectric layer 790 and the protective layer 78 is made of an inorganic material (eg, yttrium oxide, tantalum nitride, nitrous oxide, yttrium oxide, tantalum nitride, tantalum carbide). Or other materials, or the above 32 1351764

三達編號:TW3530PA 之組合)、有機材質(如:光阻、聚丙醯謎(polyarylene ether ; * PAE)、聚醯類、聚酯類、聚醇類、聚烯類、苯並環丁烯 (benzocyclclobutene ; BCB) 、 HSQ (hydrogen silsesquioxane)、MSQ(methyl silesquioxane)、石夕氧碳氫化 物(SiOC-H)、或其它材質、或上述之組合)、或上述之組合。 本發明上述實施例所揭露之晝素結構具有至少一儲 存電容於導電材料之間。於上述實施例中,導電材料之應 用包括透光材質、反射材質、或上述之組合。舉例而言, • 由於實施例中之第四導電層444、744採用透光材質,因 此晝素結構400、700可保持原有之電容值,且更進一步 增加開口率。此外’第四導電層444、744之設置可選擇 性地並不與任何閘極線或資料線相互重疊,因此第四導電 層444、744之設置除了具有上述之優點外’亦可減少閘 極線或資料線上的負載,但不限於此,亦可選擇性地部份 重疊。 再者,由於第一、第二、第四及第五實施例之第一及 第二導電層為共電位之電阻’也就是並聯設計,且第三及 第六實施例之第一、第二及第四導電層亦為並聯設計,因 此此些實施例之應用可降低電極線之負載阻抗。如此一 來’即可避免光電裝置中顯示面板於顯示晝面時產生串音 現象。 另外,本發明上述實施例所述之具有準位之電極線, 是以具有共用準位之共用電極線(Vc〇m)為實施範例,但不 限於此,亦可使用具有可變動準位之電極線或其準位之電 33Sanda number: TW3530PA combination), organic materials (such as: photoresist, polyarylene ether (* PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclobutene ( Benzcyclylbutene; BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen hydrocarbon (SiOC-H), or other materials, or a combination thereof, or a combination thereof. The halogen structure disclosed in the above embodiment of the present invention has at least one storage capacitor between the conductive materials. In the above embodiments, the application of the conductive material includes a light transmitting material, a reflective material, or a combination thereof. For example, since the fourth conductive layers 444 and 744 in the embodiment are made of a light-transmitting material, the halogen structures 400 and 700 can maintain the original capacitance value and further increase the aperture ratio. In addition, the arrangement of the fourth conductive layers 444, 744 can be selectively overlapped with any gate lines or data lines, so that the arrangement of the fourth conductive layers 444, 744 can reduce the gates in addition to the above advantages. The load on the line or data line, but not limited to this, may also be partially partially overlapped. Furthermore, since the first and second conductive layers of the first, second, fourth and fifth embodiments are a common-potential resistor', that is, a parallel design, and the first and second of the third and sixth embodiments And the fourth conductive layer is also designed in parallel, so the application of these embodiments can reduce the load impedance of the electrode lines. In this way, it is possible to avoid the occurrence of crosstalk when the display panel in the photovoltaic device displays the surface. In addition, the electrode line having the level described in the above embodiment of the present invention is a common electrode line (Vc〇m) having a common level, but is not limited thereto, and may have a variable level. Electrode wire or its level of electricity 33

三達編號·· TW3530PA 極線(如:閘極準位、或其它準 第12圖為本發明之光電) 是運用上述實施例所述 装置的不思圖。光電裝置800 更具有一與顯示面構2〇0〜7〇0。光電裝置獅 元件、操作元件、處理元件^電子7°件82()’如:控制 元件、發光元件、_元件、輪人70件、記憶元件、驅動 〜m + 件、感測元件、偵測元件、戋苴 匕功此兀件、或上述之組合。 干次,、 可攜式產品(如手機、攝影機、置:00,類型包括 戲機、手錶、音樂播放器、電子相:機4電腦、遊 類似之產品)、螢幕、電視、:土,音放映器或 ^ . 一 戶内或戶外看板、投影機内 之板4 °另外’顯示面板WO包含液晶顯示面板(如:穿 透型面板'半穿透型面板、反射型面板、雙面顯示型面板、 垂直配向型面板(VA)、水平切換型面板(lps)、多域垂直配 向塑面板(MVA) '扭曲向列型面板(TN)、超扭曲向列型面 板(STN)、圖案垂直配向型面板(pVA)、超級圖案垂直配向 型面板(S-PVA)、先進大視角型面板(ASV)、邊緣電場切換 型面板(FFS)、連續焰火狀排列型面板(CPA)、軸對稱排列 微胞面板(ASM)、光學補償彎曲排列型面板(〇CB)、超級 水平切換型面板(S-IPS)、先進超級水平切換型面板 (AS-IPS)、極端邊緣電場切換型面板(UFFS)、高分子穩定 配向型面板(PSA)、雙視角型面板(dual-view)、三視角型面 板(triple-view)、或彩色濾光片整合於矩陣上(c〇l〇r fiiter on array ; COA)型態之面板、或矩陣整合於彩色濾光片上 34 1351764Sanda number · TW3530PA pole line (such as: gate level, or other standard 12th picture is the photoelectric of the present invention) is an inconspicuous use of the device described in the above embodiment. The optoelectronic device 800 further has a display surface structure 2〇0~7〇0. Photoelectric device lion components, operating components, processing components ^ electronic 7 ° 82 () 'such as: control components, illuminating components, _ components, 70 people, memory components, drive ~ m + pieces, sensing components, detection The component, the component, or a combination of the above. Dry times, portable products (such as mobile phones, cameras, set: 00, types include theater, watches, music players, electronic phase: machine 4 computers, games similar products), screen, TV,: soil, sound Projector or ^. Indoor or outdoor billboard, projector panel 4 ° Another 'display panel WO contains liquid crystal display panel (eg: transmissive panel 'semi-transparent panel, reflective panel, double-sided display panel , Vertical Alignment Panel (VA), Horizontal Switching Panel (lps), Multi-domain Vertical Alignment Panel (MVA) 'Twisted Nematic Panel (TN), Super Twisted Nematic Panel (STN), Pattern Vertical Alignment Panel (pVA), super pattern vertical alignment panel (S-PVA), advanced large viewing angle panel (ASV), edge electric field switching panel (FFS), continuous flame-like array panel (CPA), axisymmetric array of cells Panel (ASM), optically compensated curved alignment panel (〇CB), super horizontal switching panel (S-IPS), advanced super horizontal switching panel (AS-IPS), extreme edge electric field switching panel (UFFS), high Molecularly Stabilized Alignment Panel (PSA), Double Viewing Panel ( Dual-view), triple-view, or color filter integrated into a matrix (c〇l〇r fiiter on array; COA) type panel, or matrix integrated on a color filter 34 1351764

三達編號:TW3530PA (array on color filter ; AOC)型態之面板、或其它型面板、 ' 或上述之組合。)、有機電激發光顯示面板,視其面板中之 • 晝素電極及汲極之至少一者所電性接觸之材質,如:液晶 層、有機發光層(如:小分子、高分子、或上述之組合)、 或上述之組合。 綜上所述,雖然本發明已以較佳實施例揭露如上,然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者,在不脫離本發明之精神和範圍内,當可作各種之 • 更動與潤飾。因此,本發明之保護範圍當視後附之申請專 利範圍所界定者為準。Sanda number: TW3530PA (array on color filter; AOC) type panel, or other type of panel, 'or a combination of the above. ), an organic electroluminescent display panel, depending on the material of the panel, such as a liquid crystal layer or an organic light-emitting layer (eg, a small molecule, a polymer, or Combination of the above), or a combination of the above. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

35 135176435 1351764

三達編號:TW3530PA 【圖式簡單說明】 第1圖繪示傳統之晝素結構之剖面圖。 第从圖繪示本發明第一實施例之畫素結構之上視示 μ _素結構之剖面圖。 。 ’h第2Β圖之晝素結構之形成方法之流 第:貫施例之另-晝素結構之剖面圖。 第圖、,曰不本發明第二實施例之畫素結構之上視示 =圖繪示第5A圖之畫素結構之剖面圖。 f G崎示第5心之晝素結構之形成方法之流 第7A圖繪示本發明第三實施例之晝素結構之上視示 =圖繪示第7A圖之畫素結構之剖面圖。 。’圖繪示第祕圖之晝素結構之形成方法之流 ^ 9圖繪示第三實施例之另—晝素結構之剖 圖。10A圖繪不本發明第四實施例之晝素結構之上視 := 會不第1〇A圖之晝素結構之剖面圖。 之流程圖。〜_㈣第卿圖之晝素結構之形成方法 意圖 程圖 意圖 程圖 意圖 程圖 示意圖 36 1351764Sanda number: TW3530PA [Simple description of the diagram] Figure 1 shows a cross-sectional view of a conventional halogen structure. The figure is a cross-sectional view showing the μ-primary structure on the pixel structure of the first embodiment of the present invention. . The flow of the formation method of the halogen structure of the second image of the second embodiment: a cross-sectional view of the other-formal structure of the embodiment. In the drawings, the pixel structure of the second embodiment of the present invention is not shown. Fig. 5 is a cross-sectional view showing the pixel structure of Fig. 5A. f G shows the flow of the formation method of the fifth core structure. Fig. 7A is a cross-sectional view showing the pixel structure of Fig. 7A on the basis of the pixel structure of the third embodiment of the present invention. . The figure shows a flow of a method for forming a halogen structure of the first embodiment. Fig. 9 is a cross-sectional view showing another structure of the halogen structure of the third embodiment. 10A is a cross-sectional view of a halogen structure which is not in the fourth embodiment of the present invention. Flow chart. ~_(4) Forming method of the structure of the elementary structure of the second figure Intention Plane Intent Plan Intention Plan Diagram Schematic 36 1351764

三達編號:TW3530PA 第12圖繪示本發明之光電裝置的示意圖。 【主要元件符號說明】 100、200、300、400、500、600、700 :晝素結構 101 :電容電極 102、280、380、480、580、680、780 :保護層 10 3 ·晝素電極 109、209、409、509、709 :基板Sanda Number: TW3530PA Figure 12 shows a schematic view of the photovoltaic device of the present invention. [Description of main component symbols] 100, 200, 300, 400, 500, 600, 700: Alizarin structure 101: Capacitance electrodes 102, 280, 380, 480, 580, 680, 780: Protective layer 10 3 · Alizarin electrode 109 , 209, 409, 509, 709: substrate

112、212、412、512、712 :汲極 114、214、414、514、714 :源極 116、216、416、516、716 :閘極 120、220、420、520、620、720 :半導體層 150、250、450、550、650、750 :絕緣層 162、231a、231b、282、292、431a、431b、482、492、 531a、531b、582、592、692、731a、731b、782、792 :開 口 163 :接觸洞 190、290、390、490、590、690、790 :内層介電層 222、422、522、722 :本徵區 224a、224b、424a、424b、524a、524b、624a、724a、 724b :摻雜區 241、 341、441、541、641、741 :第一導電層 242、 342、442、542、642、742 :第二導電層 243、 343、443、543、643、743 :第三導電層 37 1351764 -112, 212, 412, 512, 712: drains 114, 214, 414, 514, 714: sources 116, 216, 416, 516, 716: gates 120, 220, 420, 520, 620, 720: semiconductor layer 150, 250, 450, 550, 650, 750: insulating layers 162, 231a, 231b, 282, 292, 431a, 431b, 482, 492, 531a, 531b, 582, 592, 692, 731a, 731b, 782, 792: Opening 163: contact holes 190, 290, 390, 490, 590, 690, 790: inner dielectric layers 222, 422, 522, 722: intrinsic regions 224a, 224b, 424a, 424b, 524a, 524b, 624a, 724a, 724b: doped regions 241, 341, 441, 541, 641, 741: first conductive layers 242, 342, 442, 542, 642, 742: second conductive layers 243, 343, 443, 543, 643, 743: Three conductive layers 37 1351764 -

三達編號:TW3530PA 444、744 :第四導電層 * 800 :光電裝置 : 810 :顯示面板 ' 820 :電子元件Sanda number: TW3530PA 444, 744: fourth conductive layer * 800: photoelectric device: 810: display panel '820: electronic components

Csl :儲存電容 CS21、CS3i、CS4i、CS51、CS61、CS71 :第一儲存電容 CS52、CS62、CS72 :第二儲存電容 CS53、CS63、CS73 :第三儲存電容 • DT2、DT4卜 DT42、DT5、DT7卜 DT72 :資料線 SC2、SC4、SC5、SC7 :掃描線 Vc〇m2、V"com4、、Vcom7 .共用電才虽線 38Csl : storage capacitors CS21, CS3i, CS4i, CS51, CS61, CS71: first storage capacitors CS52, CS62, CS72: second storage capacitors CS53, CS63, CS73: third storage capacitors • DT2, DT4 DT42, DT5, DT7 DT72: data line SC2, SC4, SC5, SC7: scan line Vc〇m2, V"com4, Vcom7.

Claims (1)

100年8月±5·日修正替換頁 十、申請專利範圍: L 一種畫素結構,包含: 至少一電晶體; 電性連接於該電晶體; —第一儲存電容 —第一導電層; —内層介電層,覆蓋於該 少一第一開口; 第一導電層上 且其具有至 該第了:電層’形成於部份該内層介電層上,且瘦由 孩弟—開口電性連接於該第一導電層; 且、,工由 具有於該電晶體W :導電層上,且其 -第三導電層’形成部份該保護層上 開口電性連接於該電晶體;以及 第- 第四導電層’覆蓋於該第二導盘 電層上,以使楫兮笼以邛伤该内層介 層、μ ίΓ 電容由該第三導電層、該保護 «Λ第四導电層及該第二導電層所構成。 2. 如申請專利範㈣丨項所述之畫素結構,其中, μ第一導電層及該第三導電層之至少一 ^ rr a &材質’包含透 貝、反射材質、或上述之組合。 3. 如申請專利第丨項所述之晝素結構,更 一半導體層;以及 一絕緣層,覆蓋該半導體層,且其具有至少二第二門 二 部份的該半導體層作為該至少-電:體二 邛伤的該半導體層位於該第二導電層之下方。 39 1351764 y〆 100年8月斿日修正替換頁 申請專利範圍第3項所述之畫素結構,更包含: 該半導體層 容’由料―導電層、該絕緣層及部份 ^申請專利範園第4項所述之畫素結構,更包含: 該内層介^1特'容,由該第"導電層、該第四導電層、 Μ θ θ、5亥鈀緣層及部份該半導體層所構成。 體声申請專利範圍第3項所述之晝素結構,該半導 曰广至少一摻雜區、至少一本徵區、或上述之組合。 辞笛-道如申請專利範圍第1項所述之晝素結構,其中, : 電層、該第二導電層及該第四導電層之位 上相同。 只只 道如申請專利範圍第1項所述之晝素結構,其中’ 制位準電層該第二導電層及該第四導電層之位準包含 卞笛9:申請專利範㈣1項所述之晝素結構,其令, 该第:導電層之面積’實質上大於該第二導電層之面積。 談笛―播如巾請專利範圍第1項所述之晝素結構,其中, ο 導電層之材質包含反射材質。 判H如申請專利顧第1項所述之畫素結構,其中, 電層’連接於一共用電極線。 2·&如申請專利範圍第1項所述之晝素結構,更包含: 1中rf料線,電性連接於該電晶體之一源極及一没極之 ,、丫 一者;以及 一掃描線,電性連接於該電晶體之一閘極。 13. —種顯示面板, 之複數個晝素結構。 100年8月49日修正替換頁 包含如申請專利範圍第丨項所述 包含如申請專利範圍第13項所 14. 一種光電裝置 述之顯示面板。 15. —種畫素結構之形成 一電晶體及一第一儲存電容, 成方法包含: 方法,該畫素結構具有至少 電性連接於該電晶體,該形 形成一第一導電層; ]覆蓋-内層介電層於該第—導電層上,且其具有一第 第内層介電層上’且經由該 第一開口電性連接於該第一導電層; 有-護層於該電晶體及^二導電層上,且其具 形成-第三導電層於部份該保護層上 開口電性連接於該電晶體;以及 ,,二由Μ弟一 』蓋二第四1 電層於該第二導電層與部份該内層介 Ρ 、H ^ a 吐 谷由该第二導電層、該保護 層6亥弟四導電層及該第二導電層所構成 =如中請專利範圍第15項所述之形成方法’其中’ 5亥第一導電層及該第三導電層 光材質、反射材質、或上述之組合:者之材質,包含透 含:17.如申請專利範圍第15項所逃之形成方法,更包 vx 丨00年8月对日修正替換頁 形成一半導體層;以及 開口覆蓋一絕騎於該半導趙層上,且其具有至少二第三 1δ.如申請專利範圍第17項 素結構更包含—第:儲存電容 之2方法,該晝 層及部分該半導體層所構成。由一—導電層、該絕緣 19.如申請專利範圍第18 素結構更包含一第三儲存電容,由方法,該晝 介電f、該絕緣層及部份該=層、該内層 導體層,包含至少項斤迷之形成方法,該半 合。伽區、至少一本徵區、或上述之組 21.如申凊專利範圍第15項 該第-導電層、該第二導電声及:第四之:成方法’其中, 上相同。 导冤廣及6亥第四導電層之位準實質 該第:2導範圍第15項所述之形成方法,其中, 共用^層、该弟二導電層及該第四導電層之位準包含< 23.如申請專利範圍第15項所述 該第:導電層之面積,實質上大於該第:導成電方:之其中’ 第4電:申請專利範圍第15項所述之形成方::中: 導電層之材質包含反射材質。 該第中請專利範圍第15項所述之形成方法,其中, μ 導电層,連接於一共同電極線。 八 42 100年8月龙日修正替換頁 100年8月龙日修正替換頁 含 ;如申明專利辄圍第15項所述之形成方法’更包 極之jl,料線,電性連接於該電晶體之—源極及一沒 T 一者;以及 $成:掃描線,電性連接於該電晶體之一閘極。 第!5項所m面板之形成方法,包含如申請專利範圍 、斤迷之晝素結構之形成方法。 第2721所^種光電裝置之形成方法,包含如申請專利範圍 斤迷之顯示面板之形成方法。 ^ 29道如申請專利範圍第1項所述之晝素結構,其中, 该弟四導電層之材質包含透光材質。 /、中 Μ 3〇道如申請專職圍第15項所述之形成方法,其中, 邊第四導電層之材質包含透光材質。 "中100 years August ± 5 · day correction replacement page ten, the scope of application patent: L a pixel structure, comprising: at least one transistor; electrically connected to the transistor; - first storage capacitor - first conductive layer; The inner dielectric layer covers the first opening; the first conductive layer has a second electrical layer formed on the inner dielectric layer, and is thinned by the child-opening electrical Connecting to the first conductive layer; and, the work is performed on the transistor W: the conductive layer, and the third conductive layer forming portion is electrically connected to the transistor; and - a fourth conductive layer 'overlying the second electrically conductive layer, such that the crucible is damaging the inner via, the μ Γ capacitance from the third conductive layer, the protection « Λ fourth conductive layer and The second conductive layer is formed. 2. The pixel structure as claimed in claim 4, wherein at least one of the first conductive layer and the third conductive layer comprises a transom, a reflective material, or a combination thereof. . 3. The halogen structure according to claim 2, further comprising a semiconductor layer; and an insulating layer covering the semiconductor layer, and having at least two second portions of the semiconductor layer as the at least-electric The semiconductor layer of the body 2 is located below the second conductive layer. 39 1351764 8 8 8 〆 〆 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 修正 画 画 画 画 画 画 画 画 画 画 画 画The pixel structure described in item 4 of the garden further includes: the inner layer is formed by the first layer, the conductive layer, the fourth conductive layer, the Μ θ θ, the 5 hp palladium edge layer, and the portion The semiconductor layer is composed of. The bulk structure of the invention is claimed in claim 3, wherein the semiconductor has at least one doped region, at least one intrinsic region, or a combination thereof. The syllabic structure is as described in claim 1, wherein the electric layer, the second conductive layer and the fourth conductive layer are the same. Only the halogen structure as described in claim 1 of the patent application, wherein the 'position quasi-electrical layer, the second conductive layer and the fourth conductive layer are in a level including the flute 9: claim patent (4) The germanium structure is such that the area of the first conductive layer is substantially larger than the area of the second conductive layer. Talk about the flute-casting as a towel. Please refer to the elementary structure described in the first paragraph of the patent, in which the material of the conductive layer contains a reflective material. The pixel structure as described in claim 1, wherein the electrical layer is connected to a common electrode line. 2·& as claimed in claim 1 of the patent structure, further comprising: 1 rf material line, electrically connected to one of the source of the transistor and a faint one, and one; A scan line is electrically connected to one of the gates of the transistor. 13. A display panel, a plurality of pixel structures. The revised replacement page of August 49, 100 includes a display panel as described in claim 13 of the invention. 15. Forming a pixel structure to form a transistor and a first storage capacitor, the method comprising: the method, the pixel structure having at least electrically connected to the transistor, the shape forming a first conductive layer; An inner dielectric layer on the first conductive layer and having a first inner dielectric layer and electrically connected to the first conductive layer via the first opening; a protective layer on the transistor and And the second conductive layer is electrically connected to the transistor on the portion of the protective layer; and, The second conductive layer and a portion of the inner layer are interposed, and the H ^ a smear is composed of the second conductive layer, the protective layer 6 and the second conductive layer, and the second conductive layer is as defined in claim 15 The method for forming the method includes: a material of the first conductive layer and the third conductive layer, a reflective material, or a combination thereof; the material of the material includes: 17. The escape of the 15th item of the patent application scope The formation method, more package vx 丨 August 00 to the date correction replacement page to form a half guide a layer; and an opening covering a ride on the semi-conductive layer, and having at least two third 1δ. The method of the 17th item of the patent application further includes a method of storing a capacitor, the layer and the portion The semiconductor layer is composed of. By a conductive layer, the insulating 19. The 18th structure of the patent application further comprises a third storage capacitor, by the method, the dielectric f, the insulating layer and a portion of the layer, the inner conductor layer, The method of forming at least the item of the cuddle is included. Gamma region, at least one intrinsic region, or a group as described above 21. The first conductive layer, the second conductive sound, and the fourth: the method of forming the same as in the claim patent range, wherein the above is the same. The method of forming the fourth conductive layer of the second layer of the conductive layer and the fourth conductive layer of the sixth layer, wherein the common layer, the second conductive layer and the fourth conductive layer are included < 23. The area of the first conductive layer as described in claim 15 is substantially larger than the first: conductive electric: wherein the fourth electric: the forming party described in item 15 of the patent application scope :: Medium: The material of the conductive layer contains the reflective material. The method of forming the method of claim 15, wherein the μ conductive layer is connected to a common electrode line. 8 42 100 August August Long Day Correction Replacement Page 100 August August Long Day Correction Replacement Page contains; if the application method described in Item 15 of the patent is more than a jl, the material line is electrically connected to the The transistor has a source and a T; and a: scan line electrically connected to one of the gates of the transistor. The first! The method for forming the panel of the five items includes a method for forming a ruthenium structure such as a patent application scope. The method for forming a photovoltaic device according to the 2721th embodiment includes a method of forming a display panel as claimed in the patent application. ^ 29 The structure of the halogen as described in claim 1, wherein the material of the four conductive layers comprises a light transmissive material. /, 中中 3〇道, as described in the application method of the full-time enclosure, wherein the material of the fourth conductive layer comprises a light-transmitting material. " 4343
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