CN104062814A - 一种像素电极层、阵列基板、显示面板和显示装置 - Google Patents

一种像素电极层、阵列基板、显示面板和显示装置 Download PDF

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CN104062814A
CN104062814A CN201310088712.9A CN201310088712A CN104062814A CN 104062814 A CN104062814 A CN 104062814A CN 201310088712 A CN201310088712 A CN 201310088712A CN 104062814 A CN104062814 A CN 104062814A
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pixel electrode
layer
electrode layer
array base
base palte
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CN104062814B (zh
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姜文博
陈小川
李月
薛海林
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Beijing BOE Optoelectronics Technology Co Ltd
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract

本发明公开了一种像素电极层、阵列基板、显示面板和显示装置，所述像素电极层包括第一像素电极层、第二像素电极层和绝缘层，所述绝缘层位于所述第一像素电极层和第二像素电极层之间，使所述第一像素电极层和第二像素电极层之间绝缘，且所述第一像素电极层的像素电极和所述第二像素电极层的像素电极呈交替排列。通过本发明，能提升显示装置的开口率，存储电容也得到大幅提升，对闪烁(flicker)等不良现象的避免起到重要作用。

Description

一种像素电极层、阵列基板、显示面板和显示装置
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种像素电极层、阵列基板、显示面板和显示装置。
背景技术
随着液晶显示装置广泛地推广和应用，对液晶显示器提出了越来越高的要求，尤其是对于提高开口率提出了很高的要求。所谓液晶显示器的开口率，是指除去每一个像素的配线部、晶体管部(通常采用黑矩阵隐藏)后的光线通过部分的面积与每一个像素整体面积的比值。开口率越高，光线通过的效率越高。
目前，液晶显示器制造过程中的像素电极层，是通过在钝化层(PVX层)之后进行溅射的工艺来实现的，所有的像素电极层都在同一平面、即属于同一层，像素结构如图1所示。图1中，101为栅(Gate)线层，102为数据线(S/D，源极/漏极)层，103为像素电极层；图1中的像素电极层103都在同一平面、即属于同一层。
图1中区域a的剖面结构如图2所示，从下至上，依次为栅线层101、栅绝缘(GI，Gate Insulator)层104、有源(Active)层105、数据线层102(包括1021为源极，1022为漏极)、PVX层106、像素电极层103，其中，像素电极层103与数据线层102通过PVX层106的过孔相连。图1中区域b的剖面结构如图3所示，从下至上，依次为GI层104、数据线层102、PVX层106、像素电极层103。
在传统的显示装置中，由于像素电极都是在同一平面、即只有一层像素电极层，这样在制作过程中，相邻像素中的像素电极不能离得太近，否则就会因为受限于刻蚀设备的精度而导致相邻像素的像素电极刻蚀不干净、进而使得相邻像素的像素电极之间存在连接；由于相邻像素的像素电极之间没有刻蚀干净，因此在实际显示时连接处的像素电极材料也会发光，导致显示亮点。目前通常采用相邻像素的像素电极之间留有较大空隙(根据刻蚀设备的精度来确定)的方式，这种方式虽然能够解决以上问题，但会造成像素电极的面积缩小，由此导致显示区域缩小，进而导致开口率降低。
发明内容
有鉴于此，本发明的主要目的在于提供一种像素电极层、阵列基板、显示面板和显示装置，以提升显示装置的开口率。
为达到上述目的，本发明的技术方案是这样实现的：
本发明提供一种像素电极层，所述像素电极层包括第一像素电极层、第二像素电极层和绝缘层，所述绝缘层位于所述第一像素电极层和第二像素电极层之间，使所述第一像素电极层和第二像素电极层之间绝缘，且所述第一像素电极层的像素电极和所述第二像素电极层的像素电极呈交替排列。
本发明还提供一种阵列基板，包括所述像素电极层。
所述阵列基板还包括栅绝缘层和钝化层，所述绝缘层包括第一绝缘层和第二绝缘层，所述第一绝缘层靠近所述第一像素电极层且与所述栅绝缘层材料相同，所述第二绝缘层靠近所述第二像素电极层且与所述钝化层材料相同。
所述阵列基板还包括多个薄膜晶体管，所述薄膜晶体管具有漏极，所述第一像素电极层的像素电极通过贯穿所述栅绝缘层的过孔与所述薄膜晶体管的漏极相连，所述第二像素电极层的像素电极通过贯穿所述钝化层的过孔与薄膜晶体管的漏极相连。
所述绝缘层与所述钝化层材料相同。
本发明还提供一种显示面板，包括所述的阵列基板。
本发明还提供一种显示装置，包括所述的显示面板。
本发明所提供的一种像素电极层、阵列基板、显示面板和显示装置，采用两层像素电极层，由于这两像素电极层不在同一层，因此可以增大像素电极的面积，从而在尽量增大像素开口率的情况下不必担心会有像素电极之间的误连接产生；此外，存储电容也得到了大幅提升，对闪烁(flicker)等不良现象的避免起到了重要作用。
附图说明
图1为现有技术中阵列基板的像素结构示意图；
图2为图1中区域a的剖面结构示意图；
图3为图1中区域b的剖面结构示意图；
图4为本发明实施例的一种阵列基板的像素结构示意图；
图5为图4中区域A的一种剖面结构示意图；
图6为图4中区域B的一种剖面结构示意图；
图7为图4中区域C的一种剖面结构示意图；
图8为本发明实施例的阵列基板制作工艺的流程图；
图9为图4中区域A的另一种剖面结构示意图；
图10为图4中区域B的另一种剖面结构示意图；
图11为图4中区域C的另一种剖面结构示意图；
图12为本发明实施例的一种像素电极交替排列方式的示意图。
附图标记说明：
具体实施方式
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。
本发明实施例提供一种像素电极层，所述像素电极层包括第一像素电极层、第二像素电极层和绝缘层，所述绝缘层位于第一像素电极层和第二像素电极层之间，使第一像素电极层和第二像素电极层之间绝缘，且第一像素电极层的像素电极和第二像素电极层的像素电极呈交替排列。
本发明实施例还提供一种阵列基板，包括本发明实施例所述的像素电极层，即在本发明实施例的阵列基板中，其像素电极层包括第一像素电极层、第二像素电极层和绝缘层，所述绝缘层位于第一像素电极层和第二像素电极层之间，使第一像素电极层和第二像素电极层之间绝缘，且第一像素电极层的像素电极和第二像素电极层的像素电极呈交替排列。本发明实施例的一种交替排列方式参见图12所示，图中1031表示第一像素电极层的像素电极，1032表示第二像素电极层的像素电极，1031和1032位于不同层。需要说明的是，本发明实施例并非仅限于图12所示的这一种交替排列方式；总之，交替排列需要尽量保证让现有技术中相邻的像素电极分别位于不同的像素电极层。
较佳的，本发明实施例的阵列基板还包括栅绝缘层和钝化层，相应的，位于第一像素电极层和第二像素电极层之间的绝缘层包括第一绝缘层和第二绝缘层，且第一绝缘层靠近第一像素电极层并与栅绝缘层材料相同，第二绝缘层靠近第二像素电极层并与钝化层材料相同。
较佳的，本发明实施例的阵列基板还包括多个薄膜晶体管，所述薄膜晶体管具有漏极，第一像素电极层的像素电极通过贯穿栅绝缘层的过孔与薄膜晶体管的漏极相连，第二像素电极层的像素电极通过贯穿钝化层的过孔与薄膜晶体管的漏极相连。
较佳的，位于第一像素电极层和第二像素电极层之间的绝缘层材料与钝化层的材料相同。
需要说明的是，本发明实施例的技术方案不仅适用于通过5mask、6mask工艺制作的阵列基板，也适用于其他可行数量的mask工艺制作的阵列基板。本发明的后续实施例以6mask工艺制作的阵列基板为例进行说明，但并不构成对本发明的限定，其他可行数量的mask工艺制作的阵列基板同样适用于本发明实施例的技术方案。
如图4所示，图4为本发明实施例的一种阵列基板的像素结构示意图，其中，101为栅线层，102为数据线层，1031为第一像素电极层的像素电极，1032为第二像素电极层的像素电极。
图4中区域A的剖面结构如图5所示，从下至上，依次为栅线层101、第一像素电极层的像素电极1031、GI层104、Active层105、数据线层102(包括1021为源极，1022为漏极)、PVX层106(也称钝化层)，其中，第一像素电极层的像素电极1031位于阵列基板的GI层104下方，且第一像素电极层的像素电极1031与阵列基板的栅线层101之间通过GI层104隔开，第一像素电极层的像素电极1031通过贯穿GI层104的过孔与薄膜晶体管的漏极1022相连。
图4中区域B的剖面结构如图6所示，从下至上，依次为栅线层101、GI层104、Active层105、数据线层102(包括1021为源极，1022为漏极)、PVX层106、第二像素电极层的像素电极1032，其中，第二像素电极层的像素电极1032位于阵列基板的PVX层106上方，且第二像素电极层的像素电极1032通过贯穿PVX层106的过孔与薄膜晶体管的漏极1022相连。
图4中区域C的剖面结构如图7所示，从下至上，依次为第一像素电极层的像素电极1031、GI层104、数据线层102、PVX层106、第二像素电极层的像素电极1032。从图7中也能够明显看出，第一像素电极层的像素电极1031位于GI层104下方，第二像素电极层的像素电极1032位于PVX层106上方。
另外，本发明实施例的技术方案对于采用双钝化层的阵列基板也同样适用，结构关系可以为：第一像素电极层位于阵列基板的第一钝化层上方、第二钝化层下方，所述第二像素电极层位于阵列基板的第二钝化层上方。
本发明实施例还提供了一种阵列基板的制作方法，包括：在阵列基板上通过溅射工艺分别形成第一像素电极层和第二像素电极层，其中，第一像素电极层和第二像素电极层位于不同层，第一像素电极层与第二像素电极层之间形成有绝缘层，且第一像素电极层的像素电极和第二像素电极层的像素电极呈交替排列。
较佳的，可以在阵列基板上形成栅线层之后、且形成GI层之前，通过溅射工艺形成第一像素电极层，且将第一像素电极层与阵列基板的栅线层之间通过GI层隔开；在阵列基板上形成钝化层之后，通过溅射工艺形成第二像素电极层。
较佳的，可以将第一像素电极层通过贯穿GI层的过孔与薄膜晶体管的漏极相连，第二像素电极层通过钝化层的过孔与薄膜晶体管的漏极相连。
较佳的，在制作双钝化层的阵列基板时，可以在阵列基板上形成第一钝化层之后、且形成第一钝化层之前，通过溅射工艺形成第一像素电极层；在阵列基板上形成第二钝化层之后，通过溅射工艺形成第二像素电极层。
基于5mask工艺，制作本发明实施例的阵列基板的工艺流程如图8所示，在制作本发明实施例的阵列基板时，各层的形成顺序依次为栅线层、第一像素电极层、GI层、数据线层、PVX层、第二像素电极层。
基于6mask工艺，在制作本发明实施例的阵列基板时，各层的形成顺序依次为栅线层、第一像素电极层、GI层、Active层、数据线层、PVX层、第二像素电极层。
基于双钝化层的阵列基板，在制作本发明实施例的阵列基板时，各层的形成顺序依次为栅线层、GI层、Active层、数据线层、第一PVX层、第一像素电极层、第二PVX层、第二像素电极层。
基于双钝化层的阵列基板的像素结构也可以参见图4所示，其中，区域A的剖面结构如图9所示，从下至上，依次为栅线层101、GI层104、Active层105、数据线层102(包括1021为源极，1022为漏极)、第一PVX层1061、第一像素电极层的像素电极1031，其中，第一像素电极层的像素电极1031位于第一PVX层1061上方，并通过贯穿第一PVX层1061的过孔与薄膜晶体管的漏极1022相连。
区域B的剖面结构如图10所示，从下至上，依次为栅线层101、GI层104、Active层105、数据线层102(包括1021为源极，1022为漏极)、第一PVX层1061、第二PVX层1062、第二像素电极层的像素电极1032，其中，第二像素电极层的像素电极1032通过贯穿第一PVX层1061和第二PVX层1062的过孔与薄膜晶体管的漏极1022相连。
区域C的剖面结构如图11所示，从下至上，依次为GI层104、数据线层102、第一PVX层1061、第一像素电极层的像素电极1031、第二PVX层1062和第二像素电极层的像素电极1032。
可以看出，第一像素电极层的像素电极1031位于阵列基板的第一钝化层1061上方、第二钝化层1062下方，第二像素电极层的像素电极1032位于阵列基板的第二钝化层1062上方。
此外，本发明实施例中的像素电极除了可以采用铟锡氧化物(ITO，IndiumTin Oxide)外，还可以采用其他替代材料。本发明实施例的阵列基板可以基于传统的玻璃基板制作形成，也可以基于其他可行的柔性显示材料制作形成。
综上所述，本发明实施例采用两层像素电极，由于这两层像素电极不在同一层，因此可以增大像素电极的面积，从而在尽量增大像素开口率的情况下不必担心会有像素电极之间的误连接产生。对应阵列基板上像素电极的面积的增大，彩膜基板上的对应黑矩阵面积也需要相应缩小。此外，本发明实施例使得存储电容也得到了大幅提升，对闪烁(flicker)等不良现象的避免起到了重要作用。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (7)

1.一种像素电极层，其特征在于，所述像素电极层包括第一像素电极层、第二像素电极层和绝缘层，所述绝缘层位于所述第一像素电极层和第二像素电极层之间，使所述第一像素电极层和第二像素电极层之间绝缘，且所述第一像素电极层的像素电极和所述第二像素电极层的像素电极呈交替排列。
2.一种阵列基板，其特征在于，包括权1所述像素电极层。
3.根据权利要求2所述阵列基板，其特征在于，所述阵列基板还包括栅绝缘层和钝化层，所述绝缘层包括第一绝缘层和第二绝缘层，所述第一绝缘层靠近所述第一像素电极层且与所述栅绝缘层材料相同，所述第二绝缘层靠近所述第二像素电极层且与所述钝化层材料相同。
4.根据权利要求3所述阵列基板，其特征在于，所述阵列基板还包括多个薄膜晶体管，所述薄膜晶体管具有漏极，所述第一像素电极层的像素电极通过贯穿所述栅绝缘层的过孔与所述薄膜晶体管的漏极相连，所述第二像素电极层的像素电极通过贯穿所述钝化层的过孔与薄膜晶体管的漏极相连。
5.根据权利要求3所述阵列基板，其特征在于，所述绝缘层与所述钝化层材料相同。
6.一种显示面板，其特征在于，包括权利要求2～5任一项所述的阵列基板。
7.一种显示装置，其特征在于，包括权利要求6所述的显示面板。
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