WO2017041440A1 - 一种阵列基板及其制造方法、显示面板及其驱动方法 - Google Patents

一种阵列基板及其制造方法、显示面板及其驱动方法 Download PDF

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Publication number
WO2017041440A1
WO2017041440A1 PCT/CN2016/074029 CN2016074029W WO2017041440A1 WO 2017041440 A1 WO2017041440 A1 WO 2017041440A1 CN 2016074029 W CN2016074029 W CN 2016074029W WO 2017041440 A1 WO2017041440 A1 WO 2017041440A1
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Prior art keywords
pixel electrode
thin film
film transistor
gate
source
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PCT/CN2016/074029
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English (en)
French (fr)
Inventor
储浩
石跃
房凯迪
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/511,461 priority Critical patent/US9984637B2/en
Publication of WO2017041440A1 publication Critical patent/WO2017041440A1/zh

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Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, a display panel, and a method of driving the same.
  • LCD Liquid Crystal Display
  • the liquid crystal display comprises a liquid crystal display panel and a backlight
  • the liquid crystal display panel comprises an array substrate, a counter substrate, and a liquid crystal layer therebetween.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, a display panel, and a driving method thereof, so that operating voltages of liquid crystals in positive and negative frames tend to be equal, and problems such as flicker and afterimage are improved.
  • an array substrate including a substrate substrate, and a plurality of sub-pixel units arranged in an array on the substrate; each of the sub-pixel units including a first thin film transistor and a second thin film a transistor; the first thin film transistor includes a first gate, a first source, and a first drain, and the second thin film transistor includes a second gate, a second source, and a second drain; each of the The sub-pixel unit further includes a first pixel electrode electrically coupled to the first drain, and a second pixel electrode electrically coupled to the second drain, the first pixel electrode and the second pixel electrode being different Set and insulated from each other.
  • the first pixel electrode is provided with a plurality of first slits
  • the second pixel electrode is provided with a plurality of second slits, the first slit and the second slit Stitched settings.
  • the first gate is electrically coupled to the first gate line, and the second gate is electrically coupled to the second gate line; the first source Electrically connected to the first data line Then, the second source is electrically coupled to the second data line.
  • the first source and the second source in the same sub-pixel unit are electrically coupled respectively
  • the first data line and the second data line are the same data line.
  • the first gate line and the second gate line are disposed in parallel and in the same layer.
  • the first gate and the second gate are disposed in a same layer; the first source, the first drain, and the first The two sources and the second drain are disposed in the same layer.
  • all of the first slits are aligned in one direction, and all of the second slits are aligned in the same direction.
  • all of the first slits are aligned in at least two directions, and all of the second slits are aligned in the same direction as the first slit.
  • each of the sub-pixel units further includes a common electrode; the common electrode to the first pixel electrode and the The distances of the second pixel electrodes are different.
  • the common electrode is configured to generate an electric field with the first pixel electrode and the second pixel electrode, respectively.
  • a display panel in a second aspect, includes: an array substrate, a counter substrate, and a liquid crystal layer therebetween; further comprising a common electrode disposed on the array substrate or on the counter substrate; wherein the array substrate The array substrate of the above first aspect.
  • the array substrate does not include a common electrode
  • the pair of cassette substrates includes a common electrode.
  • a distance between the first pixel electrode and the common electrode is greater than a distance between the second pixel electrode and the common electrode, or a distance between the second pixel electrode and the common electrode is greater than the first pixel electrode and the common electrode the distance between.
  • a method for fabricating an array substrate includes: synchronizing forming a first thin film transistor and a second thin film transistor at each sub-pixel unit; the first thin film transistor includes a first gate, a first source, and a first drain, the second thin film transistor includes a second gate, a second source, and a second drain; forming a first pixel electrode electrically coupled to the first drain, and the second drain A second pixel electrode electrically coupled, the first pixel electrode and the second pixel electrode being in different layers and insulated from each other.
  • a plurality of first narrows are formed on the first pixel electrode a second slit is formed on the second pixel electrode, and the first slit and the second slit are staggered.
  • the first gate is electrically coupled to the first gate line, and the second gate is electrically coupled to the second gate line; the first source Electrically coupled to the first data line, the second source is electrically coupled to the second data line; wherein the first gate line and the second gate line are parallel, and the first gate and the The second gate is simultaneously formed.
  • the first source and the second source in the same sub-pixel unit are respectively electrically coupled
  • the first data line and the second data line are the same data line.
  • a driving method of a display panel If a distance between a first pixel electrode and a common electrode is greater than a distance between a second pixel electrode and a common electrode, the driving method includes: in the first frame, Inputting a scan signal to the first gate line row by row to turn on the first thin film transistor row by row, and input positive polarity to the first pixel electrode connected to the first thin film transistor that is turned on by a data line electrically coupled to the first source a data signal; in the second frame, the scan signal is input to the second gate line row by row to turn on the second thin film transistor row by row, and is connected to the opened second thin film transistor through the data line electrically coupled to the second source The second pixel electrode inputs a negative polarity data signal; or
  • the driving method includes: inputting a scan signal to the second gate line row by row in the first frame, so as to Opening a second thin film transistor, and inputting a positive polarity data signal to a second pixel electrode connected to the opened second thin film transistor through a data line electrically coupled to the second source; and in the second frame, to the first gate line Inputting a scan signal row by row to turn on the first thin film transistor row by row, and input a negative polarity data signal to the first pixel electrode connected to the first thin film transistor that is turned on by a data line electrically coupled to the first source;
  • the first frame and the second frame are adjacent frames. It should be noted that “the first frame and the second frame are adjacent frames” herein means that the second frame is an adjacent frame that is temporally next to the first frame.
  • An embodiment of the present invention provides an array substrate, a manufacturing method thereof, a display panel, and a driving method thereof, wherein a first thin film transistor, a second thin film transistor, and a first drain of a first thin film transistor are disposed in each sub-pixel unit.
  • the coupled first pixel electrode and the second pixel electrode electrically coupled to the second drain of the second thin film transistor may be located in the same sub-pixel unit in different frames as needed.
  • the first thin film transistor or the second thin film transistor is turned on to allow the first pixel electrode or the second pixel electrode to receive a positive or negative polarity data signal.
  • the first pixel electrode and the second pixel electrode have a certain vertical distance, when an electric field is generated between the first pixel electrode and the second pixel electrode and the common electrode, the distance is closer to the common electrode. For example, the electric field intensity generated between the second pixel electrode and the common electrode is greater than the electric field intensity generated between the first pixel electrode and the common electrode that is farther from the common electrode.
  • 1 is a schematic structural view of an array substrate
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a schematic diagram of connection of components in an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • Figure 5 is a cross-sectional view taken along line A-A of Figure 4.
  • Figure 6 is a cross-sectional view taken along line B-B of Figure 4.
  • FIG. 7 is a schematic structural diagram of a first pixel electrode according to an embodiment of the present invention.
  • FIG. 7b is a schematic structural diagram of a second pixel electrode according to an embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view taken along line C-C of FIG. 4 in the case where the array substrate includes a common electrode;
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 10 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart 1 of a driving method of a display panel according to an embodiment of the present invention.
  • FIG. 12 is a second schematic diagram of a driving method of a display panel according to an embodiment of the present invention.
  • the array substrate 01 includes a base substrate 10, and a plurality of sub-pixel units 20 arranged in an array disposed on the same side of the base substrate 10; each of the sub-pixel units 20 includes a first thin film transistor (Thin Film Transistor, TFT for short) 201, a first pixel electrode 202 electrically coupled to the first drain 2013 of the first thin film transistor 201, and the common electrode 203, further including a first gate of the first thin film transistor 201
  • the poles 2011 are electrically coupled to the first gate line 204 and the data line 205 electrically coupled to the first source 2012.
  • the working principle of the liquid crystal display panel shown in FIG. 1 and FIG. 2 is that a signal is sequentially input to the first gate line 204, and the first thin film transistor 201 connected to the first gate line 204 is turned on, and is raised by the data line 205.
  • the supplied voltage is transmitted to the first pixel electrode 202 to control the alignment state of the liquid crystal molecules by the electric field between the first pixel electrode 202 and the common electrode 203 to control the amount of light emitted by the backlight after passing through the liquid crystal layer, thereby Display the desired image.
  • the voltage supplied to the data line 205 may be a voltage having the same polarity and opposite polarity.
  • an embodiment of the present invention provides an array substrate 01, the array substrate 01 includes a substrate substrate 10, and a plurality of sub-pixel units 20 arranged in an array on the substrate;
  • Each of the sub-pixel units 20 includes a first thin film transistor 201 and a second thin film transistor 206;
  • the first thin film transistor 201 includes a first gate 2011, a first source 2012, and a first drain 2013, the first
  • the second thin film transistor 206 includes a second gate 2061, a second source 2062, and a second drain 2063.
  • each of the sub-pixel units 20 further includes a first pixel electrode 202 electrically coupled to the first drain 2013 and a second pixel electrode 207 electrically coupled to the second drain 2063.
  • the first pixel electrode 202 and the second pixel electrode 207 are disposed in different layers and insulated from each other.
  • the first pixel electrode 202 is provided with a plurality of first slits 2021
  • the second pixel electrode 207 is provided with a plurality of second slits 2071, the first slits 2021 and The second slits 2071 are staggered.
  • the first thin film transistor 201 includes a first semiconductor active layer and a gate insulating layer in addition to the first gate 2011, the first source 2012, and the first drain 2013;
  • the second thin film transistor 206 further includes a second semiconductor active layer and a gate insulating layer in addition to the second gate electrode 2061, the second source electrode 2062, and the second drain electrode 2063.
  • the structures of the first thin film transistor 201 and the second thin film transistor 206 are not limited, and may be a top gate type or a bottom gate type. Further, the materials of the first semiconductor active layer and the second semiconductor active layer are not limited, and semiconductor materials such as amorphous silicon, polycrystalline silicon, metal oxide, organic materials, and the like can be used.
  • the source and drain of the thin film transistor used in all embodiments of the present invention are symmetrical. Therefore, the source and drain of each thin film transistor are indistinguishable. Based on this, in order to distinguish the two poles of each thin film transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the first slit 2021 and the second slit 2071 are alternately disposed, that is, in a direction perpendicular to the array substrate 01, the first slit 2021 and the second slit 2071 are on a substrate.
  • the projections on the substrate 10 have no overlap.
  • the common electrode that generates an electric field with the first pixel electrode 202 and the second pixel electrode 207 may be disposed on the array substrate 01 or may not be disposed on the array substrate 01. When it is not disposed on the array substrate 01, it may be disposed on the counter substrate of the liquid crystal display device opposite to the array substrate 01.
  • the embodiment of the present invention provides an array substrate 01.
  • the first thin film transistor 201, the second thin film transistor 206, and the first electrode 2013 connected to the first drain electrode 2013 of the first thin film transistor 201 are disposed in each of the sub-pixel units 20.
  • the pixel electrode 202 and the second pixel electrode 207 electrically coupled to the second drain 2063 of the second thin film transistor 206 can make the first thin film transistor 201 or the second thin film in the same sub-pixel unit 20 in different frames as needed.
  • the transistor 206 is turned on to cause the first pixel electrode 202 or the second pixel electrode 207 to receive a positive or negative polarity data signal.
  • the distance The electric field intensity generated between the second pixel electrode 207 and the common electrode is greater than the electric field intensity generated between the first pixel electrode 202 and the common electrode, which is farther from the common electrode.
  • the absolute value of the negative polarity voltage received by the second pixel electrode 207 is relatively first.
  • the value of the positive polarity voltage received by the pixel electrode 202 is small, but since the second pixel electrode 207 is closer to the common electrode than the first pixel electrode 202, the second pixel electrode 207 and the first pixel electrode 202 are respectively made to be connected to the common electrode.
  • the generated electric field strengths tend to be equal, so that when the array substrate is applied to a liquid crystal display device, the operating voltage of the liquid crystal in the positive and negative frames tends to be equal, thereby improving problems such as flicker and afterimage.
  • the electric field intensity generated between the first pixel electrode 202 and the common electrode is greater than that between the second pixel electrode 207 and the common electrode that are farther from the common electrode. Electric field strength.
  • the first gate 2011 may be electrically coupled to the first gate line 204, and the second gate 2061 may be electrically coupled to the second gate line 208.
  • the first source 2012 can be electrically coupled to a first data line, and the second source 2062 can be electrically coupled to a second data line.
  • the first thin film transistor 201 can be controlled to be turned on or off by inputting a scan signal to the first gate line 204; when the first thin film transistor 201 is turned on, the signal can be transmitted to the first by inputting a data signal to the first data line.
  • the pixel electrode 202 is
  • the second thin film transistor 206 can be controlled to be turned on or off by inputting a scan signal to the second gate line 208; when the second thin film transistor 206 is turned on, the signal can be transmitted to the second by inputting a data signal to the second data line.
  • Pixel electrode 207 Pixel electrode 207.
  • first data line and the second data line may be the same data line, and may of course be different data lines. All the drawings of the present invention use the first data line and the second data line.
  • the same data line 205 is illustrated.
  • each row of the first thin film transistors 201 in the sub-pixel unit for example, electrically coupled to a first gate line 204; for each row of the second thin film transistors 206 in the sub-pixel unit 20, for example And electrically coupled to a second gate line 208.
  • each column of the first thin film transistor 201 in the sub-pixel unit 20 for example, electrically coupled to a first data line
  • each column of the second thin film transistor 206 in the sub-pixel unit 20 for example The second data line of the root is electrically connected.
  • the first thin film transistor 201 and the second thin film transistor 206 are not turned on at each frame in each frame, that is, the first pixel electrode 202 and the second pixel electrode 207 do not work at the same time, for example, as shown in FIG. 3 and As shown in FIG. 4, the first source 2012 and the second source 2062 located in the same sub-pixel unit 20 of the embodiment of the present invention are electrically coupled to a data line 205. That is, the first data line and the second data line electrically coupled to the first source 2012 and the second source 2062 in the same sub-pixel unit 20 are the same data line 205.
  • the first gate line 204 and the second gate line 208 are arranged in parallel and in the same layer.
  • the first gate line 204 is formed by the same patterning process, and the second gate line 208 is also formed. In this way, an increase in the number of patterning processes can be avoided.
  • the first gate 2011 and the second gate 2061 are disposed in the same layer; the first source 2012, the first drain 2013, the second source 2062, and the The second drain 2063 is disposed in the same layer.
  • first gate electrode 2011 and the second gate electrode 2061 are formed by the same patterning process.
  • the first source 2012, the first drain 2013, the second source 2062, and the second drain 2063 are formed by the same patterning process.
  • first gate line 204 and the second gate line 208 may also be formed while forming the first gate electrode 2011 and the second gate electrode 2061.
  • a first gate line 204 and a second gate line 208 are disposed between adjacent sub-pixel units 20 in the direction of the data line 205.
  • the data line 205 may be formed while forming the first source 2012, the first drain 2013, the second source 2062, and the second drain 2063.
  • all of the first slits 2021 are arranged in one direction, and all of the second slits 2071 are arranged in the same direction.
  • the electric field generated by the first pixel electrode 202 and the common electrode having the first slits 2021 arranged in the same direction, and the second pixel electrode 207 having the second slits 2071 arranged in the same direction are respectively generated by the common electrode.
  • the electric field can align liquid crystal molecules in a single domain manner.
  • all of the first slits 2021 are arranged in at least two directions, and all of the second slits 2071 are arranged in the same direction as the first slits 2021.
  • first slit 2021 and the second slit 2071 are arranged in two directions, but the embodiment of the present invention is not limited thereto, and the first slit 2021 and the first The two slits 2071 can be arranged in a plurality of directions, for example, can be arranged in four directions and eight directions, and can be set according to actual conditions.
  • All the second slits 2071 are arranged in the same direction as the first slits 2021, that is, when all the first slits 2021 are arranged in a plurality of directions, all the second slits 2071 are also arranged in the plurality of directions.
  • all the first slits 2021 are arranged in two directions
  • all the second slits 2071 are also Arranged in the above two directions
  • all the first slits 2021 are arranged in four directions
  • all the second slits 2071 are also arranged in the above four directions
  • all the first slits 2021 are arranged in eight directions
  • all The second slits 2071 are also arranged in the above eight directions.
  • the electric field generated by the first pixel electrode 202 and the common electrode of the first slit 2021 arranged in different directions, the second pixel electrode 207 having the second slit 2071 arranged in different directions, and the electric field generated by the common electrode The liquid crystal molecules can be arranged in a multi-domain manner, respectively. This can increase the viewing angle of the liquid crystal display.
  • each of the sub-pixel units 20 further includes a common electrode 203 for respectively The first pixel electrode 202 and the second pixel electrode 207 generate an electric field; wherein the distance from the common electrode 203 to the first pixel electrode 202 and the second pixel electrode 207 is different.
  • the arrangement position of the common electrode 203 is only schematically illustrated in FIG. 8 , but the embodiment of the present invention is not limited thereto, and may be located at other positions as long as it can be combined with the first pixel electrode 202 or the second pixel electrode 207 . It is enough to generate an electric field.
  • the embodiment of the present invention further provides a display panel.
  • the display panel includes the array substrate 01, the counter substrate 02, and the liquid crystal layer 03 located therebetween.
  • the common electrode 203 is disposed on the array substrate 01 or on the counter substrate 02.
  • the array substrate 01 does not include a common electrode
  • the counter substrate 02 includes a common electrode 203 .
  • an embodiment of the present invention further provides a display device including the above display panel and a driving module.
  • the display device may specifically be a product or component having any display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the embodiment of the invention further provides a method for preparing an array substrate. As shown in FIG. 10, the method includes the following steps:
  • the first thin film transistor 201 and the second thin film transistor 206 located in each sub-pixel unit 20 are synchronously formed; the first thin film transistor 201 includes a first gate 2011, a first source 2012, and a first A drain 2013, the second thin film crystal 206 tube includes a second gate 2061, a second source 2062, and a second drain 2063.
  • the first thin film transistor 201 and the second thin film transistor 206 which are formed in synchronization with each of the sub-pixel units 20 may specifically be: the first gate electrode 2011 and the second gate electrode 2061 are formed by one patterning process; formed by another patterning process. a first semiconductor active layer (not shown) and a second semiconductor active layer (not shown); forming a first source 2012, a first drain 2013, and a second source by a further patterning process 2062, a second drain 2063.
  • first gate 2011 may be electrically coupled to the first gate line 204
  • second gate 2061 may be electrically coupled to the second gate line 208
  • first source 2012 may be coupled to the first data line Electrically coupled
  • second source 2062 can be electrically coupled to the second data line.
  • first gate line 204 and the second gate line 208 are parallel, and while the first gate electrode 2011 and the second gate electrode 2061 are formed, the first gate line 204 and the second gate are formed. Line 208.
  • first data line and the second data line respectively electrically coupled to the first source 2012 and the second source 2062 in the same sub-pixel unit 20 are the same data line 205.
  • the data line 205 is formed while forming the first source 2012, the first drain 2013, the second source 2062, and the second drain 2063.
  • first pixel electrode 202 electrically coupled to the first drain 2013, and a second pixel electrode 207 electrically coupled to the second drain 2063, the first pixel electrode 202 and the second pixel
  • the electrodes 207 are located in different layers and are insulated from each other.
  • the first pixel electrode 202 is formed with a plurality of first slits 2021
  • the second pixel electrode 207 is formed with a plurality of second slits 2071, the first slits 2021 and the second The slits 2071 are staggered.
  • the embodiment of the present invention further provides a driving method of the display panel. If the distance between the first pixel electrode 202 and the common electrode 203 of the array substrate 01 is greater than the distance between the second pixel electrode 207 and the common electrode 203, As shown in FIG. 11, the driving method includes the following steps:
  • the first frame and the second frame are adjacent frames.
  • the distance from the common electrode is The electric field intensity generated between the near second pixel electrode 207 and the common electrode 203 is greater than the electric field intensity generated between the first pixel electrode 202 and the common electrode 203 which are farther from the common electrode 203.
  • the driving method includes:
  • the first frame and the second frame are adjacent frames.
  • the distance from the common electrode is The electric field intensity generated between the near first pixel electrode 202 and the common electrode 203 is greater than the electric field intensity generated between the second pixel electrode 207 and the common electrode 203 which are farther from the common electrode 203.

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Abstract

提供了一种阵列基板(01)及其制造方法、包括上述阵列基板(01)的显示面板及其驱动方法，使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。该阵列基板(01)的每个子像素单元(20)包括第一薄膜晶体管(201)和第二薄膜晶体管(206)；第一薄膜晶体管(201)包括第一栅极(2011)、第一源极(2012)和第一漏极(2013)，第二薄膜晶体管(206)包括第二栅极(2061)、第二源极(2062)和第二漏极(2063)；每个子像素单元(20)还包括与第一漏极(2013)电联接的第一像素电极(202)、与第二漏极(2063)电联接的第二像素电极(207)，第一像素电极(202)和第二像素电极(207)异层设置且绝缘。

Description

一种阵列基板及其制造方法、显示面板及其驱动方法 技术领域
本发明的实施例涉及一种阵列基板及其制造方法、显示面板及其驱动方法。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有体积小、功耗低、无辐射等特点，在当前的显示器市场中占据主导地位。
具体的，液晶显示器包括液晶显示面板和背光源，液晶显示面板包括阵列基板、对盒基板、位于二者之间的液晶层。
然而，在阵列基板的生产过程中，由于工艺参数、材料、以及杂质离子等的影响，会导致闪烁(Flicker)、残像等问题，进而影响产品良率。
发明内容
本发明的实施例提供一种阵列基板及其制造方法、显示面板及其驱动方法，使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种阵列基板，包括衬底基板、以及设置在所述衬底基板上呈阵列排布的多个子像素单元；每个所述子像素单元包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极；每个所述子像素单元还包括与所述第一漏极电联接的第一像素电极、与所述第二漏极电联接的第二像素电极，所述第一像素电极和所述第二像素电极异层设置且彼此绝缘。在一些实施方式中，所述第一像素电极上设置有多个第一狭缝，所述第二像素电极上设置有多个第二狭缝，所述第一狭缝和所述第二狭缝交错设置。
在所述第一方面的第一种可能的实现方式中，所述第一栅极与第一栅线电联接，所述第二栅极与第二栅线电联接；所述第一源极与第一数据线电联 接，所述第二源极与第二数据线电联接。
结合所述第一方面的第一种可能的实现方式，在第二种可能的实现方式中，与同一子像素单元中的所述第一源极和所述第二源极分别电联接的所述第一数据线和所述第二数据线为同一根数据线。
结合所述第一方面的第一种可能的实现方式，在第三种可能的实现方式中，所述第一栅线和所述第二栅线平行且同层设置。
在所述第一方面的第四种可能的实现方式中，所述第一栅极和所述第二栅极同层设置；所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
在所述第一方面的第五种可能的实现方式中，所有第一狭缝沿一个方向排列，所有第二狭缝沿同一个方向排列。
在所述第一方面的第六种可能的实现方式中，所有第一狭缝沿至少两个方向排列，所有第二狭缝沿与所述第一狭缝相同的方向排列。
结合所述第一方面的各种可能的实现方式，在第七种可能的实现方式中，每个所述子像素单元还包括公共电极；所述公共电极到所述第一像素电极和所述第二像素电极的距离不相同。在一些实施方式中，所述公共电极配置为分别与所述第一像素电极和所述第二像素电极产生电场。
第二方面，提供一种显示面板，包括阵列基板、对盒基板以及位于二者之间的液晶层；还包括公共电极，其设置于阵列基板上或对盒基板上；其中，所述阵列基板为上述第一方面所述的阵列基板。
在所述第二方面的第一种可能的实现方式中，所述阵列基板不包括公共电极，所述对盒基板包括公共电极。在一些实施方式中，第一像素电极和公共电极之间的距离大于第二像素电极和公共电极之间的距离，或者第二像素电极和公共电极之间的距离大于第一像素电极和公共电极之间的距离。
第三方面，提供一种制备阵列基板的方法，包括：同步形成位于每个子像素单元的第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极；形成与所述第一漏极电联接的第一像素电极、与所述第二漏极电联接的第二像素电极，所述第一像素电极和所述第二像素电极位于不同层且彼此绝缘。在一些实施方式中，所述第一像素电极上形成有多个第一狭 缝，所述第二像素电极上形成有多个第二狭缝，所述第一狭缝和所述第二狭缝交错。
在所述第三方面的第一种可能的实现方式中，所述第一栅极与第一栅线电联接，所述第二栅极与第二栅线电联接；所述第一源极与第一数据线电联接，所述第二源极与第二数据线电联接；其中，所述第一栅线和所述第二栅线平行，且与所述第一栅极和所述第二栅极同时形成。
结合所述第三方面的第一种可能的实现方式，在第二种可能的实现方式中，与同一子像素单元中的所述第一源极和所述第二源极分别电联接的所述第一数据线和所述第二数据线为同一根数据线。
第四方面，提供一种显示面板的驱动方法，若第一像素电极到公共电极之间的距离大于第二像素电极到公共电极之间的距离，则所述驱动方法包括：在第一帧，向第一栅线逐行输入扫描信号，以便逐行开启第一薄膜晶体管，并通过与第一源极电联接的数据线向开启的所述第一薄膜晶体管连接的第一像素电极输入正极性数据信号；在第二帧，向第二栅线逐行输入扫描信号，以便逐行开启第二薄膜晶体管，并通过与第二源极电联接的数据线向开启的所述第二薄膜晶体管连接的第二像素电极输入负极性数据信号；或者，
若第一像素电极到公共电极之间的距离小于第二像素电极到公共电极之间的距离，则所述驱动方法包括：在第一帧，向第二栅线逐行输入扫描信号，以便逐行开启第二薄膜晶体管，并通过与第二源极电联接的数据线向开启的所述第二薄膜晶体管连接的第二像素电极输入正极性数据信号；在第二帧，向第一栅线逐行输入扫描信号，以便逐行开启第一薄膜晶体管，并通过与第一源极电联接的数据线向开启的所述第一薄膜晶体管连接的第一像素电极输入负极性数据信号；
其中，所述第一帧和所述第二帧为相邻帧。需要说明的是，这里的“所述第一帧和所述第二帧为相邻帧”是指所述第二帧为在时间上紧接着所述第一帧的相邻帧。
本发明实施例提供一种阵列基板及其制造方法、显示面板及其驱动方法，通过在每个子像素单元中设置第一薄膜晶体管、第二薄膜晶体管、与第一薄膜晶体管的第一漏极电联接的第一像素电极、与第二薄膜晶体管的第二漏极电联接的第二像素电极，可以根据需要在不同帧中使位于同一个子像素单元 中的第一薄膜晶体管或第二薄膜晶体管开启，以便使所述第一像素电极或第二像素电极接收正极性或负极性的数据信号。
基于此，由于所述第一像素电极和所述第二像素电极之间具有一定的垂直距离，因此当第一像素电极和第二像素电极与公共电极之间产生电场时，距离公共电极较近的例如第二像素电极与公共电极之间产生的电场强度大于距离公共电极较远的例如第一像素电极与公共电极之间产生的电场强度。在此基础上，当向第一源极输入正极性电压信号，向第二源极输入负极性等同电压信号时，虽然最终第二像素电极接收的负极性电压的绝对值相对第一像素电极接收到的正极性电压的值小，但是由于第二像素电极相对第一像素电极距离公共电极更近，因此，使得第二像素电极和第一像素电极分别与公共电极产生的电场强度趋于相等，从而当该阵列基板应用于液晶显示装置时，最终使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种阵列基板的结构示意图；
图2为图1中A-A向剖视示意图；
图3为本发明实施例提供的一种阵列基板中各部件的连接示意图；
图4为本发明实施例提供的一种阵列基板的结构示意图；
图5为图4中A-A向剖视示意图；
图6为图4中B-B向剖视示意图；
图7a为本发明实施例提供的一种第一像素电极的结构示意图；
图7b为本发明实施例提供的一种第二像素电极的结构示意图；
图8为当所述阵列基板包括公共电极的情况下图4中C-C向剖视示意图；
图9为本发明实施提供的一种显示面板的结构示意图；
图10为本发明实施提供的一种阵列基板的制备方法的流程示意图；
图11为本发明实施提供的一种显示面板的驱动方法的流程示意图一；
图12为本发明实施提供的一种显示面板的驱动方法的流程示意图二。
附图标记：
01-阵列基板；02-对盒基板；03-液晶层；10-衬底基板；20-子像素单元；201-第一薄膜晶体管；202-第一像素电极；203-公共电极；204-第一栅线；205-数据线；206-第二薄膜晶体管；207-第二像素电极；208-第二栅线；2011-第一栅极；2012-第一源极；2013-第一漏极；2061-第二栅极；2062-第二源极；2063-第二漏极；2021-第一狭缝；2071-第二狭缝。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本领域技术人员所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或“一”等等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明。
图1和图2示出了一种液晶显示面板，其中像素电极和公共电极都位于阵列基板上。在图1和图2中，阵列基板01包括衬底基板10、以及设置在所述衬底基板10同一侧的呈阵列排布的多个子像素单元20；每个子像素单元20包括第一薄膜晶体管(Thin Film Transistor，简称TFT)201，与第一薄膜晶体管201的第一漏极2013电联接的第一像素电极202、以及公共电极203，还包括与所述第一薄膜晶体管201的第一栅极2011电联接的第一栅线204和与第一源极2012电联接的数据线205。
图1和图2所示的液晶显示面板的工作原理为：依次向第一栅线204输入信号，与第一栅线204相连的第一薄膜晶体管201开启，由数据线205提 供的电压传输到第一像素电极202，以便通过第一像素电极202和公共电极203之间的电场来控制液晶分子的排列状态，以控制背光源发出的光经液晶层后的出光量，从而显示所需的图像。其中，在不同帧中，对于数据线205提供的电压，可以是电压值相等极性相反的电压。
然而，在阵列基板的生产过程中，由于工艺参数、材料、以及杂质离子等的影响，会导致第一像素电极202实际接收到的电压与数据线205提供的电压之间存在差值(即△Vp)，并且当数据线205提供极性相反的电压时，上述△Vp的差值不相同(当数据线205提供负极性电压时，△Vp的值更大)，这样会导致正负帧下第一像素电极202与公共电极203之间的电场强度不相等，从而导致闪烁(Flicker)、残像等问题，进而影响产品良率。
如图3-6所示，本发明实施例提供了一种阵列基板01，该阵列基板01包括衬底基板10、以及设置在所述衬底基板上呈阵列排布的多个子像素单元20；每个所述子像素单元20包括第一薄膜晶体管201和第二薄膜晶体管206；所述第一薄膜晶体管201包括第一栅极2011、第一源极2012和第一漏极2013，所述第二薄膜晶体管206包括第二栅极2061、第二源极2062和第二漏极2063。
在此基础上，每个所述子像素单元20还包括与所述第一漏极2013电联接的第一像素电极202、与所述第二漏极2063电联接的第二像素电极207，所述第一像素电极202和所述第二像素电极207异层设置且彼此绝缘。
在该实施例中，所述第一像素电极202上设置有多个第一狭缝2021，所述第二像素电极207上设置有多个第二狭缝2071，所述第一狭缝2021和所述第二狭缝2071交错设置。
需要说明的是，第一，所述第一薄膜晶体管201除包括第一栅极2011、第一源极2012和第一漏极2013外，还包括第一半导体有源层和栅绝缘层；所述第二薄膜晶体管206除包括第二栅极2061、第二源极2062和第二漏极2063外，还包括第二半导体有源层和栅绝缘层。
在本申请中，所述第一薄膜晶体管201和第二薄膜晶体管206的结构没有限制，其可以是顶栅型，也可以是底栅型。此外，所述第一半导体有源层和第二半导体有源层的材料也没有限制，其可以采用非晶硅、多晶硅、金属氧化物、有机材料等半导体材料等。
第二，本发明所有实施例中采用的薄膜晶体管的源极、漏极是对称的， 所以每个薄膜晶体管的源极和漏极是没有区别的。基于此，为区分每个薄膜晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。
第三，所述第一狭缝2021和所述第二狭缝2071交错设置，即为：沿垂直所述阵列基板01的方向，所述第一狭缝2021和第二狭缝2071在衬底基板10上的投影无重叠。
第四，对于与第一像素电极202和第二像素电极207分别产生电场的公共电极，其可以设置在阵列基板01上，也可以不设置在阵列基板01上。当其不设置在阵列基板01上时，其可以设置在液晶显示装置的与该阵列基板01对盒的对盒基板上。
本发明实施例提供了一种阵列基板01，通过在每个子像素单元20中设置第一薄膜晶体管201、第二薄膜晶体管206、与第一薄膜晶体管201的第一漏极2013电联接的第一像素电极202、与第二薄膜晶体管206的第二漏极2063电联接的第二像素电极207，可以根据需要在不同帧中使位于同一个子像素单元20中的第一薄膜晶体管201或第二薄膜晶体管206开启，以便使所述第一像素电极202或第二像素电极207接收正极性或负极性的数据信号。
基于此，由于所述第一像素电极202和所述第二像素电极207之间具有一定的垂直距离，因此当第一像素电极202和第二像素电极207与公共电极之间产生电场时，距离公共电极较近的例如第二像素电极207与公共电极之间产生的电场强度大于距离公共电极较远的例如第一像素电极202与公共电极之间产生的电场强度。在此基础上，当向第一源极2012输入正极性电压信号，向第二源极2062输入负极性等同电压信号时，虽然最终第二像素电极207接收的负极性电压的绝对值相对第一像素电极202接收到的正极性电压的值小，但是由于第二像素电极207相对第一像素电极202距离公共电极更近，因此，使得第二像素电极207和第一像素电极202分别与公共电极产生的电场强度趋于相等，从而当该阵列基板应用于液晶显示装置时，最终使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
当然，若距离公共电极较近的是第一像素电极202，则第一像素电极202与公共电极之间产生的电场强度大于距离公共电极较远的第二像素电极207与公共电极之间产生的电场强度。在此基础上，当向第二源极2062输入正极性电压信号，向第一源极2012输入负极性等同电压信号时，虽然最终第一像 素电极202接收的负极性电压的绝对值相对第二像素电极207接收到的正极性电压的值小，但是由于第一像素电极202相对第二像素电极207距离公共电极更近，因此，使得第一像素电极202和第二像素电极207分别与公共电极产生的电场强度趋于相等，从而当该阵列基板应用于液晶显示装置时，最终使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
如图4所示，所述第一栅极2011可以与第一栅线204电联接，所述第二栅极2061可以与第二栅线208电联接。所述第一源极2012可以与第一数据线电联接，所述第二源极2062可以与第二数据线电联接。
通过向第一栅线204输入扫描信号，可以控制第一薄膜晶体管201的开启或关闭；当第一薄膜晶体管201开启时，通过向第一数据线输入数据信号，可以将该信号传递到第一像素电极202。
通过向第二栅线208输入扫描信号，可以控制第二薄膜晶体管206的开启或关闭；当第二薄膜晶体管206开启时，通过向第二数据线输入数据信号，可以将该信号传递到第二像素电极207。
需要说明的是，所述第一数据线和所述第二数据线可以为同一根数据线，当然也可以为不同数据线，本发明所有附图以所述第一数据线和第二数据线为同一根数据线205进行示意。
此外，对于每行所述子像素单元20中的第一薄膜晶体管201，例如，与一根第一栅线204电联接；对于每行所述子像素单元20中的第二薄膜晶体管206，例如，与一根第二栅线208电联接。
对于每列所述子像素单元20中的第一薄膜晶体管201，例如，与一根第一数据线电联接，对于每列所述子像素单元20中的第二薄膜晶体管206，例如，与一根第二数据线电联接。
考虑到在每帧中所述第一薄膜晶体管201和第二薄膜晶体管206不同时开启，也就是所述第一像素电极202和第二像素电极207不同时工作，因此，例如，如图3和图4所示，本发明实施例位于同一子像素单元20中的所述第一源极2012和所述第二源极2062与一根数据线205电联接。即，与同一子像素单元20中的所述第一源极2012和所述第二源极2062分别电联接的所述第一数据线和所述第二数据线为同一根数据线205。
这样，可以避免由于数据线205增加而导致阵列基板01的布线太密，从 而导致其制备过程复杂。
在一些实施方式中，如图4所示，所述第一栅线204和所述第二栅线208平行且同层设置。
即：通过同一次构图工艺即形成所述第一栅线204，也形成所述第二栅线208。这样，可以避免构图工艺次数的增加。
在一些实施方式中，所述第一栅极2011和所述第二栅极2061同层设置；所述第一源极2012、所述第一漏极2013、所述第二源极2062和所述第二漏极2063同层设置。
即：通过同一次构图工艺形成所述第一栅极2011和所述第二栅极2061。通过同一次构图工艺形成所述第一源极2012、所述第一漏极2013、所述第二源极2062和所述第二漏极2063。
当然，在形成所述第一栅极2011和第二栅极2061的同时，还可以形成所述第一栅线204和第二栅线208。在此情况下，沿数据线205的方向，相邻子像素单元20之间均设置一根第一栅线204和一根第二栅线208。
此外，在形成所述第一源极2012、第一漏极2013、第二源极2062和第二漏极2063的同时，还可以形成所述数据线205。
基于上述，可选的，参考图4所示，所有第一狭缝2021沿一个方向排列，所有第二狭缝2071沿同一个方向排列。
基于此，具有沿同一方向排列的第一狭缝2021的第一像素电极202与公共电极产生的电场、具有沿同一方向排列的第二狭缝2071的第二像素电极207分别与公共电极产生的电场，可以使液晶分子以单畴方式排列。
可选的，如图7a和7b所示，所有第一狭缝2021沿至少两个方向排列，所有第二狭缝2071沿与所述第一狭缝2021相同的方向排列。
需要说明的是，图7a和7b中仅以第一狭缝2021和第二狭缝2071沿两个方向排列为例进行说明，但本发明实施例并不限于此，第一狭缝2021和第二狭缝2071可以沿多个方向排列，例如可以沿4个方向、8个方向排列，具体可根据实际情况进行设定。
所有第二狭缝2071沿与所述第一狭缝2021相同的方向排列，即为：当所有第一狭缝2021沿多个方向排列时，所有第二狭缝2071也沿该多个方向排列；例如当所有第一狭缝2021沿2个方向排列时，所有第二狭缝2071也 沿上述2个方向排列；当所有第一狭缝2021沿4个方向排列时，所有第二狭缝2071也沿上述4个方向排列；当所有第一狭缝2021沿8个方向排列时，所有第二狭缝2071也沿上述8个方向排列。
基于此，具有沿不同方向排列的第一狭缝2021的第一像素电极202与公共电极产生的电场、具有沿不同方向排列的第二狭缝2071的第二像素电极207与公共电极产生的电场，可以分别使液晶分子以多畴方式排列。这样可以增加液晶显示器的视角。
在上述基础上，所述公共电极可以设置在阵列基板01上，即，如图8所示，所述每个所述子像素单元20还包括公共电极203，所述公共电极203用于分别与所述第一像素电极202和所述第二像素电极207产生电场；其中，所述公共电极203到所述第一像素电极202和所述第二像素电极207的距离不相同。
图8中仅示意性的绘示出所述公共电极203的设置位置，但本发明实施例并不限于此，也可以位于其他位置，只要其能与第一像素电极202或第二像素电极207产生电场即可。
本发明实施例还提供一种显示面板，如图9所示，该显示面板包括上述的阵列基板01、对盒基板02以及位于二者之间的液晶层03。其中，公共电极203设置于阵列基板01上或对盒基板02上。
可选的，如图9所示，所述阵列基板01不包括公共电极，所述对盒基板02包括公共电极203。
进一步的，本发明实施例还提供一种显示装置，其包括上述的显示面板和驱动模块。
上述显示装置具体可以是液晶显示器、液晶电视、数码相框、手机、平板电脑等具有任何显示功能的产品或者部件。
本发明实施例还提供一种阵列基板的制备方法，如图10所示，该方法包括如下步骤：
S10、参考图4所示，同步形成位于每个子像素单元20的第一薄膜晶体管201和第二薄膜晶体管206；所述第一薄膜晶体管201包括第一栅极2011、第一源极2012和第一漏极2013，所述第二薄膜晶体206管包括第二栅极2061、第二源极2062和第二漏极2063。
此处，同步形成位于每个子像素单元20的第一薄膜晶体管201和第二薄膜晶体管206具体可以是：通过一次构图工艺形成第一栅极2011和第二栅极2061；通过另一次构图工艺形成第一半导体有源层(图中未标识出)和第二半导体有源层(图中未标识出)；通过再一次构图工艺形成第一源极2012、第一漏极2013和第二源极2062、第二漏极2063。
进一步的，所述第一栅极2011可以与第一栅线204电联接，所述第二栅极2061可以与第二栅线208电联接；所述第一源极2012可以与第一数据线电联接，第二源极2062可以与第二数据线电联接。
在此基础上，例如所述第一栅线204和所述第二栅线208平行，且在形成第一栅极2011和第二栅极2061的同时，形成第一栅线204和第二栅线208。
进一步的，例如，与同一子像素单元20中的所述第一源极2012和所述第二源极2062分别电联接的所述第一数据线和所述第二数据线为同一根数据线205。
在此基础上，例如，在形成第一源极2012、第一漏极2013、第二源极2062、第二漏极2063的同时，形成所述数据线205。
S11、形成与所述第一漏极2013电联接的第一像素电极202、与所述第二漏极2063电联接的第二像素电极207，所述第一像素电极202和所述第二像素电极207位于不同层且彼此绝缘。
其中，所述第一像素电极202上形成有多个第一狭缝2021，所述第二像素电极207上形成有多个第二狭缝2071，所述第一狭缝2021和所述第二狭缝2071交错。
本发明实施例还提供一种显示面板的驱动方法，若该阵列基板01的第一像素电极202到公共电极203之间的距离大于第二像素电极207到公共电极203之间的距离，则，如图11所示，所述驱动方法包括如下步骤：
S20、在第一帧，向第一栅线204逐行输入扫描信号，以便逐行开启第一薄膜晶体管201，并通过与第一源极2012电联接的数据线205向开启的所述第一薄膜晶体管201连接的第一像素电极202输入正极性数据信号。
S21、在第二帧，向第二栅线208逐行输入扫描信号，以便逐行开启第二薄膜晶体管206，并通过与第二源极2062电联接的数据线205向开启的所述第二薄膜晶体管206连接的第二像素电极207输入负极性数据信号。
所述第一帧和所述第二帧为相邻帧。
由于所述第一像素电极202和所述第二像素电极207之间具有一定的垂直距离，因此当第一像素电极202和第二像素电极207与公共电极之间产生电场时，距离公共电极较近的第二像素电极207与公共电极203之间产生的电场强度大于距离公共电极203较远的第一像素电极202与公共电极203之间产生的电场强度。在此基础上，当向与第一源极2012相连的数据线205输入正极性电压信号，向与第二源极2062相连的数据线205输入负极性等同电压信号时，虽然最终第二像素电极207接收的负极性电压的绝对值相对第一像素电极202接收到的正极性电压的值小，但是由于第二像素电极207相对第一像素电极202距离公共电极更近，因此，使得第二像素电极207和第一像素电极202分别与公共电极产生的电场强度趋于相等，从而当该阵列基板应用于液晶显示装置时，最终使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
若该阵列基板01的第一像素电极202到公共电极203之间的距离小于第二像素电极207到公共电极203之间的距离，则，如图12所示，所述驱动方法包括：
S30、在第一帧，向第二栅线208逐行输入扫描信号，以便逐行开启第二薄膜晶体管206，并通过与第二源极2062电联接的数据线205向开启的所述第二薄膜晶体管206连接的第二像素电极207输入正极性数据信号。
S31、在第二帧，向第一栅线204逐行输入扫描信号，以便逐行开启第一薄膜晶体管201，并通过与第一源极2012电联接的数据线205向开启的所述第一薄膜晶体管201连接的第一像素电极202输入负极性数据信号。
其中，所述第一帧和所述第二帧为相邻帧。
由于所述第一像素电极202和所述第二像素电极207之间具有一定的垂直距离，因此当第一像素电极202和第二像素电极207与公共电极之间产生电场时，距离公共电极较近的第一像素电极202与公共电极203之间产生的电场强度大于距离公共电极203较远的第二像素电极207与公共电极203之间产生的电场强度。在此基础上，当向与第二源极2062相连的数据线205输入正极性电压信号，向与第一源极2012相连的数据线205输入负极性等同电压信号时，虽然最终第一像素电极202接收的负极性电压的绝对值相对第 二像素电极207接收到的正极性电压的值小，但是由于第一像素电极202相对第二像素电极207距离公共电极更近，因此，使得第一像素电极202和第二像素电极207分别与公共电极产生的电场强度趋于相等，从而当该阵列基板应用于液晶显示装置时，最终使得液晶在正负帧下的工作电压趋于相等，达到改善闪烁、残像等问题。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年9月11日递交的中国专利申请第201510580609.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括衬底基板、以及设置在所述衬底基板上呈阵列排布的多个子像素单元；其中，每个所述子像素单元包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极；
    每个所述子像素单元还包括与所述第一漏极电联接的第一像素电极、与所述第二漏极电联接的第二像素电极，所述第一像素电极和所述第二像素电极异层设置且彼此绝缘。
  2. 根据权利要求1所述的阵列基板，其中，所述第一像素电极上设置有多个第一狭缝，所述第二像素电极上设置有多个第二狭缝，所述第一狭缝和所述第二狭缝交错设置。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第一栅极与第一栅线电联接，所述第二栅极与第二栅线电联接；
    所述第一源极与第一数据线电联接，所述第二源极与第二数据线电联接。
  4. 根据权利要求3所述的阵列基板，其中，与同一子像素单元中的所述第一源极和所述第二源极分别电联接的所述第一数据线和所述第二数据线为同一根数据线。
  5. 根据权利要求3所述的阵列基板，其中，所述第一栅线和所述第二栅线平行且同层设置。
  6. 根据权利要求1至5中任一项所述的阵列基板，其中，所述第一栅极和所述第二栅极同层设置；所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
  7. 根据权利要求2至6中任一项所述的阵列基板，其中，所有第一狭缝沿一个方向排列，所有第二狭缝沿同一个方向排列。
  8. 根据权利要求2至6中任一项所述的阵列基板，其中，所有第一狭缝沿至少两个方向排列，所有第二狭缝沿与所述第一狭缝相同的方向排列。
  9. 根据权利要求1至8中任一项所述的阵列基板，其中，每个所述子像素单元还包括公共电极，所述公共电极配置为分别与所述第一像素电极和所述第二像素电极产生电场；
    所述公共电极到所述第一像素电极和所述第二像素电极的距离不相同。
  10. 一种显示面板，包括阵列基板、对盒基板以及位于二者之间的液晶层；还包括设置于阵列基板上或对盒基板上的公共电极；其中，所述阵列基板为权利要求1至9中任一项所述的阵列基板。
  11. 根据权利要求10所述的显示面板，其中，所述阵列基板不包括公共电极，所述对盒基板包括公共电极。
  12. 根据权利要求10或11所述的显示面板，其中，第一像素电极和公共电极之间的距离大于第二像素电极和公共电极之间的距离，或者第二像素电极和公共电极之间的距离大于第一像素电极和公共电极之间的距离。
  13. 一种制备权利要求1至9中任一项所述的阵列基板的方法，包括：
    同步形成位于每个子像素单元的第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极；
    形成与所述第一漏极电联接的第一像素电极、与所述第二漏极电联接的第二像素电极，所述第一像素电极和所述第二像素电极位于不同层且彼此绝缘。
  14. 根据权利要求13所述的方法，其中，所述第一像素电极上形成有多个第一狭缝，所述第二像素电极上形成有多个第二狭缝，所述第一狭缝和所述第二狭缝交错。
  15. 根据权利要求13或14所述的方法，其中，所述第一栅极与第一栅线电联接，所述第二栅极与第二栅线电联接；
    所述第一源极与第一数据线电联接，所述第二源极与第二数据线电联接；
    其中，所述第一栅线和所述第二栅线平行，且与所述第一栅极和所述第二栅极同时形成。
  16. 根据权利要求15所述的方法，其中，与同一子像素单元中的所述第一源极和所述第二源极分别电联接的所述第一数据线和所述第二数据线为同一根数据线。
  17. 一种驱动权利要求10至12中任一项所述的显示面板的方法，其中，若第一像素电极到公共电极之间的距离大于第二像素电极到公共电极之间的距离，则所述驱动方法包括：
    在第一帧，向第一栅线逐行输入扫描信号，以便逐行开启第一薄膜晶体管，并通过与第一源极电联接的数据线向开启的所述第一薄膜晶体管连接的第一像素电极输入正极性数据信号；
    在第二帧，向第二栅线逐行输入扫描信号，以便逐行开启第二薄膜晶体管，并通过与第二源极电联接的数据线向开启的所述第二薄膜晶体管连接的第二像素电极输入负极性数据信号；或者，
    若第一像素电极到公共电极之间的距离小于第二像素电极到公共电极之间的距离，则所述驱动方法包括：
    在第一帧，向第二栅线逐行输入扫描信号，以便逐行开启第二薄膜晶体管，并通过与第二源极电联接的数据线向开启的所述第二薄膜晶体管连接的第二像素电极输入正极性数据信号；
    在第二帧，向第一栅线逐行输入扫描信号，以便逐行开启第一薄膜晶体管，并通过与第一源极电联接的数据线向开启的所述第一薄膜晶体管连接的第一像素电极输入负极性数据信号；
    其中，所述第一帧和所述第二帧为相邻帧。
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