WO2016201730A1 - 一种驱动电路及其驱动方法、液晶显示器 - Google Patents

一种驱动电路及其驱动方法、液晶显示器 Download PDF

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Publication number
WO2016201730A1
WO2016201730A1 PCT/CN2015/082824 CN2015082824W WO2016201730A1 WO 2016201730 A1 WO2016201730 A1 WO 2016201730A1 CN 2015082824 W CN2015082824 W CN 2015082824W WO 2016201730 A1 WO2016201730 A1 WO 2016201730A1
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thin film
film transistor
data line
pixel
line
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PCT/CN2015/082824
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English (en)
French (fr)
Inventor
黄秋平
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深圳市华星光电技术有限公司
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Priority to US14/765,832 priority Critical patent/US20170004794A1/en
Publication of WO2016201730A1 publication Critical patent/WO2016201730A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a driving circuit and a driving method thereof, and a liquid crystal display.
  • the liquid crystal display has the characteristics of low radiation, low power consumption and small size, and has gradually become the mainstream of display devices, and is widely used in mobile phones, notebook computers, flat-panel TVs and the like.
  • a sub-pixel P 1 is currently common pixel structure and driving the liquid crystal panel, a sub-pixel P 1, a drive corresponding through one scanning line G data line D 1 is connected to the sub pixel electrode, when the scan signal progressive scan, each The TFTs of the sub-pixels are sequentially turned on, and the data signals are added to the sub-pixel electrodes through the data lines to realize image display.
  • liquid crystal displays are moving toward large size, high resolution, high definition, etc. Accordingly, the operating frequency and pixel resolution of liquid crystal panels are continuously increasing, and the problem that comes with them is that with the operating frequency and As the resolution of the panel is increased, the charging time of the liquid crystal capacitor is drastically shortened.
  • the resolution of the liquid crystal display is increased to 4K*2K or even 8K*4K or more
  • the conventional 60Hz scanning frequency is increased to 120Hz, 240Hz or even 480Hz or more
  • the time for inputting the data signal of the liquid crystal pixel data line becomes very short, only At present, 1/4, 1/8 or even 1/16, there will be a problem of insufficient charging of the liquid crystal pixels, which affects the quality of the screen display.
  • the technical problem to be solved by the present invention is to provide a driving circuit and a driving method thereof, and a liquid crystal display, which can increase the charging time of a pixel and improve the picture quality of the liquid crystal display.
  • a technical solution adopted by the present invention is to provide a driving circuit for a liquid crystal display, wherein the driving circuit includes a plurality of scanning lines and a plurality of data lines vertically intersecting each other, and a plurality of scanning lines and The plurality of data lines are divided into a plurality of pixel regions; the pixel regions of the mth row and the nth column include a pixel (P m ), a first thin film transistor (T m1 ), a second thin film transistor (T m2 ), and a first scan line (G m1 ), second scan line (G m2 ), first data line (D m1 ), and second data line (D m2 ); m, n are natural numbers; first thin film transistor (T m1 ) and second The drain of the thin film transistor (T m2 ) is connected to the pixel (P m ); the gate of the first thin film transistor (T m1 ) is connected to the first scan line (
  • the m-th row, n-th column pixel region P includes a pixel m, the first thin film transistor T m1, the second thin film transistor T m2, m scan lines G, the data line D m1 of the first and second data lines D m2;
  • the drains of the first thin film transistor T m1 and the second thin film transistor T m2 are connected to the pixel P m ;
  • the gate of the first thin film transistor T m1 is connected to the scan line G m , and the source is connected to the first data line D m1 ;
  • the gate of the second thin film transistor T m2 is connected to the scanning line G m+1 of the m+1th row, and the source is connected to the second data line D m2 .
  • the first data line D m1 and the second data line D m2 are the same data line.
  • a liquid crystal display including a display panel and a backlight source, the display panel including a driving circuit, and the driving circuit including a plurality of scanning lines perpendicularly crossing each other And a plurality of data lines, and the plurality of scan lines and the plurality of data lines are divided into a plurality of pixel regions; each of the pixel regions includes one pixel and at least two thin film transistors, and a gate and a source of each thin film transistor are respectively connected A scan line and a data line, the drain of each thin film transistor is connected to the pixel; wherein at least two thin film transistors are respectively charged to charge the pixel.
  • the pixel region of the mth row and the nth column includes a pixel (P m ), a first thin film transistor (T m1 ), a second thin film transistor (T m2 ), a first scan line (G m1 ), and a second scan line.
  • the first thin film transistor (T m1 ) and the second thin film transistor (T m2 ) The drain is connected to the pixel (P m ); the gate of the first thin film transistor (T m1 ) is connected to the first scan line (G m1 ), the source is connected to the first data line (D m1 ), and the second thin film transistor (T m2 ) The gate is connected to the second scan line (G m2 ), and the source is connected to the second data line (D m2 ).
  • the pixel region of the mth row and the nth column includes a pixel (P m ), a first thin film transistor (T m1 ), a second thin film transistor (T m2 ), a scan line (G m ), and a first data line (D).
  • the drains of the first thin film transistor (T m1 ) and the second thin film transistor (T m2 ) are connected to the pixel (P m ); the first thin film transistor (T m1 )
  • the gate is connected to the scan line (G m )
  • the source is connected to the first data line (D m1 )
  • the gate of the second thin film transistor (T m2 ) is connected to the scan line (G m+1 ) of the m+1th row, The source is connected to the second data line (D m2 ).
  • the first data line (D m1 ) and the second data line (D m2 ) are the same data line.
  • another technical solution adopted by the present invention is to provide a driving method for driving a circuit, the driving circuit including a plurality of pixel regions, each pixel region including one pixel and at least two thin film transistors, A gate line and a source of each thin film transistor are respectively connected to one scan line and one data line, and a drain of each thin film transistor is connected to the pixel, wherein the driving method comprises: sequentially dividing a plurality of thin film transistors in each pixel region Turn on to continuously charge the pixels.
  • the driving method includes: S1, at 0-T, the first scan line G m1 inputs a first level signal to control the first thin film transistor T m1 to open, and passes the first data
  • the line D m1 charges the pixel P m ; S2, at T-2T, the first scan line G m1 inputs the second level signal to control the first thin film transistor T m1 to be turned off, and the second scan line G m2 inputs the first level signal controlling the second thin film transistor T m2 is opened, charging the pixel P m by the second data line D m2; continues to scan lines of the other drive circuit as described above.
  • the step S2 specifically includes: S21.
  • the first scan line Gm1 inputs a first level signal to control the first thin film transistor Tm1 to be turned on, and the second scan line Gm2 inputs a first level signal control.
  • the second thin film transistor T m2 is turned on, and simultaneously charges the pixel P m through the first data line D m1 and the second data line D m2 ;
  • S22 at 2T-3T , the first scan line G m1 inputs the second level signal control a thin film transistor T m1 closed, the second input of the first scan line G m2 level signal for controlling the second thin film transistor T m2 opening, through the second data line to the pixel P m D m2 charge.
  • the pixel region of the mth row and the nth column of the driving includes the pixel P m , the first thin film transistor T m1 , the second thin film transistor T m2 , the scan line G m , and the first data line D m1 and the second data line D M2, the driving method comprising: M1, when 0-T, the scanning line G m a first input signal level to control the first thin film transistor T m1 opened, the first data line D m1 charging the pixel P m; M2, the T- when 2T, the scanning line G m a second input signal level to control the first thin film transistor T m1 closed, the next row scan line G m + 1 input of a first level signal for controlling the second thin film transistor T m2 is opened, the second data line D m2 charging the pixel P m; continues to scan lines of the other drive circuit as described above.
  • the step M2 comprises: M21, the T-2T, the scan lines G m a first input signal level to control the first thin film transistor T m1 opened, the next row scan line G m + 1 input to the first control signal level a second thin film transistor T m2 is opened, charging the pixel P m data line D m1 by the first and second data lines D m2, while the next line start scanning; M22, when the 2T-3T, a second input scan lines G m level signal to control the first thin film transistor T m1 closed, the next row scan line G m + 1 control input of a first level signal to open the second thin film transistor T m2, the pixel P m is charged through the second data line D m2.
  • the invention has the beneficial effects that the present invention provides a driving circuit including a plurality of scanning lines and a plurality of data lines vertically intersecting each other, and a plurality of scanning lines and a plurality of data lines, which are different from the prior art.
  • each pixel region includes one pixel and at least two thin film transistors, and a gate line and a source of each thin film transistor are respectively connected with one scan line and one data line, and a drain of each thin film transistor is connected to the pixel
  • at least two thin film transistors respectively charge the pixels when they are turned on, which can increase the charging time of the pixels and improve the picture quality of the liquid crystal display.
  • FIG. 1 is a pixel structure and a driving method of a liquid crystal panel in the prior art
  • FIG. 2 is a schematic structural view of a first embodiment of a driving circuit of the present invention
  • FIG. 3 is another schematic structural view of a first embodiment of a driving circuit of the present invention.
  • FIG. 4 is a schematic structural view of a second embodiment of a driving circuit of the present invention.
  • FIG. 5 is a schematic flow chart of a first embodiment of a driving method of the present invention.
  • FIG. 6 is a first waveform diagram of a scan line in the first embodiment of the driving method of the present invention.
  • FIG. 7 is a second waveform diagram of a scan line in the first embodiment of the driving method of the present invention.
  • FIG. 8 is a schematic flow chart of a second embodiment of a driving method of the present invention.
  • FIG. 9 is a first waveform diagram of a scan line in a second embodiment of the driving method of the present invention.
  • Figure 10 is a second waveform diagram of a scan line in a second embodiment of the driving method of the present invention.
  • Figure 11 is a schematic view showing the structure of an embodiment of a liquid crystal display of the present invention.
  • the driving circuit includes a plurality of scanning lines and a plurality of data lines vertically intersecting each other, and is divided into a plurality of pixels by a plurality of scanning lines and a plurality of data lines. a region; each pixel region includes one pixel and at least two thin film transistors, and a gate line and a source of each thin film transistor are respectively connected to one scan line and one data line, and a drain of each thin film transistor is connected to the pixel; wherein at least two The pixels are charged separately when the thin film transistors are turned on.
  • Each of the pixel regions shown in FIG. 2 includes one pixel, two thin film transistors, two scan lines, and two data lines.
  • the illustration is merely an example and does not limit the protection range of the embodiment, and may also be added. Thin film transistors, scan lines and data lines.
  • the pixel area 200 of the first row and the first column will be described below:
  • the pixel region 200 includes a pixel P 1 , a first thin film transistor T 11 , a second thin film transistor T 12 , a first scan line G 11 , a second scan line G 12 , a first data line D 11 , and a second data line D 12 .
  • the drains of the first thin film transistor T 11 and the second thin film transistor T 12 are all connected to the pixel P 1 ; the gate of the first thin film transistor T 11 is connected to the first scan line G 11 , and the source is connected to the first data line D 11 The gate of the second thin film transistor T 12 is connected to the second scan line G 12 , and the source is connected to the second data line D 12 .
  • the power source (not shown) charges the pixel P 1 through the first data line D 11 ;
  • the second scan line G a second driving signal 12 is a thin film transistor T 12 open, the power supply (not shown) to the pixel P 12 via a second data line D 1 charge;
  • two or more charging process may be performed simultaneously, may be carried out separately, but also It can be done in a time-sharing manner.
  • the first data line D 11 and the second data line D 12 in FIG. 2 may also be the same data line, that is, D 1 in FIG. 3 .
  • the present embodiment provides a driving circuit including a plurality of scanning lines and a plurality of data lines vertically crossing each other, and dividing the plurality of scanning lines and the plurality of data lines into a plurality of pixel areas;
  • the pixel area includes one pixel and at least two thin film transistors, and a gate line and a source of each thin film transistor are respectively connected to one scan line and one data line, and a drain of each thin film transistor is connected to the pixel; wherein at least two thin film transistors are connected Charging the pixels separately when opening, can increase the charging time of the pixels, and improve the picture quality of the liquid crystal display.
  • a schematic structural diagram of a second embodiment of a driving circuit of the present invention includes a plurality of scanning lines and a plurality of data lines vertically intersecting each other, and is divided into a plurality of pixels by a plurality of scanning lines and a plurality of data lines. a region; each pixel region includes one pixel and at least two thin film transistors, and a gate line and a source of each thin film transistor are respectively connected to one scan line and one data line, and a drain of each thin film transistor is connected to the pixel; wherein at least two The pixels are charged separately when the thin film transistors are turned on.
  • the pixel area 400 of the first row and the first column will be described below:
  • the pixel region 400 includes a pixel P 1 , a first thin film transistor T 11 , a second thin film transistor T 12 , a scan line G 1 , a first data line D 11 , and a second data line D 12 .
  • the drains of the first thin film transistor T 11 and the second thin film transistor T 12 are connected to the pixel P 1 ; the gate of the first thin film transistor T 11 is connected to the scan line G 1 , and the source is connected to the first data line D 11 ; The gate of the second thin film transistor T 12 is connected to the scanning line G 2 of the second row, and the source is connected to the second data line D 12 .
  • the process of the drive signal driving the scan lines G 1 of the first thin film transistor T 11 is opened, the power supply (not shown) 11 pixel P D 1 is charged by a first data line; driving signal for driving the scanning line G 2
  • a power source (not shown) charges the pixel P 1 through the second data line D 12
  • a power source (not shown) passes through the first data line D 11 to the pixel P 2 .
  • Charging; the above two charging processes may be performed simultaneously, or separately, or may be performed by time sharing.
  • first data line D 11 and the second data line D 12 may be the same data line.
  • FIG. 5 a schematic flowchart of a first embodiment of a driving method of the present invention is applied to a driving circuit as shown in FIG. 2, and the method includes:
  • the T-2T, the first scan line G 11 a second input signal level to control the first thin film transistor T 11 closed, the second input of the first scan line G 12 level signal for controlling the second thin film transistor T 12 is opened, The pixel P 1 is charged through the second data line D 12 .
  • each scan signal lasts for T time, that is, the charging time of each pixel is 2T.
  • step S2 specifically includes:
  • each scanning signal lasts for 2T, that is, the charging time of each pixel is 3T.
  • FIG. 8 a schematic flowchart of a second embodiment of a driving method of the present invention is applied to a driving circuit as shown in FIG. 4, and the method includes:
  • the scanning lines G 1 a first input signal level to control the first thin film transistor T 11 is opened, the first data line D 11 to the pixel P 1 charge;
  • the T-2T, the scan lines G 1 a second input signal level to control the first thin film transistor T 11 is closed, the next row scan line G 2 a first input signal level to control a second thin film transistor T 12 is opened, by The second data line D 12 charges the pixel P 1 .
  • each scan signal lasts for T time, that is, the charging time of each pixel is 2T.
  • step M2 specifically includes:
  • each scan signal lasts for 2T, that is, the charging time of each pixel is 3T.
  • the present embodiment charges the pixels by time sharing by two data lines, so that the original charging time of each pixel is increased from T to 2T or even 3T, which greatly increases the charging time of the pixels and improves the picture of the liquid crystal display. quality.
  • a schematic structural diagram of an embodiment of a liquid crystal display according to the present invention includes a display panel 1110 and a backlight source 1120 .
  • the display panel 1110 includes a color filter substrate 1111, an array substrate 1112, and a liquid crystal layer 1113 between the color filter substrate 1111 and the array substrate 1112.
  • a driving circuit (not shown) is formed on the array substrate 1112.
  • the driving circuit is the driving circuit described in each of the above embodiments, and details are not described herein again.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

提供了一种驱动电路，该驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由所述多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接所述像素。其中，所述至少两个薄膜晶体管打开时分别对所述像素充电。通过上述方式增加像素的充电时间，提高了液晶显示的画面质量。还提供了一种该驱动电路的驱动方法以及一种包括该驱动电路的液晶显示器。

Description

一种驱动电路及其驱动方法、液晶显示器 【技术领域】
本发明涉及液晶显示领域，特别是涉及一种驱动电路及其驱动方法、液晶显示器。
【背景技术】
液晶显示器具有低辐射、低功耗以及体积小等特点，逐渐成为显示器件的主流，广泛应用在手机、笔记本电脑、平板电视等产品上。
图1为目前所常用的液晶面板的像素结构和驱动方式，一个子像素P1，通过一条扫描线G1驱动对应的一条数据线D1和子像素电极相连，当扫描信号逐级扫描时，每个子像素的TFT依次打开，通过数据线加入数据信号到子像素电极，实现图像的显示。
目前，液晶显示器正朝着大尺寸、高分辨率、高清晰度等方向发展，相应的，液晶面板的操作频率和像素分辨率不断提高，而随之带来的问题是，随着操作频率和面板分辨率的提高，液晶电容的充电时间急剧变短。例如，当液晶显示屏的分辨率提高到4K*2K甚至8K*4K以上，传统的60Hz扫描频率提高到120Hz、240Hz甚至480Hz以上时，液晶像素数据线输入数据信号的时间变得很短，只有目前的1/4、1/8甚至1/16，这时会存在着液晶像素充电不足的问题，影响画面显示的质量。
【发明内容】
本发明主要解决的技术问题是提供一种驱动电路及其驱动方法、液晶显示器，能够增加像素的充电时间，提高液晶显示的画面质量。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种驱动电路，用于液晶显示器，驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；第m行、第n列的像素区域包 括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、第一扫描线(Gm1)、第二扫描线(Gm2)、第一数据线(Dm1)及第二数据线(Dm2)；m、n均为自然数；第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接像素(Pm)；第一薄膜晶体管(Tm1)的栅极连接第一扫描线(Gm1)，源极连接第一数据线(Dm1)；第二薄膜晶体管(Tm2)的栅极连接第二扫描线(Gm2)，源极连接第二数据线(Dm2)；其中，第一扫描线(G11)的驱动信号驱动第一薄膜晶体管(T11)打开后，通过第一数据线(D11)对像素(P1)充电；第二扫描线(G12)的驱动信号驱动第二薄膜晶体管(T12)打开后，通过第二数据线(D12)对像素(P1)充电。
其中，第m行、第n列的像素区域包括像素Pm、第一薄膜晶体管Tm1、第二薄膜晶体管Tm2、扫描线Gm、第一数据线Dm1及第二数据线Dm2；其中，第一薄膜晶体管Tm1及第二薄膜晶体管Tm2的漏极均连接像素Pm；第一薄膜晶体管Tm1的栅极连接扫描线Gm，源极连接第一数据线Dm1；第二薄膜晶体管Tm2的栅极连接第m+1行的扫描线Gm+1，源极连接第二数据线Dm2。
其中，第一数据线Dm1及第二数据线Dm2为同一条数据线。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，该液晶显示器包括显示面板及背光光源，显示面板包括一驱动电路；驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素；其中，至少两个薄膜晶体管打开时分别对像素充电。
其中，第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、第一扫描线(Gm1)、第二扫描线(Gm2)、第一数据线(Dm1)及第二数据线(Dm2)；m、n均为自然数；其中，第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接像素(Pm)；第一薄膜晶体管(Tm1)的栅极连接第一扫描线(Gm1)，源极连接第一数据线(Dm1)；第二薄膜晶体管(Tm2) 的栅极连接第二扫描线(Gm2)，源极连接第二数据线(Dm2)。
其中，第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、扫描线(Gm)、第一数据线(Dm1)及第二数据线(Dm2)；其中，第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接像素(Pm)；第一薄膜晶体管(Tm1)的栅极连接扫描线(Gm)，源极连接第一数据线(Dm1)；第二薄膜晶体管(Tm2)的栅极连接第m+1行的扫描线(Gm+1)，源极连接第二数据线(Dm2)。
其中，第一数据线(Dm1)及第二数据线(Dm2)为同一条数据线。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种驱动方法，用于驱动电路，该驱动电路包括多个像素区域，每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素，其特征在于，驱动方法包括：每个像素区域的多个薄膜晶体管分时依次打开，以对像素连续充电。
其中，驱动电路的第m行、第n列的像素区域包括像素Pm、第一薄膜晶体管Tm1、第二薄膜晶体管Tm2、第一扫描线Gm1、第二扫描线Gm2、第一数据线Dm1及第二数据线Dm2，驱动方法包括：S1、在0-T时，第一扫描线Gm1输入第一电平信号以控制第一薄膜晶体管Tm1打开，通过第一数据线Dm1对像素Pm充电；S2、在T-2T时，第一扫描线Gm1输入第二电平信号控制第一薄膜晶体管Tm1关闭，第二扫描线Gm2输入第一电平信号控制第二薄膜晶体管Tm2打开，通过第二数据线Dm2对像素Pm充电；继续按照上述方法对所述驱动电路的其他行进行扫描。
其中，步骤S2具体包括：S21、在T-2T时，第一扫描线Gm1输入第一电平信号控制第一薄膜晶体管Tm1打开，第二扫描线Gm2输入第一电平信号控制第二薄膜晶体管Tm2打开，通过第一数据线Dm1和第二数据线Dm2同时对像素Pm充电；S22、在2T-3T时，第一扫描线Gm1输入第二电平信号控制第一薄膜晶体管Tm1关闭，第二扫描线Gm2输入第一电平信号控制第二薄膜晶体管Tm2打开，通 过第二数据线Dm2对像素Pm充电。
其中，驱动的第m行、第n列的像素区域包括像素Pm、第一薄膜晶体管Tm1、第二薄膜晶体管Tm2、扫描线Gm及第一数据线Dm1及第二数据线Dm2，驱动方法包括：M1、在0-T时，扫描线Gm输入第一电平信号控制第一薄膜晶体管Tm1打开，第一数据线Dm1对像素Pm充电；M2、在T-2T时，扫描线Gm输入第二电平信号控制第一薄膜晶体管Tm1关闭，下一行的扫描线Gm+1输入第一电平信号控制第二薄膜晶体管Tm2打开，通过第二数据线Dm2对像素Pm充电；继续按照上述方法对所述驱动电路的其他行进行扫描。
其中，步骤M2具体包括：M21、在T-2T时，扫描线Gm输入第一电平信号控制第一薄膜晶体管Tm1打开，下一行的扫描线Gm+1输入第一电平信号控制第二薄膜晶体管Tm2打开，通过第一数据线Dm1和第二数据线Dm2对像素Pm充电，同时，下一行开始扫描；M22、在2T-3T时，扫描线Gm输入第二电平信号控制第一薄膜晶体管Tm1关闭，下一行的扫描线Gm+1输入第一电平信号控制第二薄膜晶体管Tm2打开，通过第二数据线Dm2对像素Pm充电。
本发明的有益效果是：区别于现有技术的情况，本发明通过提供一种驱动电路，包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素；其中，至少两个薄膜晶体管打开时分别对像素充电，能够增加像素的充电时间，提高液晶显示的画面质量。
【附图说明】
图1是现有技术中液晶面板的像素结构和驱动方式；
图2是本发明驱动电路第一实施方式的结构示意图；
图3是本发明驱动电路第一实施方式的另一种结构示意图；
图4是本发明驱动电路第二实施方式的结构示意图；
图5是本发明驱动方法第一实施方式的流程示意图；
图6是本发明驱动方法第一实施方式中扫描线的第一波形图；
图7是本发明驱动方法第一实施方式中扫描线的第二波形图；
图8是本发明驱动方法第二实施方式的流程示意图；
图9是本发明驱动方法第二实施方式中扫描线的第一波形图；
图10是本发明驱动方法第二实施方式中扫描线的第二波形图；
图11是本发明液晶显示器一实施方式的结构示意图。
【具体实施方式】
参阅图2，本发明驱动电路第一实施方式的结构示意图，该驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素；其中，至少两个薄膜晶体管打开时分别对像素充电。
图2中示出的每个像素区域包括一个像素、两个薄膜晶体管、两条扫描线以及两条数据线，该图示仅为举例，并不限制本实施方式的保护范围，其中也可以增加薄膜晶体管、扫描线和数据线。
下面以第1行、第1列的像素区域200来说明：
像素区域200包括像素P1、第一薄膜晶体管T11、第二薄膜晶体管T12、第一扫描线G11、第二扫描线G12、第一数据线D11及第二数据线D12。
其中，第一薄膜晶体管T11及第二薄膜晶体管T12的漏极均连接像素P1；第一薄膜晶体管T11的栅极连接第一扫描线G11，源极连接第一数据线D11；第二薄膜晶体管T12的栅极连接第二扫描线G12，源极连接第二数据线D12。
在具体地实施过程中，第一扫描线G11的驱动信号驱动第一薄膜晶体管T11打开后，电源(图未示)通过第一数据线D11对像素P1充电；第二扫描线G12的驱动信号驱动第二薄膜晶体管T12打开后，电源(图未示)通过第二数据线 D12对像素P1充电；以上两个充电过程可以是同时进行，也可以是分别进行，也可以是分时交叉进行。
同时参阅图3，图2中的第一数据线D11及第二数据线D12也可以是同一条数据线，即图3中的D1。
区别于现有技术，本实施方式通过提供一种驱动电路，包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素；其中，至少两个薄膜晶体管打开时分别对像素充电，能够增加像素的充电时间，提高液晶显示的画面质量。
参阅图4，本发明驱动电路第二实施方式的结构示意图，该驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由多条扫描线及多条数据线分为多个像素区域；每个像素区域包括一个像素以及至少两个薄膜晶体管，每个薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个薄膜晶体管的漏极连接像素；其中，至少两个薄膜晶体管打开时分别对像素充电。
下面以第1行、第1列的像素区域400来说明：
像素区域400包括像素P1、第一薄膜晶体管T11、第二薄膜晶体管T12、扫描线G1、第一数据线D11及第二数据线D12。
其中，第一薄膜晶体管T11及第二薄膜晶体管T12的漏极均连接像素P1；第一薄膜晶体管T11的栅极连接扫描线G1，源极连接第一数据线D11；第二薄膜晶体管T12的栅极连接第2行的扫描线G2，源极连接第二数据线D12。
在具体地实施过程中扫描线G1的驱动信号驱动第一薄膜晶体管T11打开后，电源(图未示)通过第一数据线D11对像素P1充电；扫描线G2的驱动信号驱动第二薄膜晶体管T12打开后，电源(图未示)通过第二数据线D12对像素P1充电，与此同时，电源(图未示)还通过第一数据线D11对像素P2充电；以上两个充电过程可以是同时进行，也可以是分别进行，也可以是分时交叉进行。
另外，第一数据线D11及第二数据线D12也可以是同一条数据线。
参阅图5，本发明驱动方法第一实施方式的流程示意图，该方法应用于如图2所示的驱动电路，该方法包括：
S1、在0-T时，通过第一扫描线G11输入第一电平信号以控制第一薄膜晶体管T11打开，通过第一数据线D11对像素P1充电；
S2、在T-2T时，第一扫描线G11输入第二电平信号控制第一薄膜晶体管T11关闭，第二扫描线G12输入第一电平信号控制第二薄膜晶体管T12打开，通过第二数据线D12对像素P1充电。
继续按照上述方法对所述驱动电路的其他行进行扫描。
具体如图6所示，每个扫描信号持续T时间，即每个像素的充电时间为2T。
其中，步骤S2具体包括：
S21、在T-2T时，第一扫描线G11输入第一电平信号控制第一薄膜晶体管T11打开，第二扫描线G12输入第一电平信号控制第二薄膜晶体管T12打开，通过第一数据线D11和第二数据线D12同时对像素P1充电；
S22、在2T-3T时，第一扫描线G11输入第二电平信号控制第一薄膜晶体管T11关闭，第二扫描线G12输入第一电平信号控制第二薄膜晶体管T12打开，通过第二数据线D12对像素P1充电。
具体如图7所示，每个扫描信号持续2T时间，即每个像素的充电时间为3T。
参阅图8，本发明驱动方法第二实施方式的流程示意图，该方法应用于如图4所示的驱动电路，该方法包括：
M1、在0-T时，扫描线G1输入第一电平信号控制第一薄膜晶体管T11打开，第一数据线D11对像素P1充电；
M2、在T-2T时，扫描线G1输入第二电平信号控制第一薄膜晶体管T11关闭，下一行的扫描线G2输入第一电平信号控制第二薄膜晶体管T12打开，通过第二数据线D12对像素P1充电。
继续按照上述方法对所述驱动电路的其他行进行扫描。
具体如图9所示，每个扫描信号持续T时间，即每个像素的充电时间为2T。
其中，步骤M2具体包括：
M21、在T-2T时，扫描线G1输入第一电平信号控制第一薄膜晶体管T11打开，下一行的扫描线G2输入第一电平信号控制第二薄膜晶体管T12打开，通过第一数据线D11和第二数据线D12对像素P1充电，同时，下一行开始扫描；
M22、在2T-3T时，扫描线G1输入第二电平信号控制第一薄膜晶体管T11关闭，下一行的扫描线G2输入第一电平信号控制第二薄膜晶体管T12打开，通过第二数据线D12对像素P1充电，同时，下一行继续扫描。
具体如图10所示，每个扫描信号持续2T时间，即每个像素的充电时间为3T。
区别于现有技术，本实施方式通过两条数据线分时对像素充电，使每个像素原有的充时间从T增加到了2T甚至3T，大大的增加像素的充电时间，提高液晶显示的画面质量。
参阅图11，本发明液晶显示器一实施方式的结构示意图，该液晶显示器包括显示面板1110及背光光源1120。
其中，显示面板1110包括彩膜基板1111、阵列基板1112以及该彩膜基板1111和阵列基板1112之间的液晶层1113，驱动电路(图未示)形成于所述阵列基板1112上。
该驱动电路是如上各个实施方式所述的驱动电路，这里不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种驱动电路，用于液晶显示器，其特征在于，所述驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由所述多条扫描线及多条数据线分为多个像素区域；
    第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、第一扫描线(Gm1)、第二扫描线(Gm2)、第一数据线(Dm1)及第二数据线(Dm2)；m、n均为自然数；
    所述第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接所述像素(Pm)；
    所述第一薄膜晶体管(Tm1)的栅极连接所述第一扫描线(Gm1)，源极连接所述第一数据线(Dm1)；
    所述第二薄膜晶体管(Tm2)的栅极连接所述第二扫描线(Gm2)，源极连接所述第二数据线(Dm2)；
    其中，所述第一扫描线(G11)的驱动信号驱动所述第一薄膜晶体管(T11)打开后，通过所述第一数据线(D11)对所述像素(P1)充电；
    所述第二扫描线(G12)的驱动信号驱动所述第二薄膜晶体管(T12)打开后，通过所述第二数据线(D12)对所述像素(P1)充电。
  2. 根据权利要求1所述的驱动电路，其特征在于，第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、扫描线(Gm)、第一数据线(Dm1)及第二数据线(Dm2)；
    其中，所述第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接所述像素(Pm)；
    所述第一薄膜晶体管(Tm1)的栅极连接所述扫描线(Gm)，源极连接所述第一数据线(Dm1)；
    所述第二薄膜晶体管(Tm2)的栅极连接第m+1行的扫描线(Gm+1)，源极 连接所述第二数据线(Dm2)。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述第一数据线(Dm1)及第二数据线(Dm2)为同一条数据线。
  4. 一种液晶显示器，其特征在于，所述液晶显示器包括显示面板及背光光源，所述显示面板包括一驱动电路，所述驱动电路包括互相垂直交叉的多条扫描线及多条数据线，并由所述多条扫描线及多条数据线分为多个像素区域；
    每个所述像素区域包括一个像素以及至少两个薄膜晶体管，每个所述薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个所述薄膜晶体管的漏极连接所述像素；
    其中，所述至少两个薄膜晶体管打开时分别对所述像素充电。
  5. 根据权利要求4所述的驱动电路，其特征在于，第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、第一扫描线(Gm1)、第二扫描线(Gm2)、第一数据线(Dm1)及第二数据线(Dm2)；m、n均为自然数；
    其中，所述第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接所述像素(Pm)；
    所述第一薄膜晶体管(Tm1)的栅极连接所述第一扫描线(Gm1)，源极连接所述第一数据线(Dm1)；
    所述第二薄膜晶体管(Tm2)的栅极连接所述第二扫描线(Gm2)，源极连接所述第二数据线(Dm2)。
  6. 根据权利要求4所述的驱动电路，其特征在于，第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、扫描线(Gm)、第一数据线(Dm1)及第二数据线(Dm2)；
    其中，所述第一薄膜晶体管(Tm1)及第二薄膜晶体管(Tm2)的漏极均连接所述像素(Pm)；
    所述第一薄膜晶体管(Tm1)的栅极连接所述扫描线(Gm)，源极连接所述 第一数据线(Dm1)；
    所述第二薄膜晶体管(Tm2)的栅极连接第m+1行的扫描线(Gm+1)，源极连接所述第二数据线(Dm2)。
  7. 根据权利要求6所述的驱动电路，其特征在于，所述第一数据线(Dm1)及第二数据线(Dm2)为同一条数据线。
  8. 一种驱动方法，用于驱动电路，该驱动电路包括多个像素区域，每个所述像素区域包括一个像素以及至少两个薄膜晶体管，每个所述薄膜晶体管的栅极和源极分别连接一条扫描线及一条数据线，每个所述薄膜晶体管的漏极连接所述像素，其特征在于，所述驱动方法包括：
    每个所述像素区域的多个所述薄膜晶体管分时依次打开，以对所述像素连续充电。
  9. 根据权利要求8所述的驱动方法，用于驱动电路，所述驱动电路的第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、第一扫描线(Gm1)、第二扫描线(Gm2)、第一数据线(Dm1)及第二数据线(Dm2)，其特征在于，所述驱动方法包括：
    S1、在0-T时，第一扫描线(Gm1)输入第一电平信号以控制第一薄膜晶体管(Tm1)打开，通过所述第一数据线(Dm1)对像素(Pm)充电；
    S2、在T-2T时，第一扫描线(Gm1)输入第二电平信号控制第一薄膜晶体管(Tm1)关闭，第二扫描线(Gm2)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第二数据线(Dm2)对像素(Pm)充电；
    继续按照上述方法对所述驱动电路的其他行进行扫描。
  10. 根据权利要求9所述的驱动方法，其特征在于，所述步骤S2具体包括：
    S21、在T-2T时，第一扫描线(Gm1)输入第一电平信号控制第一薄膜晶体管(Tm1)打开，第二扫描线(Gm2)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第一数据线(Dm1)和第二数据线(Dm2)同时对像素(Pm)充电；
    S22、在2T-3T时，第一扫描线(Gm1)输入第二电平信号控制第一薄膜晶体管(Tm1)关闭，第二扫描线(Gm2)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第二数据线(Dm2)对像素(Pm)充电。
  11. 根据权利要求8所述的驱动方法，用于驱动电路，所述驱动的第m行、第n列的像素区域包括像素(Pm)、第一薄膜晶体管(Tm1)、第二薄膜晶体管(Tm2)、扫描线(Gm)及第一数据线(Dm1)及第二数据线(Dm2)，其特征在于，所述驱动方法包括：
    M1、在0-T时，扫描线(Gm)输入第一电平信号控制第一薄膜晶体管(Tm1)打开，第一数据线(Dm1)对像素(Pm)充电；
    M2、在T-2T时，扫描线(Gm)输入第二电平信号控制第一薄膜晶体管(Tm1)关闭，下一行的扫描线(Gm+1)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第二数据线(Dm2)对像素(Pm)充电；
    继续按照上述方法对所述驱动电路的其他行进行扫描。
  12. 根据权利要求11所述的驱动方法，其特征在于，所述步骤M2具体包括：
    M21、在T-2T时，扫描线(Gm)输入第一电平信号控制第一薄膜晶体管(Tm1)打开，下一行的扫描线(Gm+1)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第一数据线(Dm1)和第二数据线(Dm2)对像素(Pm)充电，同时，下一行开始扫描；
    M22、在2T-3T时，扫描线(Gm)输入第二电平信号控制第一薄膜晶体管(Tm1)关闭，下一行的扫描线(Gm+1)输入第一电平信号控制第二薄膜晶体管(Tm2)打开，通过所述第二数据线(Dm2)对像素(Pm)充电。
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