WO2017012165A1 - 用于窄边框lcd的goa电路结构 - Google Patents

用于窄边框lcd的goa电路结构 Download PDF

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WO2017012165A1
WO2017012165A1 PCT/CN2015/087727 CN2015087727W WO2017012165A1 WO 2017012165 A1 WO2017012165 A1 WO 2017012165A1 CN 2015087727 W CN2015087727 W CN 2015087727W WO 2017012165 A1 WO2017012165 A1 WO 2017012165A1
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metal layer
goa circuit
circuit structure
buffer unit
layer
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PCT/CN2015/087727
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English (en)
French (fr)
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李文英
郝思坤
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深圳市华星光电技术有限公司
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Priority to US14/778,610 priority Critical patent/US20170193942A1/en
Publication of WO2017012165A1 publication Critical patent/WO2017012165A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/13685—Top gates
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a GOA circuit structure for a narrow bezel LCD.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the GOA technology is an array substrate row driving technology, which is a driving method in which a gate driving circuit is fabricated on a TFT array substrate by an array process of a liquid crystal display panel to realize a gate-by-row scanning.
  • the GOA circuit has the advantages of being able to reduce the production cost and realize a narrow bezel design, and is suitable for a liquid crystal display.
  • the GOA circuit can be classified into an amorphous silicon (a-Si) GOA circuit, an Indium Gallium Zinc Oxide (IGZO) GOA circuit, and a low temperature polysilicon (Low Temperature).
  • a-Si amorphous silicon
  • IGZO Indium Gallium Zinc Oxide
  • Low Temperature Low Temperature
  • the width of the frame is one of the aesthetic elements, which is highly valued by LCD manufacturers. Many factors will Affecting the width of the border of the LCD, such as the frame material, cutting technology, machine precision, etc., in addition to the above factors, the width of the GOA circuit is also an important factor.
  • FIG. 1 shows the basic working principle of the GOA circuit.
  • the GOA circuit mainly has two basic functions: the first is to input a gate pulse function, drive a gate line in the panel, and open the TFT in the display area so that the data line can be opposite to the pixel. Charging is performed; the second is a shift register function, after the output of the nth scan pulse signal G(n) is completed, the output of the n+1th scan pulse signal G(n+1) can be controlled by the clock signal, and Pass on here.
  • FIG. 2 shows the basic block diagram of the GOA circuit in a CMOS process.
  • the GOA circuit is composed of four parts: a latch (Latch), a NAND gate (NAND), a buffer unit (Buffer), and a reset unit (Reset), and the latch is electrically connected to the NAND gate and the heavy
  • the unit is electrically connected to the latch and the buffer unit.
  • the reset signal is input to the reset unit, the input signal is input to the latch with the first clock signal, the second clock signal is input to the NAND gate, and the output signal is output from the buffer unit.
  • the buffer unit is an output stage, it is required to have a strong driving capability.
  • the size of the TFT in the buffer unit is large, which occupies a large layout space, which is disadvantageous for reducing the width of the LCD frame.
  • the buffer unit in the conventional GOA circuit includes a first metal layer 10, a second metal layer 20, and a first metal layer 10 and a second metal layer 20.
  • the two sides of the active layer 30 correspond to the source and the drain of the TFT, and the source and the drain of the TFT are respectively connected to the ion heavily doped region of the active layer 30 via a via 601. 301.
  • a region between the source and the drain of the active layer 30 corresponding to the TFT is the channel region 302. Since the existing buffer unit forms the gate of the TFT using only the first metal layer 10, the channel region 302 of the active layer 30 is located above the gate, and has a small thickness and a large impedance. In order to improve the driving capability of the buffer unit, It is generally necessary to increase the length of the channel region 302. Although this method increases the driving capability of the buffer unit, the width of the buffer unit also increases, and the width of the corresponding GOA circuit increases, which is disadvantageous for subtraction. The width of the small LCD frame.
  • An object of the present invention is to provide a GOA circuit structure for a narrow bezel LCD capable of reducing the size of a TFT in a buffer unit and the width of a buffer unit, thereby reducing the width of the GOA circuit such that the frame of the LCD is narrow.
  • the present invention provides a GOA circuit structure for a narrow bezel LCD.
  • the device includes: a latch, a NAND gate, a buffer unit, and a reset unit, wherein the latch is electrically connected to the NAND gate and the reset unit, and the NAND gate is electrically connected to the latch and the buffer unit
  • the input signal is input to the latch, and the output signal is output from the buffer unit;
  • the buffer unit includes a plurality of TFTs composed of a first metal layer, a second metal layer, and an active layer disposed between the first metal layer and the second metal layer; each TFT has a double gate.
  • the bottom gate is formed by a first metal layer, its source and drain are formed by a second metal layer, and its top gate is also formed by a second metal layer.
  • the source and the drain are respectively located at two sides of the bottom gate and the top gate; the region of the active layer corresponding to the source and the drain of the TFT is an ion heavily doped region, and the active layer corresponds to the TFT The area between the source and the drain is the channel area.
  • the source and the drain of the TFT are respectively connected to the ion heavily doped region of the active layer via a via.
  • a bottom gate insulating layer is further disposed between the first metal layer and the active layer, and a top gate insulating layer is further disposed between the active layer and the second metal layer; the via hole penetrates the top Gate insulation layer.
  • the material of the first metal layer is a stacked combination of one or more of molybdenum, titanium, aluminum, copper, and nickel.
  • the material of the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper, and nickel.
  • the material of the active layer is low temperature polysilicon.
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the present invention also provides a GOA circuit structure for a narrow bezel LCD, comprising: a latch, a NAND gate, a buffer unit, and a reset unit, the latch electrically connected to the NAND gate and the reset unit
  • the NAND gate is connected to the latch and the buffer unit; the input signal is input to the latch, and the output signal is output from the buffer unit;
  • the buffer unit includes a plurality of TFTs composed of a first metal layer, a second metal layer, and an active layer disposed between the first metal layer and the second metal layer; each TFT has a double gate.
  • the bottom gate is formed by a first metal layer, the source and the drain thereof are formed by the second metal layer, and the top gate thereof is also formed by the second metal layer;
  • the material of the first metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper, nickel;
  • the material of the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper, nickel;
  • the material of the active layer is low temperature polysilicon.
  • the present invention provides a GOA circuit junction for a narrow bezel LCD
  • the TFT in the buffer unit is provided with a bottom gate formed by the first metal layer under the channel region of the active layer, and a top portion formed by the second metal layer above the channel region of the active layer.
  • the gate electrode, the channel region of the active layer has a thicker thickness and a smaller impedance, which significantly increases the driving capability of the TFT in the buffer unit, and the size of the TFT in the buffer unit is reduced under the same driving capability, thereby
  • the width of the buffer unit is reduced and the width of the GOA circuit is reduced, so that the border of the LCD can be made narrower.
  • FIG. 1 is a schematic diagram of the basic working principle of the GOA circuit
  • FIG. 2 is a block diagram showing the basic structure of a GOA circuit in a CMOS process
  • FIG. 3 is a top plan view of a buffer unit in a conventional GOA circuit
  • Figure 4 is a cross-sectional structural view corresponding to A-A in Figure 3;
  • FIG. 5 is a top plan view showing the structure of a GOA circuit for a narrow bezel LCD according to the present invention.
  • Fig. 6 is a schematic cross-sectional view corresponding to the position B-B in Fig. 5.
  • the present invention provides a GOA circuit structure for a narrow bezel LCD.
  • the GOA circuit structure of the present invention also includes: a latch, a NAND gate, a buffer unit, and a reset unit, wherein the latch is electrically connected to the NAND gate and a reset unit, the NAND gate is connected to the latch and the buffer unit; the input signal and the first clock signal are input to the latch, the second clock signal is input to the NAND gate, and the output signal is output from the buffer unit.
  • the buffer unit includes a plurality of TFTs composed of a first metal layer 1, a second metal layer 2, and an active layer 3 disposed between the first metal layer 1 and the second metal layer 2; There is a double gate, the bottom gate is formed by the first metal layer 1, the source and the drain are formed by the second metal layer 2, and the top gate is also formed by the second metal layer 2.
  • the source and the drain are respectively located at two sides of the bottom gate and the top gate; the active The region of the layer 3 corresponding to the source and the drain of the TFT is the ion heavily doped region 31, and the region between the source and the drain of the active layer 3 corresponding to the TFT is the channel region 32.
  • a bottom gate insulating layer 5 is further disposed between the first metal layer 1 and the active layer 3, and a top gate insulating layer 6 is further disposed between the active layer 3 and the second metal layer 2.
  • the source and the drain of the TFT are respectively connected to the ion heavily doped region 31 of the active layer 3 via a via 61 penetrating through the top gate insulating layer 6.
  • the material of the first metal layer 1 is a stack combination of one or more of molybdenum, titanium, aluminum, copper, and nickel.
  • the material of the second metal layer 2 is a stack combination of one or more of molybdenum, titanium, aluminum, copper, and nickel.
  • the material of the active layer 3 is low temperature polysilicon.
  • the material of the bottom gate insulating layer 5 and the top gate insulating layer 6 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
  • the TFT in the buffer unit is provided with a bottom gate formed of a first metal layer under the channel region 32 of the active layer 3, a second metal is provided above the channel region 32 of the active layer 3.
  • the top gate formed by layer 2, the channel region 32 of the active layer 3 has a thicker thickness and a smaller impedance, which significantly increases the driving ability of the TFT in the buffer unit, and the TFT in the buffer unit under the same driving capability.
  • the size of the buffer unit is reduced, so that the width of the buffer unit is reduced, and the width of the GOA circuit is reduced, so that the frame of the LCD can be made narrower, for example, under the same driving capability, the buffer unit in the existing GOA circuit
  • the width is about 300 ⁇ m, and the width of the buffer unit in the GOA circuit structure of the present invention is reduced to about 150 ⁇ m.
  • the GOA circuit structure of the present invention reduces the width of the GOA circuit and the frame width of the LCD by about 150 ⁇ m. .
  • the TFT in the buffer unit is provided with a bottom gate formed by the first metal layer under the channel region of the active layer, and is active.
  • a top gate formed by the second metal layer is disposed above the channel region of the layer, and the channel region of the active layer has a thicker thickness and a smaller impedance, which significantly increases the driving capability of the TFT in the buffer unit, in the same
  • the size of the TFT in the buffer unit is reduced, so that the width of the buffer unit is reduced, and the width of the GOA circuit is reduced, so that the frame of the LCD can be made narrower.

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Abstract

一种用于窄边框LCD的GOA电路结构，包括：锁存器、与非门、缓冲器单元、以及重置单元；输入信号输入锁存器，输出信号自缓冲器单元输出；该缓冲器单元包括由第一金属层(1)、第二金属层(2)、及设于第一金属层(1)与第二金属层(2)之间的有源层(3)构成的多个TFT；每一TFT均具有双栅极，其底栅极由第一金属层(1)形成，其源极与漏极由第二金属层(2)形成，其顶栅极也由第二金属层(2)形成，能够减小缓冲器单元中TFT的尺寸以及缓冲器单元的宽度，从而减小GOA电路的宽度，使得LCD的边框较窄。

Description

用于窄边框LCD的GOA电路结构 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种用于窄边框LCD的GOA电路结构。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是利用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA电路具有能够降低生产成本和实现窄边框设计的优点，适用于液晶显示器。
根据使用的有源层材料的不同，GOA电路可以分为非晶硅(Amorphous silicon，a-Si)GOA电路、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)GOA电路、低温多晶硅(Low Temperature Ploy Silicon，LTPS)GOA电路等，每种GOA电路又可以使用不同的制程。LTPS由于具有高电子迁移率和技术成熟的优点，目前被中小尺寸LCD中的GOA电路广泛使用。
随着显示技术的发展，人们对LCD的美观提出了更高的要求，边框的宽度作为审美的要素之一，受到各LCD生产商的高度重视。多种因素都会 影响LCD的边框宽度，如框胶材料、切割技术、机台精度等，除上述因素外，GOA电路的宽度也是重要的影响因素之一。
图1所示为GOA电路的基本工作原理示意图。GOA电路主要具有两项基本功能：第一是输入扫描脉冲信号(Gate pulse)功能，驱动面板内的扫描线(Gate line)，打开显示区内的TFT，使得数据线(Data line)能够对像素进行充电；第二是移位寄存功能，当第n个扫描脉冲信号G(n)输出完成后，可以通过时钟信号控制进行第n+1个扫描脉冲信号G(n+1)的输出，并依此传递下去。
图2所示为CMOS制程下GOA电路的基本结构框图。该GOA电路由四部分组成:锁存器(Latch)、与非门(NAND)、缓冲器单元(Buffer)、以及重置单元(Reset)，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元。重置信号输入重置单元，输入信号与第一时钟信号输入锁存器，第二时钟信号输入与非门，输出信号自缓冲器单元输出。由于缓冲器单元为输出级，需要具有很强的驱动能力，通常缓冲器单元内TFT的尺寸很大，占用很大的布局空间，不利于减小LCD边框的宽度。
请同时参阅图3与图4，现有的GOA电路中的缓冲器单元包括由第一金属层10、第二金属层20、及设于第一金属层10与第二金属层20之间的有源层30构成的多个TFT；每一TFT的栅极由第一金属层10形成，每一TFT的源极与漏极由第二金属层20形成，源极与漏极分别位于栅极的两侧；有源层30对应TFT的源极与漏极的区域为离子重掺杂区域301，TFT的源极与漏极分别经由一过孔601连接有源层30的离子重掺杂区域301，有源层30对应TFT的源极与漏极之间的区域为沟道区域302。由于该现有的缓冲器单元仅使用第一金属层10形成TFT的栅极，有源层30的沟道区域302位于栅极上方，厚度薄、阻抗大，为了提升缓冲器单元的驱动能力，通常需要把沟道区域302的长度增长，该种方法虽然增大了缓冲器单元的驱动能力，但是缓冲器单元的宽度也会随之增大，相应的GOA电路的宽度增大，不利于减小LCD边框的宽度。
发明内容
本发明的目的在于提供一种用于窄边框LCD的GOA电路结构，能够减小缓冲器单元中TFT的尺寸以及缓冲器单元的宽度，从而减小GOA电路的宽度，使得LCD的边框较窄。
为实现上述目的，本发明提供一种用于窄边框LCD的GOA电路结构， 包括：锁存器、与非门、缓冲器单元、以及重置单元，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元；输入信号输入锁存器，输出信号自缓冲器单元输出；
所述缓冲器单元包括由第一金属层、第二金属层、及设于第一金属层与第二金属层之间的有源层构成的多个TFT；每一TFT均具有双栅极，其底栅极由第一金属层形成，其源极与漏极由第二金属层形成，其顶栅极也由第二金属层形成。
所述源极、漏极分别位于底栅极及顶栅极的两侧；所述有源层对应TFT的源极、漏极的区域为离子重掺杂区域，所述有源层对应TFT的源极与漏极之间的区域为沟道区域。
TFT的源极与漏极分别经由一过孔连接有源层的离子重掺杂区域。
在所述第一金属层与有源层之间还设有底栅极绝缘层，在有源层与第二金属层之间还设有顶栅极绝缘层；所述过孔贯穿所述顶栅极绝缘层。
所述第一金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
所述第二金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
所述有源层的材料为低温多晶硅。
所述底栅极绝缘层与顶栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
本发明还提供一种用于窄边框LCD的GOA电路结构，包括：锁存器、与非门、缓冲器单元、以及重置单元，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元；输入信号输入锁存器，输出信号自缓冲器单元输出；
所述缓冲器单元包括由第一金属层、第二金属层、及设于第一金属层与第二金属层之间的有源层构成的多个TFT；每一TFT均具有双栅极，其底栅极由第一金属层形成，其源极与漏极由第二金属层形成，其顶栅极也由第二金属层形成；
其中，所述第一金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合；
其中，所述第二金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合；
其中，所述有源层的材料为低温多晶硅。
本发明的有益效果：本发明提供一种用于窄边框LCD的GOA电路结 构，其缓冲器单元中的TFT在有源层的沟道区域下方设有由第一金属层形成的底栅极，在有源层的沟道区域上方设有由第二金属层形成的顶栅极，有源层的沟道区域厚度较厚、阻抗较小，显著增加了缓冲器单元中的TFT的驱动能力，在相同的驱动能力下，缓冲器单元中TFT的尺寸得以减小，从而缓冲器单元的宽度减小，GOA电路的宽度减小，使得LCD的边框可以做的更窄。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为GOA电路的基本工作原理示意图；
图2为CMOS制程下GOA电路的基本结构框图；
图3为现有GOA电路中的缓冲器单元的平面俯视示意图；
图4为对应于图3中A-A处的剖面结构示意图；
图5为本发明用于窄边框LCD的GOA电路结构的平面俯视示意图；
图6为对应于图5中B-B处的剖面结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种用于窄边框LCD的GOA电路结构。请参阅图2、图5、与图6，本发明的GOA电路结构同样包括：锁存器、与非门、缓冲器单元、以及重置单元，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元；输入信号与第一时钟信号输入锁存器，第二时钟信号输入与非门，输出信号自缓冲器单元输出。
所述缓冲器单元包括由第一金属层1、第二金属层2、及设于第一金属层1与第二金属层2之间的有源层3构成的多个TFT；每一TFT均具有双栅极，其底栅极由第一金属层1形成，其源极与漏极由第二金属层2形成，其顶栅极也由第二金属层2形成。
具体地，所述源极、漏极分别位于底栅极及顶栅极的两侧；所述有源 层3对应TFT的源极、漏极的区域为离子重掺杂区域31，所述有源层3对应TFT的源极与漏极之间的区域为沟道区域32。
在所述第一金属层1与有源层3之间还设有底栅极绝缘层5，在有源层3与第二金属层2之间还设有顶栅极绝缘层6。TFT的源极与漏极分别经由一贯穿所述顶栅极绝缘层6的过孔61连接有源层3的离子重掺杂区域31。
所述第一金属层1的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
所述第二金属层2的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
所述有源层3的材料为低温多晶硅。
所述底栅极绝缘层5与顶栅极绝缘层6的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
由于上述缓冲器单元中的TFT在有源层3的沟道区域32下方设有由第一金属1层形成的底栅极，在有源层3的沟道区域32上方设有由第二金属层2形成的顶栅极，有源层3的沟道区域32厚度较厚、阻抗较小，显著增加了缓冲器单元中的TFT的驱动能力，在相同的驱动能力下，缓冲器单元中TFT的尺寸得以减小，从而缓冲器单元的宽度减小，GOA电路的宽度减小，使得LCD的边框可以做的更窄，例如在相同的驱动能力下，现有GOA电路中的缓冲器单元的宽度为300μm左右，而本发明GOA电路结构中的缓冲器单元的宽度下降为150μm左右，相比于现有技术，本发明的GOA电路结构使得GOA电路的宽度及LCD的边框宽度减小150μm左右。
综上所述，本发明的用于窄边框LCD的GOA电路结构，其缓冲器单元中的TFT在有源层的沟道区域下方设有由第一金属层形成的底栅极，在有源层的沟道区域上方设有由第二金属层形成的顶栅极，有源层的沟道区域厚度较厚、阻抗较小，显著增加了缓冲器单元中的TFT的驱动能力，在相同的驱动能力下，缓冲器单元中TFT的尺寸得以减小，从而缓冲器单元的宽度减小，GOA电路的宽度减小，使得LCD的边框可以做的更窄。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种用于窄边框LCD的GOA电路结构，包括：锁存器、与非门、缓冲器单元、以及重置单元，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元；输入信号输入锁存器，输出信号自缓冲器单元输出；
    所述缓冲器单元包括由第一金属层、第二金属层、及设于第一金属层与第二金属层之间的有源层构成的多个TFT；每一TFT均具有双栅极，其底栅极由第一金属层形成，其源极与漏极由第二金属层形成，其顶栅极也由第二金属层形成。
  2. 如权利要求1所述的用于窄边框LCD的GOA电路结构，其中，所述源极、漏极分别位于底栅极及顶栅极的两侧；所述有源层对应TFT的源极、漏极的区域为离子重掺杂区域，所述有源层对应TFT的源极与漏极之间的区域为沟道区域。
  3. 如权利要求2所述的用于窄边框LCD的GOA电路结构，其中，TFT的源极与漏极分别经由一过孔连接有源层的离子重掺杂区域。
  4. 如权利要求3所述的用于窄边框LCD的GOA电路结构，其中，在所述第一金属层与有源层之间还设有底栅极绝缘层，在有源层与第二金属层之间还设有顶栅极绝缘层；所述过孔贯穿所述顶栅极绝缘层。
  5. 如权利要求1所述的用于窄边框LCD的GOA电路结构，其中，所述第一金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
  6. 如权利要求1所述的用于窄边框LCD的GOA电路结构，其中，所述第二金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合。
  7. 如权利要求1所述的用于窄边框LCD的GOA电路结构，其中，所述有源层的材料为低温多晶硅。
  8. 如权利要求4所述的用于窄边框LCD的GOA电路结构，其中，所述底栅极绝缘层与顶栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
  9. 一种用于窄边框LCD的GOA电路结构，包括：锁存器、与非门、缓冲器单元、以及重置单元，所述锁存器电性连接与非门及重置单元，所述与非门电性连接锁存器及缓冲器单元；输入信号输入锁存器，输出信号自缓冲器单元输出；
    所述缓冲器单元包括由第一金属层、第二金属层、及设于第一金属层与第二金属层之间的有源层构成的多个TFT；每一TFT均具有双栅极，其 底栅极由第一金属层形成，其源极与漏极由第二金属层形成，其顶栅极也由第二金属层形成；
    其中，所述第一金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合；
    其中，所述第二金属层的材料为钼、钛、铝、铜、镍中的一种或多种的堆栈组合；
    其中，所述有源层的材料为低温多晶硅。
  10. 如权利要求9所述的用于窄边框LCD的GOA电路结构，其中，所述源极、漏极分别位于底栅极及顶栅极的两侧；所述有源层对应TFT的源极、漏极的区域为离子重掺杂区域，所述有源层对应TFT的源极与漏极之间的区域为沟道区域。
  11. 如权利要求10所述的用于窄边框LCD的GOA电路结构，其中，TFT的源极与漏极分别经由一过孔连接有源层的离子重掺杂区域。
  12. 如权利要求11所述的用于窄边框LCD的GOA电路结构，其中，在所述第一金属层与有源层之间还设有底栅极绝缘层，在有源层与第二金属层之间还设有顶栅极绝缘层；所述过孔贯穿所述顶栅极绝缘层。
  13. 如权利要求12所述的用于窄边框LCD的GOA电路结构，其中，所述底栅极绝缘层与顶栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
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