WO2010127515A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2010127515A1
WO2010127515A1 PCT/CN2009/072487 CN2009072487W WO2010127515A1 WO 2010127515 A1 WO2010127515 A1 WO 2010127515A1 CN 2009072487 W CN2009072487 W CN 2009072487W WO 2010127515 A1 WO2010127515 A1 WO 2010127515A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
common electrode
thin film
display panel
film transistor
Prior art date
Application number
PCT/CN2009/072487
Other languages
English (en)
French (fr)
Inventor
柳智忠
陈政欣
Original Assignee
深超光电（深圳）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深超光电（深圳）有限公司 filed Critical 深超光电（深圳）有限公司
Priority to US12/869,723 priority Critical patent/US8223286B2/en
Publication of WO2010127515A1 publication Critical patent/WO2010127515A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to a display panel, and more particularly to a display panel of high display quality. ⁇ Background technique ⁇
  • each pixel of a single gate circuit structure has a thin film transistor (TFT) 10 whose gate is connected to a horizontal scanning line 12, a source Connected to the data line 14 in the vertical direction, the drain is connected to the pixel electrode, and the thin film transistors 10 in the adjacent row have the data lines 14 connected to each other.
  • TFT thin film transistor
  • the above single-gate circuit architecture has a relatively high cost for the source chip because the number of data lines 14 is too large, and in order to reduce the cost consumption, the latter technology proposes a dual-gate circuit architecture. As shown in FIG. 2, the adjacent two rows of thin film transistors 16 share the same data line 18, so that the number of data lines 18 used can be reduced, thereby reducing the manufacturing cost of the source chip.
  • the scan line 20 and the common electrode line 22 belong to the same metal layer, and are closely spaced, so During the process, if particles accidentally fall into the panel, it is easy to cause a short circuit between the scan line 20 and the common electrode line 22 after the process is completed, thereby causing a problem that the panel display has a dark line or a bright line.
  • the two electrode layers 24 of the adjacent scan line 20 and the adjacent data line 18 are pixel display areas of two pixels, respectively, and the common electrode line 22 occupies the area of the light-transmitting area of the electrode layer 24, The portion of the light-transmitting region where the electrode layer 24 is deducted from the metal layer forming the common electrode line 22 is reduced, and the aperture ratio of the entire panel is lost.
  • the present invention has been made in view of the above problems, and has proposed a display panel of high display quality to solve the problems caused by the prior art.
  • a main object of the present invention is to provide a display panel that has a common electrode line disposed between adjacent scan lines to reduce the number of common electrode lines, thereby increasing the pixel aperture ratio of the panel and reducing the scan line and The probability of a short circuit occurring in the common electrode line.
  • the present invention provides a display panel comprising a plurality of parallel scan lines and a plurality of parallel data lines, wherein the scan lines include a first scan line and a second scan line, and the data lines and the scan lines are perpendicular to each other.
  • the display panel further includes a plurality of double-gate pixel units connected to each other by a data line, a scan line, and a common electrode line, and each of the double-gate pixel units is connected with one data line and two scan lines and a common electrode line, each of the double-gate pixel units includes a first pixel and a second pixel, the first pixel is connected to the first scan line, the first common electrode line and the first data line, and the second pixel is connected to the second scan line a first common electrode line and a first data line, wherein the first and second pixels are located on opposite sides of the first scan line and the second scan line, and the first data line and the first common electrode line are respectively And transmitting the data signal and the first common electrode signal to the first pixel and the second
  • 1 and 2 are circuit diagrams of a display panel of the prior art.
  • FIG. 3 is a schematic diagram showing the circuit layout structure of a display panel of the prior art.
  • FIG. 4 is a circuit diagram of a liquid crystal display panel of the present invention.
  • FIG. 5 is a schematic circuit diagram of a dual gate pixel unit of the present invention.
  • FIG. 6 is a schematic view showing the circuit layout structure of a first embodiment of a liquid crystal display panel of the present invention.
  • Fig. 7 is a partially enlarged schematic view showing the circuit layout structure of the first embodiment of the liquid crystal display panel of the present invention.
  • Figure 8 is a cross-sectional view showing the structure along the line A-A in the circuit layout structure of Figure 7;
  • FIG. 9 is a schematic view showing the circuit layout structure of a second embodiment of the liquid crystal display panel of the present invention.
  • Figure 10 is a partially enlarged schematic view showing the circuit layout structure of a second embodiment of the liquid crystal display panel of the present invention.
  • the main design of the present invention is to place common electrode lines between adjacent scan lines, see Figure 4 below.
  • the equivalent circuit of the liquid crystal display panel of the present invention comprises a plurality of parallel scan lines 26 and a plurality of parallel data lines 28, and the scan lines 26 include first scan lines 262 and second scan lines 264, data lines 28 and scan lines. 26 is perpendicular to each other, and the data line 28 includes a first data line 282, the scan line 26 and the plurality of common electrode lines 30 are parallel to each other, and the common electrode line 30 includes a first common electrode line 302.
  • the liquid crystal display panel of the present invention further includes a plurality of double-gate pixel units 32 arranged in a matrix, and is formed by connecting the data lines 28, the scan lines 26 and the common electrode lines 30 to each other, and each double-gate pixel unit 32 is connected.
  • the double-gate pixel unit 32 of the same row will share the same data line 28, and the dual-gate pixel unit 32 of the same column will share The same scanning line 26 and common electrode line 30 are shared.
  • the connection relationship and the positional relationship of the components in each of the dual-gate pixel units 32 are the same, and one dual-gate pixel unit 32 is taken as an example, and the first and second scan lines 262, 264 and the first data line 282 are used.
  • the connection and positional relationship between the first common electrode line 302 and the dual gate pixel unit 32 are as follows.
  • each of the dual-gate pixel units 32 includes first and second pixels 34 and 36
  • the first pixel 34 includes a first thin film transistor 342 and a correspondingly connected first liquid crystal capacitor 346, and the first storage.
  • the second pixel 36 includes a second thin film transistor 362 and a corresponding second liquid crystal capacitor 366 and a second storage capacitor 364, and the first and second pixels 34 and 36 are respectively disposed on the first scan line 262 and the second
  • the first scanning line 262 and the second scanning line 264 are disposed on opposite sides of the first common electrode line 302, and the first and second pixels 34 and 36 are disposed on the first data line.
  • the first thin film transistor 342 has a gate connected to the first scan line 262, a source connected to the first data line 282, a drain connected to the first liquid crystal capacitor 346 and one end of the first storage capacitor 344, and the first liquid crystal capacitor 346 One end is connected to the common electrode of the color filter (CF) end to receive the first common electrode signal, and the other end of the first storage capacitor 344 is connected to the first common electrode line 302, and the first data line 282 and the first common electrode line 302 are respectively Transmitting the data signal and the second common electrode signal to the first thin film transistor 342, and the first scan line 262 controls the first thin film transistor 342 to receive the data signal, thereby controlling charging and discharging of the first liquid crystal capacitor 346, and the first storage capacitor 344 is used to maintain a potential difference across the first liquid crystal capacitor 346 to prevent leakage of the first liquid crystal capacitor 346.
  • CF color filter
  • the gate of the second thin film transistor 362 is connected to the second scan line 264, the source thereof is connected to the first data line 282, and the drain thereof is connected to one end of the second liquid crystal capacitor 366 and the second storage capacitor 364, and the second liquid crystal capacitor is connected.
  • the other end of the 366 is connected to the common electrode of the color filter end to receive the first common electrode signal, and the other end of the second storage capacitor 364 is connected to the first common electrode line 302.
  • the first data line 282 and the first common electrode line 302 are respectively Transmitting the data signal and the second common electrode signal to the second thin film transistor 362, and the second scan line 264 controls the second thin film transistor 362 to receive the data signal, and further The charging and discharging of the second liquid crystal capacitor 366 is controlled, and the second storage capacitor 364 is used to maintain the potential difference between the two liquid crystal capacitors 366 to prevent the second liquid crystal capacitor 366 from leaking.
  • each common electrode line 30 and the data line 28 respectively transmit a first common electrode signal and a data signal to the connected storage capacitor 42 and the thin film transistor 38.
  • each of the liquid crystal capacitors 40 receives the first common electrode signal.
  • the thin film transistor 38 of each row is sequentially controlled by the scan line 26 to receive the data signal, thereby controlling the charging and discharging of the liquid crystal capacitor 40, and the storage capacitor 42 connected to the liquid crystal capacitor 40 is used to maintain the liquid crystal capacitor 40 at both ends. Potential difference.
  • FIG. 6 is a unit of the pixel electrode structure in the dashed box, and uses a gate line 48, a data line 50, and a common electrode line.
  • the pixel electrode structures are arranged in a matrix on the display panel, the pixel electrode structures of the same row share the same data line 50, and the pixel electrode structures of the same column share the same scan line 48 and the common electrode line 52.
  • the connection relationship and positional relationship of the components in each of the pixel electrode structures are the same, and a pixel electrode structure is taken as an example, as follows.
  • FIG. 8 is a cross-sectional view along line AA of the circuit layout structure of FIG. 7 , which can express the upper and lower stacks of the components included in FIG. 7 .
  • Department. 7 is a pixel electrode structure, which mainly includes a transparent substrate 54, a first array pixel and a second array pixel, and the first and second array pixels respectively form first and second thin film transistors 44, 46, first and second pixels. Electrodes 67, 69, and first and second scan lines 76, 78.
  • the first and second array pixels are formed by the first metal layer 56, the insulating layer 58, the semiconductor layer 60, the second metal layer 62, the protective layer 64, and the electrode layer 66, and the liquid crystal layer is disposed on the electrode layer 66.
  • the protective layer 64 is made of an insulating material, and the material of the insulating layer 58 is silicon nitride.
  • the material of the electrode layer 66 is indium tin oxide (ITO), and the electrode layer 66 is formed separately from the first and second thin film transistors 44 and 46 respectively.
  • the first and second pixel electrodes 67, 69 are connected.
  • the first metal layer 56 is disposed on the transparent substrate 54 to form the gate 72 of the first thin film transistor 44, the gate 74 of the second thin film transistor 46, the first scan line 76, the second scan line 78, and the first scan.
  • the gates 72, 74 of the transistors 44, 46 are formed as a continuous line.
  • the first metal layer 56 is formed with an insulating layer 58 formed thereon, and the insulating layer 58 is used as a gate insulating layer on the two thin film transistors 44, 46.
  • the insulating layer 58 is provided with a semiconductor layer 60.
  • the semiconductor layer 60 is divided into upper and lower layers, and the lower layer is an amorphous silicon layer (a-Si) 68, which is directly disposed on the insulating layer 58, and the upper layer is n + doped.
  • An ohmic contact layer 70 of amorphous silicon (n+ a-Si), a second metal layer 62 is disposed on the ohmic contact layer 70 and the insulating layer 58 to form sources 82, 84 of the first and second thin film transistors 44, 46.
  • the drain electrodes 86, 88 and the data line 90, the data line 90 are connected to the sources 82, 84 of the first and second thin film transistors 44, 46, and the first and second thin film transistors 44, 46 are located on the data line 90.
  • the first and second thin film transistors 44 and 46 are respectively located on opposite sides of the first and second scan lines 76 and 78, and the sources 82, 84 and the drains of the first and second thin film transistors 44 and 46 are respectively 86, 88 are respectively located above the gates 72, 74 of the first and second thin film transistors 44, 46, and the amorphous silicon layer 68 and the ohmic contact layer 70 are located at the source 82 of the first and second thin film transistors 44, 46, respectively.
  • the data line 90 intersects the common electrode line 80, the first and second scan lines 76, 78 perpendicularly.
  • the first pixel electrode 67 is disposed under the first scan line 76 and overlaps the common
  • the electrode electrode line 80 and the second scan line 78 have an overlapping area of the first pixel electrode 67 and the second scan line 78 that is smaller than an overlapping area of the first pixel electrode 67 and the common electrode line 80.
  • the second pixel electrode 69 is disposed above the second scan line 78 and overlaps the common electrode line 80 and the first scan line 76.
  • the overlap area of the second pixel electrode 69 and the first scan line 76 is smaller than that of the second pixel electrode 69.
  • the overlapping area of the common electrode lines 80 is disposed under the first scan line 76 and overlaps the common
  • the electrode electrode line 80 and the second scan line 78 have an overlapping area of the first pixel electrode 67 and the second scan line 78 that is smaller than an overlapping area of the first pixel electrode 67 and the common electrode line 80.
  • the second pixel electrode 69 is disposed above the second scan line 78 and overlaps the
  • the ohmic contact layer 70 and the second metal layer 62 are covered with a protective layer 64 having via holes 92 respectively located above the drain electrodes 86, 88 of the first and second thin film transistors 44, 46 and the semiconductor layer 60.
  • the through hole 92 is a portion where the protective layer 64 in the cross-sectional view of FIG. 8 is not connected, and when the protective layer 64 etches the through hole 92, the through hole 92 is not transmitted through the semiconductor layer 60 and continues to etch the insulating layer 58. The depth can only reach the semiconductor layer 60.
  • An electrode layer 66 is disposed on the protective layer 64, and the electrode layer 66 is in contact with the drains 86, 88 of the corresponding first and second thin film transistors 44, 46 and the semiconductor layer 60 through the via 92.
  • the second metal layer 62 as the drain electrode 86 and the semiconductor layer 60 are exposed due to the via holes, and thus can be in contact with the electrode layer 66.
  • the electrode layer 66 has through holes 94 on the first and second scan lines 76, 78, respectively.
  • a portion of the drain electrode 86 of the first thin film transistor 44 extends toward the common electrode line 80, and a portion overlapping the common electrode line 80 and the electrode layer 66 is a storage capacitor of the first thin film transistor 44; a drain of the second thin film transistor 46
  • a portion of the pole 88 extending toward the common electrode line 80 and overlapping the common electrode line 80 and the electrode layer 66 is a storage capacitor of the second thin film transistor 46.
  • the electrode layer 66 of this embodiment does not overlap with the first and second scanning lines 76, 78 on the drain electrodes 86, 88 side of the first and second thin film transistors 44, 46, so that each thin film transistor is connected.
  • a shading such as a black matrix (BM)
  • BM black matrix
  • the liquid crystal display panel manufactured by using the above circuit layout can be compared with the prior art FIG. 3 as shown in FIG. 6.
  • the two electrode layers 66 of the adjacent scan line 48 and the adjacent data line 50 are respectively two.
  • the pixel display area of the pixel, under the design of the present invention, the common electrode line 52 does not encroach on the area of the light-transmitting area of the electrode layer 66, and in addition to the same number of transistors, the common electrode line 52 used in FIG.
  • the number is smaller than that of FIG. 3, which is the same as the comparison of the equivalent circuit diagram of FIG. 4.
  • the design can increase the aperture ratio of the pixel, and at the same time, the number of common electrode lines is reduced, thereby reducing the scan line and The probability of a short circuit occurring in the common electrode line.
  • the second embodiment of the circuit layout of FIG. 9 and FIG. 10 differs from the first embodiment in that the electrode layer 66 and the drains 86 and 88 of the first and second thin film transistors 44 and 46 are on the side. 1.
  • the second scan lines 76 and 78 are partially overlapped. Therefore, at the edge of the region where the electrode layer connecting each of the thin film transistors overlaps the first and second scan lines 76 and 78, it is not necessary to provide a corresponding shade in the color filter.
  • This design can increase the distribution area of the storage capacitor at the same time, thereby reducing the panel flicker rate and increasing the aperture ratio.
  • the present invention sets the common electrode line between adjacent scan lines to reduce the number of common electrode lines, thereby increasing the pixel aperture ratio of the panel and reducing the probability of short circuit between the scan line and the common electrode line. , is a quite practical invention.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

显示面板
【技术领域】
本发明有关于一种显示面板， 特别有关于一种高显示质量的显示面板。 【背景技术】
请参阅图 1 , 在传统主动矩阵式的液晶显示器（LCD ) 中， 其单栅极电路 架构的每个像素具有薄膜晶体管 （TFT ) 10, 其栅极连接至水平方向的扫描线 12, 源极连接至垂直方向的数据线 14, 漏极则连接至像素电极， 邻行的薄膜晶 体管 10有各自连接的数据线 14。
以下介绍此传统电路架构的基本操作方式，在水平方向上的同一条扫描线 12上， 所有薄膜晶体管 10的栅极都连接在一起， 所以施加电压是连动的， 若 在某一条扫描线 12上施加足够大的正电压， 则此条扫描线在所有的薄膜晶体 管 12上都会被打开， 此时该条扫描线 12上的像素电极， 会与垂直方向的数据 线 14连接， 而经由垂直数据线 14送入对应的视频信号， 以将像素电极充电至 适当的电压。接着施加足够大的负电压， 关闭薄膜晶体管 10, 直到下次再重新 写入信号， 其间使得电荷保存在液晶电容上； 此时再启动一条水平扫描线 12, 送入其对应的视频信号。 如此依序将整个画面的视频数据写入， 再重新自第一 条重新写入信号。
上述单栅极电路架构由于数据线 14的数量过多， 因此其消耗在源极芯片 上的成本相当高， 而为了减少此成本的消耗， 后来的技术提出了一种双栅极电 路架构，也就是如图 2所示，相邻两行的薄膜晶体管 16共享同一条数据线 18, 这样一来， 就可以减少数据线 18的使用数量， 进而降低源极芯片的制造成本。
但是对于上述所提供的技术而言， 其从电路布局 (layout)来观察， 如图 3 所示， 扫描线 20与共通电极线 22属同一层金属层， 且相距极近， 所以在制作 过程中， 若有粒子不小心掉入面板当中， 容易在工艺完成后导致扫描线 20与 共通电极线 22发生短路， 进而导致面板显示上有横条暗线或是亮线等线不良 问题， 除此之外， 因为在相邻扫描线 20与相邻数据线 18的两个电极层 24为 分别两个像素的像素显示区， 而共通电极线 22占到电极层 24之透光区域之面 积， 使电极层 24扣掉形成共通电极线 22之金属层的透光区域部分变少， 进而 让整个面板的开口率有所损失。
因此， 本发明在针对上述的困扰， 提出一种高显示质量的显示面板， 以解 决现有技术所产生的问题。
【发明内容】
本发明的主要目的， 在于提供一种显示面板， 其将共通电极线设置在相邻 的扫描线之间， 以减少共通电极线的数量， 如此可提升面板的像素开口率， 并 减少扫描线与共通电极线发生短路的机率。
为达上述目的， 本发明提供一种显示面板， 包含多条平行的扫描线与多条 平行的数据线， 扫描线中包含有第一扫描线与第二扫描线， 数据线与扫描线互 相垂直， 并与多条共通电极线互相平行， 且该多个数据线中包含第一数据线， 共通电极线包含第一共通电极线，第一扫描线及第二扫描线设于第一共通电极 线的相异两侧， 显示面板还包含由数据线、 扫描线、 与共通电极线互相连接的 多个双栅极像素单元， 每一个个双栅极像素单元连接一条数据线、 两条扫描线 与一条共通电极线， 每一个个双栅极像素单元包含第一像素与第二像素， 第一 像素连接第一扫描线、 第一共通电极线与第一数据线， 第二像素连接第二扫描 线、 第一共通电极线与第一数据线， 第一、 第二像素位于第一扫描线与第二扫 描线的相异两侧，第一数据线与第一共通电极线分别传输数据信号与第一共通 电极信号至第一像素与第二像素中， 且第一、 第二扫描线分别控制第一、 第二 像素接收该数据信号。 【附图说明】
下面结合附图和实施例对发明进一步说明。
图 1与图 2为现有技术的显示面板的电路示意图。
图 3为现有技术的显示面板的电路布局结构示意图。
图 4为本发明的液晶显示面板的电路示意图。
图 5为本发明的双栅极像素单元的电路示意图。
图 6为本发明的液晶显示面板的第一实施例的电路布局结构示意图。
图 7为本发明的液晶显示面板的第一实施例的电路布局结构的局部放大示 意图。
图 8为图 7的电路布局结构中沿 A-A，切线的结构剖视图。
图 9为本发明的液晶显示面板的第二实施例的电路布局结构示意图。
图 10为本发明的液晶显示面板的第二实施例的电路布局结构的局部放大 示意图。
【具体实施方式】
本发明的主要设计是将共通电极线设置在相邻的扫描线之间，以下请参阅 图 4。本发明的液晶显示面板的等效电路包含多条平行的扫描线 26与多条平行 的数据线 28, 扫描线 26包含有第一扫描线 262与第二扫描线 264, 数据线 28 与扫描线 26互相垂直，且数据线 28中包含第一数据线 282,扫描线 26与多条 共通电极线 30互相平行， 且共通电极线 30包含第一共通电极线 302。
本发明的液晶显示面板还包含以矩阵方式排列的多个双栅极像素单元 32 , 并以数据线 28、扫描线 26与共通电极线 30彼此连接而成，每一个双栅极像素 单元 32连接一条数据线 28、 两条扫描线 26与一条共通电极线 30。 同一行的 双栅极像素单元 32会共享同一条数据线 28,同一列的双栅极像素单元 32会共 享同一条扫描线 26与共通电极线 30。每一个双栅极像素单元 32中的组件之连 接关系与位置关系都相同， 而以一个双栅极像素单元 32为例， 并将第一、 第 二扫描线 262、 264、 第一数据线 282、 第一共通电极线 302与双栅极像素单元 32彼此之间的连接与位置关系介绍如下。
请同时参阅图 5 , 每一个双栅极像素单元 32包含第一、 第二像素 34、 36, 而第一像素 34包含第一薄膜晶体管 342及其对应连接的第一液晶电容 346、第 一储存电容 344,第二像素 36包含第二薄膜晶体管 362及其对应连接的第二液 晶电容 366、 第二储存电容 364, 且第一、 第二像素 34、 36分别设于第一扫描 线 262与第二扫描线 264的相异两侧，第一扫描线 262及第二扫描线 264设于 第一共通电极线 302的相异两侧， 第一、 第二像素 34、 36设于第一数据线 282 的相异两侧。
第一薄膜晶体管 342的栅极连接第一扫描线 262, 其源极连接第一数据线 282, 其漏极连接第一液晶电容 346与第一储存电容 344的一端， 第一液晶电 容 346的另一端连接彩色滤光片（CF)端的共通电极，以接收第一共通电极信号， 第一储存电容 344的另一端连接第一共通电极线 302, 第一数据线 282与第一 共通电极线 302分别传输数据信号与第二共通电极信号至第一薄膜晶体管 342 中， 且第一扫描线 262控制第一薄膜晶体管 342接收该数据信号， 进而控制第 一液晶电容 346的充放电， 而第一储存电容 344用来维持第一液晶电容 346两 端的电位差， 以防第一液晶电容 346漏电的情况发生。
同样地， 第二薄膜晶体管 362的栅极连接第二扫描线 264, 其源极连接第 一数据线 282, 其漏极连接第二液晶电容 366与第二储存电容 364的一端， 第 二液晶电容 366的另一端连接彩色滤光片端的共通电极， 以接收第一共通电极 信号， 第二储存电容 364的另一端连接第一共通电极线 302, 第一数据线 282 与第一共通电极线 302分别传输数据信号与第二共通电极信号至第二薄膜晶体 管 362中， 且第二扫描线 264控制第二薄膜晶体管 362接收该数据信号， 进而 控制第二液晶电容 366的充放电， 而第二储存电容 364用来维持第二液晶电容 366两端的电位差， 以防第二液晶电容 366漏电的情况发生。
此图 4可与现有技术的图 2同时比较，可轻易看出共通电极线在图 2与图 4中是位于不同的位置， 而这样的结果当搭配此各自的电路布局结构图 3与图 6时， 可以明显看出共通电极线的设计位置明显不同故得知此设计能提升像素 的开口率， 且此电路设计可应用于垂直配向式 （VA type )、 扭转向列式（ TN type )、 平面转换式（IPS type ) 的液晶或是有机膜的像素设计。
请继续参阅图 4, 本发明的液晶显示面板的动作描述如下， 首先每一条共 通电极线 30与数据线 28分别传输第一共通电极信号与数据信号至连接的储存 电容 42与薄膜晶体管 38中， 且每一个液晶电容 40接收第一共通电极信号。 接着利用扫描线 26 由上而下依序控制每一行的薄膜晶体管 38接收该数据信 号， 进而控制液晶电容 40的充放电， 同时连接液晶电容 40的储存电容 42则 用来维持液晶电容 40两端的电位差。
请继续参阅其电路布局结构示意图， 以下请同时参阅图 6与图 7的电路布 局的第一实施例。 图 7为图 6中虚线方框中的像素电极结构的放大示意图， 此 虚线方框中所有的组件包含两个由电极层 66形成的像素电极、 两个薄膜晶体 管 44、 46及其周围的布线， 薄膜晶体管 44、 46为 N型， 而图 6则是以此虚线 方框中的像素电极结构为单元， 彼此利用扫描线 (Gate line)48、 数据线 (Data line)50、 及共通电极线 52相互连接而构成的阵列液晶显示面板。 且， 由于像 素电极结构在显示面板上是以矩阵方式排列， 因此同一行的像素电极结构会共 享同一条数据线 50, 同一列的像素电极结构会共享同一条扫描线 48与共通电 极线 52。每一个像素电极结构中的组件的连接关系与位置关系都相同， 而以一 个像素电极结构为例， 陈述如下。
为了清楚说明实施方式， 以下请同时参阅图 7与图 8, 图 8为图 7的电路 布局结构中沿 A-A，切线的剖视图，可表达出图 7中所包含的组件的上下堆栈关 系。 图 7为像素电极结构， 其主要包含透明基板 54、 第一阵列像素与第二阵列 像素， 第一、 第二阵列像素分别形成第一、 第二薄膜晶体管 44、 46、 第一、 第 二像素电极 67、 69, 以及第一、 第二扫描线 76、 78。 第一、 第二阵列像素由 第一金属层 56、 绝缘层 58、 半导体层 60、 第二金属层 62、 保护层 64、 电极层 66所形成， 而液晶层设在电极层上 66。 保护层 64绝缘材质， 其与绝缘层 58 的材质都为氮化硅， 电极层 66的材质为氧化铟锡（ ITO ) , 且此电极层 66形成 与第一、 第二薄膜晶体管 44、 46分别连接的第一、 第二像素电极 67、 69。
第一金属层 56设于透明基板 54上，以形成第一薄膜晶体管 44的栅极 72、 第二薄膜晶体管 46的栅极 74、 第一扫描线 76、 第二扫描线 78与在第一扫描 线 76下方与第二扫描线 78上方两者之间的共通电极线 80, 然在第一金属层 56形成时， 同时分别将第一、 第二扫描线 76、 78与第一、第二薄膜晶体管 44、 46的栅极 72、 74形成为相连的线路，第一金属层 56形成后其上形成有绝缘层 58, 绝缘层 58是在二薄膜晶体管 44、 46上作为栅极绝缘层。 绝缘层 58上设 有半导体层 60,此半导体层 60分为上下二层结构，其下层为非晶硅层 (a-Si)68, 直接设于绝缘层 58上，其上层为 n+掺杂非晶硅 ( n+ a—Si)的欧姆接触层 70, 欧姆 接触层 70与绝缘层 58上设有第二金属层 62, 以形成第一、 第二薄膜晶体管 44、 46的源极 82、 84与漏极 86、 88与数据线 90, 数据线 90连接第一、 第二 薄膜晶体管 44、 46的源极 82、 84, 又第一、 第二薄膜晶体管 44、 46位于数据 线 90的相异两侧， 第一、 第二薄膜晶体管 44、 46分别位于第一、 第二扫描线 76、 78的相异两侧， 第一、 第二薄膜晶体管 44、 46的源极 82、 84、 漏极 86、 88分别位于第一、 第二薄膜晶体管 44、 46的栅极 72、 74上方， 且非晶硅层 68与欧姆接触层 70都位于第一、 第二薄膜晶体管 44、 46的源极 82、 84与漏 极 86、 88下方， 数据线 90与共通电极线 80、 第一、 第二扫描线 76、 78垂直 相交。
另从图中可以发现，第一像素电极 67设于第一扫描线 76下方且重叠于共 通电极线 80及第二扫描线 78 , 其中第一像素电极 67与第二扫描线 78的重叠 面积小于第一像素电极 67与共通电极线 80的重叠面积。 而第二像素电极 69 设于第二扫描线 78上方且重叠于共通电极线 80及第一扫描线 76,其中第二像 素电极 69与第一扫描线 76的重叠面积小于第二像素电极 69与共通电极线 80 的重叠面积。
欧姆接触层 70与第二金属层 62上覆盖保护层 64, 此保护层 64具有分别 位于第一、 第二薄膜晶体管 44、 46的漏极 86、 88和半导体层 60上方的通孔 92。此通孔 92为图 8的剖视图中的保护层 64没有连接的部分，且在保护层 64 蚀刻出通孔 92时， 因无法透过半导体层 60并继续往绝缘层 58蚀刻， 所以通 孔 92深度仅能到达半导体层 60。
在保护层 64上设有电极层 66,此电极层 66可通过通孔 92与对应的第一、 第二薄膜晶体管 44、 46的漏极 86、 88和半导体层 60相接触。 如图 8所示， 由于通孔的缘故， 作为漏极 86的第二金属层 62和半导体层 60暴露在外， 因 此可与电极层 66相接触。 且， 为了减少杂散电容， 此电极层 66具有分别位于 第一、 第二扫描线 76、 78上的通孔 94。
另外， 与薄膜晶体管的漏极相接触的电极层 66和第一金属层 56、 第二金 属层 62重叠的部分， 可形成该薄膜晶体管的储存电容。 如第一薄膜晶体管 44 的漏极 86有一部分往共通电极线 80延伸， 并与此共通电极线 80与电极层 66 重叠的部分为第一薄膜晶体管 44的储存电容； 第二薄膜晶体管 46的漏极 88 有一部分往共通电极线 80延伸， 并与此共通电极线 80与电极层 66重叠的部 分为第二薄膜晶体管 46的储存电容。
还有， 此实施例的电极层 66并没有与第一、 第二薄膜晶体管 44、 46的漏 极 86、 88侧的第一、 第二扫描线 76、 78重叠， 所以在连接每个薄膜晶体管的 电极层边缘处， 必须于彩色滤光片中对应设置遮光物， 如黑矩阵（BM )。 如此 一来， 当显示面板制作成液晶显示器时， 每一个像素边缘才不会出现漏光， 而 影响液晶分子排列， 且邻接像素才不会出现混色的现象。
利用上述电路布局所制造出来的液晶显示面板如图 6所示，可与现有技术 的图 3同时比较， 在相邻扫描线 48与相邻数据线 50的两个电极层 66为分别 两个像素的像素显示区， 在本发明的设计下， 共通电极线 52不会侵占到电极 层 66的透光区域的面积， 另外在相同的晶体管的数量下， 图 6所使用到的共 通电极线 52的数量比图 3少， 其与图 4的等效电路图的比较结果相同， 换句 话说， 如此设计便能提升像素的开口率， 同时由于共通电极线的数量减少， 因 此更可减少扫描线与共通电极线发生短路的机率。
接着请同时参阅图 9与图 10的电路布局的第二实施例， 其与第一实施例 的差异在于电极层 66与第一、 第二薄膜晶体管 44、 46的漏极 86、 88侧的第 一、 第二扫描线 76、 78部分重叠， 所以在连接每个薄膜晶体管的电极层与第 一、 第二扫描线 76、 78重叠区域的边缘处， 不必于彩色滤光片中对应设置遮 光物， 此种设计可同时增加了储存电容的分布面积， 进而减少面板闪烁率， 且 增加其开口率。
综上所述， 本发明将共通电极线设置在相邻的扫描线之间， 以减少共通电 极线的数量， 如此可提升面板的像素开口率， 并减少扫描线与共通电极线发生 短路的机率， 是相当实用的发明。
以上所述者， 仅为本发明的较佳实施例而已， 并非用来限定本发明实施的 范围， 故凡依本发明申请专利范围所述的形状、 构造、 特征及精神所为的均等 变化与修饰， 均应包括于本发明的申请专利范围内。

Claims

权 利 要 求
1. 一种显示面板， 其特征在于： 包含，
多条平行的扫描线， 其中包含有第一扫描线与第二扫描线；
多条平行的数据线， 其与该多个扫描线互相垂直， 且该多个数据线中包含 第一数据线；
多条共通电极线， 其与该多个扫描线互相平行， 且该多个共通电极线包含 第一共通电极线，该第一扫描线及该第二扫描线设于该第一共通电极线的相异 两 4则； 以及
多个双栅极像素单元， 每一个该双栅极像素单元连接一条该数据线、 两条 该扫描线与一条该共通电极线， 每一个该双栅极像素单元包含：
第一像素， 其连接该第一扫描线、 该第一共通电极线与该第一数据线； 以 及
第二像素， 其连接该第二扫描线、 该第一共通电极线与该第一数据线， 该 第一、 第二像素位于该第一数据线的相异两侧。
2. 根据权利要求 1所述的显示面板， 其特征在于： 该第一、 第二像素位 于该第一、 第二扫描线的相异两侧。
3. 根据权利要求 1所述的显示面板， 其特征在于： 该第一像素包含， 第一薄膜晶体管， 其栅极连接该第一扫描线， 其源极连接该第一数据线； 第一液晶电容， 其一端连接该第一薄膜晶体管的漏极， 另一端连接共通电 极， 以接收第一共通电极信号， 该第一薄膜晶体管接收该第一数据线所传输的 数据信号， 该第一扫描线控制该第一薄膜晶体管的开关状态， 使该第一薄膜晶 体管根据该数据信号控制该第一液晶电容的充放电； 以及
第一储存电容， 其一端连接该第一薄膜晶体管的漏极， 另一端连接该第一 共通电极线， 以接收该第一共通电极线所传输的第二共通电极信号， 该第一储 存电容维持该第一液晶电容的两端的电位差。
4. 根据权利要求 1所述的显示面板， 其特征在于： 该第二像素包含： 第二薄膜晶体管， 其栅极连接该第二扫描线， 其源极连接该第一数据线； 第二液晶电容， 其一端连接该第二薄膜晶体管的漏极， 另一端连接共通电 极， 以接收第一共通电极信号， 该第二薄膜晶体管接收该第二数据线所传输的 数据信号， 该第二扫描线控制该第二薄膜晶体管的开关状态， 使该第二薄膜晶 体管根据该数据信号控制该第二液晶电容的充放电； 以及
第二储存电容， 其一端连接该第二薄膜晶体管的漏极， 另一端连接该第一 共通电极线， 以接收该第一共通电极线所传输的第二共通电极信号， 该第二储 存电容维持该第二液晶电容的两端的电位差。
5. 根据权利要求 1所述的显示面板， 其特征在于： 该显示面板为液晶显 示面板。
6. 根据权利要求 1所述的显示面板， 其特征在于： 该第一、 第二像素的 驱动方法包含下列步骤：
该第一数据线与该第一共通电极线分别传输数据信号与共通电极信号至 该第一、 第二像素； 以及
该第一、 第二扫描线分别控制该第一、 第二像素接收该数据信号。
7. 根据权利要求 1所述的显示面板， 其特征在于： 该多个双栅极像素单 元以矩阵方式排列。
8. 根据权利要求 3所述的显示面板， 其特征在于： 该第一薄膜晶体管的 栅极、 该多个扫描线与该多个共通电极线由第一金属层所形成， 该第一薄膜晶 体管的源、 漏极与该多个数据线由第二金属层所形成， 且该第一薄膜晶体管的 源极、 漏极位于其栅极的上方， 该第一薄膜晶体管的漏极有一部分往该第一共 通电极线延伸， 并与该第一共通电极线重叠。
9. 根据权利要求 4所述的显示面板， 其特征在于： 该第二薄膜晶体管的 栅极、 该多个扫描线与该多个共通电极线由第一金属层所形成， 该第二薄膜晶 体管的源、 漏极与该多个数据线由第二金属层所形成， 且该第二薄膜晶体管的 源极、 漏极位于其栅极的上方， 该第二薄膜晶体管的漏极有一部分往该第一共 通电极线延伸， 并与该第一共通电极线重叠。
10. 根据权利要求 8或 9所述的显示面板， 其特征在于： 该第一金属层上 覆盖有绝缘层。
11. 根据权利要求 10所述的显示面板， 其特征在于： 该绝缘层上设有半 导体层， 其位于该源极、 漏极的下方， 且该第二金属层设于该半导体层与该绝 缘层上。
12. 根据权利要求 11所述的显示面板， 其特征在于： 该半导体层与该第 二金属层上覆盖有保护层， 且该保护层分别具有位于该漏极上方的第一通孔。
13. 根据权利要求 12所述的显示面板， 其特征在于： 该保护层上设有电 极层， 该电极层形成第一像素电极与第二像素电极， 该第一像素电极设于该第 一扫描线下方且重叠于该第一共通电极线及该第二扫描线，并由该第一通孔与 对应的该漏极相接触；该第二像素电极设于该第二扫描线上方且重叠于该第一 共通电极线及该第一扫描线， 并由该第一通孔与对应的该漏极相接触， 且该第 一、 第二像素电极具有分别位于该第二、 第一扫描在线的第二通孔。
14. 根据权利要求 13所述的显示面板， 其特征在于： 该电极层与该薄膜 晶体管的漏极侧的该第一、 第二扫描线部分重叠。
15. 根据权利要求 13所述的显示面板， 其特征在于： 该第一像素电极与 该第二扫描线的重叠面积小于该第一像素电极与该第一共通电极线的重叠面 积；该第二像素电极与该第一扫描线的重叠面积小于该第二像素电极与该第一 共通电极线的重叠面积。
16. 根据权利要求 12所述的显示面板， 其特征在于： 该半导体层包含： 非晶硅层， 其设于该绝缘层上； 以及 欧姆接触层， 其设于该非晶硅层上， 并供该第二金属层与该保护层设于其 上。
17. 根据权利要求 12所述的显示面板， 其特征在于： 该第一通孔位于部 分该半导体层与部分该第二金属层上方，使该半导体层与该第二金属层通过该 电极层相连接。
18. 根据权利要求 17所述的显示面板， 其特征在于： 该第一通孔深度到 达该半导体层。
PCT/CN2009/072487 2009-05-06 2009-06-26 显示面板 WO2010127515A1 (zh)

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