WO2021249182A1 - 显示基板、显示面板及显示基板的制作方法 - Google Patents

显示基板、显示面板及显示基板的制作方法 Download PDF

Info

Publication number
WO2021249182A1
WO2021249182A1 PCT/CN2021/095818 CN2021095818W WO2021249182A1 WO 2021249182 A1 WO2021249182 A1 WO 2021249182A1 CN 2021095818 W CN2021095818 W CN 2021095818W WO 2021249182 A1 WO2021249182 A1 WO 2021249182A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
pixel electrode
branch line
line
substrate
Prior art date
Application number
PCT/CN2021/095818
Other languages
English (en)
French (fr)
Inventor
王栋
李红敏
廖力勍
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/775,430 priority Critical patent/US20220382110A1/en
Publication of WO2021249182A1 publication Critical patent/WO2021249182A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/09—Function characteristic transflective
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/30—Gray scale

Definitions

  • the embodiment of the present disclosure relates to a manufacturing method of a display substrate, a display panel, and a display substrate.
  • the different grayscale brightness of the display panel is realized by applying different voltages between the pixel electrode of the array substrate and the common electrode of the counter substrate.
  • the signal of the signal line is stored on the pixel electrode through the action of a thin film transistor (TFT).
  • TFT thin film transistor
  • the voltage on the signal line (data line) is different, and the voltage stored on the pixel electrode is different, which is common to the opposite substrate.
  • the voltage difference between the electrodes is different, and the liquid crystal is driven to deflect different amplitudes to realize different grayscale images.
  • At least one embodiment of the present disclosure provides a display substrate, including a substrate and a plurality of pixel units located on the substrate, the plurality of pixel units are arranged in an array, wherein the display substrate further includes a plurality of signals Line, for each signal line of the plurality of signal lines, the signal line is arranged in the column direction and located between the first pixel unit and the second pixel unit that are adjacent in the row direction, and the signal line is connected to the The first pixel electrode of the first pixel unit and the second pixel electrode of the second pixel unit are both arranged in different layers, and the signal line includes a first branch line and a second branch line that are connected in parallel and extend in a column direction; The orthographic projection of the first branch line on the substrate and the orthographic projection of the first pixel electrode on the substrate at least partially overlap; and the orthographic projection of the second branch line on the substrate and The orthographic projections of the second pixel electrode on the substrate at least partially overlap.
  • the voltages applied to two adjacent signal lines of the plurality of signal lines have opposite polarities.
  • the signal line further includes a trunk line, a first bridge portion, and a second bridge portion, the first bridge portion connects the first branch line and the trunk line, and the second bridge portion The part connects the second branch line and the trunk line.
  • the first bridging portion is perpendicular to the trunk line
  • the second bridging portion is perpendicular to the trunk line; or, the first bridging portion and the trunk line are arranged at an obtuse angle, so The second bridge portion is arranged at an obtuse angle with the trunk line.
  • the signal line further includes a trunk line connected to the first branch line and the second branch line, and the sum of the widths of the first branch line and the second branch line is not less than The width of the trunk line.
  • the first branch line has a first side facing the second branch line; the second branch line has a second side facing the first branch line; A pixel electrode has a third side facing the second pixel electrode; a second pixel electrode has a fourth side facing the first pixel electrode; and the first side, the third side, and the fourth side , The second side edge is arranged in sequence along the row direction.
  • the distance between the first side edge and the third side edge in the row direction is equal to the distance between the second side edge and the fourth side edge in the row direction.
  • the distance between the first side edge and the third side edge in the row direction is not less than 2.5 ⁇ m, and the distance between the second side edge and the fourth side edge in the row direction is not less than 2.5 ⁇ m .
  • the display substrate includes a storage electrode and a plurality of thin film transistors, the storage electrode and the gate electrode of the thin film transistor are arranged in the same layer, and the drain electrode of the thin film transistor and the pixel electrode Electrically connected, the storage electrode and the drain of the thin film transistor form a storage capacitor.
  • the ratio of the area of the drain electrode to the area of the pixel electrode is greater than or equal to 0.1 and less than 1.
  • the distance between the first branch line and the storage electrode in the row direction is not less than 2.5 ⁇ m, and the distance between the second branch line and the storage electrode in the row direction is not less than 2.5 ⁇ m.
  • the pixel electrode is a reflective electrode, and the pixel electrode has a reflective surface facing away from the substrate.
  • the distance in the row direction between two pixel electrodes arranged adjacently along the row direction is 3 ⁇ m to 5 ⁇ m.
  • the signal line is made of a reflective metal material.
  • At least one embodiment of the present disclosure provides a display panel including the above-mentioned display substrate.
  • the display panel is one of a reflective liquid crystal panel, a transflective liquid crystal panel, or a transmissive liquid crystal panel.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: providing a substrate; forming a plurality of pixel units and a plurality of signal lines on the substrate, and the plurality of pixel units are arranged in an array
  • Each of the pixel units includes a pixel electrode; a signal line is formed between two adjacent pixel units in the column direction, and the signal line and the pixel electrode of the pixel unit are arranged on a different layer; wherein, The signal lines are arranged in the column direction and located between the first pixel unit and the second pixel unit that are adjacent in the row direction, and the signal line is connected to the first pixel electrode of the first pixel unit and the first pixel unit
  • the second pixel electrodes are all arranged in different layers, the signal line includes a first branch line and a second branch line that are connected in parallel and extend in the column direction; the orthographic projection of the first branch line on the substrate and the first branch line The orthographic projection of a pixel electrode on the substrate at least partially overlap;
  • the signal line and the pixel electrode are arranged in different layers, and the first branch line and the second branch line of the signal line are respectively overlapped with two adjacent pixel electrodes in the vertical direction, thereby reducing, eliminating or improving the signal line and the pixel electrode
  • the parasitic capacitance between the two prevents or reduces the influence of the parasitic capacitance on the voltage difference between the pixel electrode and the common electrode, thereby improving the display effect.
  • FIG. 1 is a schematic top view of a display substrate, in which the insulating film layer is not shown.
  • FIG. 2 is a schematic diagram of the N-1th frame signal and the Nth frame signal when the column inversion driving is adopted.
  • Fig. 3 is a schematic diagram of crosstalk generated by the display substrate shown in Fig. 1.
  • Fig. 4 shows a schematic side view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic top view of the display substrate shown in FIG. 1, in which the structure of the substrate, the organic insulating layer, and the inorganic insulating layer are not shown.
  • FIG. 6 is a schematic top view of one pixel unit of the display substrate shown in FIG. 5.
  • FIG. 7 is a partial enlarged view of FIG. 5.
  • the thin film transistors, electrode groups, and signal lines are filled with patterns.
  • FIG. 8 shows a schematic top view of a display panel according to another embodiment of the present disclosure, in which structures such as a substrate, an organic insulating layer, and an inorganic insulating layer are not shown.
  • Fig. 9 is a partial enlarged view of Fig. 5.
  • Fig. 9 is a partial enlarged view of Fig. 5.
  • the thin film transistors, electrode groups, signal lines, etc. are shown, and the thin film transistors, electrode groups, and signal lines are filled with patterns.
  • Fig. 10 is a schematic cross-sectional view of Fig. 5 along line A-A.
  • Fig. 11 is a schematic cross-sectional view taken along line B-B in Fig. 5.
  • FIG. 12 shows a schematic side view of a display panel according to an embodiment of the present disclosure.
  • the pixel electrode 40 ′ receives the signal of the driving chip through the thin film transistor 20 ′ and the signal line 25 ′.
  • the pixel electrode 40' and the signal line 25' on the left form a first parasitic capacitance Cpd L
  • the pixel electrode 40' and the signal line 25" on the right form a second parasitic capacitance Cpd R.
  • the unequal distance causes the capacitance values of the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R to be unequal.
  • the voltage polarities of the two adjacent signal lines 25' and 25" are opposite, so the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R have opposite polarities, but the first parasitic capacitance Cpd
  • the capacitance values of L and the second parasitic capacitance Cpd R are not equal, and the effects of the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R on the pixel electrode cannot cancel each other, that is, the influence of the parasitic capacitance Cpd on the pixel electrode still exists.
  • the polarity of the parasitic capacitance depends on which signal line is closer to the pixel electrode.
  • the capacitance value corresponding to the first parasitic capacitance Cpd L is larger.
  • the capacitance polarity of the parasitic capacitance Cpd is the same as the first parasitic capacitance Cpd L.
  • the middle L0 gray scale display the entire data line voltage is +5V (the voltage of the common electrode is 0V), due to the parasitic capacitance Cpd Existence, at this time the upper pixel electrode of the display substrate is pulled from (2V to) 5V, for example, the voltage is pulled to (3V), the voltage difference between the pixel electrode and the common electrode is (the screen turns black relative to L127); The lower pixel electrode of the display substrate is pulled from -2V to +5V. For example, when the voltage is pulled to -1V, the voltage difference between the pixel electrode and the common electrode is -1V (the screen becomes brighter relative to L127).
  • the data signal of the middle pattern pulls the pixel voltage in the up and down holding stage. Because the pixel electrodes of the upper and lower parts of the screen are pulled to different voltages, the voltage difference between the upper and lower parts of the pixel electrode and the common electrode changes, and this change cannot be offset, which leads to the generation of crosstalk in the vertical direction.
  • the display substrate includes a substrate and a plurality of pixel units on the substrate.
  • the plurality of pixel units are arranged in multiple rows and multiple columns, and each pixel unit includes a pixel electrode.
  • a signal line is arranged between two adjacent pixel units in the same row, the signal line and the pixel electrode of the pixel unit are arranged in different layers, and the signal line includes a first branch line and a second branch line that are connected;
  • the orthographic projection of the branch line on the substrate coincides with the orthographic projection of the pixel electrode of one of the two adjacent pixel units on the substrate; the orthographic projection of the second branch line on the substrate coincides with the adjacent
  • the orthographic projection of the pixel electrode of the other of the two pixel units on the substrate overlaps.
  • the display substrate according to an embodiment of the present disclosure is, for example, an array substrate, including a substrate 1, a thin film transistor layer 2 and an inorganic insulating layer sequentially arranged in a direction perpendicular to the substrate 1 3 and pixel electrode layer 4.
  • the direction Z shown in FIG. 4 is a direction perpendicular to the substrate 1.
  • the inorganic insulating layer 3 can also be replaced with other types of insulating layers, such as a composite layer or laminate of organic insulating materials and inorganic insulating materials, as long as they can function as electrical isolation.
  • the thin film transistor layer 2 includes a plurality of thin film transistors 20, and the pixel electrode layer 4 includes a plurality of pixel electrodes 40.
  • the thin film transistor 20 includes an active layer 21 (refer to FIG. 11), a source electrode 22, a drain electrode 23, and a gate electrode 24.
  • the thin film transistor layer 2 can be understood as a combination of these layers.
  • the source electrode 22 and the drain electrode 23 are arranged in the same layer, and the gate electrodes 24 of the thin film transistors in the same row are electrically connected through the scan line 27.
  • the display substrate further includes a gate insulating layer 5 (refer to FIG. 11), an organic insulating layer 6 (refer to FIG. 11), a plurality of signal lines 25, and a plurality of storage electrodes 26.
  • the gate 24, the gate insulating layer 5, the active layer 21, the source 22 (or the drain 23 and the signal line 25), the organic insulating layer 6, the inorganic insulating layer 3, and the pixel electrode layer 4 are sequentially along the direction Z set up.
  • the signal line 25 is arranged in the same layer as the source 22 and the drain 23, and the storage electrode 26 and the gate 24 are arranged in the same layer.
  • the same layer arrangement can be understood as being formed in the same patterning process, which is beneficial to simplify the manufacturing process of the display substrate.
  • the signal line 25 and the storage electrode 26 may also be provided on other film layers.
  • the storage electrode 26 is configured to form a storage capacitor with the drain electrode 23, and the drain electrode 23 is electrically connected to the pixel electrode 40 of the pixel electrode layer 4 so that the potential is equal, which is equivalent to forming a storage capacitor between the storage electrode 26 and the pixel electrode 40 ,
  • the storage capacitor is configured to store a part of the power, so that the picture can be maintained for a period of time after the voltage of the signal line disappears;
  • the storage electrode is also configured to provide a common signal (or ground signal) for the common electrode on the opposite substrate side ), the two can be electrically connected through a conductive support pillar or conductive glue that is supported between the display substrate and the counter substrate.
  • the storage electrode 26 is a whole (in order to clearly illustrate different pixel units, the storage electrode 26 shows a dividing line between adjacent pixel units 10, which does not actually exist) and is grounded. In other embodiments of the present disclosure, a plurality of storage electrodes 26 respectively grounded are provided in the display substrate.
  • the display substrate according to the embodiment of the present disclosure is suitable for liquid crystal display, and the electric field formed after the voltage is applied to the pixel electrode and the common electrode on the opposite substrate side will drive the liquid crystal to deflect for display.
  • the pixel electrode is electrically connected to the drain electrode 23 of the thin film transistor 20, and the signal line 25 is electrically connected to the source electrode 22 of the thin film transistor 20, so that the pixel electrode can receive the driving chip through the signal line 25 and the thin film transistor 20 (not shown) Show) the drive signal.
  • the display substrate is suitable for a reflective liquid crystal panel
  • the drain electrode 23 is disposed under the reflective electrode (ie, the pixel electrode), so that the drain electrode 23 does not affect the light emission, so the area of the drain electrode 23 is It can be designed to be larger, for example, not less than 1/10 of the area of the pixel unit (which can also be understood as the area of the pixel electrode).
  • Increasing the area of the drain 23 can increase the storage capacitance between the drain 23 and the storage electrode 26. After the driving voltage disappears, the currently displayed picture can be better maintained to the next picture.
  • the area of the drain can be infinitely close to the area of the pixel unit, that is, the ratio of the two is close to 1.
  • the display substrate includes a plurality of pixel units 10 arranged in an array, each pixel unit 10 includes a pixel electrode 40, each pixel electrode 40 is connected to a corresponding thin film transistor 20, of course, the pixel unit 10 may also include other insulating film layers, such as inorganic insulating layer 3.
  • the signal line 25 is arranged between two adjacent pixel units 10 along the row direction X.
  • the term "arranged between " here can be understood to be partly arranged or completely arranged. Further, As long as the projection of the signal line 25 on the substrate 1 is partially located between the projections of the two pixel units 10 on the substrate.
  • the signal line 25 includes a trunk line 251, a first branch line 252, a second branch line 253, a first bridge portion 254, and a second bridge portion 255.
  • the first bridge portion 254 connects the trunk line 251 and the first branch line 252,
  • the second bridge portion 255 connects the trunk line 251 and the second branch line 253. That is, the first branch line 252 is connected in series with the first bridge portion 254, the second branch line 253 is connected in series with the second bridge portion 255, and then the two series circuits are connected in parallel.
  • the trunk line 251, the first branch line 252, the second branch line 253, the first bridge portion 254, and the second bridge portion 255 constitute a signal line unit.
  • the signal line 25 can be regarded as a plurality of signals connected end to end and arranged in the column direction Y
  • the line unit is constituted, and each signal line unit corresponds to (connects) a thin film transistor 20.
  • the first branch line 252 of the signal line 25 is on the substrate 1
  • the orthographic projection is at least partially overlapped with the orthographic projection of the pixel electrode 40A of the pixel unit 10A on the substrate 1, and the orthographic projection of the second branch line 253 of the signal line 25 on the substrate 1 is in contrast to the pixel electrode 40B of the pixel unit 10B.
  • the orthographic projections on the bottom 1 overlap at least partially.
  • the pixel electrode 40 and the signal line 25A on the left form a first parasitic capacitance Cpd L
  • the pixel electrode 40 and the signal line and the signal line 25B on the right form a second parasitic capacitance Cpd R.
  • the signal lines 25A, 25B and the pixel electrode 40 are located Different layers and orthographic projections overlap at least partially.
  • the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R are not related to their distance in the row direction X (or almost not related). That is, the main influence on the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R is the distance between the signal lines 25A, 25B and the pixel electrode 40 in the vertical direction Z.
  • the parasitic capacitance will not be affected, that is, whether there is a deviation in the parasitic capacitance between the signal line and the two pixel electrodes is only related to the distance in the vertical Z.
  • the vertical Z spacing is easy to control.
  • the capacitance values of the first parasitic capacitance Cpd L and Cpd r can be guaranteed to be equal.
  • the premise is to ensure that the other parameters corresponding to Cpd L and Cpd r remain consistent, for example The material is the same and the facing area is the same.
  • the voltage polarities of two adjacent signal lines are opposite, so that the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R have opposite polarities, and the capacitance values of the two are equal, so Cpd L
  • the influence of Cpd and Cpd r on the pixel electrode can cancel each other (or the voltage pulling of the signal line on the pixel electrode cancels each other out), thereby eliminating the influence of the signal line on the voltage of the pixel electrode, making the pixel electrode and the common electrode on the opposite substrate side
  • the voltage difference between them remains unchanged to ensure that the gray scale of the picture is not affected by the parasitic capacitance, thereby improving the crosstalk in the vertical direction.
  • the trunk line 251 and the first bridge portion 254 are in a vertical state, and the trunk line 251 and the second bridge portion 255 are in a vertical state, so that the trunk line 251, the first bridge portion 254, and the second bridge portion 255 are integrated. It has a "T" shape.
  • the "vertical" may have a certain deviation, for example, the connecting portion between the trunk line 251 and the first bridge portion 254 (or the second bridge portion 255) is arc-shaped or has other curved shapes; Or, due to process reasons, the included angle between the trunk line 251 and the first bridge portion 254 (or the second bridge portion 255) may have a certain deviation, for example, the included angle may be 85°-95°. It is verified through experiments that the signal line structure of the above embodiment can reduce the signal crosstalk in the vertical direction to zero, that is, LV0, so as to avoid affecting the voltage difference between the pixel electrode and the common electrode, which is beneficial to improve the display effect.
  • the signal line 25 may have other structural changes.
  • the trunk 251 of the signal line 25 and the first bridge portion 254 and the second bridge portion 255 may also form other angles, such as obtuse angles, and other structures are similar to the embodiment shown in FIG. 5.
  • the trunk line 251 and the first bridge portion 254 (or the second bridge portion 255) can also be transitioned through a curve such as a circular arc.
  • the total length of the series circuit of the first bridge portion 254 and the first branch line 252 and the first The total length of the series circuit of the second bridge portion 255 and the second branch line 253 is less than the length of the corresponding series circuit of the foregoing embodiment, which is beneficial to further reduce the impedance of the signal line, thereby facilitating the driving of the pixel electrode.
  • the width L1 of the trunk line 251 is 3um (the width of the region connected to the source of the thin film transistor is slightly larger, which is not shown in the figure).
  • the width L2 of a branch line 252, the width L3 of the second branch line 253, the width L4 of the first bridge portion 254, and the width L5 of the second bridge portion 255 are all 3um.
  • the non-trunk segments of the signal line 25 are parallel circuits, because the thickness and materials of different areas of the signal line are the same Therefore, the impedance per unit length of the non-trunk line segment is only half of the impedance per unit length of the trunk line segment, and the reduction in impedance is conducive to driving the pixel electrode.
  • the sum of the widths of the first branch line 252 and the second branch line 253 is greater than the width of the trunk line 251, That can achieve the purpose of reducing impedance.
  • the "width” here can be understood as a dimension in a direction perpendicular to the extension direction, and the direction perpendicular to the extension direction is the arrangement direction of the first branch line 252 and the second branch line 253, that is, the row direction X.
  • the pixel electrode 40 is a reflective electrode.
  • the pixel electrode 40 has a reflective surface 41 facing away from the substrate 1 for directing light away from the substrate.
  • the direction of reflection is 1, that is, the liquid crystal panel is a reflective liquid crystal panel.
  • the area of the reflective surface 41 is determined by the pixel electrode 40 and thus is positively correlated with the area of the pixel electrode 40.
  • the area of the reflective surface 41 increases with the increase of the area of the pixel electrode 40, which is beneficial to reflect more light, thereby increasing the brightness of the display panel, and thereby improving the display effect.
  • the pixel electrode does not need to transmit light, so even if a metal signal line that does not transmit light is selected and its branch line is arranged directly below the pixel electrode, the pixel aperture ratio will not be affected.
  • the display panel may also be a transflective liquid crystal panel or a transmissive liquid crystal panel including a backlight.
  • the distance d1 between two adjacent pixel electrodes is 3 ⁇ 5 ⁇ m, within this distance range, a good display effect can be guaranteed, and the requirements for the manufacturing process are also low .
  • the distance d1 between two adjacent pixel electrodes in order to ensure a good display effect and at the same time avoid color mixing between adjacent pixels due to too small pixel pitch, the distance d1 between two adjacent pixel electrodes is 4 to 5 ⁇ m In some embodiments of the present disclosure, d1 is 5 ⁇ m. Of course, the distance d1 between two adjacent pixel electrodes can also be set to be less than 3 ⁇ m.
  • the first branch line 252 has a first side a facing the second branch line 253, the second branch line 253 has a second side b facing the first branch line 252, and the pixel electrode 40A (
  • the pixel electrode 40B has a third side c facing the pixel electrode 40B (coinciding with the projected portion of the second branch line 253); the pixel electrode 40B has a fourth side d facing the pixel electrode 40A.
  • the first bridge portion 254 has a fifth side e facing the thin film transistor 20, the pixel electrode 40B includes a sixth side f facing the thin film transistor 20, and the drain electrode of the thin film transistor 20 is electrically connected to the pixel electrode 40B .
  • the first side a, the third side c, the fourth side d, and the second side b are sequentially arranged along the row direction X, and all extend along the column direction Y; the fifth side e and the sixth side The side f extends in the row direction X.
  • the orthographic projections of the first branch line 252 and the second branch line 253 will not fall between two adjacent pixel electrodes in the row direction.
  • the distance d2 between the first side a and the third side c is equal to the second side b and the fourth side.
  • the distance d3 from side d is equal to the first parasitic capacitance Cpd L and the second parasitic capacitance Cpd R can be completely cancelled (that is, the capacitance value is equal and the polarity is opposite), thereby eliminating crosstalk in the vertical direction.
  • d2 is not less than 2.5 ⁇ m
  • d3 is not less than 2.5 ⁇ m.
  • the first branch line 252 and The lateral distance d5 of the adjacent storage electrode 26 (that is, the storage electrode on the left side of the first branch line 252; because the distance between the first branch line 252 and the storage electrode on the right side is greater) is not less than 2.5 ⁇ m.
  • a thin film transistor layer 2 is formed on the substrate 1.
  • the gate 24 and the storage electrode 26 are formed on the substrate 1 (or the buffer layer on the substrate 1) through the same patterning process; the gate 24 and the storage electrode 26 are formed on the gate 24 and the storage electrode 26.
  • An active layer 21 is formed on the gate insulating layer 5; a source and drain electrode layer is formed on the active layer 21, the source and drain electrode layer includes a source 22, a drain 23, and is electrically connected to the source 22 The signal line 25.
  • an organic insulating layer 6 is formed on the thin film transistor layer 2; an inorganic insulating layer 3 is formed on the organic insulating layer 6; a pixel electrode layer 4 is formed on the inorganic insulating layer 3, wherein the pixel electrode layer 4
  • the inner pixel electrode 40 is electrically connected to the drain electrode 23 of the thin film transistor (see FIG. 5) through a via hole 30, and the via hole 30 penetrates the organic insulating layer 6 and the inorganic insulating layer 3.
  • the signal line 25 may be made of a reflective metal material such as silver.
  • the organic insulating layer 6 is made of organic materials, such as positive polymethyl methacrylate, negative polymethyl methacrylate, and other organic materials with relatively large dielectric constants.
  • the larger organic insulating layer 6 is used to reduce the parasitic capacitance between the signal line 25 and the pixel electrode 40.
  • the thickness of the organic insulating layer 6 is 1-3 ⁇ m. Under this thickness, the organic insulating layer can effectively reduce the parasitic capacitance of the signal line and the pixel electrode, and at the same time, it can affect the overall thickness of the display substrate. Less affected.
  • the inorganic insulating layer 3 is configured to further reduce the parasitic capacitance between the signal line and the pixel electrode. At the same time, the inorganic insulating layer 3 is also used as a planarization layer to provide a relatively flat surface for the pixel electrode, which is beneficial to improve the film quality of the pixel electrode. .
  • the display panel also provides a display panel, which may be a reflective liquid crystal panel, a transflective liquid crystal panel, or a transmissive liquid crystal panel.
  • the display panel includes a counter substrate 200, a liquid crystal layer 300, and the display substrate 100 according to any one of the foregoing embodiments.
  • the counter substrate 200 may be a color filter substrate, which includes a color filter (CF, Color Filter), a common electrode, and other structures.
  • the display panel may further include conductive support pillars disposed in the liquid crystal layer 300 and configured to support the counter substrate 200 and the display substrate 100, and the conductive support pillars may be electrically connected to the common electrode and the
  • the storage electrode 26 (refer to FIG. 5 and FIG. 6) provides a COM signal (usually a ground signal) for the common electrode.
  • the display device may be a display device such as a mobile phone, a tablet computer, a monitor, and a television.
  • the display device may include the aforementioned display panel (reflective, transflective, or transmissive liquid crystal display panel), and the display device may also include structures such as a housing, a main board, a processing module, a storage module, and a communication module.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示基板，包括：衬底(1)；及位于衬底(1)上的多个像素单元(10)，多个像素单元(10)呈阵列排布；其中，显示基板还包括多个信号线(25)，对于多个信号线(25)中的每一个信号线，信号线(25)沿列方向排列并位于在行方向上相邻的第一像素单元(10A)和第二像素单元(10B)之间，信号线(25)与第一像素单元(10A)的第一像素电极(40A)以及第二像素单元(10B)的第二像素电极(40B)均不同层设置，信号线(25)包括并联且在列方向上延伸的第一分支线(252)和第二分支线(253)；第一分支线(252)在衬底(1)上的正投影与第一像素电极(40A)在衬底(1)上的正投影至少部分重合；第二分支线(253)在衬底(1)上的正投影与第二像素电极(40B)在衬底(1)上的正投影至少部分重合。还包括一种显示面板以及一种制作显示基板的方法。

Description

显示基板、显示面板及显示基板的制作方法
本公开要求在2020年6月12日提交中国专利局、申请号为202010534674.5、名称为“显示基板、显示面板及显示基板的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开的实施例涉及一种显示基板、显示面板及显示基板的制作方法。
背景技术
在显示领域，以液晶显示为例，显示面板的不同灰阶亮度，是通过在阵列基板的像素电极与对置基板的公共电极之间施加不同的电压不同来实现的。具体来说，信号线的信号通过薄膜晶体管(TFT)的作用存储到像素电极上，信号线(data line)上的电压不同，存储到像素电极上的电压就不同，从而与对置基板的公共电极之间的电压差就不同，进而驱动液晶偏转不同幅度，实现不同的灰阶画面。
发明内容
本公开的至少一个实施例提供了一种显示基板，包括衬底及位于所述衬底上的多个像素单元，多个像素单元呈阵列排布，其中，所述显示基板还包括多个信号线，对于所述多个信号线中的每一个信号线，所述信号线沿列方向排列并位于在行方向上相邻的第一像素单元和第二像素单元之间，所述信号线与所述第一像素单元的第一像素电极以及所述第二像素单元的第二像素电极均不同层设置，所述信号线包括并联且在列方向上延伸的第一分支线和第二分支线；所述第一分支线在所述衬底上的正投影与第一像素电极在所述衬底上的正投影至少部分重合；以及所述第二分支线在所述衬底上的正投影与第二像素电极在所述衬底上的正投影至少部分重合。
在本公开的一个实施例中，施加于所述多个信号线中的两个相邻信号线上的电压的极性相反。
在本公开的一个实施例中，所述信号线还包括干线、第一桥接部及第二桥接部，所述第一桥接部连接所述第一分支线和所述干线，所述第二桥接部连接所述第二分支线 和所述干线。
在本公开的一个实施例中，所述第一桥接部与所述干线垂直，所述第二桥接部与所述干线垂直；或者，所述第一桥接部与所述干线成钝角设置，所述第二桥接部与所述干线成钝角设置。
在本公开的一个实施例中，所述信号线还包括与所述第一分支线及所述第二分支线连接的干线，所述第一分支线和第二分支线的宽度之和不小于所述干线的宽度。
在本公开的一个实施例中，所述第一分支线具有面向所述第二分支线的第一侧边；所述第二分支线具有面向所述第一分支线的第二侧边；第一像素电极具有面向第二像素电极的第三侧边；第二像素电极具有面向所述第一像素电极的第四侧边；以及所述第一侧边、第三侧边、第四侧边、第二侧边沿行方向顺次设置。
在本公开的一个实施例中，所述第一侧边与第三侧边在行方向上的距离等于所述第二侧边与第四侧边在行方向上的距离。
在本公开的一个实施例中，所述第一侧边与第三侧边在行方向上的距离不小于2.5μm，所述第二侧边与第四侧边在行方向上的距离不小于2.5μm。
在本公开的一个实施例中，所述显示基板包括存储电极和多个薄膜晶体管，所述存储电极与所述薄膜晶体管的栅极同层设置，所述薄膜晶体管的漏极与所述像素电极电性相连，所述存储电极与所述薄膜晶体管的漏极形成存储电容。
在本公开的一个实施例中，所述漏极的面积与像素电极的面积的比值大于等于0.1且小于1。
在本公开的一个实施例中，所述第一分支线与所述存储电极在行方向上的距离不小于2.5um，所述第二分支线与存储电极在行方向上的距离不小于2.5μm。
在本公开的一个实施例中，所述像素电极为反射电极，所述像素电极具有背向所述衬底的反射面。
在本公开的一个实施例中，沿行方向相邻设置的两个像素电极在行方向上的距离为3μm～5μm。
在本公开的一个实施例中，所述信号线由具有反射性的金属材料制成。
本公开的至少一个实施例提供了一种显示面板，包括上述显示基板。
在本公开的一个实施例中，所述显示面板为反射型液晶面板、半反半透型液晶 面板或透射型液晶面板中的一种。
本公开的至少一个实施例提供了一种显示基板的制作方法，包括：提供衬底；在所述衬底上形成多个像素单元及多个信号线，所述多个像素单元呈阵列排布，每个所述像素单元均包括像素电极；在列方向上相邻的两个像素单元之间形成信号线，所述信号线与所述像素单元的所述像素电极不同层设置；其中，所述信号线沿列方向排列并位于在行方向上相邻的第一像素单元和第二像素单元之间，所述信号线与所述第一像素单元的第一像素电极以及所述第一像素单元的第二像素电极均不同层设置，所述信号线包括并联且在列方向上延伸的第一分支线和第二分支线；所述第一分支线在所述衬底上的正投影与第一像素电极在所述衬底上的正投影至少部分重合；以及，所述第二分支线在所述衬底上的正投影与第二像素电极在所述衬底上的正投影至少部分重合。
通过将信号线与像素电极设置为不同层，并使信号线的第一分支线、第二分支线分别与两个相邻像素电极在竖向上部分重合，降低、消除或改善信号线与像素电极之间的寄生电容，避免或降低所述寄生电容对像素电极和公共电极之间的电压差产生影响，从而改善显示效果。
附图说明
图1是一种显示基板的俯视示意图，其中绝缘膜层未进行显示。
图2是采用列反转驱动时第N-1帧信号和第N帧信号的示意图。
图3是图1所示的显示基板产生串扰的原理图。
图4示出了根据本公开一个实施例的显示基板的侧视示意图。
图5是图1所示的显示基板的俯视示意图，其中衬底、有机绝缘层、无机层绝缘层等结构未进行显示。
图6是图5所示的显示基板的一个像素单元的俯视示意图。
图7是图5的局部放大图，为便于理解，以图案对薄膜晶体管、电极组、信号线进行填充。
图8示出了根据本公开的另一实施例的显示面板的俯视示意图，其中衬底、有机绝缘层、无机层绝缘层等结构未进行显示。
图9是图5的局部放大图，为便于理解，仅显示薄膜晶体管、电极组、信号线 等结构，且以图案对薄膜晶体管、电极组、信号线进行填充。
图10是图5沿A-A线的剖视示意图。
图11是图5沿B-B线的剖视示意图。
图12示出了本公开的一个实施例的显示面板的侧视示意图。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出，“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
请结合图1，像素电极40'通过薄膜晶体管20'及信号线25'接收驱动芯片的信号。其中，像素电极40'和左侧的信号线25'形成第一寄生电容Cpd L，像素电极40'和右侧的信号线25”形成第二寄生电容Cpd R。由于工艺的原因，很难保证像素电极40'与左侧的信号线25'的横向距离等于像素电极40'与右侧的信号线25”的横向距离，而电容值与距离负相关(C＝εS/(4πkd)，ε表示介电常数，S表示两板正对面积，k表示静电 力常量，d表示两板间距离)，距离不相等导致第一寄生电容Cpd L与第二寄生电容Cpd R的电容值不相等。以列反转方式驱动为例，相邻两个信号线25'、25”电压极性相反，因此第一寄生电容Cpd L与第二寄生电容Cpd R的极性相反，但第一寄生电容Cpd L与第二寄生电容Cpd R电容值不相等，第一寄生电容Cpd L与第二寄生电容Cpd R对像素电极的作用不能相互抵消，即寄生电容Cpd对像素电极的影响依然存在。而且，最终的寄生电容的极性取决于像素电极与哪一个信号线的距离更近，例如像素电极40'与左侧的信号线25'距离更近，则对应第一寄生电容Cpd L的电容值更大，寄生电容Cpd的电容极性与第一寄生电容Cpd L相同。
请结合图2及图3中的(a)，当以列反转方式对像素电极进行驱动时，信号自上向下(如箭头所示)进行扫描。在当前时刻下，上一帧信号(负帧信号)扫描完毕，正帧信号扫描到黑色画面(+5V区域)，像素电极的上部分电压保持为+2V(正帧信号已扫描完成)，像素电极的下部分电压保持为-2V(正帧信号还未扫描到)，中间L0灰阶的像素电压为﹢5V，四周L127灰阶的像素电压为+2V。
请结合图3中的(a)及图3中的(b)，当处于上述时刻时，中间L0灰阶显示，整个数据线电压为﹢5V(公共电极的电压为0V)，由于寄生电容Cpd的存在，此时显示基板的上侧像素电极由﹢2V向﹢5V拉动，例如电压被拉动到至﹢3V，像素电极与公共电极之间的电压差为﹢3V(画面相对L127变黑)；显示基板的下侧像素电极由-2V往+5V拉动，例如电压被拉动到-1V，那么像素电极与公共电极之间的电压差为-1V(画面相对L127变亮)。当中间图案与周边图案存在差异时，中间图案的数据信号对上下保持阶段的像素电压进行拉动。由于画面中上下两部分的像素电极被拉动至不同电压，导致上下部分的像素电极与公共电极之间的电压差发生变化，且此变化无法抵消，进而导致垂直方向的串扰(Crosstalk)的产生。
本公开的至少一个实施例提供一种显示基板，显示基板包括衬底及位于衬底上的多个像素单元，多个像素单元呈多行多列排布，每个像素单元均包括像素电极。其中，位于同一行的、相邻的两个像素单元之间设置有信号线，信号线与像素单元的像素电极不同层设置，信号线包括相连的第一分支线和第二分支线；第一分支线在衬底上的正投影，与相邻的两个像素单元中的一个的像素电极在衬底上的正投影部分重合；第二分支线在衬底上的正投影，与相邻的两个像素单元中的另一个的像素电极在衬底上的正投影部分重合。
请结合图4及图5，根据本公开的一个实施例的显示基板例如为阵列基板，包括衬底1、在垂直于所述衬底1的方向上依次设置的薄膜晶体管层2、无机绝缘层3及像素电极层4。图4中所示的方向Z为垂直于所述衬底1的方向。在其它实施方式中，无机绝缘层3也可替换为其它类型的绝缘层，比如，有机绝缘材质和无机绝缘材质的复合层或叠层等，只要能起到电性隔离的作用即可。所述薄膜晶体管层2包括多个薄膜晶体管20，所述像素电极层4包括多个像素电极40。
在该实施例中，所述薄膜晶体管20包括有源层21(参图11)、源极22、漏极23及栅极24，薄膜晶体管层2可理解为这几个膜层的结合。所述源极22和漏极23同层设置，同一行薄膜晶体管的栅极24通过扫描线27电性连接。所述显示基板还包括栅极绝缘层5(参图11)、有机绝缘层6(参图11)、多个信号线25、多个存储电极26。所述栅极24、栅极绝缘层5、有源层21、源极22(或漏极23和信号线25)、有机绝缘层6、无机绝缘层3、像素电极层4沿方向Z顺次设置。在该实施例中，所述信号线25与源极22、漏极23同层设置，所述存储电极26与栅极24同层设置。同层设置可理解为在同一图形化工艺中形成，这样有利于简化显示基板的制作工艺。在本公开的其他实施方式中，信号线25及存储电极26也可以设置在其他膜层。所述存储电极26配置为与漏极23形成存储电容，漏极23与像素电极层4的像素电极40电性相连因此电势相等，即相当于在存储电极26和像素电极40之间形成存储电容，存储电容配置为存储一部分电量，使信号线的电压消失后画面仍能保持一段时间；所述存储电极还被配置为还用于为对置基板侧的公共电极提供公共信号(或者说接地信号)，两者可通过支撑于显示基板和对置基板之间的导电支撑柱或导电胶进行电性连接。在该实施例中，所述存储电极26是一个整体(为清楚的示意出不同的像素单元，存储电极26在相邻的像素单元10之间示意有分界线，实际不存在)且接地。在本公开的其他实施方式中，所述显示基板中设置有多个分别接地的存储电极26。
根据本公开实施例的显示基板适用于液晶显示，像素电极与对置基板侧的公共电极被施加电压后所形成的电场，会驱使液晶偏转以进行显示。像素电极与薄膜晶体管20的漏极23电性相连，所述信号线25与薄膜晶体管20的源极22电性相连，从而使得像素电极能够通过信号线25和薄膜晶体管20接收驱动芯片(未图示)的驱动信号。
在本公开的一个实施例中，显示基板适用于反射型液晶面板，而漏极23设置于反射电极(即像素电极)的下方，这使得漏极23不会影响出光，因而漏极23的面积可以设计的较大，例如不小于像素单元面积(也可理解为像素电极的面积)的1/10，增加 漏极23的面积，可以增大漏极23与存储电极26之间的存储电容，使当前显示的画面在驱动电压消失后能更好地保持到下一个画面。理论上，漏极的面积可以无限接近于像素单元的面积，即两者比值接近1。但实际中，也需考虑漏极的面积对其他电学参数的影响。
请结合图5至图7，所述显示基板包括多个阵列排布的像素单元10，每个像素单元10包括像素电极40，每一像素电极40连接至对应的薄膜晶体管20，当然，像素单元10还可以包括其他绝缘膜层，例如无机绝缘层3。所述信号线25设置于沿行方向X上相邻的两个像素单元10之间，这里的“设置于……之间”可理解部分设置于，也可以理解为完全设置于，进一步的，只要信号线25在衬底1上的投影有部分位于两个像素单元10在衬底上的投影之间即可。
所述信号线25包括干线251、第一分支线252、第二分支线253、第一桥接部254及第二桥接部255，所述第一桥接部254连接干线251和第一分支线252，所述第二桥接部255连接干线251和第二分支线253。也就是说，第一分支线252与第一桥接部254串联，第二分支线253与第二桥接部255串联，之后两个串联电路并联。干线251、第一分支线252、第二分支线253、第一桥接部254及第二桥接部255组成一个信号线单元，信号线25可看作为首尾相连且沿列方向Y排列的多个信号线单元构成，每个信号线单元对应(连接)一个薄膜晶体管20。
请结合图5至图7，在行方向上相邻的两个像素单元10A和10B(对应的像素电极40A、40B也相邻)中，信号线25的第一分支线252在衬底1上的正投影与像素单元10A的像素电极40A在衬底1上的正投影至少部分重合，信号线25的第二分支线253在衬底1上的正投影与与像素单元10B的像素电极40B在衬底1上的正投影至少部分重合。
像素电极40与左侧的信号线25A形成第一寄生电容Cpd L，像素电极40与信号线与右侧的信号线25B形成第二寄生电容Cpd R，由于信号线25A、25B与像素电极40位于不同层并且正投影至少部分重合，理论上，第一寄生电容Cpd L及第二寄生电容Cpd R与它们在行方向X上的距离不相关(或几乎不相关)。即影响第一寄生电容Cpd L及第二寄生电容Cpd R的主要为信号线25A、25B与像素电极40在竖向Z上的距离。即使因工艺问题导致了行方向的偏差也不会影响寄生电容，即信号线与两个像素电极之间的寄生电容是否存在偏差而仅与竖向Z上的距离相关。从工艺上来讲，竖向Z上的间距是容易控制的。只要保证像素电极与信号线之间的膜层厚度均匀，即可保证第一寄生电容Cpd L 和Cpd r的电容值相等，当然，前提是保证Cpd L和Cpd r对应的其他参数保持一致，例如材料相同和正对面积相等。
在本公开的一些实施例中，相邻两个信号线的电压极性相反，从而使得第一寄生电容Cpd L和第二寄生电容Cpd R极性相反，而两者电容值相等，因而Cpd L和Cpd r对像素电极的影响能够相互抵消(或者说信号线对像素电极的电压拉动相互抵消)，藉此可消除信号线对像素电极的电压的影响，使像素电极与对置基板侧公共电极之间的电压差保持不变，保证画面灰阶不受寄生电容的影响，从而改善垂直方向的串扰。
在本公开的一些实施例中，干线251与第一桥接部254呈垂直状态，干线251与第二桥接部255呈垂直状态，从而使得干线251、第一桥接部254、第二桥接部255整体呈“T”字形。需要注意的是，由于工艺原因，“垂直”可能有一定偏差，例如，干线251与第一桥接部254(或第二桥接部255)之间的连接部呈圆弧状或具有其他曲线形状；或者，因工艺原因，干线251与第一桥接部254(或第二桥接部255)之间的夹角可能存在一定偏差，例如，该夹角可能为85°-95°。通过实验验证，采用上述实施方式的信号线结构，可使垂直方向的信号串扰降为0，即LV0，从而避免对像素电极和公共电极之间的电压差造成影响，有利于改善显示效果。
在本公开的一些实施例中，信号线25可能具有其他结构变。请结合图8，信号线25的干线251与第一桥接部254、第二桥接部255也可以成其他角度，例如钝角，其他结构则与图5所示的实施方式类似。类似的，干线251与第一桥接部254(或第二桥接部255)之间也可以通过圆弧等曲线进行过渡。在本公开的一些实施例中，在自干线251引出第一桥接部254和第二桥接部255的位置相同的情况下，第一桥接部254和第一分支线252的串联电路总长度及第二桥接部255和第二分支线253的串联电路总长度均小于前述实施方式的对应的串联电路长度，因而有利于进一步减小信号线的阻抗，从而有利于对像素电极的驱动。
请继续结合图7及图9，在本公开的一些实施例中，所述干线251的宽度L1为3um(在与薄膜晶体管的源极相连的区域宽度略大，图中未进行显示)，第一分支线252的宽度L2、第二分支线253的宽度L3、第一桥接部254的宽度L4、第二桥接部255的宽度L5均为3um。在信号线25的非干线段(第一分支线252、第二分支线253、第一桥接部254、第二桥接部255)为并联电路，由于信号线不同区域的厚度、材料均是相同的，因而非干线段的单位长度的阻抗仅为干线段的单位长度的阻抗的一半，阻抗降低有利于对像素电极的驱动。在本公开的一些实施例中，只要保证第一分支线252和第二分 支线253的宽度之和(或者第一桥接部254和第二桥接部255的宽度之和)大于干线251的宽度，即可以达到降低阻抗的目的。这里的“宽度”可理解为垂直于延伸方向的方向上的尺寸，该垂直于延伸方向的方向为第一分支线252与第二分支线253的排列方向，即行方向X。
由于信号线25设置于像素电极40的正下方，不会占用相邻像素电极40之间的空间，因而有利于增大像素电极的面积，能被驱动的液晶面积增大，进而有利于提升显示效果。在本公开的一些实施例中，如图10所示，像素电极40为反射电极，所述像素电极40具有背向所述衬底1的反射面41，用于将光线向背离所述衬底1的方向反射，亦即液晶面板为反射型液晶面板。反射面41的面积由像素电极40确定，因而与像素电极40的面积正相关。反射面41的面积随像素电极40的面积的增大而增大，因而有利于对更多光线进行反射，从而增大显示面板的亮度，进而提升显示效果。此外，在反射式液晶显示面板中，像素电极无需透光，因此即便选用不透光的金属信号线并将其分支线设置在像素电极的正下方，也不会影响像素开口率。在本公开的一些实施例中，显示面板还可以是包括背光源的半反半透液晶面板或透射型液晶面板。
请结合图6、图7及图9，相邻的两个像素电极之间的距离d1为3～5μm，在此距离范围内，可以保证良好的显示效果，同时对制作工艺的要求也较低。在本公开的一些实施例中，为保证良好的显示效果，同时也避免因像素间距过小而导致相邻像素之间的混色，相邻的两个像素电极之间的距离d1为4～5μm，在本公开的一些实施例中，d1为5μm。当然，也可以将相邻的两个像素电极之间的距离d1设置为小于3μm。
所述第一分支线252具有面向所述第二分支线253的第一侧边a，所述第二分支线253具有面向所述第一分支线252的第二侧边b，像素电极40A(与第一分支线252的投影部分重合)具有面向像素电极40B(与第二分支线253的投影部分重合)的第三侧边c；像素电极40B具有面向像素电极40A的第四侧边d。所述第一桥接部254具有面向薄膜晶体管20的第五侧边e，所述像素电极40B包括面向薄膜晶体管20的第六侧边f，该薄膜晶体管20的漏极与像素电极40B电性连接。所述第一侧边a、第三侧边c、第四侧边d、第二侧边b沿行方向X顺次设置，且均沿列方向Y延伸；第五侧边e及第六侧边f沿行方向X延伸。换言之，第一分支线252和第二分支线253的正投影不会落在行方向上相邻的两个像素电极之间。
为了使第一寄生电容Cpd L和第二寄生电容Cpd R能够完全抵消，进一步改善垂直方向上的串扰，第一侧边a和第三侧边c的距离d2等于第二侧边b和第四侧边d的距 离d3。为进一步保证第一寄生电容Cpd L和第二寄生电容Cpd R能够完全抵消(即电容值相等且极性相反)，进而消除垂直方向上的串扰，在本公开的一些实施例中，d2不小于2.5μm，d3不小于2.5μm。所述第五侧边e和第六侧边f的距离d4不小于2.5μm。本实施方式中，d2＝d3＝d4＝3.5μm。即使信号线25(或者说第一分支线252和第二分支线253)在行方向X上存在微小的位置偏差，由于第一侧边a和第三侧边c的距离d2及第二侧边b和第四侧边d的距离d3的存在，仍能保证信号线25与像素电极40的正对面积不改变，从而保证Cpd L和Cpd r的电容值相等，进而避免串扰。
进一步的，为了避免第一分支线252与存储电极26产生寄生电容及第二分支线253与存储电极26产生寄生电容，进而影响像素电极的电位而造成信号串扰，所述第一分支线252与相邻的存储电极26(即第一分支线252左侧的存储电极；因为第一分支线252与其右侧的存储电极的距离更大)的横向距离d5(标号参见图5)不小于2.5μm，所述第二分支线253与相邻的存储电极26的横向距离d6(标号参见图7)不小于2.5μm，本实施方式中d5＝d6＝4μm。
下面结合图4、图5、图10及图11，简单介绍所述显示基板的制作方法。
在衬底1上形成薄膜晶体管层2。在本公开的一些实施例中，在衬底1(或者衬底1上的缓冲层)上，通过同一图形化工艺形成栅极24及存储电极26；在栅极24及存储电极26上形成栅极绝缘层5；在栅极绝缘层5上形成有源层21；在有源层21上形成源漏电极层，源漏电极层包括源极22、漏极23及与源极22电性连接的信号线25。
而后，在所述薄膜晶体管层2上形成有机绝缘层6；在所述有机绝缘层6上形成无机绝缘层3；在所述无机绝缘层3上形成像素电极层4，其中，像素电极层4内的像素电极40通过过孔30与薄膜晶体管的漏极23(参看图5)电性连接，所述过孔30贯穿有机绝缘层6及无机绝缘层3。
在本公开的一些实施例中，信号线25可由银等具有反射性的金属材料制成。
在本公开的一些实施例中，有机绝缘层6采用有机材料制成，例如正性聚甲基丙烯酸甲酯、负性聚甲基丙烯酸甲酯等介电常数较大的有机材料，介电常数较大的有机绝缘层6用于减小信号线25与像素电极40的寄生电容。在本公开的一些实施例中，所述有机绝缘层6的厚度为1-3μm，在此厚度下，有机绝缘层能够有效减小信号线与像素电极的寄生电容，同时对显示基板的整体厚度影响较小。所述无机绝缘层3配置为进一步减小信号线与像素电极的寄生电容，同时无机绝缘层3还用作平坦化层，为像素电极 提供较为平整的表面，有利于改善像素电极的膜层质量。
本公开的至少一个实施例还提供了一种显示面板，所述显示面板可以是反射型液晶面板、半反半透型液晶面板或透射型液晶面板。请结合图12，所述显示面板包括对置基板200、液晶层300及如前述任一实施方式所述的显示基板100。所述对置基板200可以为彩膜基板，其包括彩色滤光片(CF，Color Filter)、公共电极等结构。所述显示面板还可以包括导电支撑柱，所述导电支撑柱设置在液晶层300内，配置为对对置基板200和显示基板100进行支撑，并且导电支撑柱可电性连接公共电极和所述存储电极26(参图5和图6)，从而为公共电极提供COM信号(通常为接地信号)。
本公开的至少一个实施例还提供了一种显示装置，所述显示装置可以是手机、平板电脑、显示器、电视机等显示设备。所述显示装置可以包括前述的显示面板(反射型、半反半透型或透射型液晶显示面板)，显示装置还可以包括外壳、主板、处理模块、存储模块、通讯模块等结构。
以上所述仅是本公开的较佳实施方式而已，并非对本公开做任何形式上的限制，虽然本公开已以较佳实施方式揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (17)

  1. 一种显示基板，包括：
    衬底；及
    位于所述衬底上的多个像素单元，所述多个像素单元呈阵列排布；
    其中，所述显示基板还包括多个信号线，对于所述多个信号线中的每一个信号线，所述信号线沿列方向排列并位于在行方向上相邻的第一像素单元和第二像素单元之间，所述信号线与所述第一像素单元的第一像素电极以及所述第二像素单元的第二像素电极均不同层设置，所述信号线包括并联且在列方向上延伸的第一分支线和第二分支线；所述第一分支线在所述衬底上的正投影与第一像素电极在所述衬底上的正投影至少部分重合；所述第二分支线在所述衬底上的正投影与第二像素电极在所述衬底上的正投影至少部分重合。
  2. 根据权利要求1所述的显示基板，其中，施加于所述多个信号线中的两个相邻信号线上的电压的极性相反。
  3. 根据权利要求1或2所述的显示基板，其中，所述信号线还包括干线、第一桥接部及第二桥接部，所述第一桥接部连接所述第一分支线和所述干线，所述第二桥接部连接所述第二分支线和所述干线。
  4. 根据权利要求3所述的显示基板，其中，所述第一桥接部与所述干线垂直，所述第二桥接部与所述干线垂直；或者，所述第一桥接部与所述干线成钝角设置，所述第二桥接部与所述干线成钝角设置。
  5. 根据权利要求3或4所述的显示基板，其中，所述信号线还包括与所述第一分支线及所述第二分支线连接的干线，所述第一分支线和第二分支线的宽度之和不小于所述干线的宽度。
  6. 根据权利要求1至5中任何一项所述的显示基板，其中，所述第一分支线具有面向所述第二分支线的第一侧边；
    所述第二分支线具有面向所述第一分支线的第二侧边；
    第一像素电极具有面向第二像素电极的第三侧边；
    第二像素电极具有面向所述第一像素电极的第四侧边；以及
    所述第一侧边、第三侧边、第四侧边、第二侧边沿行方向顺次设置。
  7. 根据权利要求6所述的显示基板，其中，所述第一侧边与第三侧边在行方向上的距离等于所述第二侧边与第四侧边在行方向上的距离。
  8. 根据权利要求6或7所述的显示基板，其中，所述第一侧边与第三侧边在行方向上的距离不小于2.5μm，所述第二侧边与第四侧边在行方向上的距离不小于2.5μm。
  9. 根据权利要求1至8中任何一项所述的显示基板，其中，所述显示基板包括存储电极和薄膜晶体管，所述存储电极与所述薄膜晶体管的栅极同层设置，所述薄膜晶体管的漏极与所述像素电极相连，所述存储电极与所述薄膜晶体管的漏极形成存储电容。
  10. 根据权利要求9所述的显示基板，其中，所述漏极的面积与像素电极的面积的比值大于等于0.1且小于1。
  11. 根据权利要求10所述的显示基板，其中，所述第一分支线与所述存储电极在行方向上的距离不小于2.5μm，所述第二分支线与存储电极在行方向上的距离不小于2.5μm。
  12. 根据权利要求1至11中任何一项所述的显示基板，其中，所述像素电极为反射电极，所述像素电极具有背向所述衬底的反射面。
  13. 根据权利要求1至12中任何一项所述的显示基板，其中，沿行方向相邻设置的两个像素电极之间的距离为3μm～5μm。
  14. 根据权利要求1至13中任何一项所述的显示基板，其中，所述信号线由具有反射性的金属材料制成。
  15. 一种显示面板，包括如权利要求1-14中任一项所述的显示基板。
  16. 根据权利要求15所述的显示面板，其为反射型液晶面板、半反半透型液晶面板或透射型液晶面板中的一种。
  17. 一种显示基板的制作方法，包括：
    提供衬底；
    在所述衬底上形成多个像素单元，所述多个像素单元呈阵列排布，每个所述像素单元均包括像素电极；
    在列方向上相邻的两个像素单元之间形成信号线，所述信号线与所述像素单元的所述像素电极不同层设置；
    其中，所述信号线沿列方向排列并位于在行方向上相邻的第一像素单元和第二像素单元之间，所述信号线与所述第一像素单元的第一像素电极以及所述第一像素单元的第二像素电极均不同层设置，所述信号线包括并联且在列方向上延伸的第一分支线和第二分支线；所述第一分支线在所述衬底上的正投影与第一像素电极在所述衬底上的正投影至少部分重合；所述第二分支线在所述衬底上的正投影与第二像素电极在所述衬底上的正投影至少部分重合。
PCT/CN2021/095818 2020-06-12 2021-05-25 显示基板、显示面板及显示基板的制作方法 WO2021249182A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/775,430 US20220382110A1 (en) 2020-06-12 2021-05-25 Display substrates, display panels and methods of manufacturing display substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010534674.5A CN113805392A (zh) 2020-06-12 2020-06-12 显示基板、显示面板及显示基板的制作方法
CN202010534674.5 2020-06-12

Publications (1)

Publication Number Publication Date
WO2021249182A1 true WO2021249182A1 (zh) 2021-12-16

Family

ID=78845198

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/095818 WO2021249182A1 (zh) 2020-06-12 2021-05-25 显示基板、显示面板及显示基板的制作方法

Country Status (3)

Country Link
US (1) US20220382110A1 (zh)
CN (1) CN113805392A (zh)
WO (1) WO2021249182A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11686984B2 (en) 2021-01-29 2023-06-27 Hefei Boe Optoelectronics Technology Co., Ltd. Array substrate and reflective display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591151A (zh) * 2003-09-02 2005-03-09 夏普株式会社 有源元件衬底及使用该衬底的液晶显示装置
US20070236414A1 (en) * 2006-03-28 2007-10-11 Hsiang-Lin Lin Liquid Crystal Display
US20100002159A1 (en) * 2008-07-04 2010-01-07 Chia-Chiang Hsiao Liquid crystal display panel and pixel structure thereof
CN101630685A (zh) * 2008-07-19 2010-01-20 卡西欧计算机株式会社 薄膜晶体管阵列基板
US20120194414A1 (en) * 2007-07-30 2012-08-02 Woo-Geun Lee Liquid crystal display
CN107272292A (zh) * 2017-08-18 2017-10-20 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001290172A (ja) * 1995-08-11 2001-10-19 Sharp Corp 液晶表示装置
JPH10253988A (ja) * 1997-03-11 1998-09-25 Toshiba Corp 液晶表示装置
KR100862240B1 (ko) * 2002-07-31 2008-10-09 엘지디스플레이 주식회사 반사형 액정표시장치와 그 제조방법
CN100504553C (zh) * 2004-02-06 2009-06-24 三星电子株式会社 薄膜晶体管阵列面板及包括该薄膜晶体管阵列面板的液晶显示器
KR20070028138A (ko) * 2005-09-07 2007-03-12 삼성전자주식회사 박막트랜지스터 표시판 및 이를 포함하는 액정 표시 장치
KR20070074344A (ko) * 2006-01-09 2007-07-12 삼성전자주식회사 박막 트랜지스터 기판과 그 제조 방법 및 이를 포함한 액정표시 장치
KR20090123247A (ko) * 2008-05-27 2009-12-02 삼성전자주식회사 표시 장치
CN101520583B (zh) * 2009-04-27 2012-03-21 友达光电股份有限公司 像素结构及其驱动方法、以及显示器的驱动方法
CN105572996B (zh) * 2016-02-02 2019-01-25 京东方科技集团股份有限公司 一种双栅极阵列基板及显示装置
CN105652543A (zh) * 2016-03-31 2016-06-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示器件
CN106886112B (zh) * 2017-04-27 2020-07-24 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591151A (zh) * 2003-09-02 2005-03-09 夏普株式会社 有源元件衬底及使用该衬底的液晶显示装置
US20070236414A1 (en) * 2006-03-28 2007-10-11 Hsiang-Lin Lin Liquid Crystal Display
US20120194414A1 (en) * 2007-07-30 2012-08-02 Woo-Geun Lee Liquid crystal display
US20100002159A1 (en) * 2008-07-04 2010-01-07 Chia-Chiang Hsiao Liquid crystal display panel and pixel structure thereof
CN101630685A (zh) * 2008-07-19 2010-01-20 卡西欧计算机株式会社 薄膜晶体管阵列基板
CN107272292A (zh) * 2017-08-18 2017-10-20 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11686984B2 (en) 2021-01-29 2023-06-27 Hefei Boe Optoelectronics Technology Co., Ltd. Array substrate and reflective display panel

Also Published As

Publication number Publication date
CN113805392A (zh) 2021-12-17
US20220382110A1 (en) 2022-12-01

Similar Documents

Publication Publication Date Title
US10670930B2 (en) Liquid crystal display capable of preventing display defect and rubbing failure
US9030504B2 (en) Display panel and method of driving the same
JP3321807B2 (ja) 液晶パネル用基板，液晶パネル及びそれを用いた電子機器並びに液晶パネル用基板の製造方法
KR101896377B1 (ko) 베젤이 최소화된 액정표시소자
US8816350B2 (en) Array substrate, liquid crystal panel, liquid crystal display device, and television receiver
JP5590764B2 (ja) 液晶表示装置
US7760304B2 (en) Liquid crystal display device and electronic apparatus for the reduction of color in a white display
WO2021232986A1 (zh) 像素电极、像素结构、显示面板及显示装置
US8208098B2 (en) Organic light emitting diode display and driving method thereof
GB2421832A (en) Liquid crystal display device using in-plane switching mode
US7800570B2 (en) LCD device capable of controlling a viewing angle and method for driving the same
JP5442754B2 (ja) アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機
WO2021239050A1 (zh) 显示组件和显示装置
JP5179670B2 (ja) 液晶表示装置
WO2010089820A1 (ja) アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機
WO2011010417A1 (ja) アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機
JPH10142577A (ja) 液晶表示装置及びその駆動方法
WO2013037236A1 (zh) 阵列基板及液晶显示面板
TW567371B (en) Display device
WO2021249182A1 (zh) 显示基板、显示面板及显示基板的制作方法
WO2021223488A1 (zh) 显示基板、显示面板及显示装置
WO2010127515A1 (zh) 显示面板
JP2010250265A (ja) 液晶表示装置および電子機器
JP2004145346A (ja) 液晶表示装置及びその製造方法
WO2019084979A1 (zh) 显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21822156

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21822156

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21822156

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 29.06.2023)