CN113805392A - 显示基板、显示面板及显示基板的制作方法 - Google Patents
显示基板、显示面板及显示基板的制作方法 Download PDFInfo
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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Abstract
本发明提供一种显示基板、显示面板及显示基板的制作方法,显示基板包括衬底及位于衬底上的多个像素单元,多个像素单元呈多行多列排布,每个像素单元均包括像素电极。其中,位于同一行的、相邻的两个像素单元之间设置有信号线,信号线与像素单元的像素电极不同层设置,信号线包括相连的第一分支线和第二分支线;第一分支线在衬底上的正投影,与相邻的两个像素单元中的一个的像素电极在衬底上的正投影部分重合;第二分支线在衬底上的正投影,与相邻的两个像素单元中的另一个的像素电极在衬底上的正投影部分重合。通过降低、消除或改善信号线与像素电极之间的寄生电容,避免寄生电容对像素电极和公共电极之间的电压差产生影响,从而改善显示效果。
Description
技术领域
本发明涉及显示领域,尤其涉及一种显示基板、显示面板及显示基板的制作方法。
背景技术
在显示领域,以液晶显示为例,显示面板的不同灰阶亮度,是由阵列基板的像素电极与对置基板的公共电极(com电极)之间的电压差不同来实现的。具体来说,信号线的信号通过薄膜晶体管(TFT)的作用存储到像素电极上,信号线(data line)上的电压不同,存储到像素电极上的电压就不同,从而与对置基板的公共电极之间的电压差就不同,进而驱动液晶偏转不同幅度,实现不同的灰阶画面。但是,在显示效果方面,尤其是在灰阶画面的显示方面,仍有改善的空间。
发明内容
为解决上述技术问题,本发明提供一种显示基板、显示面板及显示基板的制作方法,其通过降低、消除或改善信号线与像素电极之间的寄生电容,避免或降低所述寄生电容对像素电极和公共电极之间的电压差产生影响,从而改善显示效果。
本发明提供一种显示基板,显示基板包括衬底及位于衬底上的多个像素单元,多个像素单元呈多行多列排布,每个像素单元均包括像素电极。其中,位于同一行的、相邻的两个像素单元之间设置有信号线,信号线与像素单元的像素电极不同层设置,信号线包括相连的第一分支线和第二分支线;第一分支线在衬底上的正投影,与相邻的两个像素单元中的一个的像素电极在衬底上的正投影部分重合;第二分支线在衬底上的正投影,与相邻的两个像素单元中的另一个的像素电极在衬底上的正投影部分重合。
进一步的,施加于相邻的两个所述信号线的电压的极性相反。
进一步的,所述信号线还包括干线、第一桥接部及第二桥接部,所述第一桥接部连接所述第一分支线和所述干线,所述第二桥接部连接所述第二分支线和所述干线。
进一步的,所述第一桥接部与所述干线成垂直状态,所述第二桥接部与所述干线成垂直状态;或者,所述第一桥接部与所述干线成钝角设置,所述第二桥接部与所述干线成钝角设置。
进一步的,所述第一分支线具有面向所述第二分支线的第一侧边,所述第二分支线具有面向所述第一分支线的第二侧边;与所述第一分支线投影部分重合的像素电极具有第三侧边,所述第三侧边面向与所述第二分支线投影部分重合的像素电极;与所述第二分支线投影部分重合的像素电极具有第四侧边,所述第四侧边面向与所述第一分支线投影部分重合的像素电极;所述第一侧边、第三侧边、第四侧边、第二侧边沿行方向顺次设置。
进一步的,所述第一侧边与第三侧边在行方向上的距离,等于所述第二侧边与第四侧边在行方向上的距离。
进一步的,所述第一侧边与第三侧边在行方向上的距离不小于2.5um,所述第二侧边与第四侧边在行方向上的距离不小于2.5um。
进一步的,所述显示基板包括存储电极和多个薄膜晶体管,所述存储电极与所述薄膜晶体管的栅极同层设置,所述薄膜晶体管的漏极与所述像素电极电性相连,所述存储电极与所述薄膜晶体管的漏极形成存储电容。
进一步的,所述漏极的面积与像素电极的面积的比值大于等于0.1且小于1。
进一步的,所述第一分支线与所述存储电极在行方向上的距离不小于2.5um,所述第二分支线与存储电极在行方向上的距离不小于2.5um。
进一步的,所述像素电极为反射电极,所述像素电极具有背向所述衬底的反射面。
进一步的,沿行方向相邻设置的两个像素电极在行方向上的距离为3um~5um。
进一步的,所述信号线还包括与所述第一分支线及所述第二分支线连接的干线,所述第一分支线和第二分支线的的宽度之和不小于所述干线的宽度。
另一方面,本发明还提供一种显示面板,所述显示面板包括如前所述的显示基板。
又一方面,本发明还提供一种显示基板的制作方法,所述制作方法包括:提供衬底;在所述衬底上形成多个像素单元及多个信号线,所述多个像素单元呈多行多列状排布,每个所述像素单元均包括像素电极;其中,位于同一行的、相邻的两个像素单元之间设置有所述信号线,所述信号线与所述像素单元的所述像素电极不同层设置,所述信号线包括相连的第一分支线和第二分支线,所述第一分支线在所述衬底上的正投影,与所述相邻的两个像素电极中的一个像素电极在所述衬底上的正投影部分重合;所述第二分支线在所述衬底上的正投影,与所述相邻的两个像素电极中的另一个像素电极在所述衬底上的正投影部分重合。
通过将信号线与像素电极设置为不同层,并使信号线的第一分支线、第二分支线分别与两个相邻像素电极在竖向上部分重合,降低、消除或改善信号线与像素电极之间的寄生电容,避免或降低所述寄生电容对像素电极和公共电极之间的电压差产生影响,从而改善显示效果。
附图说明
图1是一种显示基板的俯视示意图,其中绝缘膜层未进行显示。
图2是采用列反转驱动时第N-1帧信号和第N帧信号的示意图。
图3是图1所示的显示基板产生串扰的原理图。
图4是本发明显示基板的一种实施方式的侧视示意图。
图5是图1所示的显示基板的俯视示意图,其中衬底、有机绝缘层、无机层绝缘层等结构未进行显示。
图6是图5所示的显示基板的一个像素单元的俯视示意图。
图7是图5的局部放大图,为便于理解,以图案对薄膜晶体管、电极组、信号线进行填充。
图8是本发明显示基板的另一种实施方式的俯视示意图,其中衬底、有机绝缘层、无机层绝缘层等结构未进行显示。
图9是图5的局部放大图,为便于理解,仅显示薄膜晶体管、电极组、信号线等结构,且以图案对薄膜晶体管、电极组、信号线进行填充。
图10是图5沿A-A线的剖视示意图。
图11是图5沿B-B线的剖视示意图。
图12是本发明显示面板的一种实施方式的侧视示意图。
具体实施方式
这里将详细地对示例性实施方式进行说明,其示例表示在附图中。下面的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置的例子。
在本发明使用的术语是仅仅出于描述特定实施方式的目的,而非旨在限制本发明。除非另作定义,本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”或者“一”等类似词语也不表示数量限制,而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出,“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明,而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同,并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而且可以包括电性的连接,不管是直接的还是间接的。在本发明说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式,除非上下文清楚地表示其他含义。还应当理解,本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
请结合图1,像素电极40'通过薄膜晶体管20'及信号线25'接收驱动芯片的信号。其中,像素电极40'和左侧的信号线25'形成第一寄生电容CpdL,像素电极40'和右侧的信号线25”形成第二寄生电容CpdR。由于工艺的原因,很难保证像素电极40'与左侧的信号线25'的横向距离等于像素电极40'与右侧的信号线25”的横向距离,而电容值与距离负相关(C=εS/(4πkd),ε表示介电常数,S表示两板正对面积,k表示静电力常量,d表示两板间距离),距离不相等导致第一寄生电容CpdL与第二寄生电容CpdR的电容值不相等。以列反转方式驱动为例,相邻两个信号线25'、25”电压极性相反,因此第一寄生电容CpdL与第二寄生电容CpdR的极性相反,但第一寄生电容CpdL与第二寄生电容CpdR电容值不相等,因而无法完全抵消,即寄生电容Cpd仍然存在。而且,最终的寄生电容的极性取决于像素电极与哪一个信号线的距离更近,例如像素电极40'与左侧的信号线25'距离更近,则对应第一寄生电容CpdL的电容值更大,寄生电容Cpd的电容极性与第一寄生电容CpdL相同。
请结合图2及图3a,当以列反转方式对像素电极进行驱动时,信号自上向下(如箭头所示)进行扫描。在当前时刻下,上一帧信号(负帧信号)扫描完毕,正帧信号扫描到黑色画面(+5V区域),像素电极的上部分电压保持为+2V(正帧信号已扫描完成),像素电极的下部分电压保持为-2V(正帧信号还未扫描到),中间L0灰阶的像素电压为﹢5V,四周L127灰阶的像素电压为+2V。
请结合图3a及图3b,当处于上述时刻时,中间L0灰阶显示,整个数据线电极为﹢5V(公共电极的电压为0V),由于寄生电容Cpd的存在,此时显示基板的上侧像素电极由﹢2V向﹢5V拉动,例如电压被拉动到至﹢3V,像素电极与公共电极之间的电压差为﹢3V(画面相对L127变黑);显示基板的下侧像素电极由-2V往+5V拉动,例如电压被拉动到-1V,那么像素电极与公共电极之间的电压差为-1V(画面相对L127变亮)。当中间图案与周边图案存在差异时,中间图案的数据信号对上下保持阶段的像素电压进行拉动。由于画面中上下两部分的像素电极被拉动至不同电压,导致上下部分的像素电极与公共电极之间的电压差发生变化,且此变化无法抵消,进而导致垂直方向的串扰(Crosstalk)的产生。
为解决上述技术问题,本发明提供一种显示基板,显示基板包括衬底及位于衬底上的多个像素单元,多个像素单元呈多行多列排布,每个像素单元均包括像素电极。其中,位于同一行的、相邻的两个像素单元之间设置有信号线,信号线与像素单元的像素电极不同层设置,信号线包括相连的第一分支线和第二分支线;第一分支线在衬底上的正投影,与相邻的两个像素单元中的一个的像素电极在衬底上的正投影部分重合;第二分支线在衬底上的正投影,与相邻的两个像素单元中的另一个的像素电极在衬底上的正投影部分重合。
请结合图4及图5,本实施方式的显示基板例如为阵列基板,其包括衬底1、位于衬底1上的薄膜晶体管层2、无机绝缘层3及像素电极层4。薄膜晶体管层2、无机绝缘层3及像素电极层4自下向上依次设置,其中自下向上的方向为衬底1指向薄膜晶体管层2的方向,其与竖向Z一致或平行。在其它实施方式中,无机绝缘层3也可替换为其它类型的绝缘层,比如,有机绝缘材质和无机绝缘材质的复合层或叠层等,只要能起到电性隔离的作用即可。所述薄膜晶体管层2包括多个薄膜晶体管20,所述像素电极层4包括多个像素电极2。
本实施方式中,所述薄膜晶体管20包括有源层21(参图11)、源极22、漏极23及栅极24,薄膜晶体管层2可理解为这几个膜层的结合。所述源极22和漏极23同层设置,同一行薄膜晶体管的栅极24通过扫描线27电性连接。所述显示基板还包括栅极绝缘层5(参图11)、有机绝缘层6(参图11)、多个信号线25、多个存储电极26。所述栅极24、栅极绝缘层5、有源层21、源极22(或漏极23和信号线25)、有机绝缘层6、无机绝缘层3、像素电极层4沿竖向Z顺次设置。本实施方式中,所述信号线25与源极22、漏极23同层设置,所述存储电极26与栅极24同层设置,同层设置可理解为在同一图形化工艺中形成,这样有利于简化显示基板的制作工艺。在其他实施方式中,信号线25及存储电极26也可以设置在其他膜层。所述存储电极26用于与漏极23形成存储电容,漏极23与像素电极层4的像素电极40电性相连因此电势相等,即相当于在存储电极26和像素电极40之间形成存储电容,存储电容用于存储一部分电量,使信号线的电压消失后画面仍能保持一段时间;还用于为对置基板侧的公共电极提供公共信号(或者说接地信号),两者可通过支撑于显示基板和对置基板之间的导电支撑柱或导电胶进行电性连接。本实施方式中,所述存储电极26是一个整体(为清楚的示意出不同的像素单元,存储电极26在相邻的像素单元10之间示意有分界线,实际不存在)且接地;在其他实施方式中,存储电极26的数量可以是多个并分别接地。
本实施方式的显示基板用于液晶显示,像素电极与对置基板侧的公共电极被施加电压后所形成的电场,会驱使液晶偏转以进行显示。像素电极与薄膜晶体管20的漏极23电性相连,所述信号线25与薄膜晶体管20的源极22电性相连,从而使得像素电极能够通过信号线25和薄膜晶体管20接收驱动芯片(未图示)的驱动信号。
可选的,显示基板用于反射型液晶面板,而漏极23设置于反射电极(即像素电极)的下方,这使得漏极23不会影响出光,因而漏极23的面积可以设计的较大,例如不小于像素单元面积(也可理解为像素电极的面积)的1/10,增加漏极23的面积,有利于增大漏极23与存储电极26之间的存储电容,使当前显示的画面在驱动电压消失后能更好地保持到下一个画面。理论上,漏极的面积可以无限接近于像素单元的面积,即两者比值接近1。但实际中,也需考虑漏极的面积对其他电学参数的影响。
请结合图5至图7,所述显示基板包括多个像素单元10,每个像素单元10包括像素电极40,每一像素电极40连接至对应的薄膜晶体管20,当然,像素单元10还可以包括其他绝缘膜层,例如无机绝缘层3。所述信号线25设置于沿行方向X上相邻的两个像素单元10之间,这里的“设置于……之间”可理解部分设置于,也可以理解为完全设置于,进一步的,只要信号线25在衬底1上的投影有部分位于两个像素单元10在衬底上的投影之间即可。
所述信号线25包括干线251、第一分支线252、第二分支线253、第一桥接部254及第二桥接部255,所述第一桥接部254连接干线251和第一分支线252,所述第二桥接部255连接干线251和第二分支线253。也就是说,第一分支线252与第一桥接部254串联,第二分支线253与第二桥接部255串联,之后两个串联电路并联。干线251、第一分支线252、第二分支线253、第一桥接部254及第二桥接部255组成一个信号线单元,信号线25可看作为首尾相连且沿列方向Y排列的多个信号线单元构成,每个信号线单元对应(连接)一个薄膜晶体管20。
请结合图5至图7,在行方向上相邻的两个像素单元10A和10B(对应的像素电极40A、40B也相邻)中,信号线25的第一分支线252在衬底1上的正投影与像素单元10A的像素电极40A在衬底1上的正投影部分重合,信号线25的第二分支线253在衬底1上的正投影与与像素单元10B的像素电极40B在衬底1上的正投影部分重合。
像素电极40与左侧的信号线25A形成第一寄生电容CpdL,像素电极40与信号线与右侧的信号线25B形成第二寄生电容CpdR,由于信号线25A、25B与像素电极40位于不同层并且正投影部分重合,理论上,第一寄生电容CpdL及第二寄生电容CpdR与它们在行方向X上的距离不相关(或几乎不相关)。即影响第一寄生电容CpdL及第二寄生电容CpdR的主要为信号线25A、25B与像素电极40在竖向Z上的距离。即使因工艺问题导致了行方向的偏差也不会影响寄生电容,即信号线与两个像素电极之间的寄生电容是否存在偏差而仅与竖向Z上的距离相关。从工艺上来讲,竖向Z上的间距是容易控制的。只要保证像素电极与信号线之间的膜层厚度均匀,即可保证第一寄生电容CpdL和Cpdr的电容值相等,当然,前提是保证CpdL和Cpdr对应的其他参数保持一致,例如材料相同和正对面积相等。
可选的,相邻两个信号线的电压极性相反,从而使得第一寄生电容CpdL和第二寄生电容CpdR极性相反,而两者电容值相等,因而CpdL和Cpdr能够相互抵消(或者说信号线对像素电极的电压拉动相互抵消),藉此可消除信号线对像素电极的电压的影响,使像素电极与对置基板侧公共电极之间的电压差保持不变,保证画面灰阶不受寄生电容的影响,从而改善垂直方向的串扰。
本实施方式中,干线251与第一桥接部254呈垂直状态,干线251与第二桥接部255呈垂直状态,从而使得干线251、第一桥接部254、第二桥接部255整体呈“T”字形。需要注意的是,由于工艺原因,“垂直”可能有一定偏差,例如,干线251与第一桥接部254(或第二桥接部255)通过圆弧或其他曲线连接;或者,因工艺原因,干线251与第一桥接部254(或第二桥接部255)所成角度值存在一定偏差,角度值譬如为85°~95°。通过实验验证,采用上述实施方式的信号线结构,可使垂直方向的信号串扰降为0,即LV0,从而避免对像素电极和公共电极之间的电压差造成影响,有利于改善显示效果。
在其他实施方式中,信号线25的结构也可以做一些改变。请结合图8,信号线25的干线251与第一桥接部254、第二桥接部255也可以成其他角度,例如钝角,其他结构则与图5所示的实施方式类似。类似的,干线251与第一桥接部254(或第二桥接部255)之间也可以通过圆弧等曲线进行过渡。在自干线251引出第一桥接部254和第二桥接部255的位置相同的前提下,本实施方式的第一桥接部254和第一分支线252的串联电路总长度及第二桥接部255和第二分支线253的串联电路总长度均小于前述实施方式的对应的串联电路长度,因而有利于进一步减小信号线的阻抗,从而有利于对像素电极的驱动。
请继续结合图7及图9,本实施方式中,所述干线251的宽度L1为3um(在与薄膜晶体管的源极相连的区域宽度略大,图中未进行显示),第一分支线252的宽度L2、第二分支线253的宽度L3、第一桥接部254的宽度L4、第二桥接部255的宽度L5均为3um。在信号线25的非干线段(第一分支线25、第二分支线253、第一桥接部254、第二桥接部255)为并联电路,由于信号线不同区域的厚度、材料均是相同的,因而非干线段的单位长度的阻抗仅为干线段的单位长度的阻抗的一半,阻抗降低有利于对像素电极的驱动。在其他实施方式中,只要保证第一分支线252和第二分支线253的宽度之和(或者第一桥接部254和第二桥接部255的宽度之和)大于干线251的宽度,即可以达到降低阻抗的目的。这里的“宽度”可理解为横向尺寸,横向为第一分支线252与第二分支线253的排列方向,也是行方向X。
由于信号线25设置于像素电极40的正下方,不会占用相邻像素电极40之间的空间,因而有利于增大像素电极的面积,能被驱动的液晶面积增大,进而有利于提升显示效果。优选的,所述像素电极为反射电极,所述像素电极具有背向所述衬底1的反射面41(参图10),用于将光线向背离所述衬底1的方向反射,亦即液晶面板为反射型液晶面板。反射面41的面积由像素电极40确定,因而与像素电极40的面积正相关。本实施方式中,反射面41的面积随像素电极40的面积的增大而增大,因而有利于对更多光线进行反射,从而增大显示面板的亮度,进而提升显示效果。此外,在反射式液晶显示面板中,像素电极无需透光,因此即便选用不透光的金属信号线并将其分支线设置在像素电极的正下方,也不会影响像素开口率。在其他实施方式中,显示面板还可以是包括背光源的半反半透液晶面板或透射型液晶面板。
请结合图6、图7及图9,相邻的两个像素电极之间的距离d1为3~5um,在此距离范围内,可以保证良好的显示效果,同时对制作工艺的要求也较低。优选的,为保证良好的显示效果,同时也避免因像素间距过小而导致相邻像素之间的混色,相邻的两个像素电极之间的距离d1为4-5um,本实施方式中,d1=5um。在其他实施方式中,只要工艺上能够实现,可以进一步减小相邻的两个像素电极之间的距离。
所述第一分支线252具有面向所述第二分支线253的第一侧边a,所述第二分支线253具有面向所述第一分支线252的第二侧边b,像素电极40A(与第一分支线252的投影部分重合)具有面向像素电极40B(与第二分支线253的投影部分重合)的第三侧边c;像素电极40A具有面向像素电极40B的第四侧边d。所述第一桥接部254具有面向薄膜晶体管20的第五侧边e,所述像素电极40B包括面向薄膜晶体管20的第六侧边f,该薄膜晶体管20的漏极与像素电极40B电性连接。所述第一侧边a、第三侧边c、第四侧边d、第二侧边b沿行方向X顺次设置,且均沿列方向Y延伸;第五侧边e及第六侧边f沿行方向X延伸。换言之,第一分支线252和第二分支线253的正投影不会落在相邻的两个像素电极之间。
为了使第一寄生电容CpdL和第二寄生电容CpdR能够完全抵消,进一步改善垂直方向上的串扰,第一侧边a和第三侧边c的距离d2等于第二侧边b和第四侧边d的距离d3。为进一步保证第一寄生电容CpdL和第二寄生电容CpdR能够完全抵消(即电容值相等且极性相反),进而消除垂直方向上的串扰,可选的,d2不小于2.5um,d3不小于2.5um。所述第五侧边e和第六侧边f的距离d4不小于2.5um。本实施方式中,d2=d3=d4=3.5um。即使信号线25(或者说第一分支线252和第二分支线253)在行方向X上存在微小的位置偏差,由于第一侧边a和第三侧边c的距离d2及第二侧边b和第四侧边d的距离d3的存在,仍能保证信号线25与像素电极49的正对面积不改变,从而保证CpdL和Cpdr的电容值相等,进而避免串扰。
进一步的,为了避免第一分支线252与存储电极26产生寄生电容及第二分支线253与存储电极26产生寄生电容,进而影响像素电极的电位而造成信号串扰,所述第一分支线252与相邻的存储电极26(即第一分支线252左侧的存储电极;因为第一分支线252与其右侧的存储电极的距离更大)的横向距离d5(标号参见图5)不小于2.5um,所述第二分支线253与相邻的存储电极26的横向距离d6(标号参见图7)不小于2.5um,本实施方式中d5=d6=4um。
下面结合图4、图5、图10及图11,简单介绍所述显示基板的制作方法。
在衬底1上形成薄膜晶体管层2。具体而言,在衬底1(或者衬底1上的缓冲层)上,通过同一图形化工艺形成栅极24及存储电极26;在栅极24及存储电极26上形成栅极绝缘层5;在栅极绝缘层5上形成有源层21;在有源层21上形成源漏电极层,源漏电极层包括源极22、漏极23及与源极22电性连接的信号线25。
而后,在所述薄膜晶体管层2上形成有机绝缘层6;在所述有机绝缘层6上形成无机绝缘层3;在所述无机绝缘层3上形成像素电极层4,其中,像素电极层4内的像素电极40通过过孔30与薄膜晶体管的漏极23(参看图5)电性连接,所述过孔30贯穿有机绝缘层6及无机绝缘层3。
可选的,信号线25可选择银等具有反射性的金属材料。
可选的,有机绝缘层6采用有机材料制成,例如正性聚甲基丙烯酸甲酯、负性聚甲基丙烯酸甲酯等介电常数较大的有机材料,介电常数较大的有机绝缘层6用于减小信号线25与像素电极40的寄生电容。优选的,所述有机绝缘层6的厚度为1~3um,在此厚度下,有机绝缘层能够有效减小信号线与像素电极的寄生电容,同时对显示基板的整体厚度影响较小。所述无机绝缘层3用于进一步减小信号线与像素电极的寄生电容,同时无机绝缘层3还用作平坦化层,为像素电极提供较为平整的表面,有利于改善像素电极的膜层质量。
另一方面,本发明还提供一种显示面板,所述显示面板可以是反射型液晶面板、半反半透型液晶面板或透射型液晶面板。请结合图12,所述显示面板包括对置基板200、液晶层300及如前述任一实施方式所述的显示基板100。其中,对置基板200可以为彩膜基板,其包括彩色滤光片(CF,Color Filter)、公共电极等结构。所述显示面板还可以包括导电支撑柱,所述导电支撑柱设置在液晶层300内,用于对对置基板200和显示基板100进行支撑,并且导电支撑柱可电性连接公共电极和所述存储电极26(参图5和图6),从而为公共电极提供COM信号(通常为接地信号)。
本发明还提供一种显示装置,所述显示装置可以是手机、平板电脑、显示器、电视机等显示设备。所述显示装置可以包括前述的显示面板(反射型、半反半透型或透射型液晶显示面板),显示装置还可以包括外壳、主板、处理模块、存储模块、通讯模块等结构。
以上所述仅是本发明的较佳实施方式而已,并非对本发明做任何形式上的限制,虽然本发明已以较佳实施方式揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案的范围内,当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (15)
1.一种显示基板,其特征在于,所述显示基板包括:
衬底;及
位于所述衬底上的多个像素单元,所述多个像素单元呈多行多列排布,每个所述像素单元均包括像素电极;
其中,位于同一行的、相邻的两个像素单元之间设置有信号线,所述信号线与像素单元的所述像素电极不同层设置,所述信号线包括相连的第一分支线和第二分支线;所述第一分支线在所述衬底上的正投影,与所述相邻的两个像素单元中的一个的像素电极在所述衬底上的正投影部分重合;所述第二分支线在所述衬底上的正投影,与所述相邻的两个像素单元中的另一个的像素电极在所述衬底上的正投影部分重合。
2.根据权利要求1所述的显示基板,其特征在于,施加于相邻的两个所述信号线的电压的极性相反。
3.根据权利要求1所述的显示基板,其特征在于,所述信号线还包括干线、第一桥接部及第二桥接部,所述第一桥接部连接所述第一分支线和所述干线,所述第二桥接部连接所述第二分支线和所述干线。
4.根据权利要求3所述的显示基板,其特征在于,所述第一桥接部与所述干线成垂直状态,所述第二桥接部与所述干线成垂直状态;或者,所述第一桥接部与所述干线成钝角设置,所述第二桥接部与所述干线成钝角设置。
5.根据权利要求1所述的显示基板,其特征在于,所述第一分支线具有面向所述第二分支线的第一侧边,所述第二分支线具有面向所述第一分支线的第二侧边;
与所述第一分支线投影部分重合的像素电极具有第三侧边,所述第三侧边面向与所述第二分支线投影部分重合的像素电极;与所述第二分支线投影部分重合的像素电极具有第四侧边,所述第四侧边面向与所述第一分支线投影部分重合的像素电极;
所述第一侧边、第三侧边、第四侧边、第二侧边沿行方向顺次设置。
6.根据权利要求5所述的显示基板,其特征在于,所述第一侧边与第三侧边在行方向上的距离,等于所述第二侧边与第四侧边在行方向上的距离。
7.根据权利要求5或6所述的显示基板,其特征在于,所述第一侧边与第三侧边在行方向上的距离不小于2.5um,所述第二侧边与第四侧边在行方向上的距离不小于2.5um。
8.根据权利要求1所述的显示基板,其特征在于,所述显示基板包括存储电极和薄膜晶体管,所述存储电极与所述薄膜晶体管的栅极同层设置,所述薄膜晶体管的漏极与所述像素电极相连,所述存储电极与所述薄膜晶体管的漏极形成存储电容。
9.根据权利要求8所述的显示基板,其特征在于,所述漏极的面积与像素电极的面积的比值大于等于0.1且小于1。
10.根据权利要求8所述的显示基板,其特征在于,所述第一分支线与所述存储电极在行方向上的距离不小于2.5um,所述第二分支线与存储电极在行方向上的距离不小于2.5um。
11.根据权利要求1所述的显示基板,其特征在于,所述像素电极为反射电极,所述像素电极具有背向所述衬底的反射面。
12.根据权利要求1或11所述的显示基板,其特征在于,沿行方向相邻设置的两个像素电极在行方向上的距离为3um~5um。
13.根据权利要求1所述的显示基板,其特征在于,所述信号线还包括与所述第一分支线及所述第二分支线连接的干线,所述第一分支线和第二分支线的的宽度之和不小于所述干线的宽度。
14.一种显示面板,其特征在于,所述显示面板包括如权利要求1-13中任一项所述的显示基板。
15.一种显示基板的制作方法,其特征在于,所述制作方法包括:
提供衬底;
在所述衬底上形成多个像素单元,所述多个像素单元呈多行多列排布,每个所述像素单元均包括像素电极;
其中,位于同一行的、相邻的两个像素单元之间设置有信号线,所述信号线与所述像素单元的所述像素电极不同层设置,所述信号线包括相连的第一分支线和第二分支线;所述第一分支线在所述衬底上的正投影,与所述相邻的两个像素单元中的一个的像素电极在所述衬底上的正投影部分重合;所述第二分支线在所述衬底上的正投影,与所述相邻的两个像素单元中的另一个的像素电极在所述衬底上的正投影部分重合。
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