WO2019084979A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2019084979A1
WO2019084979A1 PCT/CN2017/109758 CN2017109758W WO2019084979A1 WO 2019084979 A1 WO2019084979 A1 WO 2019084979A1 CN 2017109758 W CN2017109758 W CN 2017109758W WO 2019084979 A1 WO2019084979 A1 WO 2019084979A1
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Prior art keywords
lines
array substrate
line
disposed
data
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PCT/CN2017/109758
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English (en)
French (fr)
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何怀亮
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惠科股份有限公司
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Publication of WO2019084979A1 publication Critical patent/WO2019084979A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technologies, and more particularly to a display panel and a display device.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel including a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate Thin Film Transistor Substrate
  • a transparent electrode is present on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • the liquid crystal panel controls the orientation of the liquid crystal molecules by an electric field, changes the polarization state of the light, and realizes the purpose of display by the penetration and blocking of the optical path by the polarizing plate.
  • a current source driver, a gate driver, a plurality of data lines, and a plurality of scan lines are disposed on the array substrate of the existing liquid crystal panel, wherein the source driver is connected to the plurality of data lines, and the gate driver is connected to the plurality of scan lines.
  • the plurality of scan lines and the plurality of data lines are arranged on each other on the array substrate, the source driver is mounted and fixed at one end position of the array substrate, and the gate driver is mounted and fixed on one side position or both sides of the array substrate Position, the existing LCD panel is not easy to achieve a narrow bezel.
  • the present application can provide a display panel capable of realizing a narrow bezel.
  • the present application also provides a display device including the above display panel to realize a narrow bezel design.
  • the present application discloses a display panel, the display panel includes an array substrate, and the array substrate includes:
  • the source driver is disposed at a first end of the array substrate
  • a gate driver disposed at a second end of the array substrate, the second end being opposite to the first end;
  • each of which is connected to the gate driver, and each of the connecting lines is connected to one of the scanning lines.
  • the length of the plurality of connecting lines is gradually increased from the first side of the array substrate to the second side of the array substrate, and the plurality of connecting lines are sequentially and multiple from the first side of the array substrate.
  • the scan lines are connected, and the first side and the second side are opposite.
  • the length of the plurality of connecting lines gradually increases from the first side of the array substrate to the second side of the other side, and is sequentially connected to the scanning lines from the first side to the second side, which not only facilitates installation and production, but also causes the rows of the array substrate The cloth is compact.
  • the plurality of connecting lines are arranged in parallel with each other.
  • a plurality of connecting lines are arranged in parallel with each other, and the connecting lines can be laid on the same layer of the array substrate, which not only facilitates wiring, but also makes the arrangement of the array substrate more compact.
  • the plurality of connecting lines and the plurality of the data lines are arranged in parallel.
  • the application further lays a plurality of connecting lines and a plurality of data lines in parallel, so that the connecting lines and the data lines can be laid on the same layer of the array substrate, which further facilitates the wiring and makes the arrangement of the array substrate more compact.
  • the display panel includes a first conductive layer and a second conductive layer; the scan line is located on the first conductive layer; the connection line is disposed on the second conductive layer; the connection line and the corresponding scan line Conductive holes are provided at the intersection positions; the connection lines are electrically connected through the conductive holes and corresponding scan lines. Aligning the scan line and the connection line on the first conductive layer and the second conductive layer of the display panel, respectively, such that the scan line and The connecting lines are separated from each other, and the scanning lines and the connecting lines are connected through the conductive holes only at the corresponding positions, thereby preventing the scanning lines and the data lines from being disordered during wiring.
  • each of the connecting lines is disposed between two adjacent data lines.
  • Each of the connecting lines and the respective data lines are laid apart from each other, thereby preventing the connecting lines and the data lines from overlapping, thereby preventing the connecting lines and the data lines from overlapping and generating parasitic capacitance.
  • the data line includes an adjacent first data line and a second data line
  • the connection line includes a first connection line
  • the scan line includes a first scan line
  • the array substrate includes a first active switch and a first pixel
  • the first active switch is respectively coupled to the first scan line
  • the first active switch and the first pixel are disposed on the first data line and the second data line
  • the first connection line is connected to the first scan line
  • the first connection line is disposed between the first pixel and the second data line. Setting the first connection line between the first pixel and the second data line prevents the first connection line from being set to the first pixel position and affecting the normal development of the first pixel.
  • the vertical shift register circuit of the gate driver is disposed at the first end of the array substrate. It is convenient to electrically connect the vertical shift register circuit and the connecting line.
  • pins of the source driver are bonded to the edge of the array substrate.
  • the length of the gate driver is less than or equal to the width of the display area in the display panel. Setting the length of the gate driver to be less than or equal to the width of the display area in the display panel makes the display panel have a better effect of achieving a narrow border.
  • the gate driver is located at the top of the array substrate, and the source driver is located at the bottom of the array substrate. This is a specific way of setting the gate driver and the source driver in the present application.
  • the source driver can also be disposed on the top of the array substrate, and the gate driver can be disposed on the bottom of the array substrate.
  • the present application also discloses a display device including a backlight module and a display panel as described above.
  • the display panel of the present application has a source driver and a gate driver disposed opposite to the first end and the second end of the array substrate, the source driver and the plurality of data lines are connected; the gate driver is connected by the connection line and the scan line, and each strip The connecting lines are respectively connected to one scanning line, so that the gate driver can normally drive the scanning lines through the connecting lines. Therefore, the gate driver of the present application is disposed on the opposite end of the source driver without occupying the space of the side position of the array substrate, so that the narrow border or no border of the display panel can be realized.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present application.
  • FIG. 2 is a partial structural schematic view of a display panel according to an embodiment of the present application.
  • FIG. 3 is a partial structural schematic view of a display panel according to an embodiment of the present application.
  • FIG. 4 is an equivalent circuit board diagram of FIG. 2.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • FIGS. 1 through 4 A display panel and a display device according to embodiments of the present application are described below with reference to FIGS. 1 through 4.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application
  • FIG. 2 is a partial structural diagram of a display panel according to an embodiment of the present application, that is, FIG. 1 is a schematic diagram of a part of the structure of the display panel.
  • FIG. 2 is a schematic diagram of a pixel structure in the display panel.
  • 3 is a partial schematic view of a display panel according to an embodiment of the present application
  • FIG. 4 is a circuit diagram of an embodiment of the present application, specifically, an equivalent circuit diagram of FIG.
  • the display panel 100 of the present embodiment includes an array substrate 110 including a source driver 112, a gate driver 111, a plurality of spaced-apart data lines 113, a plurality of spaced-apart scan lines 114, and a plurality of spaced arrangements. Connection line 115.
  • the source driver 112 is disposed at the first end 101 of the array substrate 110; the gate driver 111 is disposed at the second end 102 of the array substrate 110, and the second end 102 and the first end 101 are That is, the second end 102 is the other end of the first end 101; a plurality of the data lines 113 are respectively connected to the source driver 112; and the plurality of scan lines 114 and the plurality of the data lines respectively 113 intersecting; a plurality of the connecting lines 115 are respectively connected to the gate driver 111, and each of the connecting lines 115 is connected to one of the scanning lines 114.
  • the display panel 100 has the source driver 112 and the gate driver 111 disposed opposite to the first end 101 and the second end 102 of the array substrate 110, and the source driver 112 and the plurality of data lines 113 are connected; the gate driver 111
  • the connection line 115 and the scan line 114 are connected, and each of the connection lines 115 is connected to one of the scan lines 114, so that the gate driver 111 can normally drive the scan line 114 through the connection line 115. Therefore, the gate driver 111 of the embodiment of the present application does not occupy the space of the side position of the array substrate 110 because it is disposed at the opposite end of the source driver 112, so that the narrow border or no border of the display panel 100 can be realized.
  • the length of the plurality of connecting lines 115 gradually increases from the first side 103 of the array substrate 110 to the second side 104 of the array substrate 110, and the plurality of connecting lines 115 are from the array substrate 110.
  • the first side 103 is sequentially connected to a plurality of said scan lines 114, said first side 103 being opposite to the second side 104, that is, the first side 103 being the other side of the second side 104.
  • the length of the plurality of connecting lines 115 gradually increases from the first side 103 of the array substrate 110 to the second side 104 of the other side, and is sequentially connected from the first side 103 to the second side 104 to the scanning line 14, which is convenient for installation. Production, and the arrangement of the array substrate is compact.
  • connection line of the embodiment is not limited thereto, for example, the length of the first side connection line from the second side of the array substrate to the array substrate is gradually increased.
  • connection line is set to be the same length, and only the connection line needs to be electrically connected to the position where the scan line is connected.
  • a plurality of the connecting lines 115 are disposed in parallel with each other.
  • the plurality of connecting lines 115 are disposed in parallel with each other, and the connecting lines 115 can be laid on the same layer of the array substrate, which not only facilitates wiring, but also makes the arrangement of the array substrate 110 more compact.
  • the connecting lines may also be arranged in parallel.
  • a plurality of the connecting lines 115 and the plurality of the data lines 113 are arranged in parallel.
  • the plurality of connecting lines 115 and the plurality of data lines 113 are further disposed in parallel, so that the connecting lines 115 and the data lines 113 can be laid on the same layer of the array substrate 110, thereby further facilitating the wiring and making the array
  • the arrangement of the column substrates 110 is more compact.
  • the display panel 100 includes a first conductive layer 120 and a second conductive layer 130; the scan line 114 is located in the first conductive layer 130; and the connection line 115 is disposed in the first
  • the conductive layer 131 is disposed at a position where the connecting line 115 and the corresponding scanning line 114 intersect; the connecting line 115 is electrically connected through the conductive hole 131 and the corresponding scanning line 114.
  • the scan line 114 and the connection line 115 are respectively disposed on the first conductive layer 120 and the second conductive layer 130 of the display panel 100 such that the scan line 114 and the connection line 115 are separated from each other, and are connected only through the conductive holes 131 at corresponding positions.
  • the scan line 114 and the connection line 115 prevent the scan line 114 and the data line 115 from being disordered during wiring.
  • each of the connecting lines 115 is disposed between two adjacent data lines 113.
  • the respective connecting lines and the respective data lines are laid apart from each other, thereby preventing the connecting lines and the data lines from overlapping, thereby preventing the connecting lines and the data lines from overlapping and generating parasitic capacitance.
  • the data line 113 includes adjacent first data lines 1131 and second data lines 1132, and the connection lines 115 include a first connection line 1151.
  • the scan line 114 includes a first scan line 1141 and a second scan line 1142.
  • the array substrate 110 includes a first active switch 117 and a first pixel 1161, and the first active switch 117 and the first scan line 1141, respectively.
  • the first data line 1131 and the first pixel 1161 are coupled, and the first active switch 117 and the first pixel 1161 are disposed between the first data line 1131 and the second data line 1132, and the first connection line 1151
  • the first connection line 1151 is connected between the first pixel 1161 and the second data line 1132.
  • the second data line 1132 is located in the next row of the first data line 1131; wherein the second scan line 1142 is located on a row of the first scan line 1141.
  • the first connection line 1151 is disposed between the first pixel 1161 and the second data line 1132 to prevent the first connection line 1151 from being disposed at the position of the first pixel 1161 to affect the normal development of the first pixel 1161.
  • FIG. 2 only shows the structure of one pixel of the display panel 100, and other pixel structures in the display panel can also refer to FIG. 2, which will not be described in detail herein.
  • the array substrate 100 further includes a common line 118 , and the connection line 115 covers the common line 118 .
  • the first connection line 1151 covers the common line 118.
  • the first active switch 117 and the common line 118 are coupled, and a pixel capacitor Clc and a storage capacitor Cst are disposed between the first active switch 117 and the common line 118 to drive the display panel normally.
  • the gate driver includes a vertical shift register circuit, and the vertical shift register circuit is disposed at the first end of the array substrate, thereby facilitating vertical shift register circuits and connections The wires are electrically connected.
  • the pins of the source driver are bonded to the edge of the array substrate.
  • the length of the gate driver 111 is less than or equal to the width of the display area 116 in the display panel 100. Setting the length of the gate driver 111 to be less than or equal to the width of the display region 116 in the display panel 100 makes the display panel 100 more effective in achieving a narrow bezel.
  • This embodiment preferably sets the length of the gate driver 111 equal to the width of the display area 116.
  • the gate driver 111 is located at the top of the array substrate 110, and the source driver 112 is located at the bottom of the array substrate 110. This is a specific way of setting the gate driver and the source driver in the present application.
  • the source driver can also be disposed on the top of the array substrate, and the gate driver can be disposed on the bottom of the array substrate.
  • the display panel 100 further includes a color filter substrate, and the color filter substrate and the array substrate are oppositely disposed.
  • the arrangement of the color filter substrate and the array substrate of the display panel of the present embodiment is not limited thereto.
  • the color filter substrate and the array substrate of the display panel 100 are integrally disposed on the same substrate. .
  • the present application also discloses a display device, wherein the display device includes the above display panel and a backlight module.
  • the display panel of the present embodiment can be referred to the display panel in the above embodiment, and referring to FIG. 1 and FIG. The display panel will not be described in detail one by one.
  • the display device of this embodiment may be, for example, a liquid crystal display, an OLED display, a QLED display, a curved display, or other display.
  • the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and uniform distribution.
  • the backlight module of the embodiment can be front light type or In the backlight mode, it should be noted that the backlight module of the embodiment is not limited thereto.

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  • Mathematical Physics (AREA)
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Abstract

一种显示面板（100）和显示装置，显示面板（100）包括阵列基板（110），阵列基板（110）包括源极驱动器（112）、栅极驱动器（111）、多条间隔布置的数据线（113）、多条间隔布置的扫描线（114）和多条间隔布置的连接线（115），源极驱动器（112）设置在阵列基板（110）的第一端（101），栅极驱动器（111）设置在阵列基板（110）的第二端（102），第二端（102）和第一端（101）相对，多条数据线（113）分别和源极驱动器（112）连接，多条扫描线（114）分别和多条数据线（113）交叉设置，多条连接线（115）分别和栅极驱动器（111）连接，每一条连接线（115）分别和一条扫描线（114）连接。

Description

显示面板和显示装置 【技术领域】
本申请涉及显示技术领域，更具体的说，涉及一种显示面板和显示装置。
【背景技术】
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(Backlight Module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。液晶面板是通过电场对液晶分子取向的控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，实现显示的目的。
现有液晶面板的阵列基板上设置有源极驱动器、栅极驱动器、多条数据线和多条扫描线，其中，源极驱动器和多条数据线连接，栅极驱动器和多条扫描线连接。多条扫描线和多条数据线相互交叉排列在阵列基板上，源极驱动器安装固定在阵列基板的一个端部位置处，栅极驱动器安装固定在阵列基板的一个侧部位置或两个侧部位置，现有的液晶面板不易实现窄边框。
【发明内容】
本申请可提供一种能够实现窄边框的显示面板。
此外，本申请还提供一种包括以上所述显示面板的显示装置，以实现窄边框设计。
根据本申请的一个方面，本申请公开了一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
源极驱动器，所述源极驱动器设置在所述阵列基板的第一端；
栅极驱动器，所述栅极驱动器设置在所述阵列基板的第二端，所述第二端和第一端相对；
多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置；
多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，每一条所述连接线分别和一条所述扫描线连接。
其中，多条所述连接线的长度从所述阵列基板的第一侧至所述阵列基板的第二侧逐渐增加，多条所述连接线从所述阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对。多条连接线的长度从阵列基板的第一侧至另一侧的第二侧逐渐增加，且从第一侧至第二侧依次与扫描线连接，不仅方便安装生产，而且使得阵列基板的排布紧凑。
其中，多条所述连接线相互平行设置。多条连接线相互之间平行设置，可在阵列基板的同一层铺设连接线，不仅方便布线，而且使得阵列基板的排布更加紧凑。
其中，多条所述连接线和多条所述数据线平行设置。本申请进一步将多条连接线和多条数据线平行设置，就可以在阵列基板的同一层铺设连接线和数据线，进一步方便布线，而且使得阵列基板的排布更加紧凑。
其中，所述显示面板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。将扫描线和连接线分别设置在显示面板的第一导电层和第二导电层，使得扫描线和 连接线相互分开来，仅在对应的位置处通过导电孔连通扫描线和连接线，防止扫描线和数据线在布线时乱线。
其中，每一个所述连接线设置在两个相邻所述数据线之间。将各个连接线及各个数据线相互分开进行铺设，这样就防止连接线和数据线重叠，进而防止连接线和数据线重叠而产生寄生电容。
其中，所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线，所述阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与第一扫描线、第一数据线及第一像素耦合，所述第一主动开关和第一像素设置在所述第一数据线和第二数据线之间，所述第一连接线和第一扫描线连接，所述第一连接线设置在所述第一像素和第二数据线之间。将第一连接线设置在第一像素和第二数据线之间，就防止第一连接线设置到第一像素位置处而影响第一像素正常显影。
其中，所述栅极驱动器的竖向移位寄存器电路设置在所述阵列基板的第一端。方便将竖向移位寄存器电路和连接线进行电连接。
其中，所述源极驱动器的引脚邦定到所述阵列基板的边缘。
其中，所述栅极驱动器的长度小于或等于所述显示面板中显示区域的宽度。将栅极驱动器的长度设置小于或等于显示面板中显示区域的宽度，使得显示面板实现窄边框的效果更佳。
其中，所述栅极驱动器位于所述阵列基板的顶部，所述源极驱动器位于所述阵列基板的底部。这是本申请设置栅极驱动器及源极驱动器的一种具体方式，当然，也可以将源极驱动器设置在阵列基板的顶部，以及将栅极驱动器设置在阵列基板的底部。
根据不发明的另一方面，本申请还公开了一种显示装置，所述显示装置包括背光模组和如上所述的显示面板。
由于栅极驱动器安装固定到阵列基板的一侧或两侧位置，过多占用阵列基板侧部的空间，使得液晶面板的边框尺寸过大，从而无法进一步缩减边框的宽 度。本申请显示面板将源极驱动器和栅极驱动器相对设置在阵列基板的第一端和第二端，源极驱动器和多条数据线连接；栅极驱动器通过连接线和扫描线连接，且每一条连接线分别和一条扫描线连接，这样栅极驱动器就可以通过连接线正常驱动扫描线。从而本申请栅极驱动器因设置到源极驱动器的相对端，而不会占用到阵列基板的侧部位置的空间，这样就可以实现显示面板的窄边框或无边框。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一实施例显示面板的结构示意图；
图2是本申请一实施例显示面板的部分结构示意图；
图3是本申请一实施例显示面板的部分结构示意图；
图4是图2的等效电路板图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作， 因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面参考图1至图4描述本申请实施例显示面板和显示装置。
下面结合附图1至图4和具体实施例对本申请作进一步详细说明。
在本申请一实施例中，如图1至图3所示，图1为本申请一实施例显示面板的结构示意图，图2为本申请一实施例显示面板的部分结构示意图，也就是图2为图1的部分结构示意图，具体的是，图2为显示面板中一个像素结构的示意图。以及图3为本申请一实施例显示面板的部分示意图，图4为本申请一实施例的电路图，具体是图2的等效电路图。本实施例的显示面板100包括阵列基板110，所述阵列基板110包括源极驱动器112、栅极驱动器111、多条间隔布置的数据线113、多条间隔布置的扫描线114及多条间隔布置的连接线115。
所述源极驱动器112设置在所述阵列基板110的第一端101；所述栅极驱动器111设置在所述阵列基板110的第二端102，所述第二端102和第一端101相 对，也就是说第二端102为第一端101的另一端；多条所述数据线113分别和所述源极驱动器112连接；多条所述扫描线114分别和多条所述数据线113交叉设置；多条所述连接线115分别和所述栅极驱动器111连接，每一条所述连接线115分别和一条所述扫描线114连接。
本申请实施例显示面板100将源极驱动器112和栅极驱动器111相对设置在阵列基板110的第一端101和第二端102，源极驱动器112和多条数据线113连接；栅极驱动器111通过连接线115和扫描线114连接，且每一条连接线115分别和一条扫描线114连接，这样栅极驱动器111就可以通过连接线115正常驱动扫描线114。从而本申请实施例栅极驱动器111因设置到源极驱动器112的相对端，而不会占用到阵列基板110的侧部位置的空间，这样就可以实现显示面板100的窄边框或无边框。
其中，多条所述连接线115的长度从所述阵列基板110的第一侧103至所述阵列基板110的第二侧104逐渐增加，多条所述连接线115从所述阵列基板110的第一侧103依次与多条所述扫描线114连接，所述第一侧103和第二侧104相对，也就是第一侧103为第二侧104的另一侧。多条连接线115的长度从阵列基板110的第一侧103至另一侧的第二侧104逐渐增加，且从第一侧103至第二侧104依次与扫描线14连接，这样不仅方便安装生产，而且使得阵列基板的排布紧凑。然而，需要说明的是，本实施例连接线的布线方式并不限于此，比如：从阵列基板的第二侧至阵列基板的第一侧连接线的长度逐渐增加。再比如：将连接线设置等长，而仅在连接线需要与扫描线连接的位置进行电连接。
进一步的，多条所述连接线115相互平行设置。多条连接线115相互之间平行设置，可在阵列基板的同一层铺设连接线115，不仅方便布线，而且使得阵列基板110的排布更加紧凑。然而，需要说明的是，连接线也可以不平行设置。
更进一步的，多条所述连接线115和多条所述数据线113平行设置。本申请实施例进一步将多条连接线115和多条数据线113平行设置，就可以在阵列基板110的同一层铺设连接线115和数据线113，进一步方便布线，而且使得阵 列基板110的排布更加紧凑。
其中，如图3所示，所述显示面板100包括第一导电层120和第二导电层130；所述扫描线114位于所述第一导电层130；所述连接线115设置在所述第二导电层130；所述连接线115和对应扫描线114交叉位置设有导电孔131；所述连接线115通过所述导电孔131和对应的扫描线114电连接。将扫描线114和连接线115分别设置在显示面板100的第一导电层120和第二导电层130，使得扫描线114和连接线115相互分开来，仅在对应的位置处通过导电孔131连通扫描线114和连接线115，防止扫描线114和数据线115在布线时乱线。
其中，每一个所述连接线115设置在两个相邻所述数据线113之间。将各个连接线及各个数据线相互分开进行铺设，这样就防止连接线和数据线重叠，进而防止连接线和数据线重叠而产生寄生电容。
具体的，如图2和图4所示，在一个像素结构中，所述数据线113包括相邻的第一数据线1131和第二数据线1132，所述连接线115包括第一连接线1151，所述扫描线114包括第一扫描线1141和第二扫描线1142，所述阵列基板110包括第一主动开关117和第一像素1161，所述第一主动开关117分别与第一扫描线1141、第一数据线1131及第一像素1161耦合，所述第一主动开关117和第一像素1161设置在所述第一数据线1131和第二数据线1132之间，所述第一连接线1151和第一扫描线1141连接，所述第一连接线1151设置在所述第一像素1161和第二数据线1132之间。其中，第二数据线1132位于第一数据线1131的下一行；其中，第二扫描线1142位于第一扫描线1141上一行。本申请实施例将第一连接线1151设置在第一像素1161和第二数据线1132之间，就防止第一连接线1151设置到第一像素1161位置处而影响第一像素1161正常显影。需要说明的是，图2仅示出了显示面板100的一个像素的结构，而显示面板中其他像素结构同样可以参考图2，在此不再进行一一详述。
其中，阵列基板100还包括有共通线118，连接线115覆盖到共通线118上。具体的，如图2所示，第一连接线1151覆盖到共通线118上。
在本实施例中，第一主动开关117和共通线118耦合，且在第一主动开关117和共通线118之间设置有像素电容Clc和存储电容Cst，以正常驱动显示面板。
在本实施例中，所述栅极驱动器包括有竖向移位寄存器电路，所述竖向移位寄存器电路设置在所述阵列基板的第一端，从而方便将竖向移位寄存器电路和连接线进行电连接。
在本实施例中，所述源极驱动器的引脚邦定到所述阵列基板的边缘。
在本实施例中，所述栅极驱动器111的长度小于或等于所述显示面板100中显示区域116的宽度。将栅极驱动器111的长度设置小于或等于显示面板100中显示区域116的宽度，使得显示面板100实现窄边框的效果更佳。本实施例优选将栅极驱动器111的长度设置等于显示区域116的宽度。当然，需要说明的是，本实施例将栅极驱动器111的长度设置略大于显示区域也是可以的。
其中，所述栅极驱动器111位于所述阵列基板110的顶部，所述源极驱动器112位于所述阵列基板110的底部。这是本申请设置栅极驱动器及源极驱动器的一种具体方式，当然，也可以将源极驱动器设置在阵列基板的顶部，以及将栅极驱动器设置在阵列基板的底部。
在本实施例中，显示面板100还包括有彩膜基板，彩膜基板和阵列基板相对设置。然而，需要说明的是，本实施例显示面板的彩膜基板和阵列基板的设置并不限于此，比如：在实施例中，显示面板100的彩膜基板和阵列基板通过整合设置于同一基板上。
本申请还公开了一种显示装置，其中所述显示装置包括以上显示面板以及背光模组，本实施例的显示面板可参见以上实施例中的显示面板，以及参见图1和图2，本实施例不再对显示面板进行一一详述。本实施例的显示装置可以例如为液晶显示器，OLED显示器、QLED显示器、曲面显示器或其他显示器。其中，当本申请实施例的显示装置为液晶显示器时，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可 以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    源极驱动器，所述源极驱动器设置在所述阵列基板的第一端；
    栅极驱动器，所述栅极驱动器设置在所述阵列基板的第二端，所述第二端和第一端相对；
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置；
    多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，每一条所述连接线分别和一条所述扫描线连接；
    多条所述连接线的长度从所述阵列基板的第一侧至所述阵列基板的第二侧逐渐增加，多条所述连接线从所述阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对；
    多条所述连接线相互平行设置；多条所述连接线和多条所述数据线平行设置；每一个所述连接线设置在两个相邻所述数据线之间；
    所述显示面板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接；
    所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线，所述阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与第一扫描线、第一数据线及第一像素耦合，所述第一主动开关和第一像素设置在所述第一数据线和第二数据线之间，所述第一连接线和第一扫描线连接，所述第一连接线设置在所述第一像素和第二数据线之间；
    所述源极驱动器的引脚邦定到所述阵列基板的边缘；所述源极驱动器的引脚邦定到所述阵列基板的边缘；所述栅极驱动器的长度小于或等于所述显示面 板中显示区域的宽度。
  2. 一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    源极驱动器，所述源极驱动器设置在所述阵列基板的第一端；
    栅极驱动器，所述栅极驱动器设置在所述阵列基板的第二端，所述第二端和第一端相对；
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置；
    多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，每一条所述连接线分别和一条所述扫描线连接。
  3. 如权利要求2所述的显示面板，其中，多条所述连接线的长度从所述阵列基板的第一侧至所述阵列基板的第二侧逐渐增加，多条所述连接线从所述阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对。
  4. 如权利要求2所述的显示面板，其中，多条所述连接线相互平行设置；多条所述连接线和多条所述数据线平行设置。
  5. 如权利要求2所述的显示面板，其中，所述显示面板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。
  6. 如权利要求2所述的显示面板，其中，每一个所述连接线设置在两个相邻所述数据线之间。
  7. 如权利要求6所述的显示面板，其中，所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线，所述阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与第一扫描线、第一数据线及第一像素耦合，所述第一主动开关和第一像素设置在所述第一数据线和第二数据线之间，所述第一连接线和第一扫描线连接，所述第一连接线设置在所述第一像素和第二数据线之间。
  8. 如权利要求2所述的显示面板，其中，所述栅极驱动器的竖向移位寄存器电路设置在所述阵列基板的第一端。
  9. 如权利要求2所述的显示面板，其中，所述源极驱动器的引脚邦定到所述阵列基板的边缘。
  10. 如权利要求2所述的显示面板，其中，所述栅极驱动器的长度小于或等于所述显示面板中显示区域的宽度。
  11. 一种显示装置，所述显示装置包括背光模组和显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    源极驱动器，所述源极驱动器设置在所述阵列基板的第一端；
    栅极驱动器，所述栅极驱动器设置在所述阵列基板的第二端，所述第二端和第一端相对；
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置；
    多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，每一条所述连接线分别和一条所述扫描线连接。
  12. 如权利要求11所述的显示装置，其中，多条所述连接线的长度从所述阵列基板的第一侧至所述阵列基板的第二侧逐渐增加，多条所述连接线从所述阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对。
  13. 如权利要求11所述的显示装置，其中，多条所述连接线相互平行设置；多条所述连接线和多条所述数据线平行设置。
  14. 如权利要求11所述的显示装置，其中，所述显示面板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。
  15. 如权利要求11所述的显示装置，其中，每一个所述连接线设置在两个相邻所述数据线之间。
  16. 如权利要求15所述的显示装置，其中，所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线，所述阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与第一扫描线、第一数据线及第一像素耦合，所述第一主动开关和第一像素设置在所述第一数据线和第二数据线之间，所述第一连接线和第一扫描线连接，所述第一连接线设置在所述第一像素和第二数据线之间。
  17. 如权利要求11所述的显示装置，其中，所述栅极驱动器的竖向移位寄存器电路设置在所述阵列基板的第一端。
  18. 如权利要求11所述的显示装置，其中，所述源极驱动器的引脚邦定到所述阵列基板的边缘。
  19. 如权利要求11所述的显示装置，其中，所述栅极驱动器的长度小于或等于所述显示面板中显示区域的宽度。
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Publication number Priority date Publication date Assignee Title
CN108957891B (zh) * 2018-08-21 2024-05-07 信利半导体有限公司 一种阵列基板
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120002130A1 (en) * 2010-06-30 2012-01-05 Panasonic Liquid Crystal Display Co., Ltd. Display device
CN102981331A (zh) * 2012-09-03 2013-03-20 友达光电股份有限公司 显示面板及其修补方法
CN104795043A (zh) * 2015-05-11 2015-07-22 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN105977264A (zh) * 2016-06-30 2016-09-28 京东方科技集团股份有限公司 双栅阵列基板及其制作方法、显示面板、显示装置
CN106710553A (zh) * 2017-01-09 2017-05-24 惠科股份有限公司 像素结构及显示面板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101673015B (zh) * 2009-10-19 2012-05-23 友达光电股份有限公司 主动元件阵列基板以及显示面板
CN102540525B (zh) * 2010-12-30 2015-02-25 上海天马微电子有限公司 一种液晶显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120002130A1 (en) * 2010-06-30 2012-01-05 Panasonic Liquid Crystal Display Co., Ltd. Display device
CN102981331A (zh) * 2012-09-03 2013-03-20 友达光电股份有限公司 显示面板及其修补方法
CN104795043A (zh) * 2015-05-11 2015-07-22 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN105977264A (zh) * 2016-06-30 2016-09-28 京东方科技集团股份有限公司 双栅阵列基板及其制作方法、显示面板、显示装置
CN106710553A (zh) * 2017-01-09 2017-05-24 惠科股份有限公司 像素结构及显示面板

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