CN107958653B - 阵列基板及其驱动方法、驱动电路及显示装置 - Google Patents

阵列基板及其驱动方法、驱动电路及显示装置 Download PDF

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CN107958653B
CN107958653B CN201610906144.2A CN201610906144A CN107958653B CN 107958653 B CN107958653 B CN 107958653B CN 201610906144 A CN201610906144 A CN 201610906144A CN 107958653 B CN107958653 B CN 107958653B
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thin film
switching thin
array substrate
film transistors
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CN107958653A (zh
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韩承佑
商广良
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BOE Technology Group Co Ltd
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Priority to PCT/CN2017/078560 priority patent/WO2018072396A1/en
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Abstract

本发明提供了一种阵列基板及其驱动方法、驱动电路及显示装置，属于显示技术领域。阵列基板包括交叉排布的多条栅线和多条数据线，所述栅线和所述数据线限定出多个亚像素区域，每一亚像素区域内形成有开关薄膜晶体管和像素电极，每一亚像素区域设置有多个开关薄膜晶体管，所述多个开关薄膜晶体管的栅极连接不同的栅线，所述多个开关薄膜晶体管用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号均处于有效电平时，能够将数据电压信号传递至像素电极。本发明的技术方案能够解决显示装置画面异常的问题，改善显示装置的显示效果。

Description

阵列基板及其驱动方法、驱动电路及显示装置
技术领域
本发明涉及显示技术领域，特别是指一种阵列基板及其驱动方法、驱动电路及显示装置。
背景技术
近年来，随着显示技术的快速发展，用于驱动并控制像素的薄膜晶体管也得到了发展，已由非晶硅薄膜晶体管和低温多晶硅薄膜晶体管发展到金属氧化物薄膜晶体管。
金属氧化物薄膜晶体管的电子迁移率、开态电流、开关特性等特性优良。此外，金属氧化物薄膜晶体管还具有特性不均现象少、材料和工艺成本低、工艺温度低、可利用涂布工艺、透光率高、带隙大等优点。因此，金属氧化物薄膜晶体管可以用于需要快速响应和较大电流的显示器，如高频、高分辨率、大尺寸的液晶显示器以及有机发光显示器等。
然而，现在的金属氧化物薄膜晶体管并不稳定，如果金属氧化物薄膜晶体管的栅极接低电平的时间较长，金属氧化物薄膜晶体管将出现负相偏置，阈值电压将左偏移，导致显示装置出现各种画面非正常显示的现象。
发明内容
本发明要解决的技术问题是提供一种阵列基板及其驱动方法、驱动电路及显示装置，能够解决显示装置画面异常的问题，改善显示装置的显示效果。
为解决上述技术问题，本发明的实施例提供技术方案如下：
一方面，提供一种阵列基板，包括交叉排布的多条栅线和多条数据线，所述栅线和所述数据线限定出多个亚像素区域，每一亚像素区域内形成有开关薄膜晶体管和像素电极，
每一亚像素区域设置有多个开关薄膜晶体管，所述多个开关薄膜晶体管的栅极连接不同的栅线，所述多个开关薄膜晶体管用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号均处于有效电平时，能够将数据电压信号传递至对应的像素电极。
进一步地，每一亚像素区域设置有第一开关薄膜晶体管和第二开关薄膜晶体管，所述第一开关薄膜晶体管的栅极连接第一栅线，所述第二开关薄膜晶体管的栅极连接第二栅线。
进一步地，所述第一栅线和所述第二栅线为相邻的栅线。
进一步地，所述第一开关薄膜晶体管的源极与所在亚像素区域对应的数据线连接，所述第一开关薄膜晶体管的漏极与所述第二开关薄膜晶体管的源极连接，所述第二开关薄膜晶体管的漏极与所在亚像素区域的像素电极连接。
本发明实施例还提供了一种如上所述阵列基板的驱动方法，包括：
向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号，使得所述多个开关薄膜晶体管逐个打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
进一步地，所述驱动方法包括：
向所述第一栅线和所述第二栅线输入第一电平信号，使得所述第一开关薄膜晶体管和所述第二开关薄膜晶体管依次打开，在所述亚像素区域对应的充电阶段，所述第一开关薄膜晶体管和所述第二开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述第一开关薄膜晶体管或所述第二开关薄膜晶体管处于关闭状态。
进一步地，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+1行栅线输入第一电平信号一段时间后，始终向所述第k行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+2行输入第一电平信号一段时间后，始终向第k+1行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，k为大于0小于K的奇数。
进一步地，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+2行输入第一电平信号一段时间后，始终向第j+1行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+1行输入第一电平信号一段时间后，始终向第j行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，j为大于0不大于K的偶数。
进一步地，所述第一时间周期为一帧画面的显示周期，所述第二时间周期为一帧画面的显示周期，所述第一时间周期与所述第二时间周期间隔0-N帧画面的显示周期，N为正整数。
进一步地，所述第一时间周期与所述第二时间周期交替设置。
本发明实施例还提供了一种如上所述的阵列基板的驱动电路，包括：
栅极驱动模块，用于向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号，使得所述多个开关薄膜晶体管依次打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
本发明实施例还提供了一种显示装置，包括如上所述的阵列基板，还包括如上所述的驱动电路。
本发明的实施例具有以下有益效果：
上述方案中，每一亚像素区域设置有多个开关薄膜晶体管，多个开关薄膜晶体管的栅极连接不同的栅线，当多个开关薄膜晶体管均处于打开状态时，亚像素区域能够进行充电，当多个开关薄膜晶体管中的任一个或者任意多个处于关闭状态时，亚像素区域不能进行充电，这样在驱动阵列基板进行工作时，可以在充电阶段之外，使亚像素区域的任一个开关薄膜晶体管处于打开状态，只要保证不是亚像素区域所有的开关薄膜晶体管均处于打开状态即可，最终使得每一开关薄膜晶体管处于打开状态的第一时间长度与处于关闭状态的第二时间长度的比值在预设范围内，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
附图说明
图1为现有阵列基板的结构示意图；
图2为本发明实施例阵列基板的结构示意图；
图3为本发明实施例阵列基板各栅线输入信号的时序示意图。
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
现有技术中，如图1所示，每一亚像素区域设置有一个开关薄膜晶体管，在一帧画面的显示周期内，该金属氧化物薄膜晶体管的栅电极在接收完栅极扫描信号后，金属氧化物薄膜晶体管的栅电极将一直接低电平，金属氧化物薄膜晶体管的栅极接低电平的时间较长，金属氧化物薄膜晶体管将出现负相偏置，阈值电压将左偏移。
为了解决上述问题，本发明的实施例提供一种阵列基板及其驱动方法、驱动电路及显示装置，能够解决显示装置画面异常的问题，改善显示装置的显示效果。
本实施例提供了一种阵列基板，包括交叉排布的多条栅线和多条数据线，所述栅线和所述数据线限定出多个亚像素区域，每一亚像素区域内形成有开关薄膜晶体管和像素电极，
每一亚像素区域设置有多个开关薄膜晶体管，所述多个开关薄膜晶体管的栅极连接不同的栅线，所述多个开关薄膜晶体管用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号均处于有效电平时，能够将数据电压信号传递至像素电极；所述多个开关薄膜晶体管还用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号有一个不是处于有效电平时，使得数据线上的数据电压信号不能传递至对应的像素电极。
其中，与开关薄膜晶体管的栅极连接的栅线的信号处于有效电平时，能够使连接的开关薄膜晶体管处于打开状态；与开关薄膜晶体管的栅极连接的栅线的信号不是处于有效电平时，能够使连接的开关薄膜晶体管处于关闭状态。
本实施例中，每一亚像素区域设置有多个开关薄膜晶体管，多个开关薄膜晶体管的栅极连接不同的栅线，当多个开关薄膜晶体管均处于打开状态时，亚像素区域能够进行充电，当多个开关薄膜晶体管中的任一个或者任意多个处于关闭状态时，亚像素区域不能进行充电，这样在驱动阵列基板进行工作时，可以在充电阶段之外，使亚像素区域的任一个开关薄膜晶体管处于打开状态，只要保证不是亚像素区域所有的开关薄膜晶体管均处于打开状态即可，最终使得每一开关薄膜晶体管处于打开状态的第一时间长度与处于关闭状态的第二时间长度的比值在预设范围内，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
一具体实施方式中，每一亚像素区域设置有第一开关薄膜晶体管和第二开关薄膜晶体管，所述第一开关薄膜晶体管的栅极连接第一栅线，所述第二开关薄膜晶体管的栅极连接第二栅线。在该两个开关薄膜晶体管同时打开时，亚像素区域能够进行充电。
一具体实施方式中，所述第一栅线和所述第二栅线为相邻的栅线。
进一步地，所述第一开关薄膜晶体管的源极与所在亚像素区域对应的数据线连接，所述第一开关薄膜晶体管的漏极与所述第二开关薄膜晶体管的源极连接，所述第二开关薄膜晶体管的漏极与所在亚像素区域的像素电极连接。
本发明实施例还提供了一种如上所述阵列基板的驱动方法，包括：
向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号(即高电平信号)，使得所述多个开关薄膜晶体管逐个打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
本实施例中，每一亚像素区域设置有多个开关薄膜晶体管，多个开关薄膜晶体管的栅极连接不同的栅线，当多个开关薄膜晶体管均处于打开状态时，亚像素区域能够进行充电，当多个开关薄膜晶体管中的任一个或者任意多个处于关闭状态时，亚像素区域不能进行充电，这样在驱动阵列基板进行工作时，可以在充电阶段之外，使亚像素区域的任一个开关薄膜晶体管处于打开状态，只要保证不是亚像素区域所有的开关薄膜晶体管均处于打开状态即可，最终使得每一开关薄膜晶体管处于打开状态的第一时间长度与处于关闭状态的第二时间长度的比值在预设范围内，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
一具体实施方式中，所述驱动方法包括：
向所述第一栅线和所述第二栅线输入第一电平信号，使得所述第一开关薄膜晶体管和所述第二开关薄膜晶体管依次打开，在所述亚像素区域对应的充电阶段，所述第一开关薄膜晶体管和所述第二开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述第一开关薄膜晶体管或所述第二开关薄膜晶体管处于关闭状态。
该具体实施方式中，每一亚像素区域设置有两个开关薄膜晶体管，在该两个开关薄膜晶体管同时打开时，亚像素区域能够进行充电。在充电阶段之外，可以控制其中一个开关薄膜晶体管处于打开状态，另外一个开关薄膜晶体管处于关闭状态，使两个开关薄膜晶体管不会长期处于关闭状态，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
进一步地，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+1行栅线输入第一电平信号一段时间后，始终向所述第k行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+2行输入第一电平信号一段时间后，始终向第k+1行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，k为大于0小于K的奇数。
进一步地，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+2行输入第一电平信号一段时间后，始终向第j+1行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+1行输入第一电平信号一段时间后，始终向第j行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，j为大于0不大于K的偶数。
进一步地，所述第一时间周期为一帧画面的显示周期，所述第二时间周期为一帧画面的显示周期，所述第一时间周期与所述第二时间周期间隔0-N帧画面的显示周期，N为正整数。所述第一时间周期与所述第二时间周期交替设置。
优选地，所述预设范围为0.1-10。
本发明实施例还提供了一种如上所述的阵列基板的驱动电路，包括：
栅极驱动模块，用于向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号，使得所述多个开关薄膜晶体管依次打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
本实施例中，每一亚像素区域设置有多个开关薄膜晶体管，多个开关薄膜晶体管的栅极连接不同的栅线，当多个开关薄膜晶体管均处于打开状态时，亚像素区域能够进行充电，当多个开关薄膜晶体管中的任一个或者任意多个处于关闭状态时，亚像素区域不能进行充电，这样在驱动阵列基板进行工作时，可以在充电阶段之外，使亚像素区域的任一个开关薄膜晶体管处于打开状态，只要保证不是亚像素区域所有的开关薄膜晶体管均处于打开状态即可，最终使得每一开关薄膜晶体管处于打开状态的第一时间长度与处于关闭状态的第二时间长度的比值在预设范围内，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
本发明实施例还提供了一种显示装置，包括如上所述的阵列基板，还包括如上所述的驱动电路。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
下面结合附图对本发明的技术方案进行进一步介绍：
如图2所示，阵列基板上设置有多条栅线G1、G2、G3、G4以及多条数据线D1、D2和D3。每一亚像素区域设置有两个开关薄膜晶体管，即第一开关薄膜晶体管和第二开关薄膜晶体管，第一开关薄膜晶体管的栅极连接第一栅线，第二开关薄膜晶体管的栅极连接第二栅线，第一栅线和第二栅线为相邻的栅线。第一开关薄膜晶体管的源极与所在亚像素区域对应的数据线连接，第一开关薄膜晶体管的漏极与所述第二开关薄膜晶体管的源极连接，所述第二开关薄膜晶体管的漏极与所在亚像素区域的像素电极连接。当该两个开关薄膜晶体管同时打开时，亚像素区域能够进行充电。在充电阶段之外，可以控制其中一个开关薄膜晶体管处于打开状态，另外一个开关薄膜晶体管处于关闭状态，使两个开关薄膜晶体管不会长期处于关闭状态，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
图3为本发明实施例阵列基板各栅线输入信号的时序示意图，其中示出了第一行栅线G1、第二行栅线G2、第三行栅线G3、第四行栅线G4输入的栅极扫描信号，G1和G2用于驱动第一行亚像素进行充电，G2和G3用于驱动第二行亚像素进行充电，G3和G4用于驱动第三行亚像素进行充电。
如图3所示，在第一时间周期，栅线逐行输入栅极驱动信号，开关薄膜晶体管逐行打开，其中，G1输入第一电平的时间与G2输入第一电平的时间存在重叠的第一时间段D1，在第一时间段D1，第一行亚像素能够进行像素充电，进而进行显示；在第一时间段D1之后，G1输入第二电平(即低电平信号)，第一行亚像素不再进行充电，此时G2输入第一电平的时间与G3输入第一电平的时间存在重叠的第二时间段D2，在第二时间段D2，第二行亚像素能够进行像素充电，进而进行显示，在第二时间段D2之后，G2输入第二电平，G1输入第一电平，第二行亚像素不再进行充电，同时能够使得第一行亚像素的第一薄膜晶体管处于正相偏置；第二时间段D2之后，G3输入第一电平的时间与G4输入第一电平的时间存在重叠的第三时间段D3，在第三时间段D3，第三行亚像素能够进行像素充电，进而进行显示，在第三时间段D3之后，G3输入第二电平，第三行亚像素不再进行充电；第三时间段之后，G4输入第一电平的时间与下一行栅线输入第一电平的时间存在重叠的第四时间段D4，在第四时间段D4，第四行亚像素能够进行像素充电，进而进行显示，在第四时间段D4之后，G4输入第二电平，第四行亚像素不再进行充电，同时G3输入第一电平，能够使得第三行亚像素的第一薄膜晶体管处于正相偏置。之后以此类推，在不影响显示的前提下，奇数行栅线输入第一电平，使得奇数行亚像素的第一薄膜晶体管、偶数行亚像素的第二薄膜晶体管处于正相偏置；偶数行栅线输入第一电平，使得偶数行亚像素的第一薄膜晶体管、奇数行的第二薄膜晶体管处于负相偏置。
在间隔一段时间之后，进入第二时间周期。如图3所示，在第二时间周期，栅线逐行输入栅极驱动信号，开关薄膜晶体管逐行打开，其中，G1输入第一电平的时间与G2输入第一电平的时间存在重叠的第一时间段D5，在第一时间段D5，第一行亚像素能够进行像素充电，进而进行显示；在第一时间段D5之后，G1输入第二电平，第一行亚像素不再进行充电，此时G2输入第一电平的时间与G3输入第一电平的时间存在重叠的第二时间段D6，在第二时间段D6，第二行亚像素能够进行像素充电，进而进行显示，在第二时间段D6之后，G2输入第二电平，G3输入第一电平的时间与G4输入第一电平的时间存在重叠的第三时间段D7，在第三时间段D7，第三行亚像素能够进行像素充电，进而进行显示，在第三时间段D7之后，G3输入第二电平，第三行亚像素不再进行充电；第三时间段D7之后，G4输入第一电平的时间与下一行栅线输入第一电平的时间存在重叠的第四时间段D8，在第四时间段D8，第四行亚像素能够进行像素充电，进而进行显示，在第四时间段D8之后，G4输入第二电平，第四行亚像素不再进行充电，同时G2输入第一电平，能够使得第二行亚像素的第一薄膜晶体管处于正相偏置。之后以此类推，在不影响显示的前提下，奇数行栅线输入第二电平，使得奇数行亚像素的第一薄膜晶体管、偶数行亚像素的第二薄膜晶体管处于负相偏置；偶数行栅线输入第一电平，使得偶数行亚像素的第一薄膜晶体管、奇数行的第二薄膜晶体管处于正相偏置。
其中，第一时间周期为一帧画面的显示周期，第二时间周期为一帧画面的显示周期，所述第一时间周期与所述第二时间周期之间的间隔时间为0-N帧画面的显示周期，N为正整数。第一时间周期和第二时间周期交替设置。
上述方案中，两个开关薄膜晶体管的栅极连接不同的栅线，当两个开关薄膜晶体管均处于打开状态时，亚像素区域能够进行充电并显示，当两个开关薄膜晶体管中的任一个处于关闭状态时，亚像素区域不能进行充电，这样在驱动阵列基板进行工作时，可以在充电阶段之外，使亚像素区域的任一个开关薄膜晶体管处于打开状态，只要保证不是亚像素区域所有的开关薄膜晶体管均处于打开状态即可，最终使得每一开关薄膜晶体管处于打开状态的第一时间长度与处于关闭状态的第二时间长度的比值在预设范围内，这样能够均衡开关薄膜晶体管处于负相偏置和正相偏置的时间，使得开关薄膜晶体管的阈值电压不会出现偏移，从而解决显示装置画面异常的问题，改善显示装置的显示效果。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种阵列基板，包括交叉排布的多条栅线和多条数据线，所述栅线和所述数据线限定出多个亚像素区域，每一亚像素区域内形成有开关薄膜晶体管和像素电极，其特征在于，
每一亚像素区域设置有多个开关薄膜晶体管，所述多个开关薄膜晶体管的栅极连接不同的栅线，所述多个开关薄膜晶体管用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号均处于有效电平时，能够将数据电压信号传递至对应的像素电极；所述多个开关薄膜晶体管还用于在连接所述多个开关薄膜晶体管的栅极的栅线的信号有一个不是处于有效电平时，使得数据线上的数据电压信号不能传递至对应的像素电极；
其中，相邻两行所述栅线之间仅有一行子像素，且数据电压信号传递至其中一行子像素时，数据电压信号不能传递至其他行子像素。
2.根据权利要求1所述的阵列基板，其特征在于，
每一亚像素区域设置有第一开关薄膜晶体管和第二开关薄膜晶体管，所述第一开关薄膜晶体管的栅极连接第一栅线，所述第二开关薄膜晶体管的栅极连接第二栅线。
3.根据权利要求2所述的阵列基板，其特征在于，所述第一栅线和所述第二栅线为相邻的栅线。
4.根据权利要求3所述的阵列基板，其特征在于，所述第一开关薄膜晶体管的源极与所在亚像素区域对应的数据线连接，所述第一开关薄膜晶体管的漏极与所述第二开关薄膜晶体管的源极连接，所述第二开关薄膜晶体管的漏极与所在亚像素区域的像素电极连接。
5.一种如权利要求1-4中任一项所述阵列基板的驱动方法，其特征在于，包括：
向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号，使得所述多个开关薄膜晶体管逐个打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
6.根据权利要求5所述的阵列基板的驱动方法，其特征在于，用于驱动如权利要求3所述的阵列基板，所述驱动方法包括：
向所述第一栅线和所述第二栅线输入第一电平信号，使得所述第一开关薄膜晶体管和所述第二开关薄膜晶体管依次打开，在所述亚像素区域对应的充电阶段，所述第一开关薄膜晶体管和所述第二开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述第一开关薄膜晶体管或所述第二开关薄膜晶体管处于关闭状态。
7.根据权利要求5所述的阵列基板的驱动方法，其特征在于，用于驱动如权利要求3所述的阵列基板，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+1行栅线输入第一电平信号一段时间后，始终向所述第k行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第k行和第k+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第k+2行输入第一电平信号一段时间后，始终向第k+1行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，k为大于0小于K的奇数。
8.根据权利要求5所述的阵列基板的驱动方法，其特征在于，用于驱动如权利要求3所述的阵列基板，所述驱动方法具体包括：
在第一时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+2行输入第一电平信号一段时间后，始终向第j+1行栅线输入第一电平信号；
在第二时间周期内，向阵列基板上的多条栅线依次输入第一电平信号，且向第j行和第j+1行栅线输入第一电平信号的时间部分重合，在所述重合的时间之外，停止向第j+1行输入第一电平信号一段时间后，始终向第j行栅线输入第一电平信号；
所述阵列基板上设置有K行栅线，j为大于0不大于K的偶数。
9.根据权利要求7或8所述的阵列基板的驱动方法，其特征在于，所述第一时间周期为一帧画面的显示周期，所述第二时间周期为一帧画面的显示周期，所述第一时间周期与所述第二时间周期间隔0-N帧画面的显示周期，N为正整数。
10.根据权利要求9所述的阵列基板的驱动方法，其特征在于，所述第一时间周期与所述第二时间周期交替设置。
11.一种如权利要求1-4中任一项所述的阵列基板的驱动电路，其特征在于，包括：
栅极驱动模块，用于向每一亚像素区域的多个开关薄膜晶体管连接的栅线输入第一电平信号，使得所述多个开关薄膜晶体管依次打开，其中，在所述亚像素区域对应的充电阶段，所述多个开关薄膜晶体管均处于打开状态，且在所述充电阶段之外所述多个开关薄膜晶体管中的至少一个开关薄膜晶体管处于关闭状态。
12.一种显示装置，其特征在于，包括如权利要求1-4中任一项所述的阵列基板，还包括如权利要求11所述的驱动电路。
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CN101191968A (zh) * 2006-11-27 2008-06-04 株式会社日立显示器 具有画面输入功能的图像显示装置
CN101344691A (zh) * 2007-07-12 2009-01-14 奇美电子股份有限公司 像素电路、平面显示器及像素电路的驱动方法
CN101364387A (zh) * 2007-08-07 2009-02-11 奇美电子股份有限公司 以时间多工驱动的显示面板及其驱动方法
CN101620333A (zh) * 2008-07-04 2010-01-06 统宝光电股份有限公司 具有触控功能的有源矩阵显示装置

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