WO2017166392A1 - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents

阵列基板及其制造方法、显示面板和显示装置 Download PDF

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Publication number
WO2017166392A1
WO2017166392A1 PCT/CN2016/082371 CN2016082371W WO2017166392A1 WO 2017166392 A1 WO2017166392 A1 WO 2017166392A1 CN 2016082371 W CN2016082371 W CN 2016082371W WO 2017166392 A1 WO2017166392 A1 WO 2017166392A1
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data line
array substrate
layer
pixel
disposed
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PCT/CN2016/082371
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English (en)
French (fr)
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肖丽
张慧
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京东方科技集团股份有限公司
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Priority to US15/540,132 priority Critical patent/US10216057B2/en
Publication of WO2017166392A1 publication Critical patent/WO2017166392A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • the TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the TFT-LCD has good image display quality, low energy consumption and environmental protection, and is widely used in the field of displays.
  • the display panel in the TFT-LCD is formed by pairing the array substrate and the counter substrate, and the array substrate and the counter substrate are filled with liquid crystal in the cavity behind the cassette.
  • Data lines and gate lines intersecting vertically and horizontally are formed on the array substrate, and the data lines and the gate lines are intersected to form pixel units arranged in a matrix form.
  • An embodiment of the present disclosure provides an array substrate including a substrate substrate, a plurality of gate lines disposed on the substrate substrate, a plurality of first data lines, a plurality of second data lines, and a matrix arrangement a plurality of rows and columns of pixel cells, wherein each row of the pixel cells is driven by a corresponding gate line, wherein each of the plurality of rows of pixel cells constitutes one pixel cell row group and the pixel cell row group is Receiving the same gate signal during operation of the array substrate; each column of the pixel unit is driven by a corresponding first data line and a second data line, and the adjacent first data line and the second data line are mutually Insulating, disposed in different layers, and connected to different pixel units, the adjacent first data lines and the second data lines at least partially overlapping in a direction perpendicular to a board surface of the base substrate .
  • the pixel unit of the 2m-1th row and the pixel unit of the 2mth row constitute one pixel unit row group and receive the same during operation of the array substrate.
  • the gate signal, m is a natural number greater than or equal to one.
  • an array substrate further includes a plurality of first vias and a thin film transistor disposed in each of the pixel units, wherein the first data line and each pixel unit row group The source and the drain of the thin film transistor in the row of the pixel unit are disposed in the same layer, and the second data line passes through the corresponding first via and the other pixel in the pixel unit row group.
  • the thin film transistor is electrically connected.
  • the first via hole and the gate line at least partially overlap in a direction of a board surface of the array substrate.
  • an array substrate provided by an embodiment of the present disclosure further includes a first passivation layer, wherein the first passivation layer is disposed between the first data line and the second data line.
  • the first passivation layer is an inorganic insulating layer.
  • an array substrate further includes a shield electrode layer and a common electrode, wherein the shield electrode layer is disposed between the first passivation layer and the second data line, and the shielding
  • the electrode layer is disposed in the same layer as the common electrode, is formed of the same material, and is applied with the same voltage.
  • an array substrate provided by an embodiment of the present disclosure further includes a second passivation layer, wherein the second passivation layer is disposed between the shield electrode layer and the second data line.
  • the second passivation layer is an inorganic insulating layer.
  • an array substrate further includes a planarization layer, wherein the planarization layer is disposed between the shield electrode layer and the first passivation layer.
  • the planarization layer is a resin layer.
  • an array substrate further includes a protective layer and a pixel electrode, wherein the protective layer is disposed on the second data line, and the protective layer and the pixel electrode are disposed in the same layer and are The same material is formed.
  • the protective layer is an indium tin oxide layer.
  • An embodiment of the present disclosure provides a display panel including the array substrate according to any embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display device including the display panel of any of the embodiments of the present disclosure.
  • An embodiment of the present disclosure provides a method for fabricating an array substrate, comprising: forming a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, and a plurality of rows arranged in a matrix on the substrate.
  • each of the rows of the pixel units is driven by a corresponding gate line, wherein each of the plurality of rows of pixel units constitutes one pixel unit row group; each column of pixel units is corresponding to the first data
  • the line and the second data line are driven, and the adjacent first data line and the second data line are mutually exclusive
  • the edge is disposed at a different layer and is connected to a different pixel unit, and the adjacent first data line and the second data line at least partially overlap in a direction perpendicular to a board surface of the base substrate.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a first passivation layer between the first data line and the second data line.
  • a method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a shield electrode layer and a common electrode in a same patterning process, wherein the shield electrode layer is disposed on the first passivation layer and Between the second data lines.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure further includes forming a second passivation layer between the shield electrode layer and the second data line.
  • a method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a protective layer and a pixel electrode in a same patterning process, wherein the protective layer is disposed on the second data line.
  • 1 is a top plan view of an array substrate
  • FIG. 2 is a top plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view of an example of an array substrate according to an embodiment of the present disclosure taken along line AA' in FIG. 2;
  • FIG. 4 is a cross-sectional view of still another example of an array substrate according to an AA' line in FIG. 2 according to an embodiment of the present disclosure
  • FIG. 5A to FIG. 5I are schematic cross-sectional views of a method of fabricating an array substrate corresponding to FIG. 4 according to an embodiment of the present disclosure, taken along line BB' of FIG. 2;
  • FIG. 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • the array substrate of the liquid crystal display panel can be driven by a progressive scanning method.
  • the refreshing frequency is increased, the driving time of the pixel electrode may be insufficient, which may result in poor picture quality, which hinders large-size, high-resolution liquid crystal display products.
  • development of. The array substrate of the liquid crystal display panel can also adopt the method of double-row scanning, that is, two rows of pixel electrodes are in a charging state at any time, which can provide twice the charging time of the original progressive scanning driving mode for each pixel electrode, ensuring The picture quality is especially suitable for large-size, high-resolution liquid crystal display products.
  • the two-line scanning method requires two data lines corresponding to each column of pixel units, and the two data lines need to be separated by a certain distance.
  • a black matrix may be disposed on a counter substrate (for example, a color filter substrate) on a side close to a light emitting surface of the liquid crystal display panel corresponding to the data line on the array substrate. Therefore, when the two data lines are disposed in the same layer, the width of the black matrix is correspondingly increased in the width direction of the data line, resulting in a decrease in the aperture ratio of the liquid crystal display panel.
  • a counter substrate for example, a color filter substrate
  • the charging time of each row of pixel electrodes is 1/(1024 ⁇ 60) s, which is about 16.3 ⁇ s, that is, from one Switching the gray scale to another gray scale needs to be completed in about 16.3 ⁇ s (this also includes the time required for the charging voltage to reach the required value and the total deflection of the liquid crystal).
  • the charging time of each row of pixel electrodes is 1/(512 ⁇ 60) s, which is about 32.6 ⁇ s, that is, the two-line scanning method provides twice the pixel electrode in each row of pixel units. The charging time of the progressive scan drive mode.
  • Figure 1 is a top plan view of an array substrate 100'.
  • the array substrate 100' includes a plurality of first data lines 112', a plurality of second data lines 113', a plurality of gate lines 111', and a plurality of pixel units 114', each of the pixel units 114' is provided with a thin film transistor 120' and a pixel electrode 118', wherein the first data line 112' and the second data line 113' are disposed in the same layer and respectively respectively with films in different rows of pixel units
  • the source 121' of the transistor 120' is electrically connected.
  • the drain 122' in the thin film transistor 120' is electrically connected to the pixel unit 118' through the second via 116'.
  • Each two rows of pixel units 114' receive the same gate signal during operation of the array substrate 100', for example, two gate lines for driving the first row and the second row of pixel cells in the figure receive the same during operation The gate signal, whereby the first row and the second row of pixel cells are turned on and off simultaneously.
  • the black matrix 180' covers the first data line 112', the plurality of second data lines 113', and the plurality of gate lines 111'.
  • the black matrix 180' may be disposed on the opposite substrate of the liquid crystal panel opposite to the array substrate. Upper, or can be directly disposed on the array substrate.
  • the array substrate 100' shown in FIG. 1 can realize the operation mode of two-line scanning, and can provide charging time twice that of the original progressive scanning driving mode for each pixel electrode, but compared with the progressive scanning driving method, black
  • the area covered by the matrix 180' is increased, resulting in a decrease in the aperture ratio of the liquid crystal display panel using the array substrate, thereby increasing energy consumption.
  • An embodiment of the present disclosure provides an array substrate including a substrate substrate, a plurality of gate lines disposed on the substrate substrate, a plurality of first data lines, a plurality of second data lines, and a plurality of rows arranged in a matrix form. And a plurality of columns of pixel units, wherein each row of pixel units is driven by a corresponding gate line, wherein each of the plurality of rows of pixel units constitutes one pixel unit row group and the pixel unit row group receives the same gate during operation of the array substrate a pole signal; each column of pixel units is driven by a corresponding first data line and a second data line, and the adjacent first data line and the second data line are insulated from each other, disposed in different layers, and connected to different pixel units, The first data line and the second data line at least partially overlap in a direction perpendicular to a board surface of the base substrate.
  • the array substrate provided by the embodiment of the present disclosure reduces the area occupied by the two data lines, thereby reducing the area of the black matrix corresponding to the corresponding need, thereby improving the aperture ratio of the liquid crystal display panel using the array substrate, and reducing the liquid crystal. Panel power consumption.
  • FIG. 2 is a schematic plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view of an example of an array substrate according to an AA′ line in FIG. 2 according to an embodiment of the present disclosure
  • a further example of an array substrate provided by the disclosed embodiment is a cross-sectional view along the line AA' in FIG. 2
  • FIG. 5I is an array substrate corresponding to FIG. 4 according to the embodiment of the present disclosure, along the line BB' in FIG.
  • an embodiment of the present disclosure provides an array substrate 100. It includes a substrate substrate 110, a plurality of gate lines 111 disposed on the substrate substrate 110, a plurality of first data lines 112, a plurality of second data lines 113, and a plurality of rows and columns of pixel units arranged in a matrix form. 114, wherein each row of pixel units 114 is driven by a corresponding gate line 111. In the multi-row pixel unit 114, every two rows constitute one pixel unit row group and the pixel unit row group receives the same gate signal during the operation of the array substrate 100, for example, two gate line connections for one pixel unit row group. Go to the same gate driver.
  • Each column of pixel units 114 is driven by a corresponding first data line 112 and a second data line 113, and adjacent first data lines 112 and second data lines 113 are insulated from each other, disposed in different layers, and connected to the columns.
  • the adjacent first data line 112 and second data line 113 at least partially overlap in a direction perpendicular to the board surface of the base substrate 110.
  • the adjacent first data line 112 and second data line 113 completely overlap in a direction perpendicular to the board surface of the base substrate 110.
  • the projection of the second data line 113 on the upper layer with respect to the substrate 110 completely falls into the projection of the first data line 112 of the lower layer with respect to the base substrate 110, and thus the width of the second data line 113 is less than or equal to The width of the first data line 112.
  • the first data line 112 and the second data line 113 adjacent to each other between the two columns of pixel units are respectively used to drive two columns of pixel units located on both sides thereof, and the first data line 112 is used in the figure.
  • Driving the pixel units in the first, third, fifth, ... rows in the left column, and the second data line 113 is used to drive the second, fourth, sixth, ..., rows in the right column Pixel unit in .
  • first data line 112 and the second data line 113 adjacent to each other between two columns of pixel units may be used to drive a column of pixel units located on the same side thereof, for example, the first data line 112 is used to drive pixel units in rows 1, 3, 5... of the column, and second data line 113 is used for rows 2, 4, 6... in the column Pixel unit in .
  • the two are generally occupied.
  • the area of the substrate is reduced with respect to the arrangement of the two in parallel with each other, so that the area covered by the black matrix 180 in FIG. 2 is reduced, which improves the aperture ratio of the liquid crystal display panel using the array substrate.
  • the 2m-1 row pixel unit and the 2m row pixel unit form one pixel unit row group and receive the same gate signal during the operation of the array substrate 100, m is a natural number greater than or equal to 1.
  • two rows of pixel units constituting one pixel unit row group are not adjacent, for example, the 4m-3th row and the 4th m-1th row pixel unit constitute one pixel unit row group, the 4m- 2
  • the row and the 4th row pixel unit constitute one pixel unit row group, m is a natural number greater than or equal to 1; or, if the entire array substrate includes 2n rows of pixel units, the mth row and the n+mth row pixel unit constitute one pixel Unit row group, m, n is a natural number greater than or equal to 1, and m ⁇ n.
  • the array substrate 100 further includes a plurality of first vias 115 and a thin film transistor 120 disposed in each of the pixel units 114, wherein the first data line and each pixel unit row group
  • the source and drain of the thin film transistor in one row of pixel cells are disposed in the same layer
  • the second data line is electrically connected to the thin film transistor in the other row of pixel cells in the pixel cell row group through the corresponding first via.
  • the first data line 112 and the second m-1 row pixel unit have the source 121 and the drain of the thin film transistor 120.
  • the second data line 113 passes through the first via 115 and the source 121 (or the drain 122) of the thin film transistor 120 in the second m row of pixel units.
  • the first data line 112 is disposed in the same layer as the source 121 and the drain 122 of the thin film transistor 120 in the pixel unit of the 2mth row and is electrically connected to the source 121 (or the drain 122), and the second data line 113 passes The first via 115 is electrically connected to the source 121 (or the drain 122) of the thin film transistor 120 in the pixel cell of the 2m-1th row.
  • the drain 122 of the thin film transistor 120 is electrically connected to the pixel unit 118 through the second via 116.
  • the operation principle of the two-line scanning of the array substrate 100 shown in FIG. 2 can be as follows. The following description will be described by taking a case where the pixel unit of the 2m-1th row and the pixel unit of the 2mth row constitute one pixel unit row group (m is a natural number greater than or equal to 1), but in other embodiments, the pixel unit row group constitutes The same applies to the method.
  • the gate line of the pixel unit of the first row and the gate line of the pixel unit of the second row receive the same gate turn-on signal, and simultaneously open the pixel unit of the first row and the pixel unit of the second row; Transmitting a data signal to the first row of pixel cells or the second row of pixel cells through the first data line 112, and correspondingly transmitting data signals to the second row of pixel cells or the first row of pixel cells through the second data line 113, undergoing a
  • the gate line of the pixel unit of the first row and the pixel of the second row of pixels receive the same gate-off signal, and the pixel unit of the first row and the pixel of the second row are turned off, thereby simultaneously driving the pixel unit of the first row and the pixel unit 2 rows of pixel units.
  • the gate line of the pixel unit of the third row receives the same gate turn-on signal as the gate line of the pixel unit of the fourth row, and the pixel unit of the third row and the pixel of the fourth row are turned on;
  • the data signal is transmitted to the third row of pixel units or the fourth row of pixel units through the first data line 112, and the data signal is transmitted to the fourth row of pixel units or the third row of pixel units through the second data line 113, respectively.
  • the gate line of the pixel unit of the third row and the pixel of the fourth row of pixels receive the same gate-off signal, and the pixel unit of the third row and the pixel of the fourth row are turned off, thereby simultaneously driving the pixel unit of the third row and Line 4 pixel unit.
  • the above operation is sequentially performed for each subsequent pixel unit row group until the pixel unit rows of the entire array substrate are charged, thereby completing the scanning of one frame of the screen.
  • the 2m-1th row of pixel cells and the 2mth row of pixel cells can be driven by the same output channel of the same gate driver or gate driver to receive the same gate signal.
  • the number of gate driver or gate driver output channels is reduced, simplifying circuit design and saving the cost of the gate driver.
  • the first via 115 and the gate line 111 at least partially overlap in the direction of the board surface of the array substrate 100 .
  • the first via 115 is overlapped with the gate line 111 so that the first via 115 does not occupy the area of the pixel electrode 118, thereby increasing the aperture ratio.
  • the shape of the thin film transistor 120 is not limited to the U-shaped thin film transistor as shown in FIG. 2, and may be a linear thin film transistor, which is not limited herein.
  • FIG. 3 is a cross-sectional view of an example of an array substrate according to an embodiment of the present disclosure taken along line AA' in FIG.
  • an array substrate 100 according to an embodiment of the present disclosure further includes a first passivation layer 130 , wherein the first passivation layer 130 is disposed between the first data line 112 and the second data line 113 .
  • the first passivation layer 130 insulates the adjacent first data line 112 and the second data line 113 from each other, and reduces signal crosstalk between the first data line 112 and the second data line 113.
  • the first passivation layer 130 is an inorganic insulating layer.
  • FIG. 4 is a cross-sectional view of still another example of an array substrate according to an AA' line in FIG. 2 according to an embodiment of the present disclosure.
  • an array substrate 100 according to an embodiment of the present disclosure further includes a shield electrode layer 140 and a common electrode, wherein the shield electrode layer 140 is disposed between the first passivation layer 130 and the second data line 113, and is shielded.
  • the electrode layer 140 is disposed in the same layer as the common electrode, is formed of the same material, and is applied with the same voltage.
  • the shield electrode layer 140 may reduce signal crosstalk between the first data line 112 and the second data line 113.
  • the shield electrode layer 140 may be made of indium tin oxide. (ITO) formation.
  • ITO indium tin oxide.
  • the array substrate 100 provided by an embodiment of the present disclosure may further include a second passivation layer 150 , wherein the second passivation layer 150 is disposed between the shield electrode layer 140 and the second data line 113 .
  • the second passivation layer 150 insulates the shield electrode layer 140 from the second data line 113 and reduces signal crosstalk between the first data line 112 and the second data line 113.
  • the second passivation layer 150 is an inorganic insulating layer.
  • the shielding electrode 140 may be directly formed on the first passivation layer 130.
  • the array substrate 100 may further include a planarization layer 160, wherein the planarization layer 160 is disposed on the shield electrode layer 140. Between the first passivation layer 130 and the first.
  • the planarization layer 160 can function as a flattening to facilitate uniform formation of subsequent layers while reducing signal crosstalk between the first data line 112 and the second data line 113.
  • the planarization layer 160 is, for example, a resin layer.
  • the array substrate 100 provided by an embodiment of the present disclosure may further include a protective layer 170 and a pixel electrode, wherein the protective layer 170 is disposed on the second data line 113, for example, covering the second data line 113, the protective layer 170 and the pixel electrode.
  • the same layer is disposed and formed of the same material, that is, the protective layer 170 can be formed without increasing the process.
  • the protective layer 170 may protect the second data line 113 from being oxidized by the second data line 113.
  • the protective layer 170 is, for example, an indium tin oxide (ITO) layer.
  • ITO indium tin oxide
  • An embodiment of the present disclosure provides a method for fabricating an array substrate, comprising: forming a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, and a plurality of rows arranged in a matrix on the substrate.
  • each row of pixel cells is driven by a corresponding gate line, and each of the plurality of rows of pixel cells constitutes one pixel cell row group; each column of pixel cells is composed of a corresponding first data line and a second The data line is driven, the adjacent first data line and the second data line are insulated from each other, disposed in different layers, and connected to different pixel units in the column, the adjacent first data line and the second data line are vertical At least partially overlapping in the direction of the board surface of the base substrate.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a first passivation layer between the first data line and the second data line.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a shield electrode layer between the first passivation layer and the second data line.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a second passivation layer between the shield electrode layer and the second data line.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a protective layer on the second data line.
  • FIG. 5A to FIG. 5I are schematic cross-sectional views of a method of fabricating an array substrate corresponding to FIG. 4 according to an embodiment of the present disclosure, taken along line BB′ of FIG. 2 , for illustrating that embodiments of the present disclosure are not limited thereto. It shows the specific structure and steps.
  • an embodiment of the present disclosure provides an example of a method for manufacturing an array substrate, as shown in FIG. 5A to FIG. 5I, which specifically includes the following steps:
  • Step 1 As shown in FIG. 5A, a first metal layer is formed on the base substrate 110, and a gate line 111 is formed by a first patterning process; for example, the first metal layer is formed by a magnetron sputtering method, and the first step is made.
  • the metal layer material includes any one of aluminum, molybdenum, aluminum-nickel alloy, chromium, copper, or a combination thereof; or, as the gate line 111 is formed, a common electrode line is further formed;
  • Step 2 As shown in FIG. 5B, a gate insulating layer 117 is formed on the gate line 111; for example, the gate insulating layer 117 is formed by a chemical vapor deposition method, and the material for forming the gate insulating layer 117 includes silicon nitride, silicon oxide, and oxynitride. Any one or combination of silicon;
  • Step 3 As shown in FIG. 5C, an active layer 119 is formed on the gate insulating layer 117 by a second patterning process; for example, the active layer 119 is formed by a chemical vapor deposition method, and the material for forming the active layer 119 includes amorphous Silicon, polysilicon, oxide semiconductor, etc.;
  • Step 4 As shown in FIG. 5D, a second metal layer is formed on the active layer 119, and the source 121, the drain 122, and the first data line 112 are formed by a third patterning process (the first data line 112 is as shown in FIG. 4).
  • the second metal layer is formed by magnetron sputtering, and the second metal layer material is made of any one of aluminum, molybdenum, aluminum-nickel alloy, chromium, copper, or a combination thereof;
  • Step 5 As shown in FIG. 5E, a first passivation layer 130 is formed on the source 121 and the drain 122, and a first via 115 corresponding to the source 121 is formed by a fourth patterning process (the source 121) A via 115 is shown in FIG. 4 and a second via 116 corresponding to the drain 122; for example, the first passivation layer 130 is formed by chemical vapor deposition, and the material of the first passivation layer 130 is made of oxide. Or nitride;
  • Step 6 As shown in FIG. 5F, a planarization layer 160 is formed on the first passivation layer 130 by a fifth patterning process; for example, the planarization layer 160 is formed by a chemical vapor deposition method, and a material for forming the planarization layer is, for example, Resin
  • Step 7 As shown in FIG. 5G, the shield electrode layer 140 is formed on the planarization layer 160 by a sixth patterning process; for example, the material for fabricating the shield electrode layer 140 includes indium tin oxide (ITO) or indium zinc oxide (IZO). Or, as the shield electrode layer 140 is formed, a common electrode located in the pixel unit is formed, the common electrode and the shield electrode layer being formed, for example, of the same material, and the common electrode may pass through the additionally formed via hole with the common electrode line Electrical connection
  • Step 8 As shown in FIG. 5H, a second passivation layer 150 is formed on the shield electrode layer 140 by a seventh patterning process; for example, the second passivation layer 150 is formed by a chemical vapor deposition method to form a second passivation layer.
  • the material of 150 includes an oxide or a nitride;
  • Step 9 forming a third metal layer on the second passivation layer 150, and forming a second data line 113 by the eighth patterning process (the second data line 113 is as shown in FIG. 4); for example, the third metal layer passes the magnetic Forming a method of controlling sputtering, forming a third metal layer material comprising any one of aluminum, molybdenum, aluminum-nickel alloy, chromium, copper or a combination thereof;
  • Step 10 As shown in FIG. 5I, a pixel electrode 118 located in the pixel unit and a protective layer 170 over the second data line 113 are formed on the second passivation layer 150 by the ninth patterning process (the protective layer 170 is as 4]; for example, the pixel electrode 118 and the protective layer 170 are formed of the same material, which includes, for example, indium tin oxide (ITO).
  • the protective layer 170 is as 4]; for example, the pixel electrode 118 and the protective layer 170 are formed of the same material, which includes, for example, indium tin oxide (ITO).
  • ITO indium tin oxide
  • each patterning process includes processes such as exposure, development, etching, and stripping.
  • Embodiments of the present disclosure also provide a display panel 10 including the array substrate of any of the embodiments of the present disclosure.
  • the display panel 10 further includes a counter substrate 200.
  • the display panel 10 is formed by the array substrate 100 and the counter substrate 200.
  • the array substrate 100 and the counter substrate 200 are filled in the cavity after the box. liquid crystal.
  • the opposite substrate 200 is, for example, a color filter substrate, and includes a counter substrate substrate 210, a black matrix 180, and a color film unit (not shown in FIG. 6).
  • the width of the black matrix 180 on the color filter substrate is the same as that on the array substrate.
  • the total width of one data line and the second data line is equal or larger.
  • the embodiment of the display panel illustrated in FIG. 6 is an embodiment based on the array substrate illustrated in FIG. 4, but the present disclosure is not limited thereto, and the display panel may be prepared, for example, based on the embodiment of the array substrate illustrated in FIG. 3.
  • Embodiments of the present disclosure provide a display device, including any of the embodiments of the present disclosure.
  • Display panel
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the array substrate, the display panel and the display device provided by the embodiments of the present disclosure reduce the area occupied by the two data lines, so that the area of the black matrix corresponding to the corresponding need is reduced, thereby improving the aperture ratio of the liquid crystal display panel.

Abstract

一种阵列基板（100）及其制造方法、显示面板（10）和显示装置。阵列基板（100）包括衬底基板（110）、设置于衬底基板（110）上的多条栅线（111）、多条第一数据线（112）、多条第二数据线（113）和以矩阵形式排布的多行和多列像素单元（114）。每行像素单元（114）由相应的栅线（111）驱动，多行像素单元（114）中，每两行构成一个像素单元行组且像素单元行组在阵列基板（100）的工作过程中接收相同的栅极信号；每列像素单元（114）由相应的第一数据线（112）和第二数据线（113）驱动，相邻的第一数据线（112）和第二数据线（113）相互绝缘、设置于不同的层，且连接到不同的像素单元（114），相邻的第一数据线（112）和第二数据线（113）在垂直于衬底基板（110）的板面的方向上至少部分交叠。阵列基板（100）减小了两条数据线占用的面积，使相应的黑矩阵（180）面积减小，提高了液晶显示面板的开口率。

Description

阵列基板及其制造方法、显示面板和显示装置 技术领域
本公开的实施例涉及一种阵列基板及其制造方法、显示面板和显示装置。
背景技术
TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)图像显示品质好、能耗低且环保，广泛应用于显示器领域。
TFT-LCD中的显示面板通过将阵列基板和对置基板对盒形成，阵列基板和对置基板对盒后的空腔内填充有液晶。阵列基板上形成有横纵交叉的数据线和栅线，数据线和栅线交叉形成矩阵形式排列的像素单元。
发明内容
本公开的实施例提供一种阵列基板，包括衬底基板、设置于所述衬底基板上的多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，其中，每行所述像素单元由相应的栅线驱动，所述多行像素单元中，每两行构成一个像素单元行组且所述像素单元行组在所述阵列基板的工作过程中接收相同的栅极信号；每列所述像素单元由相应的第一数据线和第二数据线驱动，相邻的所述第一数据线和所述第二数据线相互绝缘、设置于不同的层，且连接到不同的像素单元，所述相邻的第一数据线和所述第二数据线在垂直于所述衬底基板的板面的方向上至少部分交叠。
例如，在本公开一实施例提供的阵列基板中，第2m-1行所述像素单元与第2m行所述像素单元构成一个像素单元行组且在所述阵列基板的工作过程中接收相同的栅极信号，m为大于或等于1的自然数。
例如，本公开一实施例提供的阵列基板，还包括多个第一过孔和设置在每个所述像素单元中的薄膜晶体管，其中，所述第一数据线与每个像素单元行组中的一行所述像素单元中的薄膜晶体管的源极和漏极同层设置，所述第二数据线通过相应的所述第一过孔与所述像素单元行组中的另一行所述像素单元中的薄膜晶体管电连接。
例如，在本公开一实施例提供的阵列基板中，所述第一过孔与所述栅线在所述阵列基板的板面方向上至少部分交叠。
例如，本公开一实施例提供的阵列基板，还包括第一钝化层，其中，所述第一钝化层设置于所述第一数据线与所述第二数据线之间。
例如，在本公开一实施例提供的阵列基板中，所述第一钝化层为无机绝缘层。
例如，本公开一实施例提供的阵列基板，还包括屏蔽电极层和公共电极，其中，所述屏蔽电极层设置于所述第一钝化层和所述第二数据线之间，所述屏蔽电极层与所述公共电极同层设置、由相同的材料形成且被施加相同的电压。
例如，本公开一实施例提供的阵列基板，还包括第二钝化层，其中，所述第二钝化层设置在所述屏蔽电极层和所述第二数据线之间。
例如，在本公开一实施例提供的阵列基板中，所述第二钝化层为无机绝缘层。
例如，本公开一实施例提供的阵列基板，还包括平坦化层，其中，所述平坦化层设置于所述屏蔽电极层与所述第一钝化层之间。
例如，在本公开一实施例提供的阵列基板中，所述平坦化层为树脂层。
例如，本公开一实施例提供的阵列基板，还包括保护层和像素电极，其中，所述保护层设置在所述第二数据线上，所述保护层和所述像素电极同层设置且由相同的材料形成。
例如，在本公开一实施例提供的阵列基板中，所述保护层为氧化铟锡层。
本公开的实施例提供还提供一种显示面板，包括本公开任一实施例所述的阵列基板。
本公开的实施例提供还提供一种显示装置，包括本公开任一实施例所述的显示面板。
本公开的实施例提供还提供一种阵列基板的制造方法，包括：在衬底基板上形成多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，其中，每行所述像素单元由相应的栅线驱动，所述多行像素单元中，每两行构成一个像素单元行组；每列像素单元由相应的第一数据线和第二数据线驱动，相邻的所述第一数据线和所述第二数据线相互绝 缘、设置于不同的层，且连接到不同的像素单元，所述相邻的第一数据线和所述第二数据线在垂直于衬底基板的板面的方向上至少部分交叠。
例如，本公开一实施例提供的阵列基板的制造方法，还包括，在所述第一数据线和所述第二数据线之间形成第一钝化层。
例如，本公开一实施例提供的阵列基板的制造方法，还包括，在同一次图案化工艺中形成屏蔽电极层和公共电极，其中，所述屏蔽电极层设置在所述第一钝化层和所述第二数据线之间。
例如，本公开一实施例提供的阵列基板的制造方法，还包括，在所述屏蔽电极层和所述第二数据线之间形成第二钝化层。
例如，本公开一实施例提供的阵列基板的制造方法，还包括，在同一次图案化工艺中形成保护层和像素电极，其中，所述保护层设置在所述第二数据线上。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是一种阵列基板的俯视示意图；
图2是本公开实施例提供的一种阵列基板的俯视示意图；
图3是本公开实施例提供的一种阵列基板的一个示例沿图2中AA’线的剖视示意图；
图4是本公开实施例提供的一种阵列基板的又一个示例沿图2中AA’线的剖视示意图；
图5A至图5I是本公开实施例提供的一种与图4对应的阵列基板的制造方法沿图2中BB’线的剖视示意图；以及
图6是本公开实施例提供的一种显示面板的剖视示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地 说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了部分已知材料、组件和工艺技术的描述，但不会使得本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
液晶显示面板的阵列基板可由逐行扫描方式驱动，这种驱动方法在提高刷新频率时，可能造成像素电极的充电时间不足，进而导致画面质量较差，阻碍了大尺寸、高分辨率液晶显示产品的发展。液晶显示面板的阵列基板也可以采用双行扫描的方式，即任何时刻都有两行像素电极处于充电状态，可为每个像素电极提供两倍于原有逐行扫描驱动方式的充电时间，保证了画面质量，尤其适合于大尺寸、高分辨率液晶显示产品。双行扫描方式需要对每列像素单元对应设置两条数据线，而且两条数据线间需要间隔一定的距离。对应于在阵列基板上的数据线，靠近液晶显示面板出光面的一侧的对置基板(例如彩膜基板)上可设置黑矩阵。因此，当两条数据线同层设置时，在数据线的宽度方向上，黑矩阵的宽度也相应增加，导致液晶显示面板开口率的下降。
例如，当刷新频率为60Hz，像素单元的行数为1024，驱动采用逐行扫描时，每行像素电极的充电时间为1/(1024×60)s，约为16.3μs，也就是说从一个灰阶切换到另一个灰阶需要在约16.3μs内完成(这也包括充电电压达到要求值以及液晶偏转总共需要的时间)。但在双行扫描方式下，每行像素电极的充电时间为1/(512×60)s，约为32.6μs，即双行扫描方式为每行像素单元中的像素电极提供两倍于原有逐行扫描驱动方式的充电时间。
例如，图1是一种阵列基板100’的俯视示意图。该阵列基板100’包括多条第一数据线112’、多条第二数据线113’、多条栅线111’和多个像素单元 114’，每个像素单元114’中设置有薄膜晶体管120’和像素电极118’，其中，第一数据线112’和第二数据线113’同层设置且分别与不同行像素单元中的薄膜晶体管120’的源极121’电连接。薄膜晶体管120’中的漏极122’通过第二过孔116’与像素单元118’电连接。每两行像素单元114’在阵列基板100’的工作过程中接收相同的栅极信号，例如，图中用于驱动第一行和第二行像素单元的两条栅线在工作过程中接收相同的栅极信号，由此第一行和第二行像素单元被同步开启和关闭。黑矩阵180’覆盖第一数据线112’、多条第二数据线113’和多条栅线111’，该黑矩阵180’可以设置在液晶面板中与该阵列基板相对设置的对置基板之上，或者可以直接设置在该阵列基板上。
图1所示的阵列基板100’可以实现双行扫描的工作方式，可为每个像素电极提供两倍于原有逐行扫描驱动方式的充电时间，但与逐行扫描驱动方式相比，黑矩阵180’覆盖的面积增大，导致采用该阵列基板的液晶显示面板开口率的下降，从而增加了能耗。
本公开的实施例提供一种阵列基板，包括衬底基板、设置于衬底基板上的多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，其中，每行像素单元由相应的栅线驱动，多行像素单元中，每两行构成一个像素单元行组且像素单元行组在阵列基板的工作过程中接收相同的栅极信号；每列像素单元由相应的第一数据线和第二数据线驱动，相邻的第一数据线和第二数据线相互绝缘、设置于不同的层，且连接到不同的像素单元，第一数据线和第二数据线在垂直于衬底基板的板面的方向上至少部分交叠。
本公开实施例提供的阵列基板减小了两条数据线占用的面积，由此可使相应需要覆盖黑矩阵面积减小，进而提高了采用该阵列基板的液晶显示面板的开口率，降低了液晶面板的功耗。
图2是本公开一个实施例提供的一种阵列基板的俯视示意图；图3是本公开实施例提供的一种阵列基板的一个示例沿图2中AA’线的剖视示意图；图4是本公开实施例提供的一种阵列基板的又一个示例沿图2中AA’线的剖视示意图；图5I是本公开实施例提供的一种与图4对应的阵列基板沿图2中BB’线的剖视示意图。
如图2、图3、图4、图5I所示，本公开的实施例提供一种阵列基板100， 其包括衬底基板110、设置于衬底基板110上的多条栅线111、多条第一数据线112、多条第二数据线113和以矩阵形式排布的多行和多列像素单元114，其中，每行像素单元114由相应的栅线111驱动。多行像素单元114中，每两行构成一个像素单元行组且像素单元行组在阵列基板100的工作过程中接收相同的栅极信号，例如用于一个像素单元行组的两条栅线连接到同一个栅驱动器。每列像素单元114由相应的第一数据线112和第二数据线113驱动，相邻的第一数据线112和第二数据线113相互绝缘、设置于不同的层，且连接到所述列中不同的像素单元114，该相邻的第一数据线112和第二数据线113在垂直于衬底基板110的板面的方向上至少部分交叠。例如，该相邻的第一数据线112和第二数据线113在垂直于衬底基板110的板面的方向上完全交叠。例如，在上层的第二数据线113相对于衬底基板110的投影完全落入在下层的第一数据线112相对于衬底基板110的投影之中，因此第二数据线113的宽度小于等于第一数据线112的宽度。
如图2所示，两列像素单元之间彼此相邻的第一数据线112和第二数据线113分别用于驱动位于它们两侧的两列像素单元，图中第一数据线112用于驱动左侧一列中的第1、3、5......行中的像素单元，第二数据线113用于驱动右侧一列中的第2、4、6......行中的像素单元。然而，本公开的实施例不限于此，两列像素单元之间彼此相邻的第一数据线112和第二数据线113可以用于驱动位于它们同一侧的一列像素单元，例如第一数据线112用于驱动该列中的第1、3、5......行中的像素单元，第二数据线113用于该列中的第2、4、6......行中的像素单元。
例如，如图2所示，与图1中黑矩阵180’相比，由于两列像素单元之间彼此相邻的第一数据线112和第二数据线113交叠设置，二者总地占用基板面积相对于二者彼此并列设置时减小，从而图2中黑矩阵180覆盖的面积减小，提升了采用该阵列基板的液晶显示面板的开口率。
例如，在本公开一实施例提供的阵列基板100中，第2m-1行像素单元与第2m行像素单元构成一个像素单元行组且在阵列基板100的工作过程中接收相同的栅极信号，m为大于或等于1的自然数。
在本公开的另一个实施例中，构成一个像素单元行组的两行像素单元不相邻，例如，第4m-3行和第4m-1行像素单元构成一个像素单元行组，第4m-2 行和第4m行像素单元构成一个像素单元行组，m为大于或等于1的自然数；或者，如果整个阵列基板包括2n行像素单元，则第m行和第n+m行像素单元构成一个像素单元行组，m、n为大于或等于1的自然数，且m<n。
例如，本公开一实施例提供的阵列基板100，还包括多个第一过孔115和设置在每个像素单元114中的薄膜晶体管120，其中，第一数据线与每个像素单元行组中的一行像素单元中的薄膜晶体管的源极和漏极同层设置，第二数据线通过相应的第一过孔与像素单元行组中的另一行像素单元中的薄膜晶体管电连接。例如，对于上述第2m-1行像素单元与第2m行像素单元构成一个像素单元行组的情形，第一数据线112与第2m-1行像素单元中薄膜晶体管120的源极121和漏极122同层设置且与源极121(抑或漏极122)电连接，第二数据线113通过第一过孔115与第2m行像素单元中薄膜晶体管120的源极121(抑或漏极122)电连接；或者，第一数据线112与第2m行像素单元中薄膜晶体管120的源极121和漏极122同层设置且与源极121(抑或漏极122)电连接，第二数据线113通过第一过孔115与第2m-1行像素单元中薄膜晶体管120的源极121(抑或漏极122)电连接。
例如，如图2所示，薄膜晶体管120的漏极122通过第二过孔116与像素单元118电连接。
例如，对于图2所示的阵列基板100的双行扫描的工作原理可如下所述。下面的描述以第2m-1行像素单元与第2m行像素单元构成一个像素单元行组(m为大于或等于1的自然数)的情形为例进行说明，但是其他实施例中像素单元行组构成方式也同样适用。
在第一预设时刻，第1行像素单元的栅线与第2行像素单元的栅线接收相同的栅极开启信号，同时打开了第1行像素单元和第2行像素单元；与此同时，通过第一数据线112向第1行像素单元或第2行像素单元发送数据信号，相应地通过第二数据线113向第2行像素单元或第1行像素单元发送数据信号，在经历一个周期后第1行像素单元的栅线与第2行像素单元的接收相同的栅极关闭信号，同时关闭了第1行像素单元和第2行像素单元，实现同时驱动第1行像素单元和第2行像素单元。
在第二预设时刻，第3行像素单元的栅线与第4行像素单元的栅线接收相同的栅极开启信号，同时打开了第3行像素单元和第4行像素单元；与此 同时，通过第一数据线112向第3行像素单元或第4行像素单元发送数据信号，相应地通过第二数据线113向第4行像素单元或第3行像素单元发送数据信号，在经历一个周期后第3行像素单元的栅线与第4行像素单元的接收相同的栅极关闭信号，同时关闭了第3行像素单元和第4行像素单元，实现同时驱动第3行像素单元和第4行像素单元。
如上操作针对之后的各个像素单元行组依次进行，直到整个阵列基板的像素单元行都被充电，由此完成了一帧画面的扫描。
例如，第2m-1行像素单元与第2m行像素单元可由同一个栅极驱动器或栅极驱动器的同一输出通道驱动，实现接收相同的栅极信号。因此，栅极驱动器或栅极驱动器输出通道数量减少，简化了电路设计，节省了栅极驱动器的成本。
例如，如图2所示，在本公开一实施例提供的阵列基板100中，第一过孔115与栅线111在阵列基板100的板面方向上至少部分交叠。第一过孔115与栅线111交叠设置可以使第一过孔115不占用像素电极118的面积，从而提高开口率。
例如，薄膜晶体管120的形状不局限于如图2所示的U形薄膜晶体管，也可为直线形薄膜晶体管，在此不做限定。
例如，图3是本公开实施例提供的一种阵列基板的一个示例沿图2中AA’线的剖视示意图。如图3所示，本公开一实施例提供的阵列基板100，还包括第一钝化层130，其中，第一钝化层130设置于第一数据线112与第二数据线113之间。第一钝化层130使相邻的第一数据线112和第二数据线113彼此绝缘，并且减小第一数据线112和第二数据线113之间的信号串扰。
例如，在本公开一实施例提供的阵列基板100中，第一钝化层130为无机绝缘层。
例如，图4是本公开实施例提供的一种阵列基板的又一个示例沿图2中AA’线的剖视示意图。如图4所示，本公开一实施例提供的阵列基板100还包括屏蔽电极层140和公共电极，其中，屏蔽电极层140设置于第一钝化层130和第二数据线113之间，屏蔽电极层140与公共电极同层设置、由相同的材料形成且被施加相同的电压。屏蔽电极层140可以减小第一数据线112和第二数据线113之间的信号串扰。例如，屏蔽电极层140可由氧化铟锡 (ITO)形成。
例如，本公开一实施例提供的阵列基板100还可包括第二钝化层150，其中，第二钝化层150设置在屏蔽电极层140和第二数据线113之间。第二钝化层150使屏蔽电极层140和第二数据线113绝缘，并且减小第一数据线112和第二数据线113之间的信号串扰。
例如，在本公开一实施例提供的阵列基板100中，第二钝化层150为无机绝缘层。
该屏蔽电极140可以直接形成在第一钝化层130上；或者，例如，本公开一实施例提供的阵列基板100还可包括平坦化层160，其中，平坦化层160设置于屏蔽电极层140与第一钝化层130之间。平坦化层160可起到平坦化的作用，便于后续膜层的均匀形成，同时减小第一数据线112和第二数据线113之间的信号串扰。
例如，在本公开一实施例提供的阵列基板100中，平坦化层160例如为树脂层。
例如，本公开一实施例提供的阵列基板100还可包括保护层170和像素电极，其中，保护层170设置在第二数据线113上，例如覆盖第二数据线113，保护层170和像素电极同层设置且由相同的材料形成，即保护层170可以在不增加工艺的情况下形成。保护层170可以保护第二数据线113，防止第二数据线113被氧化。
例如，在本公开一实施例提供的阵列基板100中，保护层170例如为氧化铟锡(ITO)层。
本公开的实施例提供还提供一种阵列基板的制造方法，包括：在衬底基板上形成多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，其中，每行像素单元由相应的栅线驱动，多行像素单元中，每两行构成一个像素单元行组；每列像素单元由相应的第一数据线和第二数据线驱动，相邻的第一数据线和第二数据线相互绝缘、设置于不同的层，且连接到列中不同的像素单元，该相邻的第一数据线和第二数据线在垂直于衬底基板的板面的方向上至少部分交叠。
例如，本公开一实施例提供的阵列基板的制造方法还包括，在第一数据线和第二数据线之间形成第一钝化层。
例如，本公开一实施例提供的阵列基板的制造方法还包括，在第一钝化层和第二数据线之间形成屏蔽电极层。
例如，本公开一实施例提供的阵列基板的制造方法还包括，在屏蔽电极层和第二数据线之间形成第二钝化层。
例如，本公开一实施例提供的阵列基板的制造方法还包括，在第二数据线上形成保护层。
例如，图5A至图5I是本公开实施例提供的一种与图4对应的阵列基板的制造方法沿图2中BB’线的剖视示意图，以用于说明，本公开的实施例不限于其示出的具体结构和步骤。
例如，本公开的实施例提供还提供一种阵列基板的制造方法的一个示例如图5A至图5I所示，具体包含如下步骤：
步骤1:如图5A所示，在衬底基板110上形成第一金属层，通过第一次构图工艺形成栅线111；例如，第一金属层通过磁控溅射的方法形成，制作第一金属层材料包括铝、钼、铝镍合金、铬、铜中任一种或其组合；或者，随着形成栅线111，还形成公共电极线；
步骤2:如图5B所示，在栅线111上形成栅绝缘层117；例如，栅绝缘层117通过化学气相沉积法形成，制作栅绝缘层117的材料包括氮化硅、氧化硅和氮氧化硅中的任一种或其组合；
步骤3:如图5C所示，通过第二次构图工艺在栅绝缘层117上形成有源层119；例如，有源层119通过化学气相沉积法形成，制作有源层119的材料包括非晶硅、多晶硅、氧化物半导体等；
步骤4:如图5D所示，在有源层119上形成第二金属层，通过第三次构图工艺形成源极121、漏极122和第一数据线112(第一数据线112如图4所示)；例如，第二金属层通过磁控溅射的方法形成，制作第二金属层材料包括铝、钼、铝镍合金、铬、铜中任一种或其组合；
步骤5:如图5E所示，在源极121、漏极122上形成第一钝化层130，通过第四次构图工艺形成对应于源极121的第一过孔115(源极121的第一过孔115如图4所示)和对应于漏极122的第二过孔116；例如，第一钝化层130通过化学气相沉积法形成，制作第一钝化层130的材料包括氧化物或氮化物；
步骤6:如图5F所示，通过第五次构图工艺在第一钝化层130上形成平坦化层160；例如，平坦化层160通过化学气相沉积法形成，制作平坦化层的材料例如为树脂；
步骤7:如图5G所示，通过第六次构图工艺在平坦化层160上形成屏蔽电极层140；例如，制作屏蔽电极层140的材料包括氧化铟锡(ITO)或氧化铟锌(IZO)；或者，随着形成屏蔽电极层140，还形成位于像素单元内的公共电极，该公共电极与该屏蔽电极层例如由相同的材料形成，该公共电极可以与公共电极线通过另外形成的过孔电连接；
步骤8:如图5H所示，通过第七次构图工艺在屏蔽电极层140上形成第二钝化层150；例如，第二钝化层150通过化学气相沉积法形成，制作第二钝化层150的材料包括氧化物或氮化物；
步骤9:在第二钝化层150上形成第三金属层，通过第八次构图工艺形成第二数据线113(第二数据线113如图4所示)；例如，第三金属层通过磁控溅射的方法形成，制作第三金属层材料包括铝、钼、铝镍合金、铬、铜中任一种或其组合；
步骤10:如图5I所示，通过第九次构图工艺在第二钝化层150上形成位于像素单元内的像素电极118和位于第二数据线113之上的保护层170(保护层170如图4所示)；例如，像素电极118和保护层170由相同的材料形成，该材料例如包括氧化铟锡(ITO)。
例如，每次构图工艺包括曝光、显影、刻蚀、剥离等工艺。
本公开的实施例还提供一种显示面板10，包括本公开任一实施例所述的阵列基板。
例如，如图6所示，显示面板10还包括对置基板200，显示面板10通过阵列基板100和对置基板200对盒形成，阵列基板100和对置基板200对盒后的空腔内填充液晶。该对置基板200例如为彩膜基板，包括对置衬底基板210、黑矩阵180以及彩膜单元(图6中未示出)，彩膜基板上的黑矩阵180的宽度与阵列基板上第一数据线和第二数据线总的宽度相等或更大。该图6所示出的显示面板的实施例为基于图4所示的阵列基板的实施例，但是本公开不限于此，例如可基于图3所示的阵列基板的实施例来制备显示面板。
本公开的实施例提供还提供一种显示装置，包括本公开任一实施例所述 的显示面板。
例如，本公开的实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的阵列基板、显示面板和显示装置减小了两条数据线占用的面积，使相应需要覆盖黑矩阵面积减小，进而提高了液晶显示面板的开口率。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年3月29日递交的中国专利申请第201610190726.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括衬底基板、设置于所述衬底基板上的多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，其中，
    每行所述像素单元由相应的栅线驱动，所述多行像素单元中，每两行构成一个像素单元行组且所述像素单元行组在所述阵列基板的工作过程中接收相同的栅极信号；
    每列所述像素单元由相应的第一数据线和第二数据线驱动，相邻的所述第一数据线和所述第二数据线相互绝缘、设置于不同的层，且连接到不同的像素单元，所述相邻的第一数据线和所述第二数据线在垂直于所述衬底基板的板面的方向上至少部分交叠。
  2. 根据权利要求1所述的阵列基板，其中，
    第2m-1行所述像素单元与第2m行所述像素单元构成一个像素单元行组且在所述阵列基板的工作过程中接收相同的栅极信号，m为大于或等于1的自然数。
  3. 根据权利要求1或2所述的阵列基板，还包括多个第一过孔和设置在每个所述像素单元中的薄膜晶体管，其中，
    所述第一数据线与每个像素单元行组中的一行所述像素单元中的薄膜晶体管的源极和漏极同层设置，所述第二数据线通过相应的所述第一过孔与所述像素单元行组中的另一行所述像素单元中的薄膜晶体管电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第一过孔与所述栅线在所述阵列基板的板面方向上至少部分交叠。
  5. 根据权利要求1或2所述的阵列基板，还包括第一钝化层，其中，所述第一钝化层设置于所述第一数据线与所述第二数据线之间。
  6. 根据权利要求5所述的阵列基板，其中，所述第一钝化层为无机绝缘层。
  7. 根据权利要求5所述的阵列基板，还包括屏蔽电极层和公共电极，其中，所述屏蔽电极层设置于所述第一钝化层和所述第二数据线之间，所述屏蔽电极层与所述公共电极同层设置、由相同的材料形成且被施加相同的电压。
  8. 根据权利要求7所述的阵列基板，还包括第二钝化层，其中，所述第二钝化层设置在所述屏蔽电极层和所述第二数据线之间。
  9. 根据权利要求8所述的阵列基板，其中，所述第二钝化层为无机绝缘层。
  10. 根据权利要求8所述的阵列基板，还包括平坦化层，其中，所述平坦化层设置于所述屏蔽电极层与所述第一钝化层之间。
  11. 根据权利要求10所述的阵列基板，其中，所述平坦化层为树脂层。
  12. 根据权利要求10所述的阵列基板，还包括保护层和像素电极，其中，所述保护层设置在所述第二数据线上，所述保护层和所述像素电极同层设置且由相同的材料形成。
  13. 根据权利要求12所述的阵列基板，其中，所述保护层为氧化铟锡层。
  14. 一种显示面板，包括如权利要求1-13任一项所述的阵列基板。
  15. 一种显示装置，包括如权利要求14所述的显示面板。
  16. 一种阵列基板的制造方法，包括：
    在衬底基板上形成多条栅线、多条第一数据线、多条第二数据线和以矩阵形式排布的多行和多列像素单元，
    其中，每行所述像素单元由相应的栅线驱动，所述多行像素单元中，每两行构成一个像素单元行组；
    每列像素单元由相应的第一数据线和第二数据线驱动，相邻的所述第一数据线和所述第二数据线相互绝缘、设置于不同的层，且连接到不同的像素单元，所述相邻的第一数据线和所述第二数据线在垂直于衬底基板的板面的方向上至少部分交叠。
  17. 根据权利要求16所述的阵列基板的制造方法，还包括，在所述第一数据线和所述第二数据线之间形成第一钝化层。
  18. 根据权利要求17所述的阵列基板的制造方法，还包括，在同一次图案化工艺中形成屏蔽电极层和公共电极，其中，所述屏蔽电极层设置在所述第一钝化层和所述第二数据线之间。
  19. 根据权利要求18所述的阵列基板的制造方法，还包括，在所述屏蔽电极层和所述第二数据线之间形成第二钝化层。
  20. 根据权利要求19所述的阵列基板的制造方法，还包括，在同一次图 案化工艺中形成保护层和像素电极，其中，所述保护层设置在所述第二数据线上。
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