CN106229319A - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents
阵列基板及其制造方法、显示面板和显示装置 Download PDFInfo
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- 238000000034 method Methods 0.000 title abstract description 17
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- 239000010409 thin film Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 32
- 238000001514 detection method Methods 0.000 abstract description 10
- 230000002787 reinforcement Effects 0.000 abstract 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000010408 film Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 239000011787 zinc oxide Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
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- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- -1 static electricity Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 238000000576 coating method Methods 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract
一种阵列基板及其制造方法、显示面板和显示装置,该阵列基板包括衬底基板以及设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线,并且多条公共电极线与多条栅线设置在不同层,多条公共电极线与多条数据线设置在同一层且相互平行,多条栅线与多条数据线、多条公共电极线相互绝缘且交叉以限定多个亚像素单元。在该阵列基板中,公共电极线与栅线设置在不同层,公共电极线与数据线设置在同一层且相互平行,这样可以避免平行配线易于短路的问题,还便于对阵列基板的电路进行检测与维修,加强设备的检出能力,从而可以提高产品的良率。
Description
技术领域
本发明的实施例涉及一种阵列基板及其制造方法、显示面板和显示装置。
背景技术
薄膜晶体管阵列基板经过复杂的工艺流程制造,一般包括在衬底基板上沉积金属薄膜、半导体薄膜,然后通过构图工艺形成所需的金属图案(例如,栅线、数据线、公共电极线)、半导体图案(有源层)。形成信号线时,则需要对信号线的电路进行检测。因为薄膜晶体管阵列基板中有大量的平行配线,这类平行配线由于光刻胶残渣、静电、金属残留物的存在易造成开路、膜层间短路等不良现象。
发明内容
本发明至少一实施例提供一种阵列基板及其制造方法、显示面板和显示装置。在该阵列基板中,公共电极线与栅线设置在不同层,公共电极线与数据线设置在同一层且相互平行便于对阵列基板的电路进行检测与维修,加强设备的检出能力,从而可以提高产品的良率实现收益最大化。
本发明至少一实施例提供一种阵列基板,包括:衬底基板,设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线;其中,所述多条公共电极线与所述多条栅线设置在不同层;所述多条公共电极线与所述多条数据线设置在同一层且相互平行;所述多条栅线与所述多条数据线、所述多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
例如,在本发明一实施例提供的阵列基板中,所述多条数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线,在每两列相邻所述亚像素单元中,奇数行所述亚像素单元连接所述第一数据线,且偶数行所述亚像素单元连接所述第二数据线。
例如,本发明一实施例提供的阵列基板,还包括与所述栅线平行设置的第一数据线总线和第二数据线总线,其中,所述第一数据线均与所述第一数据线总线连接,所述第二数据线均与所述第二数据线总线连接。
例如,在本发明一实施例提供的阵列基板中,所述第一数据线总线与所述第二数据线总线设置在不同层。
例如,本发明一实施例提供的阵列基板,还包括与所述公共电极线设置在不同层且与所述栅线平行设置的公共电极线总线,其中,所述公共电极线均与所述公共电极线总线连接。
例如,在本发明一实施例提供的阵列基板中,所述公共电极线设置在所述栅线的上层或下层。
例如,本发明一实施例提供的阵列基板,还包括设置在每个所述亚像素单元中的薄膜晶体管、公共电极和像素电极,其中,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接,所述公共电极与所述公共电极线连接,所述像素电极与所述薄膜晶体管的漏极连接。
例如,在本发明一实施例提供的阵列基板中,所述薄膜晶体管的半导体层设置在所述数据线所在层与所述栅线所在层之间,所述半导体层与所述栅线所在层之间设置有栅绝缘层。
例如,在本发明一实施例提供的阵列基板中,在所述数据线所在层、所述栅线所在层和所述半导体层上设置有绝缘层。
例如,本发明一实施例提供的阵列基板,还包括多个栅极驱动器,其中,所述多个栅极驱动器分别设置在所述多条栅线的两端。
本发明至少一实施例还提供一种显示面板,包括上述任一阵列基板。
本发明至少一实施例还提供一种显示装置,包括上述显示面板。
本发明至少一实施例还提供一种阵列基板的制作方法,包括:提供衬底基板;在所述衬底基板上形成栅线、数据线和公共电极线;其中,所述公共电极线与所述栅线在不同层上形成;所述公共电极线与所述数据线在同一层上形成且相互平行;所述栅线与所述数据线、所述公共电极线相互绝缘且交叉以限定多个亚像素单元。
例如,在本发明一实施例提供的制作方法中,所述数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线,在每两列相邻所述亚像素单元中,奇数行所述亚像素单元连接所述第一数据线,且偶数行所述亚像素单元连接所述第二数据线。
例如,本发明一实施例提供的制作方法,还包括:形成第一数据线总线和第二数据线总线,其中,所述第一数据线均与所述第一数据线总线连接,所述第二数据线均与所述第二数据线总线连接,且所述第一数据线总线和所述第二数据线总线均与所述栅线平行。
例如,在本发明一实施例提供的制作方法中,所述第一数据线总线与所述第二数据线总线在不同层上形成。
例如,本发明一实施例提供的制作方法,还包括:形成公共电极线总线,其中,所述公共电极线总线与所述公共电极线在不同层上形成且与所述栅线平行,所述公共电极线均与所述公共电极线总线连接。
例如,在本发明一实施例提供的制作方法中,所述公共电极线在所述栅线的上层或下层形成。
例如,本发明一实施例提供的制作方法,还包括:在每个所述亚像素单元中形成薄膜晶体管、公共电极和像素电极,其中,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接,所述公共电极与所述公共电极线连接,所述像素电极与所述薄膜晶体管的漏极连接。
例如,本发明一实施例提供的制作方法,还包括:在所述数据线所在层与所述栅线所在层之间形成薄膜晶体管的半导体层,在所述半导体层与所述栅线所在层之间形成栅绝缘层。
本发明实施例提供的阵列基板及其制造方法、显示面板和显示装置,通过将阵列基板上的多条公共电极线与多条栅线设置在不同层,多条公共电极线与多条数据线设置在同一层且相互平行,从而避免了栅线与公共电极线发生短路,这样可以避免平行配线易于短路的问题,并且还便于对电路进行检测与维修,从而提高产品的良率。
附图说明
为了更清楚地说明本发明实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例,而非对本发明的限制。
图1为本发明一实施例提供的一种阵列基板的平面示意图;
图2为本发明一实施例提供的一种阵列基板的部分截面结构示意图;
图3为本发明一实施例提供的另一种阵列基板的部分截面结构示意图;
图4为本发明一实施例提供的一种阵列基板的制造方法的流程图;
图5为本发明一实施例的一种阵列基板的制造方法的过程图。
附图标记:
1-栅线;2-数据线;21-第一数据线;22-第二数据线;3-公共电极线;4-第一数据总线;5-第二数据总线;6-公共电极总线;7-栅极驱动器;8-信号输入器;9-阵列基板;901,911-衬底基板;902,912-栅极层;903,913-栅绝缘层;904,914-半导体层;905,915-源漏电极层;9051,9151-漏极;9052,9152-源极;906,916-绝缘层;907,917-像素电极;908-亚像素单元;909,919-过孔结构;910-缓冲层;918-钝化层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图,对本发明实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
目前,薄膜晶体管阵列基板上平行设置的配线(例如栅线、数据线、公共电极线等)可能由于有机物颗粒、静电、金属残留等造成开路、线间短路等问题,可以先通过检测设备中的线检测传感器(Line Detect Sensor,LDS)进行线扫描,找出发生不良的配线的位置,再通过位置检测传感器(Position Detect Sensor,PDS)对发生不良的线进行扫描找出不良的具体的位置坐标。
在目前的薄膜晶体管阵列基板的设计中,栅线与公共电极线在相同的工艺步骤中形成,且相邻两条信号线(特别是相邻的栅线和公共电极线)之间的间距较小,一般在10μm左右,相邻两条信号线容易发生短路,而目前检测设备的检测精度为28μm,发生短路不良时,检测设备无法检测出发生不良的具体位置。
本发明至少一实施例提供一种阵列基板及其制造方法、显示面板和显示装置,该阵列基板包括衬底基板以及设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线,并且多条公共电极线与多条栅线设置在不同层,多条公共电极线与多条数据线设置在同一层且相互平行,多条栅线与多条数据线、多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
在该阵列基板中,公共电极线与栅线设置在不同层,公共电极线与数据线设置在同一层且相互平行,由此便于对阵列基板的电路进行检测与维修,加强设备的检出能力,从而可以提高产品的良率。
下面通过几个实施例进行说明。
实施例一
本实施例提供一种阵列基板,图1为本发明一实施例提供的一种阵列基板的平面示意图,如图1所示,该阵列基板包括衬底基板901以及设置在衬底基板901上的多条彼此平行的栅线1(图1中加粗线所示)、多条彼此平行的数据线2和多条彼此平行的公共电极线3。多条公共电极线3与多条栅线1设置在不同层;多条公共电极线3与多条数据线2设置在同一层且相互平行;多条栅线1与多条数据线2、多条公共电极线3相互绝缘且交叉以限定多个亚像素单元908。由此,多个亚像素单元908按照阵列方式排列。
本实施例中的阵列基板,通过将多条公共电极线3与多条栅线1设置在不同层且多条公共电极线3与多条数据线2设置在同一层且相互平行,从而避免了栅线1与公共电极线3设置在同一层时需要彼此平行布线而易于发生短路的问题,并且,当阵列基板上的信号线出现短路或者断路时,便于对其进行检测与维修,从而提高产品的良率。
例如,图2为本发明一实施例提供的一种阵列基板的部分截面结构示意图。图2示出了采用底栅型薄膜晶体管的像素结构,但本发明的实施例不限于此,例如像素结构也可以采用顶栅型薄膜晶体管。
在图2所示的实施例中,栅极层902(包括薄膜晶体管的栅极以及与之连接的栅线)形成在衬底基板901上;栅绝缘层903覆盖在栅极层902和衬底基板901上;半导体层904形成在栅绝缘层903上;源漏电极层905形成在栅绝缘层903和半导体层904之上,漏极9051和源极9052彼此间隔开地设置在半导体层904上,数据线与源极9052一体形成。绝缘层906(或钝化层)形成在栅绝缘层903、半导体904以及源漏电极层905之上;绝缘层906中形成有过孔结构909以暴露出部分漏极9051,像素电极907形成在绝缘层906上,通过过孔结构909与漏极9051电连接。
如图1和图2所示,多条数据线2包括并排设置在每两列相邻亚像素单元908之间的第一数据线21和第二数据线22,且在行方向上第一数据线21与第二数据线22交替设置。在每两列相邻的亚像素单元908中,例如,奇数行亚像素单元连接第一数据线21,且偶数行亚像素单元连接第二数据线22。
该阵列基板9还可以包括第一数据线总线连接、第二数据线总线和公共电极线总线,亚像素单元包括薄膜晶体管、公共电极和像素电极(未示出)。在本实施例中,例如,相对于衬底基板901,公共电极线3设置在栅线1的上层。
例如,公共电极线3设置在相邻的两列亚像素单元之间,且该两列相邻的亚像素单元共用位于其中间的公共电极线3。
例如,本实施例中的阵列基板还可以包括与栅线1平行设置的第一数据线总线4和第二数据线总线5,例如,所有第一数据线21均与第一数据线总线4连接,所有第二数据线22均与第二数据线总线5连接。例如,在第一数据线21和第二数据线22形成后,在检测过程中,利用检测维修设备对第一数据线21和第二数据线22逐一进行扫描。
第一数据线总线4与第二数据线总线5可以设置在相同层或不同层,诸如第一数据总线4设置在栅线1所在的栅极层902,第二数据总线5设置在数据线2所在的源漏电极层904,此种情况下第一数据线21通过形成在栅绝缘层903中的过孔结构与第一数据总线4电连接;或者,第二数据总线5设置在栅线1所在的栅极层902,第一数据总线4设置在数据线2所在的源漏电极层904,此种情况下第二数据线22通过形成在栅绝缘层903中的过孔结构与第二数据总线5电连接。在实际使用中,还可以将第一数据线总线4与第二数据线总线5设置在其他层,在此不再赘述。
例如,本实施例中的阵列基板还可以包括与公共电极线3设置在不同层且与栅线1平行设置的公共电极线总线6,从而使得公共电极线3与栅线1交叉设置,并且公共电极线3均与公共电极线总线6连接,例如公共电极总线6设置在栅线层902中。在实际使用中,还可以将公共电极总线6设置在公共电极线3所在层,且与公共电极线3交叉设置。
例如,本实施例的阵列基板还可以包括设置在每个亚像素单元中的薄膜晶体管、公共电极和像素电极。在本实施例中,薄膜晶体管的栅极与栅线1连接,薄膜晶体管的源极与数据线2连接,公共电极与公共电极线3连接,像素电极与薄膜晶体管的漏极连接。该公共电极可以作为存储电极使用,例如与像素电极在垂直于衬底基板的方向上彼此至少部分重叠从而形成存储电容;或者,该公共电极可以与像素电极形成控制液晶偏转的电场,例如用于IPS(平面开关)型LCD或ADS(高级超维场转换技术)型LCD。
例如,在数据线2所在层与栅线1所在层之间设置有薄膜晶体管的半导体层904,而薄膜晶体管的栅极可以与栅线1一体形成,薄膜晶体管的源极与数据线2一体形成。该半导体层904采用半导体材料形成,该半导体材料例如为非晶硅、微晶硅、多晶硅、氧化物半导体等,该氧化物半导体例如可以为IGZO(铟镓锌氧化物)、ZnO(氧化锌)等。半导体层904所在层与薄膜晶体管的栅极和栅线1所在层之间设置有栅绝缘层903,该栅绝缘层903用于避免半导体层904与薄膜晶体管的栅极和栅线1之间导通。
例如,在数据线2所在层、栅线1所在层和半导体层上均设置有绝缘层,该绝缘层通常采用有机绝缘材料(例如,丙烯酸类树脂)或者无机绝缘材料(例如,氮化硅SiNx或者氧化硅SiOx)形成。
例如,本实施例中的像素电极可以与栅线1设置在同一层,或者设置在半导体层904与数据线2所在的源漏电极层905之间,或设置在数据线2所在的源漏电极层905与绝缘层906之间,或设置在绝缘层906上。像素电极907设置在绝缘层906上(如图2所示)时,在绝缘层906中设置有过孔结构909,像素电极907与数据线2、公共电极线3所在的源漏电极层905中的漏极9051通过该过孔结构909连接。
例如,在本实施例中,阵列基板9还可以包括多个栅极驱动器7,例如GOA(Gate-driver on Array)单元,其中,这些栅极驱动器7可以设置在每条栅线1的一端或两端。如图1所示,多个栅极驱动器7对齐设置在栅线1的两端,且各个栅线1一端设置的栅极驱动器7彼此连接,并通过设置在一个栅极驱动器7一端的信号输入端8向栅极驱动器7输入控制信号等。
在实际应用中,通常在栅线1的两端均设置栅极驱动器7,以避免栅线1过长使得栅极驱动器7施加的信号在栅线1上传输受到阻碍或延迟。
例如,在本实施例中,衬底基板901可以为玻璃基板或塑料基板。
例如,在本实施例中,栅线1、数据线2与公共电极线3分别形成完成后,即可采用开路检测机对数据线2和公共电极线3进行检测,待检测完成后,第一数据总线4、第二数据总线5和公共电极总线6可从阵列基板9上通过切割工艺去除。
实施例二
本实施例提供一种阵列基板9,图3为本发明一实施例提供的另一种阵列基板的部分截面结构示意图,如图3所示,本实施例的阵列基板中薄膜晶体管为顶栅型薄膜晶体管。
例如,如图3所示,在衬底基板911上设置缓冲层910,在缓冲层910上设置半导体层914,在半导体层914上依次形成栅绝缘层913、栅极层912和绝缘层916,在绝缘层916上形成源漏电极层915,在源漏电极层915上依次形成绝缘层916和钝化层918,在钝化层918和绝缘层916上形成过孔结构919,像素电极917通过该过孔结构919与源漏电极层915的漏极9151电连接。同样,薄膜晶体管的栅极与栅线连接,源极9152与数据线连接。
例如,本实施例的阵列基板9其他结构的特征,例如,栅线1、数据线2、公共电极线3、半导体层904等可参照实施例一中的相关描述,其技术效果与实现原理相似,在此不再赘述。
实施例三
本实施例提供一种显示面板,包括实施例一或实施例二中的阵列基板。该显示面板可以是液晶显示面板,还可以是OLED(Organic Light-Emitting Diode,有机发光二极管)显示面板、电子纸显示面板等。
例如,本实施例中的显示面板还包括与阵列基板相对设置的对置基板,显示面板通过阵列基板和对置基板对盒形成,在阵列基板和对置基板对盒后的空腔内填充液晶。该对置基板例如为彩膜基板,可以包括对置衬底基板、黑矩阵以及彩膜单元。
实施例四
本实施例提供一种显示装置,包括实施例三中的显示面板。该显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
实施例五
本实施例提供一种阵列基板的制作方法,图4为本发明一实施例提供的一种阵列基板的制造方法的流程图,如图4所示,该阵列基板的制造方法可以包括如下步骤:
步骤100、提供衬底基板901。
步骤101、在衬底基板901上形成栅线1、数据线2和公共电极线3。公共电极线3与栅线1在不同层上形成,公共电极线3与数据线2在同一层上形成且相互平行,栅线1与数据线2、公共电极线3相互绝缘且交叉以限定多个亚像素单元。
本发明的阵列基板9的制作方法,包括提供衬底基板901和在衬底基板901上形成栅线1、数据线2和公共电极线3,由于公共电极线3与栅线1在不同层上形成,且公共电极线3与数据线2在同一层上形成且相互平行,栅线1与数据线2、公共电极线3相互绝缘且交叉以限定多个亚像素单元,从而有利于检测阵列基板9是否处于短路或断路,从而提高产品的良率。
在图4所示的上述本发明的阵列基板9的实施例的基础之上,本发明的至少一实施例还可以包括以下具体内容。
本发明至少一实施例还提供一种阵列基板9的制作方法,图5为本发明的另一实施例的阵列基板9的制造方法的流程示意图,本实施例的阵列基板9的制造方法可以为上述图2所示的采用底栅型薄膜晶体管的阵列基板9的制造方法,如图5所示,该阵列基板9的制造方法可以包括如下步骤:
步骤200、提供衬底基板。该衬底基板可以为玻璃基板、石英基板等。
步骤201、在衬底基板上形成栅线以及平行于该栅线的第一数据总线和公共电极总线。
例如,在整个衬底基板上沉积一层均匀的金属薄膜,采用构图工艺形成栅线、第一数据总线和公共电极总线,该构图工艺包括在金属薄膜上均匀地涂覆一层光刻胶,通过曝光、显影、刻蚀、剥离光刻胶等工序,将金属薄膜形成电极图案。例如,该金属薄膜可以采用铝、铝合金、铜、铜合金等金属材料制备。
步骤202、在栅线、第一数据总线和公共电极总线上形成栅绝缘层和半导体层。
例如,在栅线、第一数据总线和公共电极总线上形成半导体层,该半导体层的材料,例如为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物。
在该步骤中,还可以通过构图工艺在栅绝缘层中形成过孔结构,以暴露出部分第一数据总线和部分公共电极总线。
步骤203、在半导体层上形成源漏电极层,并构造成并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线、平行于第一和第二数据线的公共电极线、以及平行于栅线的第二数据总线。栅线与数据线、公共电极线相互绝缘且交叉以限定多个亚像素单元。
在每两列相邻亚像素单元中,奇数行亚像素单元连接第一数据线,且偶数行亚像素单元连接第二数据线。第一数据线与第一数据线总线通过形成在栅绝缘层中的过孔结构连接,第二数据线均与第二数据线总线连接,公共电极线与公共电极线总线通过形成在栅绝缘层中的过孔结构连接。
例如,在半导体层上镀上一层金属薄膜,参考步骤202,同样通过构图工艺形成包括第一数据线和第二数据线,以及公共电极线和第二数据总线的电极图案。同样,例如该金属薄膜可以采用铝、铝合金、铜、铜合金等金属材料制备。
步骤204、在数据线和公共电极线所在层上形成绝缘层。
例如,在整个源漏电极层上镀上一层绝缘材料,该绝缘材料包括无机绝缘材料例如氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiOxNy)等,或者有机绝缘材料。
在该步骤中,还可以通过构图工艺在绝缘层中形成过孔结构,以暴露出部分漏极。
步骤205、在绝缘层上形成像素电极层,并构图形成像素电极。
例如,在绝缘层上沉积一层氧化铟锡(ITO)薄膜,然后通过构图工艺形成像素电极,该像素电极通过绝缘层中的过孔结构与漏极电连接。
对于制备IPS类型的阵列基板的情形,每个亚像素单元中,像素电极和公共电极可以形成在同一层,例如都形成梳状电极。在上述步骤204中,还可以通过构图工艺在绝缘层中形成过孔结构,以暴露出部分公共电极线;在上述步骤205中,形成像素电极的同时还形成公共电极,该公共电极通过绝缘层中的过孔结构与公共电极线电连接。
在本实施例中,在每个亚像素单元中形成薄膜晶体管、公共电极和像素电极,其中,薄膜晶体管的栅极与栅线连接,薄膜晶体管的源极与数据线连接,公共电极与公共电极线连接,像素电极与薄膜晶体管的漏极连接。
本发明的实施例提供一种阵列基板及其制造方法、显示面板和显示装置具有以下有益效果包括:在该阵列基板中,公共电极线与栅线设置在不同层,公共电极线与数据线设置在同一层且相互平行,这样可以避免平行配线易于短路的问题,还便于对阵列基板的电路进行检测与维修,加强设备的检出能力,从而可以提高产品的良率实现收益最大化。
有以下几点需要说明:
(1)本发明实施例附图只涉及到与本发明实施例涉及到的结构,其他结构可参考通常设计。
(2)为了清晰起见,在用于描述本发明的实施例的附图中,层或区域的厚度被放大或缩小,即这些附图并非按照实际的比例绘制。可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
(3)在不冲突的情况下,本发明的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (20)
1.一种阵列基板,包括:
衬底基板,
设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线;其中,
所述多条公共电极线与所述多条栅线设置在不同层;
所述多条公共电极线与所述多条数据线设置在同一层且相互平行;
所述多条栅线与所述多条数据线、所述多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
2.根据权利要求1所述的阵列基板,其中,所述多条数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线,在每两列相邻所述亚像素单元中,奇数行所述亚像素单元连接所述第一数据线,且偶数行所述亚像素单元连接所述第二数据线。
3.根据权利要求2所述的阵列基板,还包括:与所述栅线平行设置的第一数据线总线和第二数据线总线,
其中,所述第一数据线均与所述第一数据线总线连接,所述第二数据线均与所述第二数据线总线连接。
4.根据权利要求3所述的阵列基板,其中,所述第一数据线总线与所述第二数据线总线设置在不同层。
5.根据权利要求1所述的阵列基板,还包括:与所述公共电极线设置在不同层且与所述栅线平行设置的公共电极线总线,
其中,所述公共电极线均与所述公共电极线总线连接。
6.根据权利要求1-5中任一项所述的阵列基板,其中,所述公共电极线设置在所述栅线的上层或下层。
7.根据权利要求6所述的阵列基板,还包括:设置在每个所述亚像素单元中的薄膜晶体管、公共电极和像素电极,
其中,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接,所述公共电极与所述公共电极线连接,所述像素电极与所述薄膜晶体管的漏极连接。
8.根据权利要求7所述的阵列基板,其中,所述薄膜晶体管的半导体层在所述数据线所在层与所述栅线所在层之间,所述半导体层与所述栅线所在层之间设置有栅绝缘层。
9.根据权利要求8所述的阵列基板,其中,在所述数据线所在层、所述栅线所在层和所述半导体层上设置有绝缘层。
10.根据权利要求9所述的阵列基板,还包括多个栅极驱动器,其中,所述多个栅极驱动器分别设置在所述多条栅线的两端。
11.一种显示面板,包括权利要求1-10中任一项所述的阵列基板。
12.一种显示装置,包括权利要求11中的显示面板。
13.一种阵列基板的制作方法,包括:
提供衬底基板;
在所述衬底基板上形成栅线、数据线和公共电极线;其中,
所述公共电极线与所述栅线在不同层上形成;
所述公共电极线与所述数据线在同一层上形成且相互平行;
所述栅线与所述数据线、所述公共电极线相互绝缘且交叉以限定多个亚像素单元。
14.根据权利要求13所述的制作方法,其中,所述数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线,在每两列相邻所述亚像素单元中,奇数行所述亚像素单元连接所述第一数据线,且偶数行所述亚像素单元连接所述第二数据线。
15.根据权利要求14所述的制作方法,还包括:形成第一数据线总线和第二数据线总线,其中,所述第一数据线均与所述第一数据线总线连接,所述第二数据线均与所述第二数据线总线连接,且所述第一数据线总线和所述第二数据线总线均与所述栅线平行。
16.根据权利要求15所述的制作方法,其中,所述第一数据线总线与所述第二数据线总线在不同层上形成。
17.根据权利要求16所述的制作方法,还包括:形成公共电极线总线,其中,所述公共电极线总线与所述公共电极线在不同层上形成且与所述栅线平行,所述公共电极线均与所述公共电极线总线连接。
18.根据权利要求17所述的制作方法,其中,所述公共电极线在所述栅线的上层或下层形成。
19.根据权利要求18所述的制作方法,还包括:在每个所述亚像素单元中形成薄膜晶体管、公共电极和像素电极,其中,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接,所述公共电极与所述公共电极线连接,所述像素电极与所述薄膜晶体管的漏极连接。
20.根据权利要求19所述的制作方法,还包括:在所述数据线所在层与所述栅线所在层之间形成薄膜晶体管的半导体层,在所述半导体层与所述栅线所在层之间形成栅绝缘层。
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US10720450B2 (en) | 2020-07-21 |
US20180294282A1 (en) | 2018-10-11 |
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