WO2022116198A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2022116198A1
WO2022116198A1 PCT/CN2020/134055 CN2020134055W WO2022116198A1 WO 2022116198 A1 WO2022116198 A1 WO 2022116198A1 CN 2020134055 W CN2020134055 W CN 2020134055W WO 2022116198 A1 WO2022116198 A1 WO 2022116198A1
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WIPO (PCT)
Prior art keywords
sub
column
electrode
pixel
pixels
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Application number
PCT/CN2020/134055
Other languages
English (en)
French (fr)
Inventor
廖燕平
周茂秀
缪应蒙
杨海鹏
田丽
孙志华
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/134055 priority Critical patent/WO2022116198A1/zh
Priority to US17/622,205 priority patent/US20230258989A1/en
Priority to CN202080003217.1A priority patent/CN115151859B/zh
Publication of WO2022116198A1 publication Critical patent/WO2022116198A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
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    • G—PHYSICS
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    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • the purpose of the present disclosure is to provide an array substrate and a display panel, which can improve image quality problems such as Mura existing in products and improve product quality.
  • a first aspect of the present disclosure provides an array substrate, including:
  • each of the pixel units includes at least two sub-pixels arranged in the row direction;
  • a plurality of rows of first scan lines are sequentially arranged on the first substrate along the column direction, and at least one row of the first scan lines is disposed on one side of each row of the pixel units in the column direction, the first scan line is connected to the sub-pixel;
  • a plurality of columns of second scan lines are sequentially arranged on the first substrate along the row direction, and at least one column of the second scan lines is disposed on one side of each column of the pixel units in the row direction; wherein , the second scan line has a scan signal input end, and the second scan line is connected to the first scan line through a first via structure.
  • a plurality of columns of data lines are sequentially arranged on the first substrate along the row direction, and the data lines are connected to the sub-pixels; wherein, at least one side of the sub-pixels in each column in the row direction set the data line;
  • a plurality of rows of first common lines are sequentially arranged on the first substrate along the column direction, the first common lines are connected to the sub-pixels, wherein the pixel units in each row are in the column One side in the direction is provided with at least one row of the first common lines.
  • the sub-pixels include:
  • a sub-pixel electrode having a plurality of first electrode strips arranged at intervals in the row direction;
  • the common electrode is provided in the same layer as the sub-pixel electrode, and the common electrode has a plurality of second electrode strips arranged at intervals in the row direction, and the second electrode strips and the first electrode strips are located in the Alternately arranged in the row direction; and the common electrode and the first common line are connected through a second via structure;
  • a transistor comprising a gate electrode, an active layer, and a first electrode and a second electrode arranged in the same layer; the gate electrode is connected to the first scan line; the first electrode is connected to one end of the active layer, and the first electrode is connected to the data line; the second electrode is connected to the other end of the active layer and is connected to the sub-pixel electrode.
  • the first via structure includes a first via portion and a connection portion, the connection portion and the second scan line are located on different layers of the array substrate, and A portion of the connection portion is connected to the first scan line, and a portion of the connection portion is connected to the second scan line through the first via portion.
  • the first via structure further includes a second via portion; wherein,
  • connection part is arranged in the same layer as the common electrode and the sub-pixel electrode, and has a gap between the common electrode and the sub-pixel electrode; and the connection part is connected to the second via hole The first scan line is connected.
  • the first scan line is provided with a plurality of hollow holes
  • the orthographic projection of the second via portion on the first substrate is partially coincident with the orthographic projection of the first scan line on the first substrate, and the second via portion is on the first substrate.
  • the orthographic projection on the first substrate is partially coincident with the orthographic projection of the hollow hole on the first substrate.
  • the first substrate has a plurality of pixel regions and a plurality of columns of first wiring regions arranged in an array in the row direction and the column direction;
  • each of the pixel areas includes at least two sub-pixel areas arranged at intervals in the row direction, and the number of sub-pixel areas in each of the pixel areas is the same as the number of sub-pixels in each of the pixel units.
  • the numbers are equal, and the first electrode strip and the second electrode strip of each of the sub-pixels are arranged on one of the sub-pixel regions;
  • the first wiring area of each column and the pixel area of each column are alternately arranged in the row direction, a part of the first wiring area of the plurality of columns is the first sub-wiring area, and the other part is the second sub-wiring area, and the One of the first sub-wiring area and the second sub-wiring area is provided with at least one column of second scan lines, and the other is provided with a column of second scan lines.
  • each column of the first sub-wiring region is provided with two columns of second scan lines, and the two columns of the second scan lines on the same first sub-wiring region are respectively connected with The first scan lines in different rows are connected through the first via structure;
  • Each column of the second sub-wiring regions is provided with a column of second scan lines.
  • the array substrate further includes a plurality of columns of second common lines, the second common lines are connected to the common electrodes through a third via structure;
  • a column of the second scan lines and a column of the second common lines are arranged on the second sub-wiring region.
  • the first substrate has a plurality of rows of second wiring areas, each row of second wiring areas and each row of pixel areas are alternately arranged in the column direction, and each row of the second wiring area is alternately arranged in the column direction.
  • a row of the first scan lines and a row of the first common lines are arranged in the two wiring areas;
  • the first scan line in the same row is connected to the gates of the transistors of the sub-pixels in the same row, and the first common line in the same row and the common electrodes of the sub-pixels of the same color in the same row pass through the second Via structure connection.
  • the second scan lines in two columns are respectively connected to the first scan lines in the same row through a first via structure.
  • the plurality of columns of first wiring areas are divided into a plurality of columns of first wiring area groups, and each column of the first wiring area groups includes 8 columns sequentially arranged in the row direction
  • the first wiring area, the n-th column of the first wiring area in each column of the first wiring area group is the first sub-wiring area, and the remaining 7 columns of the first wiring area are the second sub-wiring areas, wherein 1 ⁇ n ⁇ 8, and n is a positive integer.
  • the width of the first sub-wiring region in the row direction is W1
  • the width of the second sub-wiring region in the row direction is W2
  • the sub-pixels have a width of W2.
  • the width of the region in the row direction is W3;
  • the width W1 of the first sub-wiring region is equal to the width W2 of the second sub-wiring region.
  • it further includes a first covering part, the orthographic projection of the first covering part on the first substrate and the first covering part located between two adjacent pixel regions The wiring areas are completely overlapped, wherein the first covering part and the common electrode are arranged and connected in the same layer.
  • one column of the data lines is disposed on one side of each column of sub-pixels in the row direction, and each column of data lines and each column of sub-pixels are alternately arranged in the row direction, wherein each column of sub-pixels is arranged alternately in the row direction.
  • the column data line is connected to each sub-pixel in a column of sub-pixels adjacent thereto.
  • each column of sub-pixels is provided with a column of the data lines on opposite sides in the row direction, and each sub-pixel located in an even row in each column of sub-pixels and the sub-pixels located on one side thereof and connected to The data lines in the adjacent column are connected, and the sub-pixels in the odd-numbered rows are connected with the data lines in another column adjacent to and located on the other side thereof.
  • the width of the second scan line in the row direction is greater than the width of the data line in the row direction.
  • a ratio of the width of the second scan line in the row direction to the width of the data line in the row direction is 1.1 to 2.
  • each of the pixel units includes three of the sub-pixels, which are respectively among the red sub-pixels, the green sub-pixels and the blue sub-pixels sequentially arranged in the row direction. between;
  • the red sub-pixels of one group in the adjacent two pixel units in the row direction are adjacent to the blue sub-pixels of the other group.
  • a second aspect of the present disclosure provides a display panel, which includes the array substrate described in any one of the above and a counter substrate arranged in a cell-to-cell manner with the array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of coupling waveforms of horizontal scan lines and vertical scan lines to pixel electrodes in an array substrate according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the distribution of each region in the array substrate according to another embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of an array substrate according to another embodiment of the disclosure.
  • FIG. 5 is an enlarged schematic structural diagram of the C portion of the array substrate shown in FIG. 4;
  • FIG. 6 is a schematic cross-sectional structural diagram of the array substrate shown in FIG. 5 along the Z-Z line;
  • FIG. 7 is a schematic cross-sectional structural diagram of the array substrate shown in FIG. 5 along the line L-L;
  • FIG. 8 is a schematic structural diagram of the first electrode strips in the array substrate shown in FIG. 4;
  • FIG. 9 is a schematic structural diagram of the second electrode strip in the array substrate shown in FIG. 4;
  • FIG. 10 is a schematic structural diagram of an array substrate according to another embodiment of the disclosure.
  • FIG. 11 is a schematic diagram showing the positional relationship between the array substrate and the black matrix shown in FIG. 5 .
  • first substrate; 200 sub-pixel area; 201, first sub-wiring area; 202, second sub-wiring area; 203, third wiring area; 204, second wiring area; 21a, red sub-pixel electrode; 21b, blue sub-pixel electrode; 21c, green sub-pixel electrode; 210, first electrode strip; 211, first conductive connection part; 22, common electrode; 220, second electrode strip; 221, second conductive connection part; 23, first scan line; 230, hollow hole; 24, second scan line; 25, data line; 26, first common line; 27, second common line; 28, transistor; 280, gate; 281, yes Source layer; 282, first pole; 283, second pole; 29a, gate insulating layer; 29b, passivation layer; 30, metal wire; 31, storage capacitor; 310, first plate; 311, second plate 32, black matrix; 33, the first covering part; 34, the second covering part.
  • an embodiment of the present disclosure provides an array substrate, which can be applied to a liquid crystal display panel; as shown in FIG. 1 , the array substrate may include multiple rows of horizontal scan lines 10 and multiple columns of vertical scan lines 11 .
  • the sub-pixels may include a thickness direction of the array substrate (the direction perpendicular to the row direction X and the column direction Y) ) on the opposite pixel electrode 14 and common electrode 15 and the transistor 16 connecting the pixel electrode 14 and the data line 12; the vertical scan line 11 is drawn out from the middle of the sub-pixel, and the vertical scan line 11 and the horizontal scan line 10 can pass through a
  • the hole structure 13 is connected, and the scan signal input end of the vertical scan line 11 and the data signal input end of the data line 12 can be located on the same side of the array substrate, for example, the binding side of the array substrate, so that the array substrate can be separated from the binding side.
  • the other three non-display sides on the fixed side can be made very narrow because they do not have the input end of the scan line and the input end of the data line 12, so the screen ratio can be increased, that is, the area of the display area can be increased, so that a full screen can be realized. .
  • the vertical scanning line 11 since the vertical scanning line 11 is used to transmit scanning signals, the electric field at the vertical scanning line 11 is extremely strong, which will cause a light leakage area within 20 ⁇ m near the vertical scanning line 11.
  • the matrix (BM) covers this light leakage area.
  • the vertical scan line 11 and the horizontal scan line 10 need to be connected through the via structure 13.
  • the transfer point ie: the via structure 13
  • the capacitive coupling states of the pixel electrode near the transfer point and other pixel electrodes are inconsistent.
  • the voltage V pixel of the ordinary pixel electrode is pulled by the horizontal scanning line 10 by ⁇ V p
  • the pixel electrode at the transition is not only pulled by the ⁇ V p generated by the horizontal scanning line 10 , but also pulled by the vertical scanning line.
  • the common electrode 15 and the pixel electrode 14 are arranged opposite to each other in the thickness direction of the array substrate; this design makes the overlapping area between the pixel electrode 114 and the common electrode 15 larger, so that the pixel electrode 14 and the common electrode 15 have a larger overlap area.
  • the parasitic capacitance generated between the electrodes 15 is relatively large, which in turn greatly affects the charging rate and aperture ratio of the pixel, resulting in a problem of poor display effect.
  • the embodiments of the present disclosure also provide an array substrate, which can be used for liquid crystal display, but is not limited thereto, and can also be used for organic light emitting display.
  • an array substrate which can be used for liquid crystal display, but is not limited thereto, and can also be used for organic light emitting display.
  • the following is a detailed description by taking the array substrate of the embodiment of the present disclosure used for liquid crystal display as an example.
  • the array substrate can be divided into a display area A and a non-display area B arranged around the display area A, and the non-display area B of the array substrate 2 can be provided with a sealing area B1 around the display area A, located at The sealing area B1 is close to the source electrostatic discharge area B2 of the display area A, and the fan-out area B3 is located in the sealing area B1 away from the display area A, and the source electrostatic discharge area B2 and the fan-out area B3 are located in the non-display area on the same side of the display area A B (ie: binding area).
  • the array substrate may include a first substrate 20 and pixel units disposed on the first substrate 20, first scan lines 23 and second scan lines 24, data lines 25, and first common lines 26.
  • the second common line 27 ; it should be noted that this pixel unit, the first scan line 23, the second scan line 24, the data line 25, the first common line 26, and the second common line 27 are the display located on the array substrate Structure on Zone A.
  • the first substrate 20 may be a single-layer structure.
  • the first substrate 20 may be a glass substrate, but not limited thereto, and may also be a substrate of other materials; in addition , the first substrate 20 can also be a multi-layer structure, depending on the specific situation.
  • the first substrate 20 may have a plurality of pixel regions arranged in an array in the row direction X and the column direction Y, and a plurality of columns arranged in the row direction X
  • the first wiring area and the second wiring area 204 arranged in a plurality of rows in the column direction Y; wherein, each pixel area includes at least two sub-pixel areas 200 arranged at intervals in the row direction X; and each column
  • the first wiring area and each column of pixel areas are alternately arranged in the row direction X, a part of the first wiring areas in the multiple columns is defined as the first sub-wiring area 201, and the other part is defined as the second sub-wiring area 202;
  • the wiring area 204 and each row of pixel areas are alternately arranged in the column direction Y; it should be noted that a third wiring area 203 may also be provided between two adjacent columns of sub-pixel areas 200 in each column of pixel areas.
  • the first sub-wiring region 201, the second sub-wiring region 202 and the third wiring region 203 extend in the column direction Y as a whole, and the second wiring region 204 extends in the row direction X as a whole, so it can be seen that the first sub-wiring region 204 extends in the row direction X as a whole.
  • An overlapping area exists between the wiring area 201 , the second sub-wiring area 202 , and the third wiring area 203 and the second wiring area 204 .
  • each pixel unit may include at least two sub-pixels arranged in the row direction X, the number of sub-pixels in each pixel unit is equal to the number of sub-pixel areas 200, and the number of sub-pixels in each pixel unit is equal to the number of sub-pixel areas 200.
  • Each sub-pixel corresponds to each sub-pixel region 200 in each pixel region one-to-one.
  • the number of columns of pixel units may be equal to the number of columns of the first wiring area
  • the number of rows of pixel units may be equal to the number of rows of the second wiring area 204 .
  • each pixel unit may include three sub-pixels, which are respectively between red sub-pixels, green sub-pixels and blue sub-pixels arranged in sequence in the row direction X; wherein, two adjacent sub-pixels in the row direction X The red sub-pixels of one group are adjacent to the blue sub-pixels of another group in the pixel unit.
  • the red sub-pixel mentioned in the embodiments of the present disclosure refers to the sub-pixel corresponding to the red filter unit, that is, the sub-pixel can be used to drive the liquid crystal molecules corresponding to the red filter unit to deflect, so that the The light emitted by the backlight can be emitted through the red filter unit.
  • the blue sub-pixel refers to the sub-pixel corresponding to the blue filter unit, that is, the sub-pixel can be used to drive the liquid crystal molecules corresponding to the blue filter unit to deflect, so that the light emitted by the backlight can be emitted through the blue filter unit.
  • the green sub-pixel refers to the sub-pixel corresponding to the green filter unit, that is, the sub-pixel can be used to drive the liquid crystal molecules corresponding to the green filter unit to deflect, so that the light emitted by the backlight can be emitted through the green filter unit. .
  • each pixel unit may include at least two sub-pixels spaced in the row direction X; specifically, it may include three sub-pixels corresponding to the red, green, and blue filter units respectively, but it is worth noting that this
  • the pixel unit of the disclosed embodiment is not limited to the aforementioned three sub-pixels, and more can be provided, for example: four, etc., and the colors corresponding to the sub-pixels are not limited to the aforementioned red, green, blue, but also For other colors, such as: white, yellow, etc., as the case may be.
  • each sub-pixel may include sub-pixel electrodes 21a, 21b, 21c, a common electrode 22, and a transistor 28, wherein:
  • the sub-pixel electrodes 21a, 21b, and 21c may have a plurality of first electrode strips 210 arranged at intervals in the row direction X, and the first electrode strips 210 may be disposed on the sub-pixel area 200; it should be understood that the sub-pixel electrodes 21a , 21b, 21c may further include first conductive connection parts 211 located on the same side of each first electrode strip 210 and connected to each first electrode strip 210, that is to say, the sub-pixel electrodes 21a, 21b, 21c may be similar as a whole In the shape of a "comb", the first conductive connection portion 211 may be disposed at the second wiring area 204 .
  • the first electrode strip 210 may be bent as a whole, and its bending angle ⁇ 1 is 150° to 170°.
  • the first electrode strip 210 may include a two-part structure, The angle ⁇ 1 between the two parts of the structure is 150° to 160°; for example: 150°, 156°, 162°, 166°, 170°, etc.; in other words, the extension direction of the two parts of the structure and the column direction Y
  • the included angles ⁇ 2 and ⁇ 3 between them are respectively 5° to 15°, for example: 5°, 7°, 9°, 12°, 15° and so on.
  • the sub-pixel electrode in the red sub-pixel can be defined as the red sub-pixel electrode 21a
  • the sub-pixel electrode in the blue sub-pixel can be defined as the blue sub-pixel electrode 21b
  • the sub-pixel electrode in the green sub-pixel can be defined as the blue sub-pixel electrode 21b.
  • the green sub-pixel electrode 21c the red sub-pixel electrode 21a, the blue sub-pixel electrode 21b and the green sub-pixel electrode 21c all have a plurality of first electrode strips 210 arranged at intervals in the row direction X.
  • the red sub-pixel electrode 21a, the blue sub-pixel electrode 21b and the green sub-pixel electrode 21c have the same structure, for example, the number, size, shape and gap of the first electrode strips 210 are the same, and the shape of the first conductive connection portion 211 is the same. and dimensions and their relative positions to the first electrode strips 210 are the same.
  • the common electrode 22 and the sub-pixel electrodes 21a, 21b, and 21c may be disposed in the same layer; for example, the aforementioned common electrode 22 and the sub-pixel electrodes 21a, 21b, and 21c may be transparent electrodes.
  • the common electrode 22 and the sub-pixel electrodes 21a, 21b, 21c can be made of ITO (Indium Tin Oxide) material, but not limited to this, and can also be IZO (Indium Zinc Oxide) and other materials. It should be understood that there is a gap (ie, no contact) between the common electrode 22 and the sub-pixel electrodes 21a, 21b, 21c.
  • the common electrode 22 can have a plurality of second electrode strips 220, and the second electrode strips 220 can be located in the sub-pixel region 200; and the common electrode 22 can also have a second conductive connection portion 221 to connect the second electrode strips 220 is connected, and the second conductive connection portion 221 may be located in the second wiring area 204 .
  • the second electrode strips 220 and the first electrode strips 210 of the common electrode 22 are alternately arranged in the row direction X, that is, the sub-pixel electrodes and the common electrode 22 can be in a state of being inserted into each other, that is, the embodiment of the present disclosure
  • the array substrate can be IPS (In-Plane Switching, plane switching) mode, this design can reduce the parasitic capacitance generated between the sub-pixel electrode and the common electrode, thereby improving the pixel charging rate and aperture ratio; but not limited to this,
  • the common electrode 22 and the sub-pixel electrode can also be located on different layers of the array substrate and disposed opposite to each other, and one of the common electrode 22 and the sub-pixel electrode is a slit electrode with a slit, and the other is a plate electrode without a slit That is to say, the array substrate of the embodiment of the present disclosure can also be in the FFS (Fringe Field Switching, fringe field switching technology) mode, depending on the specific situation.
  • FFS Frringe Field Switching
  • the common electrodes 22 of the sub-pixels can be connected to each other to form a whole.
  • the second electrode strips 220 may be bent, and the bending angle ⁇ 1 of the second electrode strips is 150° to 170°.
  • the second electrode strips 220 may include two part structures, and the angle ⁇ 1 between the two part structures is 150° to 160°; for example: 150°, 156°, 162°, 166°, 170°, etc.;
  • the included angles ⁇ 2 and ⁇ 3 between the extension direction and the column direction Y are respectively 5° to 15°, such as 5°, 7°, 9°, 12°, 15° and so on.
  • the second electrode strips 220 and the first electrode strips 210 may be substantially parallel, that is, the bending angle ⁇ 1 of the second electrode strips 220 may be the same as the bending angle ⁇ 1 of the first electrode strips 210 .
  • the color can be reduced. biased to improve the display effect.
  • first electrode strips 210 and the second electrode strips 220 in each sub-pixel are not limited to being alternately arranged in the row direction X as mentioned above, but can also be alternately arranged in the column direction Y, depending on actual needs. Depends.
  • the overall shape of the sub-pixel region 200 can also be in the same bending shape as the first electrode strips 210 .
  • the overall shape of the first sub-wiring area 201, the second sub-wiring area 202 and the third wiring area 203 can also be the same bending shape as the first electrode strip 210, so that the sub-pixel electrodes in the array substrate can be arranged
  • the cloth is denser.
  • the overall shape of the second wiring region 204 can be adapted to the shape of the signal lines (eg, the first scan line 23 and the first common line 26 ) thereon.
  • each transistor 28 of each sub-pixel may be located in the second wiring region 204 . It should be understood that the entire transistor 28 may be located on the side of the sub-pixel electrodes 21a, 21b, 21c and the common electrode 22 close to the first substrate 20, that is, the transistor 28 may be fabricated prior to the sub-pixel electrode and the common electrode 22 on the first substrate 20 . As shown in FIG. 4 and FIG. 5 , each transistor 28 may be connected to a sub-pixel electrode, but not limited to this, and one transistor 28 may be connected to a plurality of sub-pixel electrodes, or a sub-pixel electrode may be connected to a plurality of transistors 28, etc. etc., as the case may be.
  • the transistor 28 includes a gate electrode 280 , an active layer 281 , and a first electrode 282 and a second electrode 283 arranged in the same layer; the first electrode 282 is connected to the active layer.
  • One end of 281 is connected; the second pole 283 is connected to the other end of the active layer 281; and the second pole 283 can be connected to the sub-pixel electrode through the fourth via structure K4, specifically, the fourth via structure K4 can be connected to the sub-pixel electrode
  • the first conductive connections 211 of the electrodes are connected. It should be understood that one of the first electrode 282 and the second electrode 283 may be a source electrode, and the other may be a drain electrode; and the fourth via structure K4 may be located in the second wiring region 204 .
  • the gate 280, the first electrode 282 and the second electrode 283 mentioned above can be made of metal materials, for example, can be made of aluminum, molybdenum and other metal materials; the gate 280 , the first pole 282 and the second pole 283 may be a composite layer structure or a single layer structure, depending on the specific situation.
  • the transistor 28 of the embodiment of the present disclosure may be a bottom-gate type, that is, the active layer 281 is located on the side of the gate electrode 280 away from the first substrate 20 .
  • the active layer 281 and the gate A gate insulating layer 29a may be formed between the electrodes 280 . That is to say, in the process of fabricating the array substrate, the gate electrode 280 can be formed on the first substrate 20 first; after that, the gate insulating layer 29a covering the gate electrode 280 is formed; then, the gate insulating layer 29a is formed with the The gate electrode 280 is opposite to the active layer 281 .
  • the entire gate insulating layer 29a is disposed on the first substrate 20, that is, the gate insulating layer 29a not only covers the gate electrode 280, but also covers other structures fabricated prior to the gate insulating layer 29a. It should be understood that the gate insulating layer 29a can be made of inorganic materials, such as silicon oxide, silicon oxynitride and other materials.
  • the aforementioned transistors 28 can be fabricated on the first substrate 20 before the sub-pixel electrodes, that is, in the process of fabricating the array substrate, the transistors 28 can be firstly formed on the first substrate 20;
  • the sub-pixel electrode and the common electrode 22 are formed; it should be noted that after the first electrode 282 and the second electrode 283 of the transistor 28 are formed on the first substrate 20, and before the sub-pixel electrode and the common electrode 22 are formed, the A passivation layer 29b, as shown in FIG. 7, this passivation layer 29b covers the first electrode 282 and the second electrode 283, and the first conductive connection part 211 of the sub-pixel electrode can pass through the first electrode on the passivation layer 29b.
  • the four-via structure K4 is connected to the second pole 283 .
  • the passivation layer 29b is disposed on each region of the first substrate 20 as a whole, that is to say, the passivation layer 29b not only covers the first pole 282 and the second pole 283, but also covers the passivation layer 29b before the passivation layer 29b.
  • Other structures fabricated on the first substrate 20 can be understood that the passivation layer 29b can be made of inorganic materials, such as silicon oxide, silicon oxynitride and other materials.
  • An organic insulating layer (not shown in the figure) can also be formed between the passivation layer 29b and the sub-pixel electrodes, that is to say, in the process of fabricating the array substrate, a passivation layer can be formed on the first substrate 20 first 29b; after that, an organic insulating layer is formed on the passivation layer 29b; then, a sub-pixel electrode is formed on the organic insulating layer; wherein, the first conductive connection portion 211 of the sub-pixel electrode can pass through the organic insulating layer and passivation
  • the fourth via structure K4 on the layer 29b is connected to the second pole 283 .
  • the planarization is achieved by providing the organic insulating layer, so as to facilitate the subsequent coating of the sub-pixel electrode material, and at the same time increase the distance between the sub-pixel electrode and the layer where the second electrode 283 is located, thereby avoiding the need for The signal line on the layer where the second electrode 283 is located interferes with the sub-pixel electrode.
  • the array substrate of the embodiment of the present disclosure may not be provided with an organic insulating layer.
  • a color filter layer (not shown in the figure) can also be formed between the passivation layer 29b and the organic insulating layer, that is, in the process of fabricating the array substrate, a passivation can be formed on the first substrate 20 first layer 29b; then, a color filter layer is formed on the passivation layer 29b; then, an organic insulating layer is formed on the color filter layer; wherein, the first conductive connection portion 211 of the sub-pixel electrode can penetrate through the organic insulating layer , the color filter layer, the fourth via structure K4 on the passivation layer 29b is connected to the second pole 283 ; for example, the color filter layer may include the aforementioned red, green, blue and other filter units.
  • the array substrate of the embodiment of the present disclosure may not be provided with a color filter layer, and the color filter layer may be provided in the opposite substrate.
  • the transistor 28 of the embodiment of the present disclosure is not limited to a bottom-gate type, and may also be a top-gate type, depending on the specific situation.
  • the first scan lines 23 may be arranged in multiple rows and sequentially arranged on the first substrate 20 along the column direction Y; the first scan lines 23 may be located in the second wiring area 204 .
  • the first scan line 23 can be formed between the first substrate 20 and the common electrode 22, that is, in the process of fabricating the array substrate, the first scan line 23 can be formed on the first substrate 20 first, Then, the common electrode 22 and the sub-pixel electrodes are formed.
  • the first scan line 23 and the gate electrode 280 of the transistor 28 may be disposed in the same layer and connected to each other. It should be understood that the gate electrode 280 of the transistor 28 and the first scan line 23 may have an integrated structure.
  • At least one row of first scan lines 23 may be disposed on each row of the second wiring regions 204 , in other words, at least one row of first scan lines 23 may be disposed on one side of each row of pixel units in the column direction Y.
  • a row of first scan lines 23 may be set in each row of the second wiring regions 204 , wherein the first scan lines 23 in the same row are connected to the gates of the transistors of the sub-pixels in the same row, that is, the first scan lines 23 in the same row
  • the scan lines 23 may provide scan signals for each sub-pixel in a row of pixel units; but not limited thereto, two rows of the first scan lines 23 may also be arranged between the second wiring areas 204 in each row, depending on the specific situation.
  • the first common lines 26 may be arranged in multiple rows and sequentially arranged on the first substrate along the column direction Y.
  • the first common line 26 is connected to the sub-pixels, and is used for providing common signals to the sub-pixels.
  • the first common line 26 can be formed between the first substrate 20 and the common electrode 22, that is, in the process of fabricating the array substrate, the first common line 26 can be formed on the first substrate 20 first, and then the first common line 26 can be formed on the first substrate 20. Then, the common electrode 22 and the sub-pixel electrodes are formed.
  • the first common line 26 can be disposed in the same layer as the first scan line 23 , and the first common line 26 can be connected to the common electrode 22 through the second via structure K2 so as to provide a common signal for the common electrode 22 Specifically, the first common line 26 can be connected to the second conductive connection portion 221 of the common electrode 22 through the second via structure K2 . It should be noted that the second via structure K2 can be located in the second wiring area 204 .
  • At least one row of first common lines 26 may be provided on each row of second wiring regions 204 , in other words, at least one row of first common lines 26 may be provided on one side of each row of pixel units in the column direction Y.
  • each row of the second wiring areas 204 may be provided with a row of the first common lines 26 .
  • the first common line 26 in the same row is connected with the common electrodes of the sub-pixels of the same color in the same row through the second via structure K2, for example, the first common line 26 in the same row is connected with the common electrodes of the red sub-pixels in the same row.
  • the second conductive connection portion 221 of the electrode 22 is connected through the second via structure K2.
  • the second via structure K2 mentioned here may at least penetrate the gate insulating layer 29a and the passivation layer 29b mentioned above; optional Ground, when the array substrate includes the aforementioned organic insulating layer and the color filter layer, the second via structure K2 mentioned here can also penetrate through the organic insulating layer and the color filter layer.
  • one row of first scan lines 23 and one row of first common lines 26 may be arranged on each row of the second wiring regions 204 . It should be understood that there is no connection between the first common lines 26 and the first scan lines 23 .
  • the second common lines 27 may be arranged in multiple columns and sequentially arranged on the first substrate 20 along the row direction X.
  • This second common line 27 may be formed between the first substrate 20 and the common electrode 22 . That is to say, in the process of fabricating the array substrate, the second common line 27 can be formed on the first substrate 20 first, and then the common electrode 22 and the sub-pixel electrodes are formed.
  • the second common line 27 is connected with the common electrode 22 and the sub-pixel electrodes.
  • the aforementioned passivation layer 29b is formed between the electrodes.
  • the second common line 27 can be disposed in the same layer as the first electrode 282 and the second electrode 283 of the transistor 28 , wherein the aforementioned first common line 26 can be disposed in the same layer as the first scan line 23 , and The first scan line 23 can be disposed on the same layer as the gate 280 of the transistor 28. Therefore, it can be seen that the second common line 27 in the embodiment of the present disclosure is fabricated after the first common line 26. It should be noted that the second common line The aforementioned gate insulating layer 29 a is formed between 27 and the first common line 26 .
  • the second common line 27 can be connected to the common electrode 22 through the third via structure K3.
  • the third via structure K3 mentioned here may at least penetrate through the aforementioned passivation layer 29b, further, when the array substrate includes the aforementioned organic insulating layer and the color filter layer, the third via structure K3 mentioned here can also penetrate through the organic insulating layer and the color filter layer.
  • the third via structure K3 may be located in the second wiring area 204 , and the second common line 27 may be connected to the second conductive connection portion 221 of the common electrode 22 through the third via structure K3 .
  • At least one of the first common line 26 and the second common line 27 has a common signal input end to provide a common signal for the common electrode 22; optionally, the second common line 27 has a common signal input end, and the second common line 27 can transmit the received common signal to the first common line 26 and the common electrode 22, but is not limited thereto, and both the first common line 26 and the second common line 27 may have common signal input terminals.
  • each column of the second sub-wiring regions 202 may be provided with one column of the second common lines 27 .
  • the shape of the portion of the second common line 27 opposite to the first electrode strip 210 in the row direction X may match the shape of the first electrode strip 210 , that is, the first electrode strip 210 is bent
  • the portion of the second common line 27 opposite to the first electrode strip 210 in the row direction X may also be bent and may be substantially parallel to the first electrode strip 210 .
  • first common line 26 or only the second common line 27 may be provided, depending on the specific situation.
  • the second scan lines 24 may be arranged in multiple columns and sequentially arranged on the first substrate 20 along the row direction X.
  • the second scan line 24 can be formed between the first substrate 20 and the common electrode 22 , that is, in the process of fabricating the array substrate, the second scan line 24 can be formed on the first substrate 20 first line 24, and then the common electrode 22 and the sub-pixel electrode are formed.
  • the second scan line 24 can be disposed in the same layer as the first electrode 282 and the second electrode 283 of the transistor 28 . It should be understood that the second scan line 24 and the first electrode 282 and the second electrode of the transistor 28 There is a gap (ie: no contact) between 283.
  • At least one column of second scan lines 24 is provided in each column of the first wiring area, in other words, at least one column of second scan lines 24 is provided on one side of each row of pixel units in the row direction X.
  • the aforementioned two adjacent pixel units in the row direction X have a group of red sub-pixels adjacent to another group of blue sub-pixels. Therefore, it can be seen that the second scan line 24 in the embodiment of the present disclosure It may be located between two adjacent columns of red sub-pixels and blue sub-pixels.
  • the shape of the portion of the second scan line 24 opposite to the first electrode strip 210 in the row direction X may match the shape of the first electrode strip 210 , that is, when the first electrode strip 210 is bent , the portion of the second scan line 24 opposite to the first electrode strip 210 in the row direction X may also be bent and parallel to the first electrode strip 210 .
  • the second scan line 24 is connected to a row of the first scan line 23 through the first via structure K1 , the second scan line 24 has a scan signal input end, and the second scan line 24 receives the The scan signal can be sequentially transmitted to the gate 280 of the corresponding transistor 28 through the first via structure K1 and the first scan line 23 to control the on and off of the transistor 28 .
  • the first via structure K1 may include a first via portion K11 and a connection portion K12, the connection portion K12 and the second scan line 24 are located on different layers of the array substrate, and a portion of the connection portion K12 is connected to the first via portion K12.
  • the scan line 23 is connected, and the part of the connection portion K12 is connected to the second scan line 24 through the first via portion K11 .
  • the connecting portion K12 is disposed in the same layer as the common electrode 22 and the sub-pixel electrode, and has a gap (ie: no contact) with the common electrode 22 and the sub-pixel electrode.
  • the first via structure K1 may further include In the second via portion K13, the connecting portion K12 can be connected to the first scan line 23 through the second via portion K13; that is, part of the connecting portion K12 can be connected to the first scan line 23 through the second via portion K13 , and the part of the connection part K12 is connected to the second scan line 24 through the first via part K11 .
  • the connecting portion K12 when the connecting portion K12 is disposed in the same layer as the common electrode 22 and the sub-pixel electrode, the first via portion K11 can at least penetrate through the passivation layer 29b. Further, the array substrate includes the aforementioned organic insulating layer. When forming the color filter layer, the first via portion K11 mentioned here can also penetrate the organic insulating layer and the color filter layer; and the second via portion K13 can penetrate at least the gate insulating layer 29a and the passivation layer 29b, Further, when the array substrate includes the aforementioned organic insulating layer and the color filter layer, the second via portion K13 mentioned here may also penetrate through the organic insulating layer and the color filter layer.
  • the first scan line 23 may be provided with a plurality of hollow holes 230 , and the orthographic projection of the aforementioned second via portion K13 on the first substrate 20 is the same as that of the first scan line 23 on the first scan line 23 .
  • the orthographic portion of the first substrate 20 is overlapped, and the orthographic portion of the second via portion K13 on the first substrate 20 is overlapped with the orthographic portion of the hollow hole 230 on the first substrate 20. This design can reduce the Parasitic capacitance generated between the connection portion K12 and the first scan line 23 .
  • first via structure K1 may be located in the second wiring area 204, and the first common line 26 may be designed to avoid the first via structure K1, that is: the aforementioned The orthographic projection of the first via structure K1 on the first substrate 20 does not coincide with the orthographic projection of the first common line 26 on the first substrate 20 .
  • connection portion K12 is not limited to be provided in the same layer as the common electrode 22.
  • the connection portion K12 can be provided in the same layer as the first scan line 23 and directly connected, that is, the aforementioned second via hole does not need to be provided.
  • Section K13 wherein, when the connection portion K12 and the first scan line 23 can be disposed on the same layer, the connection portion K12 can extend in the column direction as a whole, and it can be located in the first wiring between two adjacent pixel units in the row direction X area.
  • each row of the first scan lines 23 may be connected to two columns of the second scan lines 24, in other words, the two columns of the second scan lines 24 are respectively connected to the same row of the first scan lines 23 through a first via structure K1, That is to say, each row can be driven by two sets of scanning signals, which can strengthen the scanning signals to improve the display effect.
  • each row of the first scan lines 23 may also be connected to one column of the second scan lines 24 or to three or more columns of the second column scan lines. It should be noted that, in order to ensure display uniformity, the number of the second scan lines 24 connected to the first scan lines 23 in each row needs to be the same.
  • the number of the second scan line can be reduced. 24 and the sub-pixel electrode overlap area, so that the coupling capacitance generated between the second scan line 24 and the sub-pixel electrode can be reduced, so as to improve the ⁇ V p generated by the scanning signal at the second scan line 24 pulling the pixel electrode, conditions, thereby improving the Mura phenomenon and improving product quality.
  • the coupling capacitance generated between the second scan line 24 and the sub-pixel electrode is negligibly small.
  • the human eye is currently the most sensitive to green because the number ratio of green, red, and blue in the cones responsible for perceiving color is 40:20:1; that is, in practical applications , compared with green, red and blue have less influence on the transmittance of the liquid crystal display panel.
  • the present disclosure further designs the second scan line 24 between adjacent red sub-pixels and blue sub-pixels, even if the first The two scan lines 24 cause light leakage at the red sub-pixels and the blue sub-pixels, which are not easily noticed by the human eye, and the impact is relatively small. Therefore, the width of the black matrix here can be reduced or the design of the black matrix here can be omitted to improve the Pixel aperture ratio.
  • the second scan lines 24 are arranged on both the first sub-wiring area 201 and the second sub-wiring area 202; scan line 24, and a column of second scan lines 24 is disposed on the other.
  • each column of the first sub-wiring area 201 is provided with two columns of second scan lines 24, and each column of the second sub-wiring area 202 is provided with a column of second scan lines 24; wherein, the same first sub-wiring area
  • the two columns of the second scan lines 24 on the 201 are respectively connected with the first scan lines 23 of different rows through the first via structure K1, which can reduce the processing difficulty while ensuring the display effect.
  • the number of signal lines on the first sub-wiring region 201 can be equal to the number of signal lines on the second sub-wiring region 202; wherein, the first sub-wiring region 201 is mentioned above.
  • Two columns of second scan lines 24 are provided, and one column of second scan lines 24 is provided in the second sub-wiring region 202, so that the number of signal lines on the second sub-wiring region 202 is the same as the number of signal lines on the first sub-wiring region 201. If the number is the same, one column of the aforementioned second common lines 27 may also be provided on each column of the second sub-wiring regions 202 .
  • the pixel unit in the 4K resolution display panel has 3840 columns and 2160 rows, wherein each pixel unit includes red sub-pixels, green sub-pixels and blue sub-pixels arranged in sequence in the row direction. Therefore, the sub-pixels in the 4K resolution display panel have 3840 ⁇ 3 columns and 2160 rows, that is, the first wiring area has 3840 columns, and the second wiring area 204 has 2160 rows.
  • each row of the second wiring area 204 is provided with a row of the first scan lines 23, that is, the first scan lines have 2160 rows; and the aforementioned two columns of the second scan lines 24 are connected to one row of the first scan lines 23, That is, the second scan line 24 has 2160 ⁇ 2 columns.
  • the number of columns of the first wiring area and the number of columns of the second scan lines 24 are 8:9; that is to say, every 8 columns of the first wiring area is a group, and a total of 9 columns of the second scan lines 24 are arranged; namely: One column of first wiring areas in each group of first wiring areas is a first sub-wiring area 201, and two columns of second scan lines 24 are arranged in this first sub-wiring area 201; and the remaining 7 columns of first wiring areas are second sub-wiring areas In the area 202, each column of the second sub-wiring area 202 is provided with a column of second scan lines 24 and a column of second common lines 27.
  • each column of first wiring area groups includes 8 columns of first wiring areas sequentially arranged in the row direction X, that is: each column In the first wiring area group, the first wiring area in the first column, the first wiring area in the second column, the first wiring area in the third column, the first wiring area in the fourth column, the first wiring area in the fifth column, and the first wiring area in the sixth column A wiring area, the first wiring area in the seventh column, and the first wiring area in the eighth column are arranged in sequence in the row direction X.
  • the arrangement direction of the first wiring areas in the first wiring area groups in each column is the same; Among them, the first wiring area of the n-th column in each column of the first wiring area group is the first sub-wiring area 201, and the remaining 7 columns of the first wiring area are the second sub-wiring area 202, where 1 ⁇ n ⁇ 8, and n It is a positive integer, that is to say, the first wiring areas 201 in the first wiring area groups of each column are located in the same number of columns.
  • the display panel of the embodiment of the present disclosure is not limited to the aforementioned 4K resolution; it can also be other resolutions. Therefore, the total number of first wiring areas, the first sub-wiring area 201 and the second sub-wiring area The proportion and positional relationship of the area 202 are not limited to the aforementioned contents, and may also be determined according to specific circumstances, as long as the display uniformity of the entire panel can be ensured.
  • the second sub-wiring regions 202 in the plurality of columns of second sub-wiring regions 202 may not be provided with the second common lines 27, and the second sub-wiring regions 202 without the second common lines 27 may be Evenly arranged in the display panel, depending on the actual needs.
  • the data lines 25 are arranged in multiple columns and are sequentially arranged on the first substrate 20 along the row direction X.
  • the data lines 25 are connected to the sub-pixels for providing data signals to the sub-pixels.
  • the data line 25 is formed between the first substrate 20 and the common electrode 22, that is, in the process of fabricating the array substrate, the data line 25 can be formed on the first substrate 20 first, and then formed The common electrode 22 and the sub-pixel electrodes.
  • the data line 25 has a data signal input terminal, and the data line 25 is connected to the first pole 282 of the transistor 28 , that is, the data line 25 can transmit the received data signal to the first pole 282 of the transistor 28 .
  • the data line 25 and the first electrode 282 of the transistor 28 may be disposed in the same layer.
  • each of the first sub-wiring region 201 , the second sub-wiring region 202 and the third wiring region 203 can be provided with at least one column of data lines 25 , in other words, at least one side of each column of sub-pixels in the row direction X Set data line 25.
  • one column of data lines 25 is arranged on one side of each column of sub-pixels in the row direction X, and each column of data lines 25 and each column of sub-pixels are alternately arranged in the row direction X, in other words, A column of data lines 25 may be disposed on the first sub-wiring region 201 , the second sub-wiring region 202 and the third wiring region 203 , wherein each column of data lines 25 is connected to each sub-pixel in an adjacent column of sub-pixels.
  • each column of sub-pixels is provided with a column of data lines 25 on opposite sides in the row direction X, that is, the first sub-wiring located between two adjacent columns of sub-pixels.
  • Two columns of data lines 25 are arranged on the area 201, the second sub-wiring area 202, and the third wiring area 203; wherein, in each column of sub-pixels, each sub-pixel located in an even row and a column of data lines located on one side and adjacent to it 25 connection, each sub-pixel located in an odd row is connected to another column of data lines 25 located on the other side and adjacent to it, that is: each column of sub-pixels is matched and connected to two columns of data lines 25, and the two columns of data lines 25 They are located on opposite sides of each column of sub-pixels in the row direction X, which can improve the charging time.
  • the distances between the two columns of data lines 25 on both sides of the sub-pixel and the sub-pixel can be equal, so that the two sides of the sub-pixel are pulled in the same way by the data signal, so that when the brightness is L0, there is basically no space on both sides of the sub-pixel.
  • the voltage difference generated by the data signal makes it unnecessary to consider the problem of light leakage at the first sub-wiring region 201 , the second sub-wiring region 202 and the third wiring region 203 .
  • the data lines 25 are compared to the second common line 27 and the second scan line. 24 is closer to the column of subpixels to which it is connected.
  • the shape of the portion of the data line 25 opposite to the second electrode strip 220 in the row direction X may match the shape of the second electrode strip 220 , that is, the second electrode strip 220 is curved.
  • the portion of the data lines 25 opposite to the second electrode strips 220 in the row direction can also be folded, and can be substantially parallel to the second electrode strips 220 .
  • the width of the second scan line 24 in the row direction X may be greater than the width of the data line 25 in the row direction X; optionally, the width of the second scan line 24 in the row direction X is equal to
  • the ratio of the widths of the data lines 25 in the row direction X may be 1.1 to 2, such as: 1.1, 1.3, 1.5, 1.7, 2, etc.
  • the widths of the data lines 25 in the row direction X may be about 6 ⁇ m
  • the width of the second scan line 24 in the row direction X may be about 10 ⁇ m, but not limited to this, and may also be other values, depending on the specific situation.
  • the width of the second common line 27 in the row direction X may be equal to the width of the second scan line 24 .
  • the width of the aforementioned first sub-wiring region 201 in the row direction X may be W1
  • the width of the second sub-wiring region 202 in the row direction X may be W2
  • the width of the region 200 in the row direction X may be W3; wherein, 0 ⁇ (W1-W2)/(2 ⁇ W3) ⁇ 4%, and W1, W2 and W3 are positive numbers; this design can avoid the second scan line Risk of vertical streaks at 24.
  • the width W1 of the first sub-wiring region 201 and the width W2 of the second sub-wiring region 202 may be equal to reduce the design difficulty.
  • the array substrate may further include a first covering portion 33 , an orthographic projection of the first covering portion 33 on the first substrate 20 and a first wiring region located between two adjacent pixel regions
  • the first covering part 33 and the common electrode 22 of the sub-pixels are arranged and connected in the same layer, that is to say, the first covering part 33 can cover the signal lines between adjacent pixel regions (for example, the second scanning Line 24, data line 25, second common line 27) are covered to shield the signal, thereby alleviating and eliminating the influence of the signal here on the electric field at the sub-pixel area 200, thereby improving or eliminating the electrical field between adjacent pixel areas.
  • the black matrix BM it is not necessary to design the black matrix to improve the pixel aperture ratio.
  • the orthographic projection of the first covering portion 33 on the first substrate 20 does not overlap with the second wiring region 204; the opposite sides of the first covering portion 33 in the column direction Y are adjacent to The second conductive connection portions 221 of the common electrodes 22 of the two rows of sub-pixels are connected to each other.
  • the array substrate may further include a second covering portion 34, an orthographic projection of the second covering portion 34 on the first substrate 20 and a third wiring area located between two adjacent sub-pixel areas 200 in each pixel area 203 are completely overlapped, and the second covering portion 34 and the common electrode 22 of the sub-pixels are arranged and connected in the same layer.
  • the signal line (for example: the data line 25) is covered to shield the signal, thereby alleviating and eliminating the influence of the signal on the electric field at the sub-pixel region 200, thereby improving or eliminating the adjacent two sub-pixel regions in each pixel region.
  • the problem of light leakage at the position between 200 can reduce the area of the black matrix BM here or do not need to design the black matrix to improve the pixel aperture ratio.
  • the orthographic projection of the second covering portion 34 on the first substrate 20 does not overlap with the second wiring region 204 ; the opposite sides of the second covering portion 34 in the column direction Y are adjacent to each other.
  • the second conductive connection portions 221 of the common electrodes 22 of the two rows of sub-pixels are connected to each other.
  • the second conductive connection parts 221 of the common electrodes 22 of adjacent sub-pixels in the row direction X are connected, and the second conductive connection parts 221 may cover part of the second wiring area 204, although the second conductive connection parts 221 of the common electrodes 22
  • the conductive connection portion 221 covers part of the second wiring area 204 and can shield the scan signal on the first scan line 23.
  • the coupling electric field between the sub-pixel electrode and the first scan line 23 may cause liquid crystals during display.
  • the arrangement is disordered, therefore, the second wiring area 204 also needs to be covered by the black matrix 32 .
  • metal lines 30 may also be disposed on opposite sides of each sub-pixel in the row direction X, and the metal lines 30 are disposed closer to the sub-pixels than the data lines 25; wherein, the metal lines 30 in the embodiment of the present disclosure may be combined with the first and second sub-pixels.
  • a common line 26 is disposed on the same layer and connected to the first common line 26.
  • the metal line 30 can play the role of shielding signals, so as to alleviate and eliminate the influence of data signals and scan signals on the electric field at the sub-pixel area 200, and improve the display. Effect.
  • the aforementioned scan signal input end of the second scan line 24 , the common signal input end of the second common line 27 , and the data signal input end of the data line 25 may be located on the first substrate 20 .
  • the first substrate 20 has a first side and a second side opposite to each other in the column direction Y; the scan signal input end of the second scan line 24, the common signal input end of the second common line 27 and the data
  • the data signal input ends of the lines 25 are all close to the first side or are all close to the second side, so that the other sides of the first substrate 20 do not have the scan signal input ends of the second scan line 24 and the common signal of the second common line 27
  • the input end and the data signal input end of the data line 25, therefore, the other sides can be made very narrow, so that the proportion of the display area A can be increased to realize full-screen display.
  • the area B4 where the gate 280 driving circuit used to provide the scan signal for the second scan line 24 is located may be located in the non-display area B, and specifically may be located in the source electrostatic discharge area B2 and the fan-out area between the areas B3 and inside the sealing area B1.
  • the gate 280 driving circuit for providing scan signals for the second scan lines 24 may not be disposed on the first substrate 20 , and it can be connected to the second substrate 20 through a flexible circuit board.
  • the scan lines 24 are electrically connected.
  • each via structure or via portion mentioned in the present disclosure may be a structure in which the holes are filled with conductive materials.
  • the array substrate of the embodiment of the present disclosure may further include a storage capacitor 31, and the storage capacitor 31 may include a first electrode plate 310 and a second electrode plate 311 opposite to each other in the thickness direction of the array substrate, and the first electrode plate 310 may be
  • the second electrode plate 311 can be placed on the same layer as the first common line 26 and connected to the first electrode 282 and the second electrode 283 of the transistor 28 , and the second electrode plate 311 can be placed with the second electrode 283 of the transistor 28
  • the first conductive connection portion 211 of the sub-pixel electrode can be connected to the second electrode plate 311 through the fourth via structure K4, so as to realize the first conductive connection portion 211 of the sub-pixel electrode and the transistor 28. Diode 283 is connected.
  • the first sub-wiring region 201 is provided with two columns of second scan lines 24 and a column of data lines 25, and the second sub-wiring region 202 is provided with a column of second scan lines 24, a column of The second common line 27 and a column of data lines 25;
  • the third wiring area 203 is provided with a column of data lines 25, and each row of the first scan lines 23 and two columns of the second scan lines 24 are connected through the first via structure K1; this array substrate Can be used in 4K 60Hz display panels.
  • the first sub-wiring region 201 is provided with two columns of second scan lines 24 and two columns of data lines 25
  • the second sub-wiring region 202 is provided with one column of second scan lines 24 and one column of second scan lines 24 .
  • the common line 27 and two columns of data lines 25; the third wiring area 203 is provided with two columns of data lines 25, and each row of the first scan line 23 and the two columns of the second scan line 24 are connected through the first via structure K1; this array substrate Available in 4K 120Hz or 8K 60Hz display panels.
  • 4K and 8K refer to the resolution of the display panel, and 60Hz and 120Hz refer to the refresh rate of the display panel.
  • An embodiment of the present disclosure further provides a display panel, which includes the array substrate described in any of the above embodiments; it should be understood that the display panel may be a liquid crystal panel, and therefore, the display panel may also include a cell-to-cell with the array substrate The disposed opposite substrate and the liquid crystal molecules located between the opposite substrate and the array substrate.
  • the opposite substrate may not need to provide a color filter layer, and at this time, the opposite substrate may include a second substrate (not shown in the figure) and a black matrix 32 disposed on the side of the second substrate facing the array substrate, as shown in FIG. 11 .
  • a color filter layer may be provided in the opposite substrate.
  • Embodiments of the present disclosure also provide an electronic device including the aforementioned display panel.
  • the specific type of electronic equipment is not particularly limited, and any type of electronic equipment commonly used in the art can be used, such as LCD TVs, mobile phones, computers, watches, etc.
  • the specific use of the device is selected accordingly, and details are not repeated here.
  • the electronic device also includes other necessary components and components. Taking a display as an example, such as a casing, a circuit board, a power cord, etc. The specific use requirements of the system should be supplemented accordingly, and will not be repeated here.
  • the term “same layer arrangement” is used to mean that two layers, components, components, elements or sections may be formed by the same patterning process, and that the two layers, components, components , elements or parts are generally formed of the same material.
  • patterning process generally includes steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-shot patterning process means a process of forming patterned layers, features, members, etc. using one mask.
  • ordinal numbers such as “first”, “second”, “third”, and “fourth” are provided to avoid confusion of constituent elements, and are not intended to be limited in quantity.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.

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Abstract

一种阵列基板及显示面板。该阵列基板可包括：第一衬底（20）；多个像素单元，沿行方向和列方向阵列排布在所述第一衬底（20）上；每个所述像素单元包括至少两个在所述行方向上排布的子像素；多行第一扫描线（23），沿所述列方向依次排布在所述第一衬底（20）上，且每行所述像素单元在所述列方向上的一侧设置至少一行所述第一扫描线（23），所述第一扫描线（23）与所述子像素连接；多列第二扫描线（24），沿所述行方向依次排布在所述第一衬底（20）上，且每列所述像素单元在所述行方向上的一侧设置至少一列所述第二扫描线（24）；其中，所述第二扫描线（24）具有扫描信号输入端，所述第二扫描线（24）通过第一过孔结构与所述第一扫描线（23）连接。该方案能够在实现全面屏的同时，可改善产品存在的Mura现象。

Description

阵列基板及显示面板 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及显示面板。
背景技术
随着全面屏概念在中小尺寸显示产品上应用的普及，对于大尺寸显示产品(例如：电视)也在追求极致的时尚外观；其中，电视市场已向“无边框”时代迈进，全面屏已成为电视市场新的发展方向，但目前大尺寸全面屏显示产品存在Mura(亮度不均匀)等画质问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种阵列基板及显示面板，能够改善产品存在的Mura等画质问题，提高产品质量。
本公开第一方面提供了一种阵列基板，其中，包括：
第一衬底；
多个像素单元，沿行方向和列方向阵列排布在所述第一衬底上；每个所述像素单元包括至少两个在所述行方向上排布的子像素；
多行第一扫描线，沿所述列方向依次排布在所述第一衬底上，且每行所述像素单元在所述列方向上的一侧设置至少一行所述第一扫描线，所述第一扫描线与所述子像素连接；
多列第二扫描线，沿所述行方向依次排布在所述第一衬底上，且每列所述像素单元在所述行方向上的一侧设置至少一列所述第二扫描线；其中，所述第二扫描线具有扫描信号输入端，所述第二扫描线通过第一过孔结构与所述第一扫描线连接。
在本公开的一种示例性实施例中，还包括：
多列数据线，沿所述行方向上依次排布在所述第一衬底上，所述数据线与所述子像素连接；其中，每列所述子像素在所述行方向上的至少一侧设置所述数据线；
多行第一公共线，沿所述列方向上依次排布在所述第一衬底上，所述第一公共线与所述子像素连接，其中，每行所述像素单元在所述列方向上的一侧设置至少一行所述第一公共线。
在本公开的一种示例性实施例中，所述子像素包括：
子像素电极，具有多个在所述行方向上间隔排布的第一电极条；
公共电极，与所述子像素电极同层设置，所述公共电极具有多个在所述行方向上间隔排布的第二电极条，所述第二电极条与所述第一电极条在所述行方向上交替排布；且所述公共电极与所述第一公共线通过第二过孔结构连接；
晶体管，包括栅极、有源层及同层设置的第一极和第二极；所述栅极与所述第一扫描线连接；所述第一极与所述有源层的一端连接，且所述第一极与所述数据线连接；所述第二极与所述有源层的另一端连接，并与所述子像素电极连接。
在本公开的一种示例性实施例中，所述第一过孔结构包括第一过孔部及连接部，所述连接部与所述第二扫描线位于所述阵列基板的不同层，且所述连接部的部分与所述第一扫描线连接，所述连接部的部分通过所述第一过孔部与所述第二扫描线连接。
在本公开的一种示例性实施例中，所述第一过孔结构还包括第二过孔部；其中，
所述连接部与所述公共电极和所述子像素电极同层设置，并与所述公共电极和所述子像素电极之间具有间隙；且所述连接部通过所述第二过孔部与所述第一扫描线连接。
在本公开的一种示例性实施例中，所述第一扫描线设有多个镂空孔；
其中，所述第二过孔部在所述第一衬底上的正投影与所述第一扫描线在所述第一衬底上的正投影部分重合，且所述第二过孔部在所述第一衬底上的正投影与所述镂空孔在所述第一衬底上的正投影部分重合。
在本公开的一种示例性实施例中，其中，所述第一衬底具有多个在所述行方向和所述列方向阵列排布的像素区和多列第一布线区；
其中，每个所述像素区包括至少两个在所述行方向间隔排布的子像素区，每个所述像素区中子像素区的个数与每个所述像素单元中子像素的个数相等，且每个所述子像素的第一电极条和第二电极条设置在一所述子像素区上；
其中，每列第一布线区与每列像素区在所述行方向上交替排布，所述多列第一布线区中一部分为第一子布线区，另一部分为第二子布线区，所述第一子布线区和所述第二子布线区中一者上设置有至少一列第二扫描线，另一者上设置有一 列第二扫描线。
在本公开的一种示例性实施例中，每列所述第一子布线区上设置有两列第二扫描线，且同一所述第一子布线区上的两列第二扫描线分别与不同行第一扫描线通过所述第一过孔结构连接；
每列所述第二子布线区设置有一列第二扫描线。
在本公开的一种示例性实施例中，所述阵列基板还包括多列第二公共线，所述第二公共线通过第三过孔结构与所述公共电极连接；
其中，所述第二子布线区上设置有一列所述第二扫描线和一列所述第二公共线。
在本公开的一种示例性实施例中，所述第一衬底具有多行第二布线区，每行第二布线区与每行像素区在所述列方向上交替排布，每行第二布线区设置一行所述第一扫描线和一行所述第一公共线；
其中，同一行所述第一扫描线与同一行中各子像素的晶体管的栅极连接，同一行所述第一公共线与同一行中同种颜色的子像素的公共电极通过所述第二过孔结构连接。
在本公开的一种示例性实施例中，两列所述第二扫描线分别通过一所述第一过孔结构与同一行所述第一扫描线连接。
在本公开的一种示例性实施例中，所述多列第一布线区划分成多列第一布线区组，每列所述第一布线区组包括在所述行方向上依次排布的8列第一布线区，每列所述第一布线区组中第n列第一布线区为所述第一子布线区，其余7列第一布线区为所述第二子布线区，其中，1≤n≤8，且n为正整数。
在本公开的一种示例性实施例中，所述第一子布线区在所述行方向上的宽度为W1，所述第二子布线区在所述行方向上的宽度为W2，所述子像素区在所述行方向上的宽度为W3；
其中，0≤(W1-W2)/(2×W3)≤4％，且W1、W2和W3为正数。
在本公开的一种示例性实施例中，所述第一子布线区的宽度W1与所述第二子布线区的宽度W2相等。
在本公开的一种示例性实施例中，还包括第一覆盖部，所述第一覆盖部在所述第一衬底上的正投影与位于相邻两所述像素区之间的第一布线区完全重合，其中，所述第一覆盖部与所述公共电极同层设置并连接。
在本公开的一种示例性实施例中，每列子像素在所述行方向上的一侧设置一列所述数据线，每列数据线与每列子像素在所述行方向上交替排布，其中，每列 数据线和与其相邻的一列子像素中各子像素连接。
在本公开的一种示例性实施例中，每列子像素在所述行方向上的相对两侧均设置一列所述数据线，每列子像素中位于偶数行的各子像素和位于其一侧并与之相邻的一列所述数据线连接，位于奇数行的各子像素和位于其另一侧并与之相邻的另一列所述数据线连接。
在本公开的一种示例性实施例中，所述第二扫描线在所述行方向上的宽度大于所述数据线在所述行方向上的宽度。
在本公开的一种示例性实施例中，所述第二扫描线在所述行方向上的宽度与所述数据线在所述行方向上的宽度之比为1.1至2。
在本公开的一种示例性实施例中，每个所述像素单元包括三个所述子像素，分别为在所述行方向上依次排布的红色子像素、绿色子像素和蓝色子像素之间；
其中，在所述行方向上相邻两所述像素单元中一组的红色子像素与另一组的蓝色子像素相邻。
本公开第二方面提供了一种显示面板，其中，包括上述任一项所述的阵列基板和与所述阵列基板对盒设置的对置基板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为本公开一实施例所述的阵列基板的结构示意图；
图2为本公开一实施例所述的阵列基板中横向扫描线和竖向扫描线对像素电极的耦合波形示意图；
图3为本公开另一实施例所述的阵列基板中各区域的分布示意图；
图4为本公开另一实施例所述的阵列基板的结构示意图；
图5为图4中所示的阵列基板的C部的放大结构示意图；
图6为图5中所示的阵列基板沿Z-Z线的剖视结构示意图；
图7为图5中所示的阵列基板沿L-L线的剖视结构示意图；
图8为图4中所示的阵列基板中第一电极条的结构示意图；
图9为图4中所示的阵列基板中第二电极条的结构示意图；
图10为本公开又一实施例所述的阵列基板的结构示意图；
图11为图5中所示的阵列基板与黑矩阵的位置关系示意图。
附图标记：
10、横向扫描线；11、竖向扫描线；12、数据线；13、过孔结构；14、像素电极；15、公共电极；16、晶体管；
20、第一衬底；200、子像素区；201、第一子布线区；202、第二子布线区；203、第三布线区；204、第二布线区；21a、红色子像素电极；21b、蓝色子像素电极；21c、绿色子像素电极；210、第一电极条；211、第一导电连接部；22、公共电极；220、第二电极条；221、第二导电连接部；23、第一扫描线；230、镂空孔；24、第二扫描线；25、数据线；26、第一公共线；27、第二公共线；28、晶体管；280、栅极；281、有源层；282、第一极；283、第二极；29a、栅绝缘层；29b、钝化层；30、金属线；31、存储电容；310、第一极板；311、第二极板；32、黑矩阵；33、第一覆盖部；34、第二覆盖部。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
为实现全面屏设计，本公开实施例提供了一种阵列基板，可应用于液晶显示面板中；如图1所示，此阵列基板可包括多行横向扫描线10、多列竖向扫描线11、多列延伸数据线12以及多个在行方向X和列方向Y上阵列排布的多个子像素，此子像素可包括在阵列基板的厚度方向(垂直于行方向X和列方向Y的方向)上相对的像素电极14和公共电极15以及连接像素电极14和数据线12的晶体管16；竖向扫描线11从子像素中间引出，且竖向扫描线11与横向扫描线10可通过一过孔结构13连接，且竖向扫描线11的扫描信号输入端和数据线12的数据信号输入端可位于阵列基板的同一侧，例如，阵列基板的绑定侧，这样可使阵列基板中除了绑定侧的其他三个非显示侧因为没有扫描线的输入端和数据线12的输入端，可以做的很窄，因此可以提高屏占比，即：提高显示区的面 积，从而可以实现全面屏。
其中，由于竖向扫描线11用来传输扫描信号，因此，竖向扫描线11处电场极强，会导致竖向扫描线11附近20μm的范围内为漏光区，为了解决漏光问题，需要用黑矩阵(BM)将此漏光区遮盖住，具体地，在设计黑矩阵时还需考虑对盒精度的影响，这样导致像素开口率大幅度减小。
此外，竖向扫描线11和横向扫描线10需要通过过孔结构13转接，在转接点(即：过孔结构13)处，由于竖向扫描线11和像素电极14存在耦合电容，导致竖向扫描线11关断时，靠近转接点处的像素电极和其他像素电极(可定义为普通像素电极)电容耦合状态不一致。结合图2说明，横向扫描线10对普通像素电极的电压V pixel的拉动都是ΔV p，转接处的像素电极除了受到横向扫描线10产生的ΔV p的拉动以外，还受竖向扫描线11的电压V gate产生的ΔV p’的拉动。因此，转接点处像素电极相比于其他点会变暗，多个转接点连成一线，显示上即为暗线Mura，影响显示。
此外，如图1所示，公共电极15与像素电极14在阵列基板的厚度方向相对设置；这样设计使得像素电极114与公共电极15之间的交叠面积较大，从而使得像素电极14与公共电极15之间产生的寄生电容较大，继而使得像素的充电率及开口率受到很大影响，导致显示效果较差的问题。
为解决上述问题，本公开实施例还提供了一种阵列基板，可用于液晶显示，但不限于此，也可用于有机发光显示。下面以本公开实施例的阵列基板用于液晶显示为例进行详细说明。
其中，如图3所示，此阵列基板可划分有显示区A和环绕显示区A设置的非显示区B，阵列基板2的非显示区B可设置有环绕显示区A的密封区B1，位于密封区B1靠近显示区A的源静电释放区B2，以及位于密封区B1远离显示区A的扇出区B3，且源静电释放区B2和扇出区B3位于显示区A同一侧的非显示区B(即：绑定区)中。
在本公开的实施例中，阵列基板可包括第一衬底20和设置在第一衬底20上的像素单元、第一扫描线23和第二扫描线24，数据线25、第一公共线26、第二公共线27；需要说明的是，此像素单元、第一扫描线23、第二扫描线24、数据线25、第一公共线26、第二公共线27为位于阵列基板的显示区A上的结构。
其中，结合图4至图7所示，第一衬底20可为单层结构，举例而言，此第一衬底20可为玻璃基板，但不限于此，也可为其他材质基板；此外，第一衬底20也可为多层结构，视具体情况而定。
在本公开的实施例中，结合图4至图7所示，第一衬底20可具有多个在行方向X和列方向Y上阵列排布的像素区、多列在行方向X上排布的第一布线区和多行在列方向Y 上排布的第二布线区204；其中，每个像素区包括至少两个在行方向X上间隔排布的子像素区200；且每列第一布线区与每列像素区在行方向X上交替排布，多列第一布线区中一部分定义为第一子布线区201，另一部分定义为第二子布线区202；每行第二布线区204与每行像素区在列方向Y上交替排布；需要说明的是，每列像素区中相邻两列子像素区200之间还可设置有第三布线区203，应当理解的是，第一子布线区201、第二子布线区202及第三布线区203整体为在列方向Y上延伸，而第二布线区204整体为在行方向X上延伸，因此可知，第一子布线区201、第二子布线区202及第三布线区203与第二布线区204之间存在交叠区域。
如图4所示，像素单元可设置多个，多个像素单元可沿行方向X和列方向Y阵列排布在第一衬底上。需要说明的是，每个像素单元可包括至少两个在行方向X上排布的子像素，每个像素单元中子像素的个数与子像素区200的个数相等，每个像素单元中各子像素与每个像素区中各子像素区200一一对应。此外，像素单元的列数可与第一布线区的列数相等，像素单元的行数可与第二布线区204的行数相等。
举例而言，每个像素单元可包括三个子像素，分别为在行方向X上依次排布的红色子像素、绿色子像素和蓝色子像素之间；其中，在行方向X上相邻两像素单元中一组的红色子像素与另一组的蓝色子像素相邻。
应当理解的是，本公开实施例提到的红色子像素指的是与红色滤光单元相对应的子像素，即：此子像素可用于驱动与红色滤光单元对应的液晶分子发生偏转，使得背光源发出的光线可通过红色滤光单元射出。同理，蓝色子像素指的是与蓝色滤光单元相对应的子像素，即：此子像素可用于驱动与蓝色滤光单元对应的液晶分子发生偏转，使得背光源发出的光线可通过蓝色滤光单元射出。绿色子像素指的是与绿色滤光单元相对应的子像素，即：此子像素可用于驱动与绿色滤光单元对应的液晶分子发生偏转，使得背光源发出的光线可通过绿色滤光单元射出。
也就是说，每个像素单元可包括至少两个在行方向X上间隔的子像素；具体可包括分别与红色、绿色、蓝色滤光单元对应的三个子像素，但值得说明的是，本公开实施例的像素单元不限于前述提到的三个子像素，也可设置更多，例如：四个等等，且子像素对应的颜色不限于前述提到的红色、绿色，蓝色，也可为其他颜色，例如：白色、黄色等等，视具体情况而定。
在本公开的一实施例中，每个子像素可包括子像素电极21a、21b、21c、公共电极22和晶体管28，其中：
子像素电极21a、21b、21c可具有多个在行方向X间隔排布的第一电极条210，此第一电极条210可设置在子像素区200上；应当理解的是，子像素电极21a、21b、21c还可 包括位于各第一电极条210的同一侧并与各第一电极条210连接的第一导电连接部211，也就是说，子像素电极21a、21b、21c整体可呈类似“梳子”的形状，此第一导电连接部211可设置在第二布线区204处。
结合图4、图5及图8所示，第一电极条210整体可呈弯折状，其弯折角度α1为150°至170°，具体地，第一电极条210可包括两部分结构，这两部分结构之间的夹角α1为150°至160°；比如：150°、156°、162°、166°、170°等等；换言之，这两部分结构的延伸方向与列方向Y之间的夹角α2、α3分别为5°至15°，比如：5°、7°、9°、12°、15°等等。
需要说明的是，红色子像素中的子像素电极可定义为红色子像素电极21a，蓝色子像素中的子像素电极可定义为蓝色子像素电极21b，绿色子像素中的子像素电极可定义为绿色子像素电极21c，此红色子像素电极21a、蓝色子像素电极21b及绿色子像素电极21c均具有多个在行方向X间隔排布的第一电极条210，应当理解的是，红色子像素电极21a、蓝色子像素电极21b和绿色子像素电极21c的结构相同，例如：第一电极条210的条数、尺寸、形状、间隙等都相同，第一导电连接部211的形状和尺寸及其与第一电极条210的相对位置均相同。
如图4和图5所示，公共电极22可与子像素电极21a、21b、21c同层设置；举例而言，前述提到的公共电极22和子像素电极21a、21b、21c可为透明电极，且公共电极22和子像素电极21a、21b、21c可采用ITO(氧化铟锡)材料制作而成，但不限于此，也可为IZO(氧化铟锌)等材料。应当理解的是，公共电极22与子像素电极21a、21b、21c之间具有间隙(即：不接触)。
具体地，公共电极22可具有多个第二电极条220，此第二电极条220可位于子像素区200；且公共电极22还可具有第二导电连接部221，以将各第二电极条220连接，此第二导电连接部221可位于第二布线区204。其中，公共电极22的第二电极条220与第一电极条210在行方向X上交替排布，即：子像素电极与公共电极22可呈相互插合状态，也就是说，本公开实施例的阵列基板可为IPS(In-Plane Switching，平面转换)模式，这样设计可减小子像素电极与公共电极之间产生的寄生电容，从而可提升像素充电率及开口率；但不限于此，公共电极22与子像素电极也可位于阵列基板的不同层并相对设置，且公共电极22与子像素电极中一者为具有缝隙的狭缝电极，另一者为不具有狭缝的板状电极，也就是说，本公开实施例的阵列基板也可为FFS(Fringe Field Switching，边缘场开关技术)模式，视具体情况而定。
需要说明的是，各子像素的公共电极22可相互连接形成为一个整体。
在本公开的实施例中，结合图4、图5及图9所示，第二电极条220可呈弯折状，其弯折角度β1为150°至170°，具体地，第二电极条220可包括两部分结构，这两部分结构 之间的夹角β1为150°至160°；比如：150°、156°、162°、166°、170°等等；换言之，这两部分结构的延伸方向与列方向Y之间的夹角β2、β3分别为5°至15°，比如：5°、7°、9°、12°、15°等等。
其中，第二电极条220与第一电极条210可基本平行，也就是说，第二电极条220的弯折角度β1可与第一电极条210的弯折角度α1相同。
基于前述内容，通过将子像素电极的第一电极条210和公共电极22的第二电极条220设置成弯折状，并将其弯折角度设计为150°至170°，这样可减小色偏，提高显示效果。
需要说明的是，每个子像素中第一电极条210和第二电极条220不限于前述提到的在行方向X上交替排布，还可在列方向Y上交替排布，具体视实际需求而定。
此外，还需要说明的是，在第一电极条210和第二电极条220呈前述提到的弯折状时，子像素区200整体的形状也可呈与第一电极条210相同的弯折状，且第一子布线区201、第二子布线区202和第三布线区203整体的形状也可呈与第一电极条210相同的弯折状，以使得阵列基板中子像素电极能够排布的更加密集。而第二布线区204整体形状可与其上信号线(例如：第一扫描线23、第一公共线26)的形状相适配。
结合图4、图5和图7可知，每个子像素的晶体管28可位于第二布线区204。应当理解的是，此晶体管28整体可位于子像素电极21a、21b、21c和公共电极22靠近第一衬底20的一侧，也就是说，晶体管28可先于子像素电极和公共电极22制作在第一衬底20上。如图4和图5所示，每个晶体管28可与一子像素电极连接，但不限于此，也可一个晶体管28与多个子像素电极连接，或一个子像素电极与多个晶体管28连接等等，视具体情况而定。
具体地，结合图4、图5及图7所示，晶体管28包括栅极280、有源层281及同层设置的第一极282和第二极283；此第一极282与有源层281的一端连接；第二极283与有源层281的另一端连接；且第二极283可通过第四过孔结构K4与子像素电极连接，具体可通过第四过孔结构K4与子像素电极的第一导电连接部211连接。应当理解的是，第一极282和第二极283中的一者可为源极，另一者可为漏极；且第四过孔结构K4可位于第二布线区204。
在本公开的实施例中，前述提到的栅极280、第一极282和第二极283可采用金属材料制作而成，例如：可采用铝、钼等金属材料制作而成；此栅极280、第一极282和第二极283可为复合层结构，也可为单层结构，视具体情况而定。
如图7所示，本公开实施例的晶体管28可为底栅型，即：有源层281位于栅极280远离第一衬底20的一侧，应当理解的是，有源层281与栅极280之间可形成有栅绝缘层 29a。也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成栅极280；之后，再形成覆盖栅极280的栅绝缘层29a；然后，在栅绝缘层29a上形成与栅极280正对的有源层281。需要说明的是，此栅绝缘层29a整层设置在第一衬底20上，也就是说，栅绝缘层29a不仅覆盖栅极280，还可覆盖先于栅绝缘层29a制作的其他结构。应当理解的是，此栅绝缘层29a可采用无机材料制作而成，例如：氧化硅、氮氧化硅等材料。
其中，前述提到晶体管28可先于子像素电极制作在第一衬底20上，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成晶体管28；之后，再形成子像素电极和公共电极22；需要说明的是，在第一衬底20上形成晶体管28的第一极282和第二极283之后，以及形成子像素电极和公共电极22之前，还可形成一层钝化层29b，如图7所示，此钝化层29b覆盖第一极282和第二极283，而子像素电极的第一导电连接部211可经贯穿钝化层29b上的第四过孔结构K4与第二极283连接。
其中，此钝化层29b整层设置在第一衬底20的各区域上，也就是说，钝化层29b不仅覆盖第一极282和第二极283，还可覆盖先于钝化层29b制作在第一衬底20上的其他结构。应当理解的是，此钝化层29b可采用无机材料制作而成，例如：氧化硅、氮氧化硅等材料。
在钝化层29b与子像素电极之间还可形成有机绝缘层(图中未示出)，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成钝化层29b；之后，再在钝化层29b上形成有机绝缘层；然后，再在有机绝缘层上形成子像素电极；其中，子像素电极的第一导电连接部211可经贯穿有机绝缘层和钝化层29b上的第四过孔结构K4与第二极283连接。
在本公开的实施例中，通过设置有机绝缘层在实现平坦化，以在利于后续涂覆子像素电极材料的同时，还可增加子像素电极与第二极283所在层的距离，从而可避免第二极283所在层上的信号线对子像素电极产生干扰。
需要说明的是，本公开实施例的阵列基板也可不设置有机绝缘层。
在钝化层29b与有机绝缘层之间还可形成彩色滤光层(图中未示出)，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成钝化层29b；之后，再在钝化层29b上形成彩色滤光层；然后，再在彩色滤光层上形成有机绝缘层；其中，子像素电极的第一导电连接部211可经贯穿有机绝缘层、彩色滤光层、钝化层29b上的第四过孔结构K4与第二极283连接；举例而言，彩色滤光层可包括前述提到的红色、绿色、蓝色等滤光单元。
需要说明的是，本公开实施例的阵列基板也可不设置彩色滤光层，此彩色滤光层可设置在对置基板中。
此外，本公开实施例的晶体管28不限于底栅型，也可为顶栅型，视具体情况而定。
如图4所示，第一扫描线23可设置多行，并沿列方向Y依次排布在第一衬底20上；此第一扫描线23可位于第二布线区204。其中，第一扫描线23可形成在第一衬底20与公共电极22之间，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成第一扫描线23，然后再形成公共电极22和子像素电极。举例而言，此第一扫描线23可与晶体管28的栅极280同层设置且相连接，应当理解的是，晶体管28的栅极280与第一扫描线23可为一体式结构。
在本公开的实施例中，每行第二布线区204上可设置至少一行第一扫描线23，换言之，每行像素单元在列方向Y上的一侧设置至少一行第一扫描线23。举例而言，每行第二布线区204可设置一行第一扫描线23，其中，同一行第一扫描线23与同一行中各子像素的晶体管的栅极连接，也就是说，一行第一扫描线23可为一行像素单元中各子像素提供扫描信号；但不限于此，每行第二布线区204之间也可设置两行第一扫描线23，视具体情况而定。
如图4所示，第一公共线26可设置多行，并沿列方向Y上依次排布在第一衬底上。此第一公共线26与子像素连接，用于为子像素提供给公共信号。此第一公共线26可形成在第一衬底20与公共电极22之间，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成第一公共线26，然后再形成公共电极22和子像素电极。举例而言，此第一公共线26可与第一扫描线23同层设置，此第一公共线26可通过第二过孔结构K2与公共电极22连接，以能够为公共电极22提供公共信号；具体地，第一公共线26可通过第二过孔结构K2与公共电极22的第二导电连接部221连接，需要说明的是，此第二过孔结构K2可位于第二布线区204。
在本公开的实施例中，每行第二布线区204上可设置至少一行第一公共线26，换言之，每行像素单元在列方向Y上的一侧设置至少一行第一公共线26。举例而言，每行第二布线区204可设置一行第一公共线26。其中，同一行第一公共线26与同一行中同种颜色的子像素的公共电极通过第二过孔结构K2连接，例如：同一行第一公共线26均与同一行中红色子像素的公共电极22的第二导电连接部221通过第二过孔结构K2连接。
在第一公共线26通过第二过孔结构K2与公共电极22连接时，此处提到的第二过孔结构K2可至少贯穿前述提到的栅绝缘层29a和钝化层29b；可选地，在阵列基板包括前述提到的有机绝缘层和彩色滤光层时，此处提到的第二过孔结构K2还可贯穿有机绝缘层和彩色滤光层。
基于前述可知，每行第二布线区204上可设置一行第一扫描线23和一行第一公共线26，应当理解的是，第一公共线26与第一扫描线23之间无连接。
如图4所示，第二公共线27可设置多列，并沿行方向X依次排布在第一衬底20上。此第二公共线27可形成在第一衬底20与公共电极22之间。也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成第二公共线27，然后再形成公共电极22和子像素电极，此第二公共线27与公共电极22和子像素电极之间形成有前述提到的钝化层29b。
举例而言，此第二公共线27可与晶体管28的第一极282和第二极283同层设置，其中，前述提到第一公共线26可与第一扫描线23同层设置，且第一扫描线23可与晶体管28的栅极280同层设置，因此可知，本公开实施例的第二公共线27在第一公共线26之后制作而成，需要说明的是，第二公共线27与第一公共线26之间形成有前述提到的栅绝缘层29a。
在本公开的实施例中，此第二公共线27可通过第三过孔结构K3与公共电极22连接。具体地，如图4所示，在第二公共线27通过第三过孔结构K3与公共电极22连接时，此处提到的第三过孔结构K3可至少贯穿前述提到的钝化层29b，进一步地，在阵列基板包括前述提到的有机绝缘层和彩色滤光层时，此处提到的第三过孔结构K3还可贯穿有机绝缘层和彩色滤光层，需要说明的是，第三过孔结构K3可位于第二布线区204，第二公共线27可通过第三过孔结构K3与公共电极22的第二导电连接部221连接。
其中，第一公共线26和第二公共线27中至少一者具有公共信号输入端，以为公共电极22提供公共信号；可选地，第二公共线27具有公共信号输入端，第二公共线27可将接收到的公共信号传输至第一公共线26和公共电极22，但不限于此，也可第一公共线26和第二公共线27均具有公共信号输入端。
在本公开的实施例中，每列第二子布线区202可设置一列第二公共线27。举例而言，第二公共线27中与第一电极条210在行方向X上相对的部位的形状可与第一电极条210的形状相匹配，即：在第一电极条210呈弯折状时，第二公共线27中与第一电极条210在行方向X上相对的部位也可呈弯折状，并可与第一电极条210基本平行。
应当理解的是，本公开实施例中也可仅设置第一公共线26，或仅设置第二公共线27，视具体情况而定。
如图4所示，第二扫描线24可设置多列，并沿行方向X依次排布在第一衬底20上。举例而言，此第二扫描线24可形成在第一衬底20与公共电极22之间，也就是说，在制作阵列基板的过程中，可先在第一衬底20上形成第二扫描线24，然后再形成公共电极22和子像素电极。举例而言，此第二扫描线24可与晶体管28的第一极282和第二极283同层设置，应当理解的是，第二扫描线24与晶体管28的第一极282和第二极283之间具有间隙(即：不接触)。
其中，如图4所示，每列第一布线区设置至少一列第二扫描线24，换言之，每行像 素单元在行方向X上的一侧设置至少一列第二扫描线24。需要说明的是，前述提到在行方向X上相邻两像素单元中一组的红色子像素与另一组的蓝色子像素相邻，因此可知，本公开实施例的第二扫描线24可位于相邻两列红色子像素与蓝色子像素之间。
举例而言，第二扫描线24中与第一电极条210在行方向X相对的部位的形状可与第一电极条210的形状相匹配，即：在第一电极条210呈弯折状时，第二扫描线24中与第一电极条210在行方向X相对的部位也可呈弯折状，并可与第一电极条210相平行。
在本公开的实施例中，第二扫描线24通过第一过孔结构K1与一行第一扫描线23连接，此第二扫描线24具有扫描信号输入端，此第二扫描线24接收到的扫描信号可依次经第一过孔结构K1、第一扫描线23传输至对应晶体管28的栅极280，以控制此晶体管28的开、关。
可选地，此第一过孔结构K1可包括第一过孔部K11及连接部K12，此连接部K12与第二扫描线24位于阵列基板的不同层，且连接部K12的部分与第一扫描线23连接，连接部K12的部分通过第一过孔部K11与第二扫描线24连接。
进一步地，连接部K12与公共电极22和子像素电极同层设置，并与公共电极22和子像素电极之间具有间隙(即：不接触)，在此情况下，第一过孔结构K1还可包括第二过孔部K13，连接部K12可通过第二过孔部K13与第一扫描线23连接；也就是说，连接部K12的部分可通过第二过孔部K13与第一扫描线23连接，且连接部K12的部分通过第一过孔部K11与第二扫描线24连接。
需要说明的是，在连接部K12与公共电极22和子像素电极同层设置时，此第一过孔部K11可至少贯穿钝化层29b，进一步地，在阵列基板包括前述提到的有机绝缘层和彩色滤光层时，此处提到的第一过孔部K11还可贯穿有机绝缘层和彩色滤光层；而第二过孔部K13可至少贯穿栅绝缘层29a和钝化层29b，进一步地，在阵列基板包括前述提到的有机绝缘层和彩色滤光层时，此处提到的第二过孔部K13还可贯穿有机绝缘层和彩色滤光层。
在本公开的实施例中，第一扫描线23可设有多个镂空孔230，前述提到的第二过孔部K13在第一衬底20上的正投影与第一扫描线23在第一衬底20上的正投影部分重合，且第二过孔部K13在第一衬底20上的正投影与镂空孔230在第一衬底20上的正投影部分重合，这样设计可减小连接部K12与第一扫描线23之间产生的寄生电容。
需要说明的是，前述提到的第一过孔结构K1可位于第二布线区204，其中，第一公共线26可在此第一过孔结构K1处做避让设计，即：前述提到的第一过孔结构K1在第一衬底20上的正投影不与第一公共线26在第一衬底20上的正投影 重合。
应当理解的是，连接部K12不限于与公共电极22同层设置，例如：连接部K12可与第一扫描线23同层设置并直接连接，即：不需要设置前述提到的第二过孔部K13。其中，在连接部K12可与第一扫描线23同层设置时，此连接部K12整体可在列方向上延伸，且其可位于在行方向X上相邻两像素单元之间的第一布线区上。
可选地，每行第一扫描线23可与两列第二扫描线24连接，换言之，两列第二扫描线24分别通过一第一过孔结构K1与同一行第一扫描线23连接，也就是说，每行可通过两组扫描信号进行驱动，这样可加强扫描信号，以提高显示效果。但不限于此，每行第一扫描线23也可与一列第二扫描线24连接或与三列或更多列第二列扫描线连接。需要说明的是，为了保证显示均一性，每行第一扫描线23连接的第二扫描线24的数量需一致。
基于前述内容可知，本公开实施例通过将第二扫描线24设置在第一布线区，相比于图1中将竖向扫描线11从子像素中间引出的方案，可减小第二扫描线24与子像素电极的交叠面积，从而可减小第二扫描线24与子像素电极之间产生的耦合电容，以改善第二扫描线24处扫描信号对像素电极拉动而产生的ΔV p，的情况，从而改善Mura现象，提高产品质量。需要说明的是，本公开实施例中第二扫描线24与子像素电极之间产生的耦合电容小到忽略不计。
此外，由于负责感知颜色的视锥细胞中用于感知绿红蓝三种视锥细胞的数量比例为40：20：1，因此，人眼目前对绿色最敏感；也就是说，在实际应用中，红色和蓝色相比于绿色对液晶显示面板的透过率影响较小，基于此，本公开进一步将第二扫描线24设计在相邻的红色子像素与蓝色子像素之间，即使第二扫描线24导致红色子像素和蓝色子像素处出现漏光，人眼也不易察觉，影响比较小，因此，可减小此处黑矩阵的宽度或可省略此处黑矩阵的设计，以提高像素开口率。
在本公开的实施例中，由于第二扫描线24提供的扫描信号较强，因此，为了保证显示均一性，如图4所示，每列第一子布线区201上设置第二扫描线24，即：第一子布线区201和第二子布线区202上均设置第二扫描线24；具体地，第一子布线区201和第二子布线区202中一者上设置至少一列第二扫描线24，而另一者上设置一列第二扫描线24。
可选地，每列第一子布线区201上设置有两列第二扫描线24，且每列第二子布线区202均设置有一列第二扫描线24；其中，同一第一子布线区201上的两列第二扫描线24分别与不同行第一扫描线23通过第一过孔结构K1连接，这样在保证显示效果的同时，可降低加工难度。
需要说明的是，为进一步保证显示均一性，可使得第一子布线区201上信号 线的数量与第二子布线区202上信号线的数量相等；其中，前述提到第一子布线区201设置有两列第二扫描线24，而第二子布线区202设置有一列第二扫描线24，为了使得第二子布线区202上信号线的数量与第一子布线区201上信号线的数量一致，还可在每列第二子布线区202上设置一列前述提到的第二公共线27。
以4K分辨率的显示面板为例，4K分辨率的显示面板中像素单元具有3840列和2160行，其中，每个像素单元包括在行方向上依次排布的红色子像素、绿色子像素和蓝色子像素，因此，4K分辨率的显示面板中子像素具有3840×3列和2160行，也就是说，第一布线区具有3840列，第二布线区204具有2160行。其中，前述提到每行第二布线区204设置一行第一扫描线23，即：第一扫描线具有2160行；且前述提到两列第二扫描线24与一行第一扫描线23连接，也就是说，第二扫描线24具有为2160×2列。其中，第一布线区的列数与第二扫描线24的列数为8:9；也就是说，每8列第一布线区为一组，一共设置9列第二扫描线24；即：每组第一布线区中1列第一布线区为第一子布线区201，此第一子布线区201设置两列第二扫描线24；而其余7列第一布线区为第二子布线区202，每列第二子布线区202设置一列第二扫描线24和一列第二公共线27。
换言之，本公开实施例中多列第一布线区划分成多列第一布线区组，每列第一布线区组包括在行方向X上依次排布的8列第一布线区，即：每列第一布线区组中第1列第一布线区、第2列第一布线区、第3列第一布线区、第4列第一布线区、第5列第一布线区、第6列第一布线区、第7列第一布线区、第8列第一布线区在行方向X上依次排布，需要说明的是，各列第一布线区组中第一布线区的排列方向相同；其中，每列第一布线区组中第n列第一布线区为第一子布线区201，其余7列第一布线区为第二子布线区202，其中，1≤n≤8，且n为正整数，也就是说，各列第一布线区组中第一布线区201位于相同列数。
需要说明的是，本公开实施例的显示面板不限于前述提到的4K分辨率；也可为其他分辨率，因此，第一布线区的总数量、第一子布线区201和第二子布线区202的占比及位置关系不限于前述提到内容，也可根据具体情况而定，只要能够保证整个面板显示均一性即可。
此外，还需要说明的是，多列第二子布线区202中部分第二子布线区202也可不设置第二公共线27，其中，不设置第二公共线27的第二子布线区202可均匀排布在显示面板中，具体视实际需求而定。
如图4和图5所示，数据线25设置多列，并沿行方向X上依次排布在第一衬底20上，数据线25与子像素连接，用于为子像素提供数据信号。举例而言，数据线25形成在第一衬底20与公共电极22之间，也就是说，在制作阵列基板的过程中，可先在第一 衬底20上形成数据线25，然后再形成公共电极22和子像素电极。其中，数据线25具有数据信号输入端，数据线25与晶体管28的第一极282连接，即：数据线25可将其接收到的数据信号传输至晶体管28的第一极282。可选地，此数据线25可与晶体管28的第一极282同层设置。
在本公开的实施例中，第一子布线区201、第二子布线区202及第三布线区203均可设置至少一列数据线25，换言之，每列子像素在行方向X上的至少一侧设置数据线25。
一可选实施例中，如图4所示，每列子像素在行方向X上的一侧设置一列数据线25，每列数据线25与每列子像素在行方向X上交替排布，换言之，第一子布线区201、第二子布线区202及第三布线区203上可设置一列数据线25，其中，每列数据线25和与其相邻的一列子像素中各子像素连接。
另一可选实施例中，如图10所示，每列子像素在行方向X上的相对两侧均设置一列数据线25，也就是说，位于相邻两列子像素之间的第一子布线区201、第二子布线区202、第三布线区203上设置两列数据线25；其中，每列子像素中位于偶数行的各子像素和位于其一侧并与之相邻的一列数据线25连接，位于奇数行的各子像素和位于其另一侧并与之相邻的另一列数据线25连接，即：每列子像素都匹配连接两列数据线25，且这两列数据线25分别位于每列子像素在行方向X上的相对两侧，这样可提升充电时间。
应当理解的是，子像素两侧的两列数据线25与子像素之间的间距可相等，这样使得子像素两侧受到数据信号拉动一致，从而在亮度为L0时子像素两侧基本无有数据信号产生的压差，继而使得第一子布线区201、第二子布线区202和第三布线区203处可以不需要考虑漏光问题。
需要说明的是，无论第一子布线区201、第二子布线区202上设置一列数据线25，还是两列数据线25，此数据线25相比于第二公共线27、第二扫描线24更靠近与其连接的一列子像素处。
在本公开的实施例中，数据线25中与第二电极条220在行方向X上相对的部位的形状可与第二电极条220的形状相匹配，即：在第二电极条220呈弯折状时，数据线25中与第二电极条220在行方向上相对的部位也可呈弯折状，并可与第二电极条220基本平行。
在本公开的一实施例中，第二扫描线24在行方向X上的宽度可大于数据线25行方向X上的宽度；可选地，第二扫描线24在行方向X上的宽度与数据线25在行方向X上的宽度之比可为1.1至2，比如：1.1、1.3、1.5、1.7、2等等，举例而言，数据线25在行方向X上的宽度可为6μm左右，第二扫描线24的宽度在行方 向X上的宽度可为10μm左右，但不限于此，也可为其他数值，视具体情况而定。
可选地，第二公共线27在行方向X上的宽度可与第二扫描线24的宽度相等。
在本公开的一实施例中，前述提到的第一子布线区201在行方向X上的宽度可为W1，第二子布线区202在行方向X上的宽度可为W2，而子像素区200在行方向X上的宽度可为W3；其中，0≤(W1-W2)/(2×W3)≤4％，且W1、W2和W3为正数；这样设计可避免第二扫描线24处出现竖纹Mura的风险。
可选地，第一子布线区201的宽度W1与第二子布线区202的宽度W2可相等，以降低设计难度。
在本公开的一实施例中，阵列基板还可包括第一覆盖部33，此第一覆盖部33在第一衬底20上的正投影与位于相邻两像素区之间的第一布线区完全重合，此第一覆盖部33与子像素的公共电极22同层设置并连接，也就是说，第一覆盖部33可将位于相邻像素区之间的各信号线(例如：第二扫描线24、数据线25、第二公共线27)覆盖，以起到屏蔽信号作用，从而缓解和消除此处信号对子像素区200处电场的影响，从而改善或消除相邻像素区之间的位置漏光的问题，以减小此处黑矩阵BM的面积或无需设计黑矩阵，以提高像素开口率。
需要说明的是，此第一覆盖部33在第一衬底20上的正投影与第二布线区204不交叠；此第一覆盖部33在列方向Y上的相对两侧分别与相邻两行子像素的公共电极22的第二导电连接部221相接。
此外，阵列基板还可包括第二覆盖部34，此第二覆盖部34在第一衬底20上的正投影与位于每个像素区中相邻两子像素区200之间的第三布线区203完全重合，此第二覆盖部34与子像素的公共电极22同层设置并连接，也就是说，第二覆盖部34可将位于每个像素区的相邻两子像素区200之间的信号线(例如：数据线25)覆盖，以起到屏蔽信号作用，从而缓解和消除此处信号对子像素区200处电场的影响，从而改善或消除每个像素区中相邻两子像素区200之间的位置漏光的问题，以减小此处黑矩阵BM的面积或无需设计黑矩阵，以提高像素开口率。
需要说明的是，此第二覆盖部34在第一衬底20上的正投影与第二布线区204不交叠；此第二覆盖部34在列方向Y上的相对两侧分别与相邻两行子像素的公共电极22的第二导电连接部221相接。
应当理解的是，在行方向X相邻子像素的公共电极22的第二导电连接部221相接，此第二导电连接部221可覆盖部分第二布线区204，虽然公共电极22的第二导电连接部221覆盖部分第二布线区204，可起到屏蔽第一扫描线23上扫描信号的作用，但子像素电极与第一扫描线23之间存在的耦合电场在显示过程中会导致液晶排布紊乱，因此，第 二布线区204处还需要黑矩阵32进行遮盖。
其中，每个子像素在行方向X上的相对两侧还可设置金属线30，此金属线30相比于数据线25更靠近子像素设置；其中，本公开实施例的金属线30可与第一公共线26同层设置并与第一公共线26相接，此金属线30可起到屏蔽信号的作用，以缓解和消除数据信号和扫描信号对子像素区200处电场的影响，提高显示效果。
在本公开的实施例中，前述提到的第二扫描线24的扫描信号输入端、第二公共线27的公共信号输入端和数据线25的数据信号输入端可位于第一衬底20的同一侧，例如：第一衬底20具有在列方向Y上相对设置的第一侧和第二侧；第二扫描线24的扫描信号输入端、第二公共线27的公共信号输入端和数据线25的数据信号输入端均靠近第一侧或均靠近第二侧，这样可使第一衬底20的其他侧没有第二扫描线24的扫描信号输入端、第二公共线27的公共信号输入端和数据线25的数据信号输入端，因此，其他侧可以做的很窄，从而可以提高显示区A占比，以实现全面屏显示。
需要说明的是，如图3所示，用于为第二扫描线24提供扫描信号的栅极280驱动电路所在的区域B4可位于非显示区B，具体可位于源静电释放区B2和扇出区B3之间，并位于密封区B1内侧。但不限于此，用于为第二扫描线24提供扫描信号的栅极280驱动电路也可不设置在第一衬底20上，其可通过一柔性电路板与第一衬底20上的第二扫描线24电连接。
此外，还需要说明的是，本公开中提到的各过孔结构或过孔部可为孔内填充有导电材料的结构。
其中，本公开实施例的阵列基板还可包括存储电容31，此存储电容31可包括在阵列基板的厚度方向上相对的第一极板310和第二极板311，此第一极板310可与第一公共线26同层设置并相连，第二极板311可与晶体管28的第一极282和第二极283同层设置，且第二极板311可与晶体管28的第二极283连接；需要说明的是，子像素电极的第一导电连接部211可通过第四过孔结构K4与第二极板311连接，以实现子像素电极的第一导电连接部211与晶体管28的第二极283连接。
基于前述内容，在本公开一实施例的阵列基板中，第一子布线区201设置两列第二扫描线24和一列数据线25，第二子布线区202设置一列第二扫描线24、一列第二公共线27和一列数据线25；第三布线区203设置一列数据线25，且每行第一扫描线23与两列第二扫描线24通过第一过孔结构K1连接；此阵列基板可用于4K 60Hz的显示面板中。
在本公开另一实施例的阵列基板中，第一子布线区201设置两列第二扫描线24和两列数据线25，第二子布线区202设置一列第二扫描线24、一列第二公共线27和两列数据线25；第三布线区203设置两列数据线25，且每行第一扫描线23与两列第二扫描线 24通过第一过孔结构K1连接；此阵列基板可用于4K 120Hz或8K 60Hz的显示面板中。
需要说明的是，前述提到的4K和8K指的是显示面板的分辨率，60Hz和120Hz指的是显示面板的刷新率。
本公开实施例还提供了一种显示面板，其包括上述任一实施例所描述的阵列基板；应当理解的是，此显示面板可为液晶面板，因此，显示面板还可包括与阵列基板对盒设置的对置基板和位于对置基板和阵列基板之间的液晶分子。
其中，在阵列基板中具有前述提到的彩色滤光层时，对置基板中可不需要再设置彩色滤光层，此时，对置基板中可包括第二衬底(图中未示出)和设置在第二衬底面向阵列基板一侧的黑矩阵32，如图11所示。
应当理解的是，在阵列基板中不具有前述提到的彩色滤光层时，可在对置基板中设置彩色滤光层。
本公开实施例还提供了一种电子设备，其包括前述所描述的显示面板。
在本公开的实施例中，电子设备的具体类型不受特别的限制，本领域常用的电子设备类型均可，具体例如液晶电视、手机、电脑、手表等等，本领域技术人员可根据该电子设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该电子设备除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域善解人意可根据该电子设备的具体使用要求进行相应地补充，在此不再赘述。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
本说明书中的“第一”、“第二”、“第三”、“第四”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途 或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种阵列基板，其中，包括：
    第一衬底；
    多个像素单元，沿行方向和列方向阵列排布在所述第一衬底上；每个所述像素单元包括至少两个在所述行方向上排布的子像素；
    多行第一扫描线，沿所述列方向依次排布在所述第一衬底上，且每行所述像素单元在所述列方向上的一侧设置至少一行所述第一扫描线，所述第一扫描线与所述子像素连接；
    多列第二扫描线，沿所述行方向依次排布在所述第一衬底上，且每列所述像素单元在所述行方向上的一侧设置至少一列所述第二扫描线；其中，所述第二扫描线具有扫描信号输入端，所述第二扫描线通过第一过孔结构与所述第一扫描线连接。
  2. 根据权利要求1所述的阵列基板，其中，还包括：
    多列数据线，沿所述行方向上依次排布在所述第一衬底上，所述数据线与所述子像素连接；其中，每列所述子像素在所述行方向上的至少一侧设置所述数据线；
    多行第一公共线，沿所述列方向上依次排布在所述第一衬底上，所述第一公共线与所述子像素连接，其中，每行所述像素单元在所述列方向上的一侧设置至少一行所述第一公共线。
  3. 根据权利要求2所述的阵列基板，其中，所述子像素包括：
    子像素电极，具有多个在所述行方向上间隔排布的第一电极条；
    公共电极，与所述子像素电极同层设置，所述公共电极具有多个在所述行方向上间隔排布的第二电极条，所述第二电极条与所述第一电极条在所述行方向上交替排布；且所述公共电极与所述第一公共线通过第二过孔结构连接；
    晶体管，包括栅极、有源层及同层设置的第一极和第二极；所述栅极与所述第一扫描线连接；所述第一极与所述有源层的一端连接，且所述第一极与所述数据线连接；所述第二极与所述有源层的另一端连接，并与所述子像素电极连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第一过孔结构包括第一过孔部及连接部，所述连接部与所述第二扫描线位于所述阵列基板的不同层，且所述连接部的部分与所述第一扫描线连接，所述连接部的部分通过所述第一过孔部与所述第二扫描线连接。
  5. 根据权利要求4所述的阵列基板，其中，所述第一过孔结构还包括第二过 孔部；其中，
    所述连接部与所述公共电极和所述子像素电极同层设置，并与所述公共电极和所述子像素电极之间具有间隙；且所述连接部通过所述第二过孔部与所述第一扫描线连接。
  6. 根据权利要求5所述的阵列基板，其中，所述第一扫描线设有多个镂空孔；
    其中，所述第二过孔部在所述第一衬底上的正投影与所述第一扫描线在所述第一衬底上的正投影部分重合，且所述第二过孔部在所述第一衬底上的正投影与所述镂空孔在所述第一衬底上的正投影部分重合。
  7. 根据权利要求3至6中任一项所述的阵列基板，其中，所述第一衬底具有多个在所述行方向和所述列方向阵列排布的像素区和多列第一布线区；
    其中，每个所述像素区包括至少两个在所述行方向间隔排布的子像素区，每个所述像素区中子像素区的个数与每个所述像素单元中子像素的个数相等，且每个所述子像素的第一电极条和第二电极条设置在一所述子像素区上；
    其中，每列第一布线区与每列像素区在所述行方向上交替排布，所述多列第一布线区中一部分为第一子布线区，另一部分为第二子布线区，所述第一子布线区和所述第二子布线区中一者上设置有至少一列第二扫描线，另一者上设置有一列第二扫描线。
  8. 根据权利要求7所述的阵列基板，其中，
    每列所述第一子布线区上设置有两列第二扫描线，且同一所述第一子布线区上的两列第二扫描线分别与不同行第一扫描线通过所述第一过孔结构连接；
    每列所述第二子布线区设置有一列第二扫描线。
  9. 根据权利要求8所述的阵列基板，其中，
    所述阵列基板还包括多列第二公共线，所述第二公共线通过第三过孔结构与所述公共电极连接；
    其中，所述第二子布线区上设置有一列所述第二扫描线和一列所述第二公共线。
  10. 根据权利要求9所述的阵列基板，其中，所述第一衬底具有多行第二布线区，每行第二布线区与每行像素区在所述列方向上交替排布，每行第二布线区设置一行所述第一扫描线和一行所述第一公共线；
    其中，同一行所述第一扫描线与同一行中各子像素的晶体管的栅极连接，同一行所述第一公共线与同一行中同种颜色的子像素的公共电极通过所述第二过孔结构连接。
  11. 根据权利要求10所述的阵列基板，其中，两列所述第二扫描线分别通过一所述第一过孔结构与同一行所述第一扫描线连接。
  12. 根据权利要求11所述的阵列基板，其中，所述多列第一布线区划分成多列第一布线区组，每列所述第一布线区组包括在所述行方向上依次排布的8列第一布线区，每列所述第一布线区组中第n列第一布线区为所述第一子布线区，其余7列第一布线区为所述第二子布线区，其中，1≤n≤8，且n为正整数。
  13. 根据权利要求9所述的阵列基板，其中，所述第一子布线区在所述行方向上的宽度为W1，所述第二子布线区在所述行方向上的宽度为W2，所述子像素区在所述行方向上的宽度为W3；
    其中，0≤(W1-W2)/(2×W3)≤4％，且W1、W2和W3为正数。
  14. 根据权利要求13所述的阵列基板，其中，所述第一子布线区的宽度W1与所述第二子布线区的宽度W2相等。
  15. 根据权利要求7所述的阵列基板，其中，还包括第一覆盖部，所述第一覆盖部在所述第一衬底上的正投影与位于相邻两所述像素区之间的第一布线区完全重合，其中，所述第一覆盖部与所述公共电极同层设置并连接。
  16. 根据权利要求2所述的阵列基板，其中，每列子像素在所述行方向上的一侧设置一列所述数据线，每列数据线与每列子像素在所述行方向上交替排布，其中，每列数据线和与其相邻的一列子像素中各子像素连接。
  17. 根据权利要求2所述的阵列基板，其中，每列子像素在所述行方向上的相对两侧均设置一列所述数据线，每列子像素中位于偶数行的各子像素和位于其一侧并与之相邻的一列所述数据线连接，位于奇数行的各子像素和位于其另一侧并与之相邻的另一列所述数据线连接。
  18. 根据权利要求2所述的阵列基板，其中，所述第二扫描线在所述行方向上的宽度大于所述数据线在所述行方向上的宽度。
  19. 根据权利要求18所述的阵列基板，其中，所述第二扫描线在所述行方向上的宽度与所述数据线在所述行方向上的宽度之比为1.1至2。
  20. 根据权利要求1所述的阵列基板，其中，每个所述像素单元包括三个所述子像素，分别为在所述行方向上依次排布的红色子像素、绿色子像素和蓝色子像素之间；
    其中，在所述行方向上相邻两所述像素单元中一组的红色子像素与另一组的蓝色子像素相邻。
  21. 一种显示面板，其中，包括权利要求1至20中任一项所述的阵列基板和 与所述阵列基板对盒设置的对置基板。
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