WO2018040578A1 - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents

阵列基板及其制造方法、显示面板和显示装置 Download PDF

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WO2018040578A1
WO2018040578A1 PCT/CN2017/080797 CN2017080797W WO2018040578A1 WO 2018040578 A1 WO2018040578 A1 WO 2018040578A1 CN 2017080797 W CN2017080797 W CN 2017080797W WO 2018040578 A1 WO2018040578 A1 WO 2018040578A1
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Prior art keywords
common electrode
data line
line
gate
lines
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PCT/CN2017/080797
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English (en)
French (fr)
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王洪惠
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/569,219 priority Critical patent/US10720450B2/en
Publication of WO2018040578A1 publication Critical patent/WO2018040578A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • the thin film transistor array substrate process is complicated in manufacturing process, and generally includes depositing a metal thin film, a semiconductor thin film on a base substrate, and then forming a desired metal pattern (for example, a gate line, a data line, a common electrode line) and a semiconductor pattern by a patterning process ( Active layer).
  • a desired metal pattern for example, a gate line, a data line, a common electrode line
  • Active layer a patterning process
  • At least one embodiment of the present invention provides an array substrate, the array substrate includes: a substrate substrate, a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines disposed on the substrate; a plurality of common electrode lines and the plurality of gate lines are disposed in different layers; the plurality of common electrode lines and the plurality of data lines are disposed in the same layer and parallel to each other; the plurality of gate lines and the plurality of lines The data lines, the plurality of common electrode lines are insulated from each other and intersect to define a plurality of sub-pixel units.
  • the plurality of data lines include a first data line and a second data line disposed side by side between each of the two adjacent sub-pixel units.
  • the odd-numbered rows of the sub-pixel units are connected to the first data line
  • the even-numbered rows of the sub-pixel units are connected to the second data line.
  • the array substrate provided by at least one embodiment of the present invention further includes a first data line bus and a second data line bus disposed in parallel with the gate line, wherein the first data line and the first data are A line bus connection, the second data line being connected to the second data line bus.
  • the first data line bus and the second data line bus are disposed at different layers.
  • the array substrate provided by at least one embodiment of the present invention further includes the common electrode
  • the lines are disposed on different common layers of the common electrode line bus disposed in parallel with the gate lines, wherein the common electrode lines are all connected to the common electrode line bus.
  • the common electrode line is disposed on an upper layer or a lower layer of the gate line.
  • the array substrate provided by at least one embodiment of the present invention further includes a thin film transistor, a common electrode, and a pixel electrode disposed in each of the sub-pixel units, wherein a gate of the thin film transistor is connected to the gate line
  • the source of the thin film transistor is connected to the data line
  • the common electrode is connected to the common electrode line
  • the pixel electrode is connected to a drain of the thin film transistor.
  • a semiconductor layer of the thin film transistor is disposed between a layer where the data line is located and a layer where the gate line is located, where the semiconductor layer and the gate line are located
  • a gate insulating layer is disposed between the layers.
  • an insulating layer is disposed on a layer where the data line is located, a layer where the gate line is located, and the semiconductor layer.
  • the array substrate provided by at least one embodiment of the present invention further includes a plurality of gate drivers, wherein the plurality of gate drivers are respectively disposed at two ends of the plurality of gate lines.
  • At least one embodiment of the present invention also provides a display panel including any of the above array substrates.
  • At least one embodiment of the present invention also provides a display device including the above display panel.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: providing a substrate; forming a gate line, a data line, and a common electrode line on the substrate; wherein the common electrode line
  • the gate lines are formed on different layers; the common electrode lines are formed on the same layer as the data lines and are parallel to each other; the gate lines and the data lines and the common electrode lines are insulated from each other and intersect to define a plurality of Sub-pixel units.
  • the data line includes a first data line and a second data line disposed side by side between each of the two sub-pixel units adjacent to each other in two columns.
  • the odd-numbered rows of the sub-pixel units are connected to the first data line
  • the even-numbered rows of the sub-pixel units are connected to the second data line.
  • the manufacturing method provided by at least one embodiment of the present invention further includes: forming a first data line bus and a second data line bus, wherein the first data line is connected to the first data line bus, The second data lines are all connected to the second data line bus, and the first data line bus and the second data line bus are both parallel to the gate line.
  • the first data line bus and the second data line bus are formed on different layers.
  • the manufacturing method provided by at least one embodiment of the present invention further includes: forming a common electrode line bus, wherein the common electrode line bus and the common electrode line are formed on different layers and parallel to the gate line.
  • the common electrode lines are all connected to the common electrode line bus.
  • the common electrode line is formed on an upper layer or a lower layer of the gate line.
  • the manufacturing method provided by at least one embodiment of the present invention further includes: forming a thin film transistor, a common electrode, and a pixel electrode in each of the sub-pixel units, wherein a gate of the thin film transistor is connected to the gate line
  • the source of the thin film transistor is connected to the data line
  • the common electrode is connected to the common electrode line
  • the pixel electrode is connected to a drain of the thin film transistor.
  • the manufacturing method provided by at least one embodiment of the present invention further includes: forming a semiconductor layer of a thin film transistor between a layer where the data line is located and a layer where the gate line is located, where the semiconductor layer and the gate line are located A gate insulating layer is formed between the layers.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the invention.
  • FIG. 2 is a partial cross-sectional structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a partial cross-sectional structural view of another array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a process diagram of a method of fabricating an array substrate according to an embodiment of the invention.
  • wirings such as gate lines, data lines, common electrode lines, etc. disposed in parallel on a thin film transistor array substrate may cause problems such as open circuit or short circuit between the organic particles, static electricity, metal residues, etc., and may pass through the detecting device first.
  • Line Detect Sensor LDS performs line scan to find out the location of the defective wiring, and then scans the bad line through the Position Detect Sensor (PDS) to find the bad specific Position coordinates.
  • the gate lines are formed in the same process step as the common electrode lines, and the spacing between adjacent two signal lines (especially adjacent gate lines and common electrode lines) is higher. Small, generally around 10 ⁇ m, the adjacent two signal lines are prone to short circuit, and the detection accuracy of the current detection equipment is 28 ⁇ m. When a short circuit occurs, the detection device cannot detect the specific position where the defect occurs.
  • At least one embodiment of the present invention provides an array substrate and a method of fabricating the same, a display panel, and a display device, the array substrate including a substrate substrate and a plurality of gate lines, a plurality of data lines, and a plurality of the plurality of gate lines disposed on the substrate a common electrode line, and a plurality of common electrode lines and a plurality of gate lines are disposed in different layers, the plurality of common electrode lines and the plurality of data lines are disposed in the same layer and parallel to each other, the plurality of gate lines and the plurality of data lines, and more The strip common electrode lines are insulated from each other and intersect to define a plurality of sub-pixel units.
  • the common electrode line and the gate line are disposed in different layers, and the common electrode line and the data line are disposed in the same layer and parallel to each other, thereby facilitating detection and maintenance of the circuit of the array substrate, and enhancing the detection capability of the device. , which can improve the yield of the product.
  • FIG. 1 is a schematic diagram of an embodiment of the present invention.
  • a schematic plan view of an array substrate, as shown in FIG. 1, the array substrate includes a base substrate 901 and a plurality of parallel gate lines 1 (shown by thick lines in FIG. 1) disposed on the base substrate 901, and more The data lines 2 are parallel to each other and the plurality of common electrode lines 3 are parallel to each other.
  • the plurality of common electrode lines 3 and the plurality of gate lines 1 are disposed in different layers; the plurality of common electrode lines 3 and the plurality of data lines 2 are disposed in the same layer and are parallel to each other; the plurality of gate lines 1 and the plurality of data lines 2 and The strip common electrode lines 3 are insulated from each other and intersect to define a plurality of sub-pixel units 908. Thereby, the plurality of sub-pixel units 908 are arranged in an array manner.
  • the plurality of common electrode lines 3 and the plurality of data lines 2 are disposed in the same layer and parallel to each other, thereby
  • the problem that the gate line 1 and the common electrode line 3 need to be parallel to each other when the common electrode line 3 is disposed in the same layer is easy to be short-circuited, and when the signal line on the array substrate is short-circuited or broken, it is easy to detect and repair it. , thereby increasing the yield of the product.
  • FIG. 2 is a schematic partial cross-sectional structural view of an array substrate according to an embodiment of the invention. 2 shows a pixel structure using a bottom gate type thin film transistor, but embodiments of the present invention are not limited thereto, and for example, a pixel structure may also employ a top gate type thin film transistor.
  • a gate layer 902 (including a gate of a thin film transistor and a gate line connected thereto) is formed on a base substrate 901; a gate insulating layer 903 covers the gate layer 902 and the substrate On the substrate 901, a semiconductor layer 904 is formed on the gate insulating layer 903; a source/drain electrode layer 905 is formed over the gate insulating layer 903 and the semiconductor layer 904, and a drain electrode 9051 and a source electrode 9052 are disposed on the semiconductor layer 904 at a distance from each other.
  • the data line is formed integrally with the source 9052.
  • An insulating layer 906 (or a passivation layer) is formed over the gate insulating layer 903, the semiconductor layer 904, and the source/drain electrode layer 905; a via structure 909 is formed in the insulating layer 906 to expose a portion of the drain electrode 9051, and the pixel electrode 907 is formed On the insulating layer 906, it is electrically connected to the drain 9051 through the via structure 909.
  • the plurality of data lines 2 include a first data line 21 and a second data line 22 disposed side by side between each two columns of adjacent sub-pixel units 908, and the first data line in the row direction. 21 is alternately arranged with the second data line 22. In every two columns of adjacent sub-pixel units 908, for example, odd row sub-pixel cells are connected to the first data line 21, and even row sub-pixel cells are connected to the second data line 22.
  • the array substrate 9 may further include a first data line bus, a second data line bus, and a common electrode line bus, and the sub-pixel unit includes a thin film transistor, a common electrode, and a pixel electrode (not shown).
  • the common electrode line 3 is disposed at The upper layer of the gate line 1.
  • the common electrode line 3 is disposed between adjacent two columns of sub-pixel units, and the two columns of adjacent sub-pixel units share the common electrode line 3 located therebetween.
  • the array substrate in the embodiment of the present invention may further include a first data line bus 4 and a second data line bus 5 disposed in parallel with the gate line 1, for example, all of the first data lines 21 and the first data line bus 4 is connected, and all of the second data lines 22 are connected to the second data line bus 5.
  • the first data line 21 and the second data line 22 may be scanned one by one using the inspection service device.
  • the first data line bus 4 and the second data line bus 5 may be disposed in the same layer or different layers, such as the first data line bus 4 is disposed on the gate layer 902 where the gate line 1 is located, and the second data line bus 5 is disposed in the data
  • the source/drain electrode layer 905 where the line 2 is located in this case, the first data line 21 is electrically connected to the first data line bus line 4 through a via structure formed in the gate insulating layer 903; or, the second data line bus 5 is disposed
  • the first data line bus 4 is disposed on the source/drain electrode layer 905 where the data line 2 is located, in which case the second data line 22 passes through the via hole formed in the gate insulating layer 903.
  • the structure is electrically connected to the second data line bus 5.
  • the first data line bus 4 and the second data line bus 5 may be disposed in other layers, and details are not described herein again.
  • the array substrate in the embodiment of the present invention may further include a common electrode line bus line 6 disposed in a different layer from the common electrode line 3 and disposed in parallel with the gate line 1, such that the common electrode line 3 and the gate line 1 are disposed to cross each other, And the common electrode lines 3 are all connected to the common electrode line bus 6, for example, the common electrode line bus 6 is disposed in the gate line layer 902.
  • the common electrode line bus 6 may also be disposed at a layer where the common electrode line 3 is located, and disposed at a crossover with the common electrode line 3.
  • the array substrate of the embodiment of the present invention may further include a thin film transistor, a common electrode, and a pixel electrode disposed in each of the sub-pixel units.
  • the gate of the thin film transistor is connected to the gate line 1
  • the source of the thin film transistor is connected to the data line 2
  • the common electrode is connected to the common electrode line 3
  • the pixel electrode is connected to the drain of the thin film transistor.
  • the common electrode may be used as a storage electrode, for example, in a direction perpendicular to the substrate, the common electrode and the pixel electrode at least partially overlap each other to form a storage capacitor; or the common electrode may form an electric field for controlling liquid crystal deflection with the pixel electrode
  • IPS Plane Switch
  • ADS Advanced Super Dimensional Field Conversion Technology
  • a semiconductor layer 904 of a thin film transistor is disposed between a layer where the data line 2 is located and a layer where the gate line 1 is located, and a gate of the thin film transistor may be integrally formed with the gate line 1 and a source of the thin film transistor It is formed integrally with the data line 2.
  • the semiconductor layer 904 is formed of a semiconductor material such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide semiconductor or the like, and the oxide semiconductor may be, for example, IGZO (indium gallium zinc oxide) or ZnO (zinc oxide). Wait.
  • a gate insulating layer 903 is disposed between the layer where the semiconductor layer 904 is located and the gate of the thin film transistor and the gate line 1 is disposed. The gate insulating layer 903 is used to prevent the semiconductor layer 904 from being between the gate of the thin film transistor and the gate line 1. through.
  • an insulating layer is disposed on the layer where the data line 2 is located, the layer where the gate line 1 is located, and the semiconductor layer, and the insulating layer is usually made of an organic insulating material (for example, an acrylic resin) or an inorganic insulating material (for example, silicon nitride SiNx). Or silicon oxide SiOx) is formed.
  • an organic insulating material for example, an acrylic resin
  • an inorganic insulating material for example, silicon nitride SiNx. Or silicon oxide SiOx
  • the pixel electrode in the embodiment of the present invention may be disposed in the same layer as the gate line 1, or between the semiconductor layer 904 and the source/drain electrode layer 905 where the data line 2 is located, or may be disposed at the data line 2
  • the source/drain electrode layer 905 is interposed between the insulating layer 906 and the insulating layer 906.
  • a via structure 909 is disposed in the insulating layer 906, and the pixel electrode 907 is in the source/drain electrode layer 905 where the data line 2 and the common electrode line 3 are located.
  • the drains 9051 are connected by the via structure 909.
  • the array substrate 9 may further include a plurality of gate drivers 7, such as GOA (Gate-driver on Array) cells, wherein the gate drivers 7 may be disposed at one end of each gate line 1. Or both ends. As shown in FIG. 1, a plurality of gate drivers 7 are arranged in alignment at both ends of the gate line 1, and gate drivers 7 provided at one end of each gate line 1 are connected to each other and through signal input provided at one end of a gate driver 7. The terminal 8 inputs a control signal or the like to the gate driver 7.
  • GOA Gate-driver on Array
  • the gate driver 7 is usually disposed at both ends of the gate line 1 to prevent the gate line 1 from being too long so that the signal applied by the gate driver 7 is blocked or delayed on the gate line 1.
  • the base substrate 901 may be a glass substrate or a plastic substrate.
  • the data line 2 and the common electrode line 3 may be detected by using an open circuit detector, and after the detection is completed, the first The data line bus 4, the second data line bus 5, and the common electrode line bus 6 can be removed from the array substrate 9 by a dicing process.
  • FIG. 3 is a partial cross-sectional structural view of another array substrate according to an embodiment of the present invention.
  • the thin film transistor in the array substrate is a top gate thin film transistor.
  • a buffer layer 910 is disposed on the base substrate 911, a semiconductor layer 914 is disposed on the buffer layer 910, and a gate insulating layer 913, a gate layer 912, and an insulating layer 916 are sequentially formed on the semiconductor layer 914.
  • a source/drain electrode layer 915 is formed on the insulating layer 916, an insulating layer 916 and a passivation layer 918 are sequentially formed on the source/drain electrode layer 915, and a via structure 919 is formed on the passivation layer 918 and the insulating layer 916, and the pixel electrode 917 passes
  • the via structure 919 is electrically connected to the drain 9151 of the source/drain electrode layer 915.
  • the gate of the thin film transistor is connected to the gate line, and the source 9152 is connected to the data line.
  • the features of other structures of the array substrate in the embodiment of the present invention for example, the gate line 1, the data line 2, the common electrode line 3, the semiconductor layer 904, and the like can be referred to the above related description, and the technical effects thereof are similar to the implementation principle. This will not be repeated here.
  • Embodiments of the present invention also provide a display panel including any of the above array substrates.
  • the display panel may be a liquid crystal display panel, or may be an OLED (Organic Light-Emitting Diode) display panel, an electronic paper display panel, or the like.
  • OLED Organic Light-Emitting Diode
  • the display panel in the embodiment of the present invention further includes an opposite substrate disposed opposite to the array substrate.
  • the display panel is formed by the array substrate and the opposite substrate, and the cavity between the array substrate and the opposite substrate is opposite to the box. Fill the liquid crystal.
  • the opposite substrate is, for example, a color filter substrate, and may include a counter substrate, a black matrix, and a color film unit.
  • Embodiments of the present invention also provide a display device including any of the above display panels.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 4 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention. As shown in FIG. 4, the method for fabricating the array substrate may include The following steps:
  • Step 100 providing a substrate.
  • Step 101 forming gate lines, data lines, and common electrode lines on the base substrate.
  • the common electrode lines and the gate lines are formed on different layers
  • the common electrode lines and the data lines are formed on the same layer and parallel to each other
  • the gate lines and the data lines and the common electrode lines are insulated from each other and intersect to define a plurality of sub-pixel units.
  • the gate line and the data line and the common electrode line are insulated from each other and intersect
  • the fork defines a plurality of sub-pixel units, thereby facilitating detection of whether the array substrate is in a short circuit or an open state, thereby improving the yield of the product.
  • FIG. 5 is a schematic flowchart of a method for fabricating an array substrate according to another embodiment of the present invention. As shown in FIG. 5, the method for fabricating the array substrate includes the following steps:
  • Step 200 providing a substrate.
  • the base substrate may be a glass substrate, a quartz substrate, or the like.
  • Step 201 Form a gate line on the base substrate and a first data line bus and a common electrode line bus parallel to the gate line.
  • a uniform metal film is deposited on the entire substrate, and a gate line, a first data line bus, and a common electrode line bus are formed by a patterning process, and the patterning process includes uniformly coating a lithography on the metal film.
  • the glue forms a gate line and a pattern of the first data line bus and the common electrode line bus parallel to the gate line by processes such as exposure, development, etching, and stripping of the photoresist.
  • the metal film can be prepared using a metal material such as aluminum, aluminum alloy, copper, or copper alloy.
  • Step 202 forming a gate insulating layer and a semiconductor layer on the gate line, the first data line bus, and the common electrode line bus.
  • the material of the semiconductor layer is, for example, a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • GZO gallium zinc oxide
  • a via structure may also be formed in the gate insulating layer by a patterning process to expose a portion of the first data line bus and a portion of the common electrode line bus.
  • Step 203 forming a source/drain electrode layer on the semiconductor layer, and configured to be disposed side by side between the first data line and the second data line between each two columns of adjacent sub-pixel units, parallel to the first data line and the second data A common electrode line of the line, and a second data line bus parallel to the gate line.
  • the gate lines and the data lines, the common electrode lines are insulated from each other and intersect to define a plurality of sub-pixel units.
  • the odd-row sub-pixel units are connected to the first data line
  • the even-numbered sub-pixel units are connected to the second data line.
  • the first data line is connected to the first data line bus through a via structure formed in the gate insulating layer
  • the second data line is connected to the second data line bus
  • the common electrode line and the common electrode line bus are formed in the gate insulating layer.
  • the via structure is connected.
  • a metal thin film is plated on the semiconductor layer, and referring to step 202, an electrode pattern including the first data line and the second data line, and the common electrode line and the second data line bus line is also formed by a patterning process.
  • the metal thin film can be prepared using a metal material such as aluminum, aluminum alloy, copper, or copper alloy.
  • Step 204 forming an insulating layer on the layer where the data line and the common electrode line are located.
  • an insulating material is plated over the entire source-drain electrode layer, and the insulating material includes an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like, or an organic insulating material.
  • an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like, or an organic insulating material.
  • a via structure may also be formed in the insulating layer by a patterning process to expose a portion of the drain.
  • Step 205 depositing a transparent conductive film on the insulating layer and patterning it to form a pixel electrode.
  • ITO indium tin oxide
  • the pixel electrode and the common electrode may be formed in the same layer, for example, both of which form a comb electrode.
  • a via structure may be formed in the insulating layer by a patterning process to expose a portion of the common electrode line; in the above step 205, a common electrode is formed while forming the pixel electrode, and the common electrode passes through the insulating layer. The via structure in the middle is electrically connected to the common electrode line.
  • a thin film transistor, a common electrode and a pixel electrode are formed in each sub-pixel unit, wherein a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and the common electrode is The common electrode line is connected, and the pixel electrode is connected to the drain of the thin film transistor.
  • An array substrate and a manufacturing method thereof, a display panel and a display device provided by embodiments of the present invention have at least one of the following beneficial effects:
  • the common electrode line and the gate line are disposed in different layers, and the common electrode line and the data line are disposed in the same layer and parallel to each other, so that the problem that the parallel wiring is easy to be short-circuited can be avoided;

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Abstract

一种阵列基板及其制造方法、显示面板和显示装置，该阵列基板包括衬底基板(901)以及设置在所述衬底基板(901)上的多条栅线(1)、多条数据线(2)和多条公共电极线(3)，并且多条公共电极线(3)与多条栅线(1)设置在不同层，多条公共电极线(3)与多条数据线(2)设置在同一层且相互平行，多条栅线(1)与多条数据线(2)、多条公共电极线(3)相互绝缘且交叉以限定多个亚像素单元(908)。在该阵列基板中，公共电极线(3)与栅线(1)设置在不同层，公共电极线(3)与数据线(2)设置在同一层且相互平行，这样可以避免平行配线易于短路的问题，还便于对阵列基板的电路进行检测与维修，加强设备的检出能力，从而可以提高产品的良率。

Description

阵列基板及其制造方法、显示面板和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法、显示面板和显示装置。
背景技术
薄膜晶体管阵列基板工艺制造流程复杂，一般包括在衬底基板上沉积金属薄膜、半导体薄膜，然后通过构图工艺形成所需的金属图案(例如，栅线、数据线、公共电极线)和半导体图案(有源层)。形成信号线时，往往需要对信号线的电路进行检测。薄膜晶体管阵列基板中有大量的平行配线，在平行配线之间由于存在光刻胶残渣、静电以及金属残留物，从而易出现开路、膜层间短路等不良现象。
发明内容
本发明至少一实施例提供一种阵列基板，该阵列基板包括：衬底基板，设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线；其中，所述多条公共电极线与所述多条栅线设置在不同层；所述多条公共电极线与所述多条数据线设置在同一层且相互平行；所述多条栅线与所述多条数据线、所述多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
例如，在本发明至少一实施例提供的阵列基板中，所述多条数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线，在每两列相邻所述亚像素单元中，奇数行所述亚像素单元连接所述第一数据线，且偶数行所述亚像素单元连接所述第二数据线。
例如，本发明至少一实施例提供的阵列基板，还包括与所述栅线平行设置的第一数据线总线和第二数据线总线，其中，所述第一数据线均与所述第一数据线总线连接，所述第二数据线均与所述第二数据线总线连接。
例如，在本发明至少一实施例提供的阵列基板中，所述第一数据线总线与所述第二数据线总线设置在不同层。
例如，本发明至少一实施例提供的阵列基板，还包括与所述公共电极 线设置在不同层且与所述栅线平行设置的公共电极线总线，其中，所述公共电极线均与所述公共电极线总线连接。
例如，在本发明至少一实施例提供的阵列基板中，所述公共电极线设置在所述栅线的上层或下层。
例如，本发明至少一实施例提供的阵列基板，还包括设置在每个所述亚像素单元中的薄膜晶体管、公共电极和像素电极，其中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述公共电极与所述公共电极线连接，所述像素电极与所述薄膜晶体管的漏极连接。
例如，在本发明至少一实施例提供的阵列基板中，所述薄膜晶体管的半导体层设置在所述数据线所在层与所述栅线所在层之间，所述半导体层与所述栅线所在层之间设置有栅绝缘层。
例如，在本发明至少一实施例提供的阵列基板中，在所述数据线所在层、所述栅线所在层和所述半导体层上设置有绝缘层。
例如，本发明至少一实施例提供的阵列基板，还包括多个栅极驱动器，其中，所述多个栅极驱动器分别设置在所述多条栅线的两端。
本发明至少一实施例还提供一种显示面板，包括上述任一阵列基板。
本发明至少一实施例还提供一种显示装置，包括上述显示面板。
本发明至少一实施例还提供一种阵列基板的制作方法，包括：提供衬底基板；在所述衬底基板上形成栅线、数据线和公共电极线；其中，所述公共电极线与所述栅线在不同层上形成；所述公共电极线与所述数据线在同一层上形成且相互平行；所述栅线与所述数据线、所述公共电极线相互绝缘且交叉以限定多个亚像素单元。
例如，在本发明至少一实施例提供的制作方法中，所述数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线，在每两列相邻所述亚像素单元中，奇数行所述亚像素单元连接所述第一数据线，且偶数行所述亚像素单元连接所述第二数据线。
例如，本发明至少一实施例提供的制作方法，还包括：形成第一数据线总线和第二数据线总线，其中，所述第一数据线均与所述第一数据线总线连接，所述第二数据线均与所述第二数据线总线连接，且所述第一数据线总线和所述第二数据线总线均与所述栅线平行。
例如，在本发明至少一实施例提供的制作方法中，所述第一数据线总线与所述第二数据线总线在不同层上形成。
例如，本发明至少一实施例提供的制作方法，还包括：形成公共电极线总线，其中，所述公共电极线总线与所述公共电极线在不同层上形成且与所述栅线平行，所述公共电极线均与所述公共电极线总线连接。
例如，在本发明至少一实施例提供的制作方法中，所述公共电极线在所述栅线的上层或下层形成。
例如，本发明至少一实施例提供的制作方法，还包括：在每个所述亚像素单元中形成薄膜晶体管、公共电极和像素电极，其中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述公共电极与所述公共电极线连接，所述像素电极与所述薄膜晶体管的漏极连接。
例如，本发明至少一实施例提供的制作方法，还包括：在所述数据线所在层与所述栅线所在层之间形成薄膜晶体管的半导体层，在所述半导体层与所述栅线所在层之间形成栅绝缘层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种阵列基板的平面示意图；
图2为本发明一实施例提供的一种阵列基板的部分截面结构示意图；
图3为本发明一实施例提供的另一种阵列基板的部分截面结构示意图；
图4为本发明一实施例提供的一种阵列基板的制作方法的流程图；
图5为本发明一实施例的一种阵列基板的制作方法的过程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。 基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，薄膜晶体管阵列基板上平行设置的配线(例如栅线、数据线、公共电极线等)可能由于有机物颗粒、静电、金属残留等造成开路、线间短路等问题，可以先通过检测设备中的线检测传感器(Line Detect Sensor，LDS)进行线扫描，找出发生不良的配线的位置，再通过位置检测传感器(Position Detect Sensor，PDS)对发生不良的线进行扫描找出不良的具体的位置坐标。
在目前的薄膜晶体管阵列基板的设计中，栅线与公共电极线在相同的工艺步骤中形成，且相邻两条信号线(特别是相邻的栅线和公共电极线)之间的间距较小，一般在10μm左右，相邻两条信号线容易发生短路，而目前检测设备的检测精度为28μm，发生短路不良时，检测设备无法检测出发生不良的具体位置。
本发明至少一实施例提供一种阵列基板及其制造方法、显示面板和显示装置，该阵列基板包括衬底基板以及设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线，并且多条公共电极线与多条栅线设置在不同层，多条公共电极线与多条数据线设置在同一层且相互平行，多条栅线与多条数据线、多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
在该阵列基板中，公共电极线与栅线设置在不同层，公共电极线与数据线设置在同一层且相互平行，由此便于对阵列基板的电路进行检测与维修，加强设备的检出能力，从而可以提高产品的良率。
本发明的实施例提供一种阵列基板，图1为本发明一实施例提供的一 种阵列基板的平面示意图，如图1所示，该阵列基板包括衬底基板901以及设置在衬底基板901上的多条彼此平行的栅线1(图1中加粗线所示)、多条彼此平行的数据线2和多条彼此平行的公共电极线3。多条公共电极线3与多条栅线1设置在不同层；多条公共电极线3与多条数据线2设置在同一层且相互平行；多条栅线1与多条数据线2、多条公共电极线3相互绝缘且交叉以限定多个亚像素单元908。由此，多个亚像素单元908按照阵列方式排列。
本发明的实施例中的阵列基板，通过将多条公共电极线3与多条栅线1设置在不同层，多条公共电极线3与多条数据线2设置在同一层且相互平行，从而避免了栅线1与公共电极线3设置在同一层时需要彼此平行布线而易于发生短路的问题，并且，当阵列基板上的信号线出现短路或者断路的问题时，便于对其进行检测与维修，从而提高了产品的良率。
例如，图2为本发明一实施例提供的一种阵列基板的部分截面结构示意图。图2示出了采用底栅型薄膜晶体管的像素结构，但本发明的实施例不限于此，例如像素结构也可以采用顶栅型薄膜晶体管。
在图2所示的实施例中，栅极层902(包括薄膜晶体管的栅极以及与之连接的栅线)形成在衬底基板901上；栅绝缘层903覆盖在栅极层902和衬底基板901上；半导体层904形成在栅绝缘层903上；源漏电极层905形成在栅绝缘层903和半导体层904之上，漏极9051和源极9052彼此间隔开地设置在半导体层904上，数据线与源极9052一体形成。绝缘层906(或钝化层)形成在栅绝缘层903、半导体层904以及源漏电极层905之上；绝缘层906中形成有过孔结构909以暴露出部分漏极9051，像素电极907形成在绝缘层906上，通过过孔结构909与漏极9051电连接。
如图1和图2所示，多条数据线2包括并排设置在每两列相邻亚像素单元908之间的第一数据线21和第二数据线22，且在行方向上第一数据线21与第二数据线22交替设置。在每两列相邻的亚像素单元908中，例如，奇数行亚像素单元连接第一数据线21，偶数行亚像素单元连接第二数据线22。
该阵列基板9还可以包括第一数据线总线、第二数据线总线和公共电极线总线，亚像素单元包括薄膜晶体管、公共电极和像素电极(未示出)。在本发明的实施例中，例如，相对于衬底基板901，公共电极线3设置在 栅线1的上层。
例如，公共电极线3设置在相邻的两列亚像素单元之间，且该两列相邻的亚像素单元共用位于其中间的公共电极线3。
例如，本发明的实施例中的阵列基板还可以包括与栅线1平行设置的第一数据线总线4和第二数据线总线5，例如，所有第一数据线21均与第一数据线总线4连接，所有第二数据线22均与第二数据线总线5连接。例如，在第一数据线21和第二数据线22形成之后，可以利用检测维修设备对第一数据线21和第二数据线22逐一进行扫描。
第一数据线总线4与第二数据线总线5可以设置在相同层或不同层，诸如第一数据线总线4设置在栅线1所在的栅极层902，第二数据线总线5设置在数据线2所在的源漏电极层905，此种情况下第一数据线21通过形成在栅绝缘层903中的过孔结构与第一数据线总线4电连接；或者，第二数据线总线5设置在栅线1所在的栅极层902，第一数据线总线4设置在数据线2所在的源漏电极层905，此种情况下第二数据线22通过形成在栅绝缘层903中的过孔结构与第二数据线总线5电连接。在实际使用中，还可以将第一数据线总线4与第二数据线总线5设置在其他层，在此不再赘述。
例如，本发明的实施例中的阵列基板还可以包括与公共电极线3设置在不同层且与栅线1平行设置的公共电极线总线6，从而使得公共电极线3与栅线1交叉设置，并且公共电极线3均与公共电极线总线6连接，例如公共电极线总线6设置在栅线层902中。在实际使用中，还可以将公共电极线总线6设置在公共电极线3所在层，且与公共电极线3交叉设置。
例如，本发明的实施例的阵列基板还可以包括设置在每个亚像素单元中的薄膜晶体管、公共电极和像素电极。在本发明的实施例中，薄膜晶体管的栅极与栅线1连接，薄膜晶体管的源极与数据线2连接，公共电极与公共电极线3连接，像素电极与薄膜晶体管的漏极连接。该公共电极可以作为存储电极使用，例如，在垂直于衬底基板的方向上，公共电极与像素电极彼此至少部分重叠以形成存储电容；或者，该公共电极可以与像素电极形成控制液晶偏转的电场，例如用于IPS(平面开关)型LCD或ADS(高级超维场转换技术)型LCD。
例如，在数据线2所在层与栅线1所在层之间设置有薄膜晶体管的半导体层904，而薄膜晶体管的栅极可以与栅线1一体形成，薄膜晶体管的源极 与数据线2一体形成。该半导体层904采用半导体材料形成，该半导体材料例如为非晶硅、微晶硅、多晶硅、氧化物半导体等，该氧化物半导体例如可以为IGZO(铟镓锌氧化物)、ZnO(氧化锌)等。半导体层904所在层与薄膜晶体管的栅极和栅线1所在层之间设置有栅绝缘层903，该栅绝缘层903用于避免半导体层904与薄膜晶体管的栅极和栅线1之间导通。
例如，在数据线2所在层、栅线1所在层和半导体层上均设置有绝缘层，该绝缘层通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成。
例如，本发明的实施例中的像素电极可以与栅线1设置在同一层，或者，设置在半导体层904与数据线2所在的源漏电极层905之间，或者，设置在数据线2所在的源漏电极层905与绝缘层906之间，或者，设置在绝缘层906上。像素电极907设置在绝缘层906上(如图2所示)时，在绝缘层906中设置有过孔结构909，像素电极907与数据线2、公共电极线3所在的源漏电极层905中的漏极9051通过该过孔结构909连接。
例如，在本发明的实施例中，阵列基板9还可以包括多个栅极驱动器7，例如GOA(Gate-driver onArray)单元，其中，这些栅极驱动器7可以设置在每条栅线1的一端或两端。如图1所示，多个栅极驱动器7对齐设置在栅线1的两端，且各个栅线1一端设置的栅极驱动器7彼此连接，并通过设置在一个栅极驱动器7一端的信号输入端8向栅极驱动器7输入控制信号等。
在实际应用中，通常在栅线1的两端均设置栅极驱动器7，以避免栅线1过长使得栅极驱动器7施加的信号在栅线1上传输受到阻碍或延迟。
例如，在本发明的实施例中，衬底基板901可以为玻璃基板或塑料基板。
例如，在本发明的实施例中，栅线1、数据线2与公共电极线3分别形成之后，可采用开路检测机对数据线2和公共电极线3进行检测，待检测完成之后，第一数据线总线4、第二数据线总线5和公共电极线总线6可以从阵列基板9上通过切割工艺去除。
例如，图3为本发明一实施例提供的另一种阵列基板的部分截面结构示意图，如图3所示，本发明的实施例中阵列基板中的薄膜晶体管为顶栅型薄膜晶体管。
例如，如图3所示，在衬底基板911上设置缓冲层910，在缓冲层910上设置半导体层914，在半导体层914上依次形成栅绝缘层913、栅极层912和绝缘层916，在绝缘层916上形成源漏电极层915，在源漏电极层915上依次形成绝缘层916和钝化层918，在钝化层918和绝缘层916上形成过孔结构919，像素电极917通过该过孔结构919与源漏电极层915的漏极9151电连接。同样，薄膜晶体管的栅极与栅线连接，源极9152与数据线连接。
例如，本发明的实施例中阵列基板的其他结构的特征，例如，栅线1、数据线2、公共电极线3、半导体层904等可以参照上述相关描述，其技术效果与实现原理相似，在此不再赘述。
本发明的实施例还提供一种显示面板，包括上述任一阵列基板。该显示面板可以是液晶显示面板，还可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板、电子纸显示面板等。
例如，本发明的实施例中的显示面板还包括与阵列基板相对设置的对置基板，显示面板通过阵列基板和对置基板对盒形成，在阵列基板和对置基板对盒后的空腔内填充液晶。该对置基板例如为彩膜基板，可以包括对置衬底基板、黑矩阵以及彩膜单元。
本发明的实施例还提供一种显示装置，包括上述任一显示面板。该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的实施例还提供一种阵列基板的制作方法，图4为本发明一实施例提供的一种阵列基板的制作方法的流程图，如图4所示，该阵列基板的制作方法可以包括如下步骤：
步骤100、提供衬底基板。
步骤101、在衬底基板上形成栅线、数据线和公共电极线。
例如，公共电极线与栅线在不同层上形成，公共电极线与数据线在同一层上形成且相互平行，栅线与数据线、公共电极线相互绝缘且交叉以限定多个亚像素单元。
例如，由于公共电极线与栅线在不同层上形成，且公共电极线与数据线在同一层上形成且相互平行，栅线与数据线、公共电极线相互绝缘且交 叉以限定多个亚像素单元，从而有利于检测阵列基板是否处于短路或断路状态，从而提高了产品的良率。
例如，图5为本发明的另一实施例提供的阵列基板的制作方法的流程示意图，如图5所示，该阵列基板的制作方法包括如下步骤：
步骤200、提供衬底基板。
例如，该衬底基板可以为玻璃基板、石英基板等。
步骤201、在衬底基板上形成栅线以及平行于该栅线的第一数据线总线和公共电极线总线。
例如，在整个衬底基板上沉积一层均匀的金属薄膜，采用构图工艺形成栅线、第一数据线总线和公共电极线总线，该构图工艺包括在金属薄膜上均匀地涂覆一层光刻胶，通过曝光、显影、刻蚀、剥离光刻胶等工序，形成栅线以及平行于该栅线的第一数据线总线和公共电极线总线的图案。例如，该金属薄膜可以采用铝、铝合金、铜、铜合金等金属材料制备。
步骤202、在栅线、第一数据线总线和公共电极线总线上形成栅绝缘层和半导体层。
例如，该半导体层的材料，例如为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物。
在该步骤中，还可以通过构图工艺在栅绝缘层中形成过孔结构，以暴露出部分第一数据线总线和部分公共电极线总线。
步骤203、在半导体层上形成源漏电极层，并构造成并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线、平行于第一数据线和第二数据线的公共电极线、以及平行于栅线的第二数据线总线。栅线与数据线、公共电极线相互绝缘且交叉以限定多个亚像素单元。
在每两列相邻亚像素单元中，奇数行亚像素单元连接第一数据线，且偶数行亚像素单元连接第二数据线。第一数据线与第一数据线总线通过形成在栅绝缘层中的过孔结构连接，第二数据线均与第二数据线总线连接，公共电极线与公共电极线总线通过形成在栅绝缘层中的过孔结构连接。
例如，在半导体层上镀上一层金属薄膜，参考步骤202，同样通过构图工艺形成包括第一数据线和第二数据线，以及公共电极线和第二数据线总线的电极图案。同样，例如该金属薄膜可以采用铝、铝合金、铜、铜合金等金属材料制备。
步骤204、在数据线和公共电极线所在层上形成绝缘层。
例如，在整个源漏电极层上镀上一层绝缘材料，该绝缘材料包括无机绝缘材料例如氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiOxNy)等，或者有机绝缘材料。
在该步骤中，还可以通过构图工艺在绝缘层中形成过孔结构，以暴露出部分漏极。
步骤205、在绝缘层上沉积透明导电薄膜，并对其进行构图以形成像素电极。
例如，在绝缘层上沉积一层氧化铟锡(ITO)薄膜，然后通过构图工艺形成像素电极，该像素电极通过绝缘层中的过孔结构与漏极电连接。
对于制备IPS类型的阵列基板的情形，每个亚像素单元中，像素电极和公共电极可以形成在同一层，例如都形成梳状电极。在上述步骤204中，还可以通过构图工艺在绝缘层中形成过孔结构，以暴露出部分公共电极线；在上述步骤205中，形成像素电极的同时还形成公共电极，该公共电极通过绝缘层中的过孔结构与公共电极线电连接。
在本发明的实施例中，在每个亚像素单元中形成薄膜晶体管、公共电极和像素电极，其中，薄膜晶体管的栅极与栅线连接，薄膜晶体管的源极与数据线连接，公共电极与公共电极线连接，像素电极与薄膜晶体管的漏极连接。
本发明的实施例提供的一种阵列基板及其制造方法、显示面板和显示装置至少具有以下一项有益效果：
(1)在该阵列基板中，公共电极线与栅线设置在不同层，公共电极线与数据线设置在同一层且相互平行，这样可以避免平行配线易于短路的问题；
(2)便于对阵列基板的电路进行检测与维修，加强了设备的检出能力；
(3)提高了产品的良率以实现收益最大化。
有以下几点需要说明：
(1)本发明实施例的附图只涉及到本发明的实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或区 域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年9月5日递交的中国专利申请第201610802113.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，
    设置在所述衬底基板上的多条栅线、多条数据线和多条公共电极线；其中，
    所述多条公共电极线与所述多条栅线设置在不同层；
    所述多条公共电极线与所述多条数据线设置在同一层且相互平行；
    所述多条栅线与所述多条数据线、所述多条公共电极线相互绝缘且交叉以限定多个亚像素单元。
  2. 根据权利要求1所述的阵列基板，其中，所述多条数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线，在每两列相邻所述亚像素单元中，奇数行所述亚像素单元连接所述第一数据线，且偶数行所述亚像素单元连接所述第二数据线。
  3. 根据权利要求2所述的阵列基板，还包括：与所述栅线平行设置的第一数据线总线和第二数据线总线，
    其中，所述第一数据线均与所述第一数据线总线连接，所述第二数据线均与所述第二数据线总线连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第一数据线总线与所述第二数据线总线设置在不同层。
  5. 根据权利要求1-4中任一项所述的阵列基板，还包括：与所述公共电极线设置在不同层且与所述栅线平行设置的公共电极线总线，
    其中，所述公共电极线均与所述公共电极线总线连接。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述公共电极线设置在所述栅线的上层或下层。
  7. 根据权利要求6所述的阵列基板，还包括：设置在每个所述亚像素单元中的薄膜晶体管、公共电极和像素电极，
    其中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述公共电极与所述公共电极线连接，所述像素电极与所述薄膜晶体管的漏极连接。
  8. 根据权利要求7所述的阵列基板，其中，所述薄膜晶体管的半导体 层在所述数据线所在层与所述栅线所在层之间，所述半导体层与所述栅线所在层之间设置有栅绝缘层。
  9. 根据权利要求8所述的阵列基板，其中，在所述数据线所在层、所述栅线所在层和所述半导体层上设置有绝缘层。
  10. 根据权利要求9所述的阵列基板，还包括多个栅极驱动器，其中，所述多个栅极驱动器分别设置在所述多条栅线的两端。
  11. 一种显示面板，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种显示装置，包括权利要求11中的显示面板。
  13. 一种阵列基板的制作方法，包括：
    提供衬底基板；
    在所述衬底基板上形成栅线、数据线和公共电极线；其中，
    所述公共电极线与所述栅线在不同层上形成；
    所述公共电极线与所述数据线在同一层上形成且相互平行；
    所述栅线与所述数据线、所述公共电极线相互绝缘且交叉以限定多个亚像素单元。
  14. 根据权利要求13所述的制作方法，其中，所述数据线包括并排设置在每两列相邻所述亚像素单元之间的第一数据线和第二数据线，在每两列相邻所述亚像素单元中，奇数行所述亚像素单元连接所述第一数据线，且偶数行所述亚像素单元连接所述第二数据线。
  15. 根据权利要求14所述的制作方法，还包括：形成第一数据线总线和第二数据线总线，其中，所述第一数据线均与所述第一数据线总线连接，所述第二数据线均与所述第二数据线总线连接，且所述第一数据线总线和所述第二数据线总线均与所述栅线平行。
  16. 根据权利要求15所述的制作方法，其中，所述第一数据线总线与所述第二数据线总线在不同层上形成。
  17. 根据权利要求13-16中任一项所述的制作方法，还包括：形成公共电极线总线，其中，所述公共电极线总线与所述公共电极线在不同层上形成且与所述栅线平行，所述公共电极线均与所述公共电极线总线连接。
  18. 根据权利要求13-17中任一项所述的制作方法，其中，所述公共电极线在所述栅线的上层或下层形成。
  19. 根据权利要求13-18中任一项所述的制作方法，还包括：在每个 所述亚像素单元中形成薄膜晶体管、公共电极和像素电极，其中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述公共电极与所述公共电极线连接，所述像素电极与所述薄膜晶体管的漏极连接。
  20. 根据权利要求13-19中任一项所述的制作方法，还包括：在所述数据线所在层与所述栅线所在层之间形成薄膜晶体管的半导体层，在所述半导体层与所述栅线所在层之间形成栅绝缘层。
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