WO2021062640A1 - 电子基板及其制作方法、显示面板 - Google Patents

电子基板及其制作方法、显示面板 Download PDF

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Publication number
WO2021062640A1
WO2021062640A1 PCT/CN2019/109479 CN2019109479W WO2021062640A1 WO 2021062640 A1 WO2021062640 A1 WO 2021062640A1 CN 2019109479 W CN2019109479 W CN 2019109479W WO 2021062640 A1 WO2021062640 A1 WO 2021062640A1
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Prior art keywords
detection
cutting surface
lines
layer
electronic substrate
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PCT/CN2019/109479
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English (en)
French (fr)
Inventor
肖云升
青海刚
董向丹
刘庭良
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/963,776 priority Critical patent/US11430854B2/en
Priority to PCT/CN2019/109479 priority patent/WO2021062640A1/zh
Priority to EP19945397.8A priority patent/EP4040171A4/en
Priority to CN201980001890.9A priority patent/CN113287028B/zh
Publication of WO2021062640A1 publication Critical patent/WO2021062640A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the embodiments of the present disclosure relate to an electronic substrate, a manufacturing method thereof, and a display panel.
  • OLED organic light-emitting diode
  • At least one embodiment of the present disclosure provides an electronic substrate including a base substrate, the base substrate including a display area and a peripheral area located outside the display area.
  • the electronic substrate further includes a plurality of sub-pixels and a plurality of data lines in the display area, and a plurality of signal input pads and a plurality of first detection lines and a plurality of second detection lines in the peripheral area.
  • the plurality of data lines are configured to provide data signals for the plurality of sub-pixels; the plurality of signal input pads are electrically connected to the plurality of data lines; the plurality of first detection lines and the plurality of second detection lines It is located on a side of the plurality of signal input pads far away from the display area, and is electrically connected to the plurality of signal input pads.
  • the plurality of first detection lines are made of non-metallic conductive material, the plurality of second detection lines are made of metal conductive material, and at least one of the first detection lines is arranged between every two adjacent second detection lines;
  • the electronic substrate includes a cutting surface, the first detection line includes a first cutting surface, the first cutting surface is a first part of the cutting surface of the electronic substrate, and the first cutting surface is the non-metallic Cut surface of conductive material.
  • the material of the first detection line is a conductive semiconductor material.
  • the material of the first detection line includes silicon or conductive metal oxide.
  • the material of the first detection line includes low temperature polysilicon.
  • the second detection line includes a second cutting surface, the second cutting surface is the second part of the cutting surface of the electronic substrate, and the second cutting surface is the metal conductive material cut surface.
  • the base substrate includes a third cutting surface
  • the third cutting surface is a third part of the cutting surface of the electronic substrate
  • the third cutting surface is located on the plurality of first detection lines
  • the plurality of second detection lines are far away from the side of the display area, and are flush with the first cutting surface and the second cutting surface.
  • At least one of the plurality of sub-pixels includes a transistor and a storage capacitor; the transistor includes an active layer, a first gate insulating layer, a gate, and a second gate sequentially stacked on the base substrate. An insulating layer, an interlayer insulating layer, and a source/drain electrode layer.
  • the active layer is located on the side of the gate close to the base substrate;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode and the gate electrode are arranged in the same layer, and the second capacitor electrode is located between the second gate insulating layer and the interlayer insulating layer.
  • the first detection line and the active layer are provided in the same layer.
  • the second detection line and the first capacitance electrode or the second capacitance electrode are provided in the same layer.
  • the multiple signal input pads and the source and drain electrode layers are arranged in the same layer.
  • the orthographic projection of the first inspection line on the base substrate and the orthographic projection of the second inspection line on the base substrate are alternately arranged one by one.
  • At least one embodiment of the present disclosure further provides a display panel including the above-mentioned electronic substrate.
  • At least one embodiment of the present disclosure further provides a method for manufacturing an electronic substrate, including: forming a plurality of sub-pixels and a plurality of data lines in a display area on a base substrate, and the plurality of data lines are configured as the plurality of sub-pixels.
  • the pixels provide data signals; a plurality of signal input pads are formed in the peripheral area outside the display area of the base substrate, and the plurality of signal input pads are connected to the plurality of data lines; and in the peripheral area A plurality of first detection lines and a plurality of second detection lines are formed, and the plurality of first detection lines and the plurality of second detection lines are located on the side of the plurality of signal input pads away from the display area, and are connected to the The multiple signal input pads are electrically connected.
  • the plurality of first detection lines are made of non-metallic conductive material, the plurality of second detection lines are made of metal conductive material, and at least one of the first detection lines is arranged between every two adjacent second detection lines;
  • the electronic substrate includes a cutting surface, the first detection line includes a first cutting surface, the first cutting surface is a first part of the cutting surface of the electronic substrate, and the first cutting surface is the non-metallic Cut surface of conductive material.
  • the manufacturing method further includes: providing a detection circuit in the detection area outside the display area and the peripheral area, wherein the plurality of first detection lines and the plurality of second detection lines also extend To the detection area so as to be electrically connected to a detection circuit; and detect the plurality of data lines through the detection circuit, the first detection line, and the plurality of second detection lines.
  • the manufacturing method further includes: cutting the first detection line and the second detection line to separate the detection area from the peripheral area and the display area, and form the second detection line. One cutting surface.
  • cutting the first detection line and the second detection line is still forming a second cutting surface of the second detection line, and the second cutting surface is a cutting surface of the metal conductive material .
  • forming the first detection line includes forming a semiconductor material layer and performing a patterning process and a conductive process on the semiconductor material layer to form the plurality of first detection lines.
  • the material of the semiconductor material layer includes silicon or conductive metal oxide.
  • forming at least one of the plurality of sub-pixels includes forming a transistor and a storage capacitor, including: sequentially forming the active layer, the first gate insulating layer, the gate, and the second layer on the base substrate.
  • Two gate insulating layers, interlayer insulating layers, and source and drain electrode layers are formed in the same patterning process as the first capacitor electrode and the gate of the storage capacitor, and the second capacitor electrode is formed on the second gate Between the insulating layer and the interlayer insulating layer.
  • the plurality of first detection lines and the active layer are formed in the same patterning process.
  • FIG. 1 is one of the schematic plan views of an electronic substrate provided by some embodiments of the present disclosure
  • FIG 2 is the second schematic plan view of an electronic substrate provided by some embodiments of the disclosure.
  • 3A is one of the cross-sectional views of the electronic substrate provided by some embodiments of the present disclosure.
  • 3B is the second cross-sectional view of the electronic substrate provided by some embodiments of the present disclosure.
  • 4A is the third cross-sectional view of the electronic substrate provided by some embodiments of the present disclosure.
  • 4B is the fourth cross-sectional view of the electronic substrate provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of an electronic substrate provided by some embodiments of the disclosure.
  • FIG. 6 is a flowchart of a manufacturing method of an electronic substrate provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of an electronic manufacturing method provided by some embodiments of the disclosure.
  • the manufacturing process of the display panel it is necessary to perform poor detection on the formed signal line, for example, to detect whether there is a short circuit or open circuit on the signal line.
  • a detection area is formed outside the panel area of the substrate, and the detection circuit in the detection area is electrically connected to the signal line in the panel area through the detection line to detect the signal line and repair the substrate in time. The bad. After the inspection is completed, the inspection area will be cut to form a panel.
  • the embodiments of the present disclosure provide an electronic substrate that uses a non-metallic conductive material to form the above-mentioned detection line or a part of the detection line, so as to avoid a short circuit between adjacent detection lines caused by metal debris in the cutting process.
  • FIG. 1 shows one of the schematic plan views of an electronic substrate provided by an embodiment of the present disclosure.
  • the electronic substrate is an electronic substrate (for example, an array substrate) for a display panel, but the embodiment of the present disclosure does not limit this .
  • FIG. 1 shows the situation of the electronic substrate in the detection process.
  • the base substrate 301 includes a display area 21, a peripheral area (non-display area) 22 outside the display area 21, and a detection area 23.
  • the detection area 23 Located on the side of the peripheral area 22 away from the display area 21, the display area 21 and the peripheral area 22 correspond to the electronic substrate 20, and the inspection area 23 is cut off along the cutting line 200 on the side of the peripheral area 22 away from the display area 21 after the inspection is completed Thus, the electronic substrate 20 is formed.
  • the display area 21 includes at least one signal line, and the signal line may be a power line, a gate line, a data line, or the like. As shown in FIG. 1, the display area 21 includes a plurality of gate lines 212, a plurality of data lines 213, and a plurality of sub-pixels 210 arranged in an array.
  • the gate line is configured to provide gate signals for the plurality of sub-pixels 210
  • the data line is configured to provide data signals for the plurality of sub-pixels.
  • the electronic substrate is an array substrate applied to an organic light emitting diode (OLED) display panel.
  • the electronic substrate may also be an array substrate applied to a liquid crystal display panel and a quantum dot light emitting diode display panel, which is not limited in the embodiments of the present disclosure.
  • Each sub-pixel 210 includes a light-emitting element (OLED) and a pixel circuit that drives the light-emitting element to emit light.
  • the pixel circuit is electrically connected to the corresponding gate line 212 and data line 213, respectively.
  • the pixel circuit includes a conventional 2T1C (that is, two transistors and a capacitor) pixel circuit, 4T2C, 5T1C, 7T1C and other nTmC (n, m are positive integers) pixel circuits, and in different embodiments, the pixel circuit can also It further includes a compensation circuit.
  • the compensation circuit includes an internal compensation circuit or an external compensation circuit.
  • the compensation circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may also include a reset circuit, a light emission control circuit, a detection circuit, etc., as required.
  • the electronic substrate 20 further includes a gate driving circuit 240 located in the peripheral area 22, and the gate driving circuit 240 is, for example, a GOA structure (gate on array).
  • the gate driving circuit 240 is connected to the gate line 212 and provides gate driving signals for the sub-pixels 210 of the display area 21 through the gate line 212.
  • the electronic substrate 20 may further include a first power line 211 and a second power line 215 configured to provide the sub-pixel 210 with a first power voltage and a second power voltage, respectively.
  • the first power line 211 is located in the display area 21; the second power line 215 is located in the peripheral area 22, and the second power line 215 may have a U-shaped structure surrounding the display area 21.
  • the first power supply line 211 is configured to provide a high power supply voltage VDD
  • the second power supply line 215 is configured to provide a low power supply voltage VSS.
  • a power bus line 216 connected to a plurality of first power lines 211.
  • the detection area 23 includes a detection circuit, which is connected to the signal line or circuit in the display area 21 and the peripheral area 22 through the detection line to perform defective detection (such as detecting a short circuit or open circuit on the signal line), so as to detect problems
  • the electronic substrate can be inspected in time.
  • the detection circuit 230 includes a shorting bar, a switching element, and the like.
  • FIG. 1 exemplarily shows the data line detection circuit 230 in the detection area 23, and the data detection circuit 230 is configured to be electrically connected to the data line 213 to detect the data line 213.
  • the electronic substrate 20 further includes a plurality of first detection lines 231 and a plurality of second detection lines 232, the first detection lines 231 and the second detection lines 232 are located in the peripheral area 22, one end of which is electrically connected to the data line 213, and the other end extends
  • the detection area 23 is electrically connected to the data line detection circuit 230, thereby electrically connecting the data line 213 and the data line detection circuit 230.
  • the following exemplarily describes the technical solutions provided by the embodiments of the present disclosure through the first detection line and the second detection line used to detect the data line. This is not a limitation of the present disclosure, and the technical solutions provided by the embodiments of the present disclosure are also applicable. For other detection lines.
  • the data line 213 may be directly electrically connected to the detection line, or may be electrically connected to the detection line through other structures.
  • FIG. 1 shows an example in which the data line 213 is connected to the detection line through a signal input pad.
  • the electronic substrate 20 further includes a plurality of signal input pads 220 located in the peripheral area 22.
  • the plurality of signal input pads 220 are located on the side of the multiple detection lines close to the display area 21, and are connected to the multiple data lines respectively.
  • 213 and multiple detection lines are electrically connected; for example, the signal input pad 220 is a bonding pad, which is used for bonding and connecting with an external circuit (for example, an IC circuit board) to receive a data driving signal.
  • the plurality of signal input pads 220 are electrically connected to the plurality of data lines 213 in a one-to-one correspondence.
  • a plurality of data lines 213 are electrically connected to a plurality of signal input pads 220 in a one-to-one correspondence through a plurality of data line lead wires 221.
  • the multiple data lines may also be electrically connected to multiple signal input pads 220 through a multiplexing circuit (MUX) to reduce the number and distribution density of the signal input pads 220; one signal input pad 220 corresponds to Multiple (for example, 2 or 3) data lines 213 are connected.
  • MUX multiplexing circuit
  • the plurality of signal input pads 220 are electrically connected to a plurality of detection lines (including the first detection line 231 and the second detection line 232) in a one-to-one correspondence.
  • FIG. 1 also exemplarily shows the detection electrodes 241, 261, 251, and 271 electrically connected to the second power line 215, the gate driving circuit 240, the power bus 216, and the data line detection circuit 230, respectively.
  • the first detection line 231 and the second detection line 232 are cut together with the base substrate of the electronic substrate, so one end of the first detection line 231 and the second detection line 232 is connected to the edge of the electronic substrate 20 ( That is, the cutting position) is flush.
  • the first detection line 231 includes the first cutting surface
  • the second detection line 232 includes the second detection line.
  • Cutting surface, the base substrate 301 includes a third cutting surface, the first cutting surface, the second cutting surface, and the third cutting surface are all part of the cutting surface of the electronic substrate, and the first cutting surface and the second cutting surface are all the same as those of the electronic substrate.
  • the third cutting surface of the base substrate 301 is flush.
  • the material of the first detection line 231 is a conductive semiconductor material, such as a doped semiconductor material.
  • the material of the first detection line 231 includes silicon (for example, low-temperature polysilicon) or conductive metal oxide.
  • the material of the first detection line 231 includes conductive materials obtained by conducting metal oxide semiconductor materials, such as heavily doped indium tin oxide (IGZO), indium zinc oxide (IZO), and zinc oxide (ZnO). , Zinc Aluminum Oxide (AZO), etc.
  • IGZO heavily doped indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO Zinc Aluminum Oxide
  • the first detection line 231 can be formed in the same layer with the active layer of a certain transistor in the pixel of the display area in the same patterning process, so that the process cost can be saved.
  • the transistor may be a switching transistor, a driving transistor, etc. in a pixel circuit.
  • the material of the second detection line 232 is a metal conductive material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W ), titanium (Ti) and an alloy material combined with the above metals.
  • a metal conductive material such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W ), titanium (Ti) and an alloy material combined with the above metals.
  • the plurality of first detection lines 231 are made of non-metallic conductive material
  • the plurality of second detection lines 232 are made of metal conductive material
  • at least one first detection line 213 is provided between every two adjacent second detection lines 232.
  • a plurality of first detection lines 231 and a plurality of second detection lines 232 are alternately arranged one by one in a direction parallel to the surface of the electronic substrate, and the orthographic projection of the first detection line 231 on the base substrate 301 is the same as the second detection line.
  • the orthographic projections of the lines 232 on the base substrate 301 are alternately arranged one by one (refer to FIGS. 4A and 4B below).
  • the multiple data lines 213 in the display area 21 are alternately electrically connected to the first detection line 231 and the second detection line 232 through the data line lead-out line 221.
  • multiple first detection lines 231 may also be arranged between two adjacent second detection lines 232 to further increase the distance between the metal wires to reduce the risk of short circuit.
  • the embodiments of the present disclosure do not limit this.
  • first detection line 231 made of non-metallic material is provided between every two adjacent second detection lines 232, even if the material of the second detection line 232 is metal, the distance between them is different from that of the first detection line 232.
  • the distance between the line 231 and the second detection line 232 becomes larger than that, that is, compared to the case where the first detection line 231 and the second detection line 232 are made of metal materials, the distance between adjacent metal lines becomes larger. Large, it can also effectively reduce the risk of short circuit during cutting.
  • the first detection line 231 and the second detection line 232 may be located on different layers, which increases the distance between the first detection line 231 and the second detection line 232, and can further reduce the risk of short circuit during cutting.
  • the distribution density of the detection lines can be reduced, and the distance between the detection lines can be increased, thereby further reducing the risk of short circuits.
  • the area occupied by the detection lines on the substrate can be further saved, which is beneficial to wiring.
  • FIGS. 4A and 4B respectively show a cross-sectional view of FIG. 2 along the section lines II' and I-II
  • FIGS. 4A and 4B show different examples of a cross-sectional view of the electronic substrate shown in FIG. 1 along the cutting line 200
  • the electronic substrate as an organic light emitting diode display substrate as an example, the electronic substrate provided by the embodiment of the present disclosure will be exemplarily described in conjunction with FIGS. 2, 3A-3B, and 4A-4B.
  • Each pixel 210 in the display area includes at least one light-emitting element (for example, an organic light-emitting diode) 203 and a pixel circuit connected thereto, and the light-emitting element emits light under the driving of the pixel circuit.
  • the pixel circuit includes a conventional OLED pixel drive circuit, such as a switch transistor, a drive transistor, a storage capacitor, etc., or may further include a reset transistor, a light emission control transistor, etc.
  • the embodiment of the present disclosure does not limit the specific structure of the pixel circuit.
  • FIG. 3A only shows the transistor 201 and the storage capacitor 202 directly connected to the light-emitting element in the pixel circuit.
  • the transistor 201 may be a driving transistor configured to work in a saturated state and control the magnitude of the current for driving the light-emitting element 203 to emit light.
  • the transistor 201 may also be a light-emission control transistor, which is used to control whether a current for driving the light-emitting element 203 to emit light flows. The embodiment of the present disclosure does not limit this.
  • the transistor 201, the storage capacitor 202, and the light-emitting element 203 are located on a base substrate 301.
  • the base substrate 301 is a flexible substrate, and the material of the flexible substrate is, for example, polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, or polyacrylate. , Polyetherimide, Polyethersulfone, etc.
  • the electronic substrate may further include a buffer layer 302 disposed between the base substrate 301 and the pixel circuit.
  • the buffer layer 302 can prevent moisture and/or oxygen from penetrating through the base substrate 301 into the pixel circuit and causing corrosion, and can also help provide a flat surface for forming the pixel circuit, for example.
  • the material of the buffer layer 302 may be silicon nitride, silicon oxide, or silicon oxynitride.
  • the buffer layer may also include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.
  • the transistor 201 includes an active layer 121, a gate 122, a first gate insulating layer 133, and a source-drain electrode layer (including a source 123 and a drain 124).
  • the active layer 121 includes a channel region and a source region and a drain region located on opposite sides of the channel region.
  • the storage capacitor 202 includes a first capacitor electrode 202a, a second gate insulating layer 134, and a second capacitor electrode 202b.
  • the first capacitor electrode 202a of the storage capacitor 202 and the gate 122 of the transistor 201 are arranged in the same layer.
  • “same layer arrangement” in the embodiments of the present disclosure means that multiple layer structures are formed from the same material layer through the same or different processes, and are not necessarily located on the same level, or have the same height or thickness.
  • source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable, so the two can be interchanged as needed .
  • the transistor 201 is a top-gate type, but the embodiments of the present disclosure are not limited to the specific type of the transistor.
  • the transistor can also be a bottom-gate type or a double-gate type. And when the transistors are of different types, the stacked structure on the base substrate is adjusted accordingly to be different from each other.
  • the transistor 201 is, for example, a thin film transistor, and its active layer 121 may be amorphous silicon, polysilicon (such as low-temperature polysilicon or high-temperature polysilicon), oxide semiconductor (such as IGZO), etc., and the transistor 201 may be N-type or P-type.
  • the light emitting element 203 includes a first electrode 127, a second electrode 129, and a light emitting layer 128 disposed between the first electrode 127 and the second electrode 129, wherein the first electrode 127 is electrically connected to the drain 124 of the transistor 201.
  • the first electrode 127 is a pixel electrode
  • the second electrode 129 is a common electrode.
  • One of the first electrode 127 and the second electrode 129 is an anode, and the other is a cathode; for example, the first electrode 127 is an anode, and the second electrode 129 is a cathode.
  • the light-emitting element 203 may include at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like in addition to the light emitting layer 128.
  • the light-emitting element 203 may have a top-emission, bottom-emission, or double-emission structure.
  • the light-emitting element 203 has a top-emitting structure
  • the first electrode 127 is reflective and the second electrode 129 is transmissive or semi-transmissive.
  • the first electrode 127 is a transparent conductive oxide material such as indium tin oxide (ITO).
  • the first electrode 127 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminate structure;
  • the second electrode 129 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the first detection line 231 and the active layer 121 of the transistor 201 are located in the same layer, and both can be formed from the same semiconductor material layer through the same patterning process. For example, after the semiconductor material layer undergoes a patterning process, at least a portion of the semiconductor material layer corresponding to the first detection line is conducted to form the first detection line.
  • the semiconductor pattern corresponding to the first detection line can be conducted (such as Figure 7);
  • the portion corresponding to the first detection line can be separately conductive, such as laser annealing, ion doping, plasma Surface treatment, etc.
  • the signal input pad 220 and the conductive layer of the topmost layer (farthest away from the base substrate 301) below the light-emitting element in the display area 21 are arranged in the same layer to facilitate the subsequent bonding process.
  • the signal input pad 220 and the source and drain electrode layers of the transistor 201 are located in the same layer, and both can be formed of the same conductive material through the same patterning process.
  • the second detection line 232 can also be provided in the same layer as the conductive layer in the display area 21 to save process.
  • the second detection line 232 is arranged in the same layer as the gate 122 of the transistor 201 and the first capacitor electrode 202a of the storage capacitor 202.
  • the material of the first detection line 231 is a non-metallic conductive material, this is compared with the case where the first detection line 231 and the second detection line 232 are both metal conductor materials. This setting increases the distance between adjacent metal detection lines and effectively reduces the risk of short circuits.
  • the second detection line 232 and the second capacitor electrode 202b of the storage capacitor 202 are arranged in the same layer. Since the layer where the second capacitor electrode 202b is located is farther away from the layer where the gate 122 is located, that is, this arrangement increases the distance between the first detection line 231 and the second detection line 232, Further reduce the risk of short circuit.
  • the detection lines can also be distributed in three or more layers, thereby further reducing the distribution density of the detection lines and reducing the risk of short circuits.
  • first cutting surface 411 and the second cutting surface 412 are both perpendicular to the base substrate 301.
  • the first cutting surface 411 is a cutting surface of a non-metal conductive material
  • the second cutting surface 412 is a cutting surface of a metal conductive material.
  • the data line lead-out lines 221 may also be distributed in multiple layers to reduce the distribution density, thereby reducing the risk of short circuits.
  • a plurality of data line lead-out lines 221 may be distributed on the conductive layer where the gate 122 is located and the conductive layer where the second capacitor electrode 202b is located.
  • the data line lead-out lines 221 are alternately arranged in the same layer as the gate electrode 122 and the second capacitor electrode 202b.
  • the electronic substrate 20 further includes an interlayer insulating layer 135 disposed on the first detection line 231 and the second detection line 232.
  • the signal input pad 220 is electrically connected to the first detection line 231 through the first via 401 that penetrates the first gate insulating layer 133, the second gate insulating layer 134, and the interlayer insulating layer 135, and is electrically connected to the first detection line 231 through the second
  • the second via 402 of the gate insulating layer 134 and the interlayer insulating layer 135 is electrically connected to the data line lead line 221.
  • the material of the interlayer insulating layer 135 is an inorganic insulating material, which is denser than an organic insulating material, and can effectively prevent the first detection line 231 and the second detection line 232 from being corroded due to air penetration.
  • the material of the interlayer insulating layer 135 is silicon oxide, silicon nitride, or silicon oxynitride, or metal oxynitride insulating materials such as aluminum oxide and titanium nitride.
  • the electronic substrate 20 further includes a planarization layer 170 disposed on the source and drain electrode layers of the transistor 20, and the planarization layer provides a substantially flat surface for the formation of the light-emitting element 203.
  • the planarization layer 170 is made of an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and other organic insulating materials.
  • the first electrode 127 of the light-emitting element 203 is electrically connected to the drain 124 of the transistor 201 through the via hole in the planarization layer 170.
  • the planarization layer 170 exposes the signal input pad 220 to facilitate the bonding connection between the signal input pad 220 and an external circuit (such as a flexible circuit board).
  • a pixel defining layer 180 is provided on the planarization layer 170 and the first electrode 127, and the pixel defining layer 180 forms an opening at a position corresponding to the first electrode 127 to at least partially expose the first electrode 127, in the opening
  • the light-emitting layer 128 is formed.
  • a second electrode 129 is formed on the light-emitting layer 128 and the pixel defining layer 180.
  • the material of the planarization layer 170 and the pixel defining layer 180 is an organic material or an inorganic material, for example, the organic material is a resin such as polyimide (PI).
  • PI polyimide
  • At least one embodiment of the present disclosure further provides a display panel 30 including the electronic substrate 20 described above.
  • the display panel is an OLED display panel, and correspondingly, the electronic substrate 20 included therein is an OLED substrate.
  • the display panel 30 further includes an encapsulation layer 501 and a cover plate 502 disposed on the electronic substrate 20.
  • the encapsulation layer 501 is configured to seal the light-emitting element 203 to prevent external moisture and oxygen from entering the light-emitting element and the driving circuit. Penetration caused damage to the device.
  • the encapsulation layer 501 includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked.
  • a water-absorbing layer (not shown) may be further provided between the encapsulation layer 501 and the electronic substrate 20, configured to absorb residual water vapor or sol of the light-emitting element 203 in the preliminary manufacturing process.
  • the cover plate 502 is, for example, a glass cover plate.
  • the cover plate 502 and the packaging layer 501 may be an integral structure.
  • At least one embodiment of the present disclosure further provides a display device including the above-mentioned electronic substrate or display panel.
  • the display device can be, for example, a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a notebook computer, a navigator, and other products or components with any display function.
  • At least one embodiment of the present disclosure further provides a method for manufacturing the electronic substrate described above.
  • the manufacturing method at least includes: forming a plurality of sub-pixels and a plurality of data lines in a display area on a base substrate, and the plurality of data lines are configured to The plurality of sub-pixels provide data signals, a plurality of signal input pads are formed in the peripheral area outside the display area of the base substrate, the plurality of signal input pads are connected to the plurality of data lines, and the A plurality of first detection lines and a plurality of second detection lines are formed in the peripheral area, and the plurality of first detection lines and the plurality of second detection lines are located on the side of the plurality of signal input pads away from the display area, and The multiple signal input pads are electrically connected.
  • the plurality of first detection lines are made of non-metallic conductive material, the plurality of second detection lines are made of metal conductive material, and at least one of the first detection lines is arranged between every two adjacent second detection lines;
  • the electronic substrate includes a cutting surface, the first detection line includes a first cutting surface, the first cutting surface is a first part of the cutting surface of the electronic substrate, and the first cutting surface is the non-metallic Cut surface of conductive material.
  • the manufacturing method further includes: providing a detection circuit in the detection area outside the display area and the peripheral area, wherein the plurality of first detection lines and the plurality of second detection lines also extend To the detection area so as to be electrically connected to a detection circuit; and detect the plurality of data lines through the detection circuit, the first detection line, and the plurality of second detection lines.
  • the manufacturing method further includes: cutting the first detection line and the second detection line to separate the detection area from the peripheral area and the display area, and form the second detection line. One cutting surface.
  • cutting the first detection line and the second detection line is still forming a second cutting surface of the second detection line, and the second cutting surface is a cutting surface of the metal conductive material .
  • forming the first detection line includes forming a semiconductor material layer and performing a patterning process and a conductive process on the semiconductor material layer to form the plurality of first detection lines.
  • the material of the semiconductor material layer includes silicon or conductive metal oxide.
  • forming at least one of the plurality of sub-pixels includes forming a transistor and a storage capacitor, including: sequentially forming the active layer, the first gate insulating layer, the gate, and the second layer on the base substrate.
  • Two gate insulating layers, interlayer insulating layers, and source and drain electrode layers are formed in the same patterning process as the first capacitor electrode and the gate of the storage capacitor, and the second capacitor electrode is formed on the second gate Between the insulating layer and the interlayer insulating layer.
  • the plurality of first detection lines and the active layer are formed in the same patterning process.
  • FIG. 6 is a flowchart of a method for manufacturing an array substrate provided by at least one embodiment of the present disclosure. The following will describe the electronic substrate provided by this embodiment in conjunction with FIG. 1-2, FIG. 3A-3B, FIG. 4A-4B, and FIG. The production method is exemplified.
  • the manufacturing method includes the following steps S601-S607.
  • Step S601 forming a buffer layer 302 on the base substrate 301.
  • the base substrate 301 includes a display area 21, a peripheral area 22 and a detection area 23.
  • the base substrate 301 may be a rigid substrate, such as a glass substrate, a silicon substrate, or a stainless steel substrate.
  • the base substrate 301 may also be an organic flexible substrate, for example, including polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, and polyether. Imide, polyethersulfone, etc.
  • the buffer layer 302 may include inorganic insulating materials, such as silicon oxides such as silicon oxide, silicon nitride, silicon oxynitride, etc., silicon nitrides or silicon oxynitrides, or metal oxynitrides such as aluminum oxide and titanium nitride. ⁇ Insulation material.
  • the buffer layer 302 may be formed by a process such as chemical vapor deposition process.
  • Step S602 A semiconductor material layer is formed on the buffer layer, and a first patterning process is performed on the semiconductor material layer to form an active layer of the transistor in the display area, and a semiconductor pattern corresponding to the first detection line 231 is formed in the peripheral area .
  • the semiconductor pattern also extends to the detection area 23 for electrical connection with a detection circuit to be formed or provided in the detection area.
  • the material of the semiconductor material layer may be a simple semiconductor material or a compound semiconductor material.
  • it may include amorphous silicon, polysilicon (low temperature polysilicon or high temperature polysilicon), metal oxide semiconductor (such as IGZO, AZO), and the like.
  • the first patterning process may use a conventional photolithography process, including steps such as photoresist coating, exposure, development, etching, and photoresist stripping, which will not be repeated here.
  • Step S603 Referring to FIGS. 3A, 3B, and 4A, a first gate insulating layer 313 and a first conductive layer are sequentially formed on the semiconductor material layer, and a patterning process is performed on the first conductive layer to form the gate 122 of the transistor and the storage capacitor
  • the first capacitor electrode 202 a of 202 and the second detection line 232 are formed in the peripheral area 22.
  • the second detection line 232 also extends to the detection area 23.
  • a plurality of first detection lines 231 and a plurality of second detection lines 232 are parallel to the surface of the base substrate 301. Arrange alternately one by one in the direction.
  • the data line lead-out line 221 can also be formed by performing a patterning process on the first conductive layer.
  • the first gate insulating layer may be a single-layer structure of silicon nitride or silicon oxide or a multilayer structure formed by stacking silicon nitride and silicon oxide.
  • the material of the first conductive layer includes gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and a combination of the above metals Alloy materials; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.
  • the first conductive layer can be formed by sputtering, physical vapor deposition, chemical vapor deposition, or other processes.
  • the second patterning process may adopt a conventional photolithography process, including steps of photoresist coating, exposure, development, etching, and photoresist stripping, which will not be repeated here.
  • Step S604 Conducting the semiconductor pattern in the peripheral area to form at least one first detection line 231.
  • the conductorization treatment includes a doping treatment, and the conductorization treatment is realized by doping the semiconductor pattern in the peripheral area.
  • the doping can be achieved through an ion implantation process.
  • FIG. 7 shows a schematic diagram of conducting conduction treatment through an ion implantation process.
  • the semiconductor material layer can be ion implanted by means of a mask plate 310 to selectively dope the semiconductor material layer, and the mask plate 310 exposes the semiconductor pattern 231 a that will form the first detection line.
  • the doping element may be boron (B) element or phosphorus (P) element.
  • the mask 310 may be a mask used to perform the first patterning process on the semiconductor material layer.
  • the mask 310 may also The active layer 121 of the transistor is exposed. Since the gate 122 formed in advance can shield the channel region of the active layer, the plasma treatment will not affect the channel region. This can save the cost of the mask.
  • the ion implantation process also simultaneously doped the source region and the drain region of the active layer to conduct the source region and the drain region.
  • Step S605 sequentially forming a second gate insulating layer 134 and a second conductive layer on the first conductive layer, and performing a third patterning process on the second conductive layer to form a second capacitor electrode 202b of a storage capacitor.
  • the patterning process of the second conductive layer can also form the data line lead-out line 221.
  • the patterning process of the second conductive layer can also form the emission control signal (EM) line (not shown) of the electronic substrate.
  • EM emission control signal
  • the second detection line 132 may also be formed during the patterning process of the second conductive layer, that is, formed on the same layer as the second capacitor electrode 202b.
  • Step S606 An interlayer insulating layer and a third conductive layer are sequentially formed on the second conductive layer, and the third conductive layer is subjected to a fourth patterning process to form the source and drain electrode layers of the transistor, the data line 213, and the formation in the peripheral area Signal input pad 220.
  • the patterning process of the third conductive layer can also form the first power line 211 parallel to the data line 213.
  • the second gate insulating layer 314 and the interlayer insulating layer 315 are also etched to form via holes at positions corresponding to the data line lead-out lines 221, so as to facilitate the data lines and the corresponding data lines.
  • the lead wire 221 is electrically connected.
  • the first gate insulating layer 313, the second gate insulating layer 314, and the interlayer insulating layer 315 are also etched to respectively etch the layers corresponding to the active layer.
  • Via holes (such as the first via 401 and the second via 402) are formed in the source region, the drain region, and the regions of the first detection line and the second detection line to facilitate the source and drain of the transistor and the active layer
  • the contact and the signal input pad are respectively connected to the data line lead-out line 221, the first detection/231 and the second detection line 232.
  • the etching process may be a dry etching process or a wet etching process.
  • Step S607 sequentially forming a planarization layer and a light emitting element on the third conductive layer.
  • a planarization layer 170, a first electrode 127, a pixel defining layer 180, an organic light-emitting layer 128, and a second electrode 129 are sequentially formed on the third conductive layer.
  • a via is formed in the planarization layer 170 so that the first electrode 127 and the drain 124 of the driving transistor 201 are electrically connected through the via.
  • a patterning process is performed on the pixel defining layer 170 to form an opening to define a light-emitting area, and the opening exposes at least part of the first electrode 127. Then, an organic light-emitting layer 128 and a second electrode 129 are sequentially formed corresponding to the opening, thereby forming the light-emitting element 203.
  • the manufacturing method further includes providing a detection circuit, such as a data detection circuit 230, in the detection area 23.
  • the detection circuit is electrically connected to the first detection line and the second detection line extending to the peripheral area.
  • the detection circuit 230 may be formed on the base substrate 301 together with the device structure of the display area.
  • the manufacturing method further includes detecting a signal line (such as a data line) corresponding to the detection line through the detection circuit and the first detection line and the second detection line.
  • a signal line such as a data line
  • the manufacturing method may also include repairing the defective signal line.
  • the manufacturing method further includes cutting the first inspection line and the second inspection line along the cutting line 200 after the inspection is completed to separate the inspection area 23 from the peripheral area and the display area to form an electronic substrate including the display area and the peripheral area, and A first cutting surface of the first detection line 231, a second cutting surface of the second detection line 232, and a third cutting surface of the base substrate are formed.
  • laser cutting or knife wheel cutting can be used for cutting.
  • the manufacturing method further includes packaging the electronic substrate 20 after cutting to form an organic light emitting diode display panel.

Abstract

一种电子基板及其制作方法、显示面板。该电子基板包括衬底基板，该衬底基板包括显示区和位于该显示区外的周边区。该电子基板还包括位于该显示区中的多个子像素、多条数据线和多个信号输入垫、以及位于该周边区的多条第一检测线和多条第二检测线，该多条第一检测线与多条第二检测线位于该多个信号输入垫远离该显示区的一侧，并通过该多个信号输入垫与多条数据线电连接。该多条第一检测线为非金属导电材料，该多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条第一检测线。该电子基板可以有效降低检测线之间的短路风险。

Description

电子基板及其制作方法、显示面板 技术领域
本公开实施例涉及一种电子基板及其制作方法、显示面板。
背景技术
近年来，平板显示技术已成为主流的显示技术，丰富和便利了人们的生活。例如，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。如何优化显示面板的制作工艺是本领域关注的问题。
发明内容
本公开至少一实施例提供一种电子基板，包括衬底基板，所述衬底基板包括显示区和位于所述显示区外的周边区。所述电子基板还包括位于所述显示区中的多个子像素和多条数据线、以及位于所述周边区的多个信号输入垫及多条第一检测线和多条第二检测线。所述多条数据线配置为为所述多个子像素提供数据信号；所述多个信号输入垫和所述多条数据线电连接；所述多条第一检测线和多条第二检测线位于所述多个信号输入垫远离所述显示区的一侧，与所述多个信号输入垫电连接。所述多条第一检测线为非金属导电材料，所述多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条所述第一检测线；所述电子基板包括切割面，所述第一检测线包括第一切割面，所述第一切割面为所述电子基板的切割面的第一部分，且所述第一切割面为所述非金属的导电材料的切割面。
在一些示例中，所述第一检测线的材料为导体化处理的半导体材料。
在一些示例中，所述第一检测线的材料包括硅或导电金属氧化物。
在一些示例中，所述第一检测线的材料包括低温多晶硅。
在一些示例中，所述第二检测线包括第二切割面，所述第二切割面为所述电子基板的切割面的第二部分，且所述第二切割面为所述金属导 电材料的切割面。
在一些示例中，所述衬底基板包括第三切割面，所述第三切割面为所述电子基板的切割面的第三部分，所述第三切割面位于所述多条第一检测线和所述多条第二检测线远离所述显示区一侧，且与所述第一切割面和所述第二切割面均齐平。
在一些示例中，所述多个子像素中的至少一个包括晶体管和存储电容；所述晶体管包括依次层叠于所述衬底基板上的有源层、第一栅绝缘层、栅极、第二栅绝缘层、层间绝缘层及源漏电极层，所述有源层位于所述栅极靠近所述衬底基板的一侧；所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，所述第二电容电极位于所述第二栅绝缘层和与所述层间绝缘层之间。
在一些示例中，所述第一检测线与所述有源层同层设置。
在一些示例中，所述第二检测线与所述第一电容电极或所述第二电容电极同层设置。
在一些示例中，所述多个信号输入垫与所述源漏电极层同层设置。
在一些示例中，所述第一检测线在所述衬底基板上的正投影与所述第二检测线在所述衬底基板上的正投影一一交替排列。
本公开至少一实施例还提供一种显示面板，包括上述电子基板。
本公开至少一实施例还提供一种电子基板的制作方法，包括：在衬底基板上的显示区中形成多个子像素和多条数据线，所述多条数据线配置为为所述多个子像素提供数据信号；在所述衬底基板的所述显示区外的周边区中形成多个信号输入垫，所述多个信号输入垫和所述多条数据线连接；以及在所述周边区形成多条第一检测线和多条第二检测线，所述多条第一检测线和多条第二检测线位于所述多个信号输入垫远离所述显示区的一侧，与所述多个信号输入垫电连接。所述多条第一检测线为非金属导电材料，所述多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条所述第一检测线；所述电子基板包括切割面，所述第一检测线包括第一切割面，所述第一切割面为所述电子基板的切割面的第一部分，且所述第一切割面为所述非金属的导电材料的切割面。
在一些示例中，所述制作方法还包括：在所述显示区和周边区外的检测区中提供检测电路，其中，所述多条第一检测线和所述多条第二检测线还延伸至所述检测区从而与检测电路电连接；以及通过所述检测电路、所述第一检测线和所述多条第二检测线对所述多条数据线进行检测。
在一些示例中，所述制作方法还包括：切割所述第一检测线和所述第二检测线，以将所述检测区与所述周边区及所述显示区分离，并形成所述第一切割面。
在一些示例中，切割所述第一检测线和所述第二检测线还还在形成所述第二检测线的第二切割面，所述第二切割面为所述金属导电材料的切割面。
在一些示例中，形成所述第一检测线包括：形成半导体材料层并对所述半导体材料层进行构图工艺和导体化处理以形成所述多条第一检测线。
在一些示例中，所述半导体材料层的材料包括硅或导电金属氧化物。
在一些示例中，形成所述多个子像素中的至少一个包括形成晶体管和存储电容，包括：在所述衬底基板上依次形成所述的有源层、第一栅绝缘层、栅极、第二栅绝缘层、层间绝缘层及源漏电极层，与所述存储电容的第一电容电极与所述栅极在同一构图工艺中形成，所述第二电容电极形成于所述第二栅绝缘层和与所述层间绝缘层之间。
在一些示例中，所述多条第一检测线与所述有源层在同一构图工艺中形成。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本公开一些实施例提供的电子基板的平面示意图之一；
图2为本公开一些实施例提供的电子基板的平面示意图之二；
图3A为本公开一些实施例提供的电子基板的剖视图之一；
图3B为本公开一些实施例提供的电子基板的剖视图之二；
图4A为本公开一些实施例提供的电子基板的剖视图之三；
图4B为本公开一些实施例提供的电子基板的剖视图之四；
图5为本公开一些实施例提供的电子基板的示意图；
图6为本公开一些实施例提供的电子基板的制作方法的流程图；
图7为本公开一些实施例提供的电子制作方法的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
在显示面板的制作过程中，需要对形成的信号线进行不良检测，例如检测信号线上是否存在短路或断路的情形。例如，在显示面板的制作过程中，在基板的面板区之外形成检测区，检测区中的检测电路通过检测线与面板区中的信号线电连接以对该信号线进行检测以及时修复基板的不良。待检测完毕，会将检测区切除从而形成面板。
发明人发现，由于检测线的分布比较密集，线间距较小，在切割过程中，切割会导致检测线中的金属碎屑飞溅，引起相邻的检测线之间的短路。例如，在采用激光切割时，激光会导致金属导线融化并产生飞溅 的金属碎屑，从而引起相邻的检测线之间的短路。由于检测线与显示区的信号线电连接，检测线之间的短路会引起信号线之间的短路，造成显示不良。
本公开实施例提供一种电子基板，采用非金属的导电材料形成上述检测线或检测线的一部分，从而可以避免切割过程中的金属碎屑导致的相邻检测线之间短路情形。
图1示出了本公开实施例提供的一种电子基板的平面示意图之一，例如，该电子基板为用于显示面板的电子基板(例如为阵列基板)，然而本公开实施例对此不作限制。
图1示出了该电子基板在检测过程中的情形，如图所示，衬底基板301包括显示区21、显示区21外的周边区(非显示区)22以及检测区23，检测区23位于周边区22远离显示区21的一侧，显示区21和周边区22对应于电子基板20，在检测完成后沿着周边区22远离显示区21一侧的切割线200将该检测区23切除从而形成该电子基板20。
显示区21包括至少一条信号线，该信号线可以是电源线、栅线、数据线等。如图1示，显示区21包括多条栅线212、多条数据线213以及阵列排布的多个子像素210。该栅线配置为为多个子像素210提供栅信号，数据线配置为为多个子像素提供数据信号。
例如，该电子基板为应用于有机发光二极管(OLED)显示面板的阵列基板。在另一些示例中，该电子基板也可以为应用于液晶显示面板和量子点发光二极管显示面板的阵列基板，本公开实施例对此不作限制。
每个子像素210包括发光元件(OLED)以及驱动该发光元件发光的像素电路，该像素电路分别与对应的栅线212和数据线213电连接。例如，像素电路包括常规的2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路，并且不同的实施例中，该像素电路还可以进一步包括补偿电路，该补偿电路包括内部补偿电路或外部补偿电路，补偿电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以包括复位电路、发光控制电路、检测电路等。
如图1所示，电子基板20还包括位于周边区22的栅极驱动电路240，该栅极驱动电路240例如为GOA结构(gate on array)。该栅极驱动电路240与栅线212连接，并通过栅线212为显示区21的子像素210提供栅极驱动信号。
电子基板20还可以包括第一电源线211和第二电源线215，配置为为子像素210分别提供第一电源电压和第二电源电压。如图1所示，第一电源线211位于显示区21；第二电源线215位于周边区22，第二电源线215可以为U型结构环绕显示区21。例如，第一电源线211配置为提供高电源电压VDD，第二电源线215配置为低电源电压VSS。图1中还示出了与多条第一电源线211连接的电源总线(bus line)216。
检测区23包括检测电路，该检测电路通过检测线与显示区21和周边区22中的信号线或电路连接，以进行不良检测(例如检测信号线上的短路或断路情形)，从而在发现问题时可以及时对电子基板进行检测。例如，该检测电路230包括短路棒(shorting bar)、开关元件等。
图1中示例性地示出了检测区23中的数据线检测电路230，数据检测电路230配置为与数据线213电连接以对数据线213进行检测。电子基板20还包括多条第一检测线231和多条第二检测线232，该第一检测线231和第二检测线232位于周边区22，其一端与数据线213电连接，另一端延伸至检测区23与数据线检测电路230电连接，从而将数据线213与数据线检测电路230电连接。以下通过对用于检测数据线的第一检测线和第二检测线对本公开实施例提供的技术方案进行示例性说明，这并不作为对本公开的限制，本公开实施例提供的技术方案也适用于其它检测线。
数据线213可以直接与检测线电连接，也可以通过其它结构与检测线电连接。图1示出了数据线213通过信号输入垫与检测线连接的示例。如图1所示，电子基板20还包括位于周边区22的多个信号输入垫220，该多个信号输入垫220位于多条检测线靠近显示区21的一侧，分别且与多条数据线213以及多条检测线电连接；例如，该信号输入垫220为绑定电极(bonding pad)，用于与外部电路(例如IC电路板)绑定连接以接收数据驱动信号。
例如，该多个信号输入垫220与多条数据线213一一对应电连接。如图1所示，多条数据线213通过多条数据线引出线221与多个信号输入垫220一一对应电连接。在另一些示例中，该多条数据线也可以通过多路复用电路(MUX)与多个信号输入垫220电连接，以降低信号输入垫220的数目和分布密度；一个信号输入垫220对应连接多条(例如2条或3条)数据线213。
例如，该多个信号输入垫220与多条检测线(包括第一检测线231和第二检测线232)一一对应电连接。
图1中还示例性地示出了分别与第二电源线215、栅极驱动电路240、电源总线216、以及数据线检测电路230电连接的检测电极241、261、251和271。待检测和修复完毕，沿着检测区23与周边区22之间的切割线200进行切割，使得检测区23与周边区22分离以去除检测区，从而得到了如图2所示的电子基板20。在该电子基板20中，第一检测线231和第二检测线232与电子基板的衬底基板一起被切割，因此第一检测线231和第二检测线232的一端与电子基板20的边缘(即切割位置)齐平。也就是说，在切割线200处，也即第一检测线231和第二检测线232远离显示区21的一侧，第一检测线231包括第一切割面，第二检测线232包括第二切割面，衬底基板301包括第三切割面，该第一切割面、第二切割面和第三切割面均为电子基板的切割面的一部分，且第一切割面和第二切割面均与衬底基板301的第三切割面齐平，具体参考后文关于图4A和图4B的描述。
例如，第一检测线231的材料为导体化处理的半导体材料，例如为经过掺杂的半导体材料。
例如，第一检测线231的材料包括硅(例如低温多晶硅)或导电金属氧化物。
例如，第一检测线231的材料包括金属氧化物半导体材料经过导体化处理后得到的导电材料，例如为重掺杂铟锡氧化物(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一检测线231可以与显示区的像素中某个晶体管的有源层在同一构图工艺中同层形成，从而可以节省工艺成本。在不同实施例中， 该晶体管可以为像素电路中的开关晶体管、驱动晶体管等。
例如，第二检测线232的材料为金属导电材料，例如可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)、钛(Ti)以及以上金属组合而成的合金材料。
多条第一检测线231为非金属导电材料，多条第二检测线232为金属导电材料，每相邻两条第二检测线232之间设置有至少一条第一检测线213。例如，多条第一检测线231和多条第二检测线232在平行于电子基板的表面的方向上一一交替排列，第一检测线231在衬底基板301上的正投影与第二检测线232在衬底基板301上的正投影一一交替排列(参考下图4A和4B)。例如，如图2所示，显示区21中的多条数据线213通过数据线引出线221交替与第一检测线231和第二检测线232电连接。
在另一些示例中，相邻的两条第二检测线232之间也可以设置多条第一检测线231以进一步拉大金属导线之间的距离以降低短路风险。本公开实施例对此不作限制。
由于每相邻两条第二检测线232之间设置有至少一条非金属材料的第一检测线231，因此，即便第二检测线232的材料为金属，由于它们之间的间距与第一检测线231和第二检测线232之间的间距相比变大，也即相较于第一检测线231和第二检测线232均为金属材料的情形，相邻的金属线之间的间距变大，也可以有效降低切割时的短路风险。例如，第一检测线231和第二检测线232可以位于不同层，拉大了第一检测线231和第二检测线232之间的距离，还可以进一步降低切割时的短路风险。
如上所述，通过将检测线分别设置在不同的多层，可以降低检测线的分布密度，增大检测线的间距，从而进一步降低短路的风险。例如，通过降低检测线的分布密度，还可以进一步节省检测线在该基板上的占用的面积，有利于布线。
图3A和3B分别示出了图2沿剖面线I-I’和I-II的剖视图，图4A和图4B示出了图1所示电子基板沿切割线200方向的剖视图的不同示例，也即为图2所示电子基板的侧面(切割面)示意图。以下将以该电 子基板为有机发光二极管显示基板为例、结合图2、图3A-3B以及图4A-4B对本公开实施例提供的电子基板进行示例性说明。
显示区的每个像素210包括至少一个发光元件(例如为有机发光二极管)203以及与之连接的像素电路，该有发光元件在像素电路的驱动下发光。例如，该像素电路包括常规的OLED像素驱动电路，例如包括开关晶体管、驱动晶体管及存储电容等，或者还可以进一步包括复位晶体管、发光控制晶体管等，本公开实施例不限制像素电路的具体结构。
为了清楚起见，图3A仅示出了该像素电路中与该发光元件直接连接的晶体管201以及存储电容202。例如，该晶体管201可以是驱动晶体管，配置为工作在饱和状态下并控制驱动发光元件203发光的电流的大小。例如，该晶体管201也可以为发光控制晶体管，用于控制驱动发光元件203发光的电流是否流过。本公开的实施例对此不作限制。
如图3A所示，晶体管201、存储电容202和发光元件203位于衬底基板301上。例如，衬底基板301为柔性基板，该柔性基板的材料例如为如聚酰亚胺(PI)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚碳酸酯、聚乙烯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜等。
例如，该电子基板还可以包括设置于衬底基板301与像素电路之间的缓冲层302。该缓冲层302可以阻挡湿气和/或氧渗透穿过衬底基板301进入像素电路造成腐蚀，还可以例如有助于提供形成像素电路的平坦表面。例如，该缓冲层302的材料可以是氮化硅、氧化硅或者硅的氮氧化物。例如，该缓冲层也可以包括氧化硅层和氮化硅层交替堆叠的结构。
如图3A所示，晶体管201包括有源层121、栅极122、第一栅绝缘层133和源漏电极层(包括源极123和漏极124)。例如，该有源层121包括沟道区以及位于该沟道区相对两侧的源极区和漏极区。存储电容202包括第一电容电极202a、第二栅绝缘层134和第二电容电极202b。例如，存储电容202的第一电容电极202a与晶体管201的栅极122同层设置。
需要说明的是，本公开实施例中“同层设置”是指多种层结构由同一材料层通过相同或不同的工艺形成，而并不一定位于同一水平面上、 或者具有相同的高度或厚度。
还需要说明的是，这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，因此根据需要二者是可以互换的。
在图3A中，晶体管201为顶栅型，但是本公开的实施例并不限制于晶体管的具体类型，该晶体管除了可以为顶栅型之外，其也可以为底栅型或双栅型等，并且当晶体管为不同的类型时，衬底基板上的叠层结构也相应调整而彼此不同。
例如，晶体管201例如为薄膜晶体管，其有源层121可以为非晶硅、多晶硅(例如低温多晶硅或高温多晶硅)、氧化物半导体(例如IGZO)等，且晶体管201可以为N型或P型。
发光元件203包括第一电极127、第二电极129以及设置于第一电极127和第二电极129之间的发光层128，其中，第一电极127与晶体管201的漏极124电连接。这里第一电极127为像素电极，而第二电极129为公共电极。第一电极127和第二电极129之一为阳极，另一个为阴极；例如，第一电极127为阳极，第二电极129为阴极。例如，在至少一个示例中，发光元件203除了发光层128之外还可以包括空穴注入层、空穴传输层、电子注入层、电子传输层等至少之一。
例如，发光元件203可以为顶发射、底发射或双面发射结构。例如，发光元件203为顶发射结构，第一电极127具有反射性而第二电极129具有透射性或半透射性，例如第一电极127为氧化铟锡(ITO)等透明导电氧化物材料。例如，第一电极127为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极129为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，如图3A所示，第一检测线231和晶体管201的有源层121位于同一层，二者可以由同一半导体材料层经同一构图工艺形成。例如，在该半导体材料层经过构图工艺后，对该半导体材料层至少对应于第一检测线的部分进行导体化处理以形成该第一检测线。例如，对于半导体材料层为多晶硅的情况，例如在对于晶体管的有源层的源极区和漏极区进行掺杂的同时，可以对对应于第一检测线的半导体图案进行导体化处 理(如图7所示)；例如，对于半导体材料层为非晶硅或氧化物半导体的情况，可以单独对对应于第一检测线的部分进行导体化处理，例如采用激光退火、离子掺杂、等离子体表面处理等。
例如，信号输入垫220与显示区21中发光元件以下的最顶层(最远离衬底基板301)的导电层同层设置以方便后续的邦定工艺。例如，如图3A和3B所示，信号输入垫220与晶体管201的源漏电极层位于同一层，二者可以由同一导电材料经同一构图工艺形成。
例如，第二检测线232也可以与显示区21中的导电层同层设置以节省工艺。例如，如图3B和图4A所示，第二检测线232与晶体管201的栅极122以及存储电容202的第一电容电极202a同层设置。
由于在本公开至少一实施例提供的电子基板中，第一检测线231的材料为非金属导电材料，相比与第一检测线231和第二检测线232均为金属导体材料的情形，这种设置增大了相邻金属检测线之间的间距，有效降低了短路风险。
在另一些示例中，如图4B所示，第二检测线232与存储电容202的第二电容电极202b同层设置。由于第二电容电极202b所在层相比与栅极122所在层更加远离第一检测线231所在层，也即这种设置拉大了第一检测线231与第二检测线232之间的间距，进一步降低了短路风险。
在再一些示例中，还可以将检测线分布在三层或更多层中，从而进一步减小检测线的分布密度，降低短路风险。
图4A和图4B示出了第一检测线231的第一切割面411、第二检测线232的第二切割面412及衬底基板301的第三切割面413，它们均为电子基板20的切割面410的一部分。例如，第一切割面411和第二切割面412均垂直于衬底基板301。
第一切割面411为非金属导电材料的切割面，第二切割面412为金属导电材料的切割面。
例如，数据线引出线221也可以分布在多层以降低分布密度，从而降低短路风险。参考图3A和图3B，多条数据线引出线221可以分布在栅极122所在导电层以及第二电容电极202b所在导电层。例如，在平行于电子基板的表面的方向上，数据线引出线221交替与栅极122及第 二电容电极202b同层设置。
例如，电子基板20还包括设置于第一检测线231和第二检测线上232的层间绝缘层135。如图3A所示，信号输入垫220通过贯穿第一栅绝缘层133、第二栅绝缘层134和层间绝缘层135的第一过孔401与第一检测线231电连接，通过贯穿第二栅绝缘层134和层间绝缘层135的第二过孔402与数据线引出线221电连接。
例如，该层间绝缘层135的材料为无机绝缘材料，该无机绝缘材料相比于有机绝缘材料更加致密，可以有效防止第一检测线231和第二检测线上232因空气渗透而受到腐蚀。例如，层间绝缘层135的材料为硅的氧化物、硅的氮化物或硅的氮氧化物、或者氧化铝、氮化钛等金属氮氧化物绝缘材料。
例如，该电子基板20还包括设置于晶体管20的源漏电极层上的平坦化层170，该平坦化层为发光元件203的形成提供一个基本平坦的表面。例如，该平坦化层170为有机绝缘材料，例如可以包括聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。
如图3A所示，发光元件203的第一电极127通过该平坦化层170中的过孔与晶体管201的漏极124电连接。在周边区22，该平坦化层170暴露出该信号输入垫220，以便于该信号输入垫220与外部电路(如柔性电路板)的邦定连接。
例如，在平坦化层170和第一电极127之上设置有像素界定层180，像素界定层180在对应于第一电极127的位置形成开口以至少部分暴露出第一电极127，在该开口中形成发光层128。在发光层128以及像素界定层180上形成第二电极129。
例如，该平坦化层170和像素界定层180的材料为有机材料或无机材料，例如该有机材料为聚酰亚胺(PI)等树脂。
如图5所示，本公开至少一实施例还提供一种显示面板30，包括上述电子基板20。
例如，该显示面板为OLED显示面板，相应地其包括的电子基板20为OLED基板。例如，该显示面板30还包括设置于电子基板20上 的封装层501和盖板502，该封装层501配置为对发光元件203进行密封以防止外界的湿气和氧向该发光元件及驱动电路的渗透而造成对器件的损坏。例如，封装层501包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层501与电子基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件203在前期制作工艺中残余的水汽或者溶胶。盖板502例如为玻璃盖板。例如，盖板502和封装层501可以为一体的结构。
本公开至少一实施例还提供一种显示装置，包括上述电子基板或显示面板。该显示装置例如可以数码相框、智能手环、智能手表、手机、平板电脑、显示器、笔记本电脑、导航仪等具有任何显示功能的产品或者部件。
本公开至少一实施例还提供上述电子基板的制作方法，该制作方法至少包括：在衬底基板上的显示区中形成多个子像素和多条数据线，所述多条数据线配置为为所述多个子像素提供数据信号，在所述衬底基板的所述显示区外的周边区中形成多个信号输入垫，所述多个信号输入垫和所述多条数据线连接，在所述周边区形成多条第一检测线和多条第二检测线，所述多条第一检测线和多条第二检测线位于所述多个信号输入垫远离所述显示区的一侧，与所述多个信号输入垫电连接。所述多条第一检测线为非金属导电材料，所述多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条所述第一检测线；所述电子基板包括切割面，所述第一检测线包括第一切割面，所述第一切割面为所述电子基板的切割面的第一部分，且所述第一切割面为所述非金属的导电材料的切割面。
在一些示例中，所述制作方法还包括：在所述显示区和周边区外的检测区中提供检测电路，其中，所述多条第一检测线和所述多条第二检测线还延伸至所述检测区从而与检测电路电连接；以及通过所述检测电路、所述第一检测线和所述多条第二检测线对所述多条数据线进行检测。
在一些示例中，所述制作方法还包括：切割所述第一检测线和所述第二检测线，以将所述检测区与所述周边区及所述显示区分离，并形成 所述第一切割面。
在一些示例中，切割所述第一检测线和所述第二检测线还还在形成所述第二检测线的第二切割面，所述第二切割面为所述金属导电材料的切割面。
在一些示例中，形成所述第一检测线包括：形成半导体材料层并对所述半导体材料层进行构图工艺和导体化处理以形成所述多条第一检测线。
在一些示例中，所述半导体材料层的材料包括硅或导电金属氧化物。
在一些示例中，形成所述多个子像素中的至少一个包括形成晶体管和存储电容，包括：在所述衬底基板上依次形成所述的有源层、第一栅绝缘层、栅极、第二栅绝缘层、层间绝缘层及源漏电极层，与所述存储电容的第一电容电极与所述栅极在同一构图工艺中形成，所述第二电容电极形成于所述第二栅绝缘层和与所述层间绝缘层之间。
在一些示例中，所述多条第一检测线与所述有源层在同一构图工艺中形成。
图6为本公开至少一实施例提供的阵列基板的制作方法的流程图，以下将结合图1-图2、图3A-3B、图4A-4B和图6对该实施例提供的电子基板的制作方法进行示例性说明。
如图6所示，该制作方法包括如下步骤S601-S607。
步骤S601：在衬底基板301上形成缓冲层302。
如图1所示，该衬底基板301包括显示区21、周边区22以及检测区23。
例如，衬底基板301可以为刚性基板，例如玻璃基板、硅基板或者不锈钢基板。该衬底基板301也可以是有机柔性衬底，例如包括聚酰亚胺(PI)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚碳酸酯、聚乙烯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜等。
例如，缓冲层302可以包括无机绝缘材料，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等金属氮氧化物绝缘材料。
例如，该缓冲层302可以采用化学气相淀积工艺等工艺形成。
步骤S602：在缓冲层上形成半导体材料层，并在对该半导体材料层进行第一构图工艺以在显示区形成晶体管的有源层、以及在周边区形成对应于第一检测线231的半导体图案。例如，该半导体图案还延伸至检测区23，用于与该检测区中将要形成或提供的检测电路电连接。
例如，该半导体材料层的材料可以为单质半导体材料或化合物半导体材料，例如可以包括非晶硅、多晶硅(低温多晶硅或高温多晶硅)、金属氧化物半导体(如IGZO、AZO)等。
例如，该第一构图工艺可以采用常规的光刻工艺，包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤，这里不再赘述。
步骤S603：参照图3A、3B和4A，在该半导体材料层上依次形成第一栅绝缘层313及第一导电层，并对该第一导电层进行构图工艺形成晶体管的栅极122以及存储电容202的第一电容电极202a，以及在周边区22形成第二检测线232。该第二检测线232还延伸至检测区23。每两条第二检测线232之间有至少一条第一检测线231，如图3B所示，多条第一检测线231和多条第二检测线232在平行于衬底基板301的表面的方向上一一交替排布。
例如，如图3A所示，对该第一导电层进行构图工艺还可以形成该数据线引出线221。
例如，该第一栅绝缘层可以为氮化硅或氧化硅的单层结构或者由氮化硅和氧化硅堆叠形成的多层结构。
例如，该第一导电层的材料包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，可以通过溅射、物理气相淀积、化学气相淀积等工艺形成该第一导电层。
例如，该第二构图工艺可以采用常规的光刻工艺，包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤，这里不再赘述。
步骤S604：对该周边区的半导体图案进行导体化处理形成至少一 条第一检测线231。
例如，该导体化处理包括掺杂处理，通过对该周边区的半导体图案进行掺杂实现导体化处理。
例如，该掺杂可以通过离子注入工艺实现。图7示出了通过离子注入工艺进行导体化处理的示意图。
如图7所示，可以借助掩膜板310对半导体材料层进行离子注入从而对半导体材料层进行有选择的掺杂，掩膜板310暴露出将形成第一检测线的半导体图案231a。例如，在半导体材料层为硅材料的情形下，掺杂元素可以为硼(B)元素或磷(P)元素。
例如，如图7所示，掩膜板310可以为用于对半导体材料层进行第一构图工艺的掩膜板，该掩膜板除了暴露出对应于第一检测线的半导体图案231a外，还暴露出晶体管的有源层121。而由于在先形成的栅极122可以对有源层的沟道区起到屏蔽作用，因此等离子体处理不会对沟道区造成影响。这样可以节省掩膜板的成本。例如，该离子注入工艺还同时对有源层的源极区和漏极区进行掺杂而将该源极区和漏极区进行导体化。
步骤S605：在该第一导电层上依次形成第二栅绝缘层134及第二导电层，并对该第二导电层进行第三构图工艺形成存储电容的第二电容电极202b。
例如，如图3B所示，对该第二导电层进行构图工艺还可以形成该数据线引出线221。
例如，对该第二导电层进行构图工艺还可以形成该电子基板的发光控制信号(EM)线(未示出)。
在另一示例中，如图4B所示，该第二检测线132也可以在对该第二导电层进行构图工艺的时候形成，即与第二电容电极202b形成在同一层。
步骤S606：在该第二导电层上依次形成层间绝缘层和第三导电层，并对该第三导电层进行第四构图工艺形成晶体管的源漏电极层、数据线213以及在周边区形成信号输入垫220。
对该第三导电层进行构图工艺还可以形成与数据线213平行的第 一电源线211。
在形成第三导电层之前，还对第二栅绝缘层314和层间绝缘层315进行刻蚀，以分别在对应于数据线引出线221的位置形成过孔，以便于数据线与对应的数据线引出线221电连接。
如图3A和3B所示，在形成第三导电层之前，还对第一栅绝缘层313、第二栅绝缘层314和层间绝缘层315进行刻蚀，以分别在对应于有源层的源极区、漏极区以及第一检测线和第二检测线的区域形成过孔(如第一过孔401和第二过孔402)，以便于晶体管的源极和漏极与有源层接触、以及信号输入垫分别与数据线引出线221、第一检测/231和第二检测线232的连接。例如，该刻蚀工艺可以是干法刻蚀工艺或湿法刻蚀工艺。
步骤S607：在该第三导电层上依次形成平坦化层及发光元件。
例如，在该第三导电层上依次形成平坦化层170、第一电极127、像素界定层180、有机发光层128以及第二电极129。
例如，在平坦化层170中形成过孔，使得第一电极127与驱动晶体管201的漏极124通过该过孔形成电连接。
例如，对该像素界定层170进行构图工艺以形成开口从而定义发光区，该开口暴露出第一电极127的至少部分。然后，对应该开口依次形成有机发光层128和第二电极129，从而形成该发光元件203。
例如，该制作方法还包括在检测区23提供检测电路，例如数据检测电路230。该检测电路与延伸至周边区的第一检测线和第二检测线电连接。例如，该检测电路230可以与显示区的器件结构一道形成在衬底基板301上。
例如，该制作方法还包括通过该检测电路以及该第一检测线和第二检测线对于该检测线对应连接的信号线(如数据线)进行检测。
例如，如果经过检测发现信号线上存在不良(例如短路或断路)，该制作方法还可以包括对不良的信号线进行修复。
例如，该制作方法还包括在检测完毕后沿着切割线200切割第一检测线和第二检测线以将检测区23与周边区、显示区分离形成包括显示区和周边区的电子基板，并形成第一检测线231的第一切割面、第二检 测线232的第二切割面以及衬底基板的第三切割面。例如，可以使用激光切割或刀轮切割进行切割。
例如，该制作方法还包括在切割后对电子基板20进行封装从而形成有机发光二极管显示面板。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种电子基板，包括：
    衬底基板，包括显示区和位于所述显示区外的周边区；
    多个子像素，位于所述显示区中；
    多条数据线，位于所述显示区中，配置为为所述多个子像素提供数据信号；
    多个信号输入垫，位于所述周边区，所述多个信号输入垫和所述多条数据线电连接；
    多条第一检测线和多条第二检测线，位于所述周边区且位于所述多个信号输入垫远离所述显示区的一侧，与所述多个信号输入垫电连接，
    其中，所述多条第一检测线为非金属导电材料，所述多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条所述第一检测线；
    所述电子基板包括切割面，所述第一检测线包括第一切割面，所述第一切割面为所述电子基板的切割面的第一部分，且所述第一切割面为所述非金属的导电材料的切割面。
  2. 如权利要求1所述的电子基板，其中，所述第一检测线的材料为导体化处理的半导体材料。
  3. 如权利要求1-2任一所述的电子基板，其中，所述第一检测线的材料包括硅或导电金属氧化物。
  4. 如权利要求1-3任一所述的电子基板，其中，所述第一检测线的材料包括低温多晶硅。
  5. 如权利要求1-4任一所述的电子基板，其中，所述第二检测线包括第二切割面，所述第二切割面为所述电子基板的切割面的第二部分，且所述第二切割面为所述金属导电材料的切割面。
  6. 如权利要求5任一所述的电子基板，其中，所述衬底基板包括第三切割面，所述第三切割面为所述电子基板的切割面的第三部分，所述第三切割面位于所述多条第一检测线和所述多条第二检测线远离所述显示区一侧，且与所述第一切割面和所述第二切割面均齐平。
  7. 如权利要求1-6任一所述的电子基板，其中，所述多个子像素中的至少一个包括晶体管和存储电容；
    所述晶体管包括依次层叠于所述衬底基板上的有源层、第一栅绝缘层、栅极、第二栅绝缘层、层间绝缘层及源漏电极层，所述有源层位于所述栅极靠近所述衬底基板的一侧；
    所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，所述第二电容电极位于所述第二栅绝缘层和与所述层间绝缘层之间。
  8. 如权利要求7所述的电子基板，其中，所述第一检测线与所述有源层同层设置。
  9. 如权利要求7或8所述的电子基板，其中，所述第二检测线与所述第一电容电极或所述第二电容电极同层设置。
  10. 如权利要求7-9任一所述的电子基板，其中，所述多个信号输入垫与所述源漏电极层同层设置。
  11. 如权利要求1-10任一所述的电子基板，其中，所述第一检测线在所述衬底基板上的正投影与所述第二检测线在所述衬底基板上的正投影一一交替排列。
  12. 一种显示面板，包括如权利要求1-11任一所述的电子基板。
  13. 一种电子基板的制作方法，包括：
    在衬底基板上的显示区中形成多个子像素和多条数据线，所述多条数据线配置为为所述多个子像素提供数据信号；
    在所述衬底基板的所述显示区外的周边区中形成多个信号输入垫，所述多个信号输入垫和所述多条数据线连接；以及
    在所述周边区形成多条第一检测线和多条第二检测线，所述多条第一检测线和多条第二检测线位于所述多个信号输入垫远离所述显示区的一侧，与所述多个信号输入垫电连接，
    其中，所述多条第一检测线为非金属导电材料，所述多条第二检测线为金属导电材料，每相邻两条第二检测线之间设置有至少一条所述第一检测线；
    所述电子基板包括切割面，所述第一检测线包括第一切割面，所述第一切割面为所述电子基板的切割面的第一部分，且所述第一切割面为所述非金属的导电材料的切割面。
  14. 如权利要求13所述的制作方法，还包括：在所述显示区和周边区外的检测区中提供检测电路，其中，所述多条第一检测线和所述多 条第二检测线还延伸至所述检测区从而与检测电路电连接；以及
    通过所述检测电路、所述第一检测线和所述多条第二检测线对所述多条数据线进行检测。
  15. 如权利要求13或14所述的制作方法，还包括：切割所述第一检测线和所述第二检测线，以将所述检测区与所述周边区及所述显示区分离，并形成所述第一切割面。
  16. 如权利要求15所述的制作方法，其中，切割所述第一检测线和所述第二检测线，形成所述第二检测线的第二切割面，所述第二切割面为所述金属导电材料的切割面。
  17. 如权利要求13-16任一所述的制作方法，其中，形成所述第一检测线包括：
    形成半导体材料层并对所述半导体材料层进行构图工艺和导体化处理以形成所述多条第一检测线。
  18. 如权利要求17所述的制作方法，其中，所述半导体材料层的材料包括硅或导电金属氧化物。
  19. 如权利要求17或18所述的制作方法，其中，形成所述多个子像素中的至少一个包括形成晶体管和存储电容，包括：
    在所述衬底基板上依次形成所述的有源层、第一栅绝缘层、栅极、第二栅绝缘层、层间绝缘层及源漏电极层，
    与所述存储电容的第一电容电极与所述栅极在同一构图工艺中形成，所述第二电容电极形成于所述第二栅绝缘层和与所述层间绝缘层之间。
  20. 如权利要求19的制作方法，其中，所述多条第一检测线与所述有源层在同一构图工艺中形成。
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