WO2014015636A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2014015636A1
WO2014015636A1 PCT/CN2012/087235 CN2012087235W WO2014015636A1 WO 2014015636 A1 WO2014015636 A1 WO 2014015636A1 CN 2012087235 W CN2012087235 W CN 2012087235W WO 2014015636 A1 WO2014015636 A1 WO 2014015636A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
test
array substrate
electrode
insulating
Prior art date
Application number
PCT/CN2012/087235
Other languages
English (en)
French (fr)
Inventor
吴昊
陈雅娟
尹岩岩
王磊
Original Assignee
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to US14/127,935 priority Critical patent/US8975631B2/en
Publication of WO2014015636A1 publication Critical patent/WO2014015636A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • Embodiments of the present invention relate to the field of liquid crystal display technologies, and in particular, to an array substrate, a method for preparing the same, and a display device. Background technique
  • an ADvanced Super Dimension Switch (AD-SDS, ADS for short) type array substrate has a wide viewing angle and the like, and thus is widely used.
  • the ADS technology mainly forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules are directly between the slit electrodes in the liquid crystal cell and above the electrode. Both can produce rotation, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the ADS type array substrate includes a plurality of pixel units. As shown in FIG. 1 and FIG. 2, in each of the pixel units, a gate line 05 made of a gate material is formed on the glass substrate 09. A gate insulating layer 03 is deposited over the gate line, an active layer 07 having a predetermined pattern is disposed above the gate insulating layer 03, and an active drain metal layer is disposed over the active layer 07 for making a source having a predetermined pattern a pole 08 and a drain 010, a first transparent conductive layer for forming the pixel electrode 01 (ie, a plate electrode) is disposed above the source/drain metal layer, and a passivation layer 04 is deposited over the first transparent conductive layer, and A second transparent conductive layer for forming the common electrode 02 (i.e., the slit electrode) is disposed above the passivation layer 04, wherein a plurality of slits are formed between the common electrodes 02.
  • a liquid crystal panel has a plurality of pixel units, and the pixel electrode 01 of each pixel unit display area of the imaging area of the liquid crystal panel is covered by a multilayer structure which is subsequently fabricated, so that the TFT semiconductor characteristics cannot be tested before the substrate is cut.
  • a detection module dedicated to testing is provided at an edge portion (i.e., a non-display area) of the entire liquid crystal panel.
  • the detection modules are fabricated simultaneously with the layer structures in the display area, but are only produced to the pixel electrode layer, and the multilayer structure above the pixel electrodes is not fabricated, so the pixel electrodes of the detection modules can be measured by the test device; During the test, the same voltage and current are applied to the pixel electrode of the detecting module and the pixel electrode of the pixel unit, and the semiconductor characteristics of the pixel electrode in the other pixel unit are inferred by testing the semiconductor characteristics of the pixel electrode of the detecting module.
  • the test result obtained by testing the pixel electrode of the detection module is greatly different from the actual characteristics of the pixel electrode of each pixel unit, which is disadvantageous for the thin film transistor ( In-depth analysis and discussion of TFT), sometimes it is impossible to know exactly how the actual working condition of the designed TFT is, which causes great uncertainty.
  • the present invention provides an array substrate capable of individually testing the pixel electrodes of each pixel unit, thereby improving the accuracy of the pixel electrode test in each individual pixel region.
  • an array substrate including a plurality of pixel units, each of the pixel units including a first transparent conductive layer and a second transparent conductive layer, the first transparent conductive layer forming a pixel electrode, The second transparent conductive layer forms a common electrode, and the second transparent conductive layer is located on the surface of the pixel unit, and an insulating protective layer is disposed between the first transparent conductive layer and the second transparent conductive layer; a pixel electrode of each of the pixel units extends out of the test portion, the second transparent conductive layer is further formed with a test block corresponding to the test portion, the test block is laterally isolated from the common electrode, and the insulation
  • the portion of the protective layer between the test block and the test portion is provided with at least one via, and the test block and the test portion are electrically connected through the via.
  • an array substrate comprising a plurality of pixel units, wherein each of the pixel units comprises:
  • a pixel electrode formed on the second insulating layer, the pixel electrode being electrically connected to the drain through a through hole of the second insulating layer, wherein a test portion extending from the pixel electrode is located at the data line Above
  • first insulating protection layer formed on the second insulating layer, wherein the first insulating protective layer is disposed in the same layer as the pixel electrode;
  • a second insulating protective layer formed on the gate layer and the pixel electrode, the second insulating protective layer having at least one via;
  • a common electrode formed on the second insulating protective layer and the test block, the test block and the test portion being electrically connected by at least one via provided in the second insulating protective layer.
  • a display device comprising any of the above array substrates.
  • a method for fabricating an array substrate comprising: fabricating a source/drain metal layer on a substrate, forming a source and a drain of the corresponding pattern, and forming a data line of the corresponding pattern;
  • test block Forming a second transparent conductive layer on the second insulating protective layer and forming a common electrode of the corresponding pattern, And a strip-shaped test block, the test block being electrically connected to the test portion through at least one via provided in the second insulating protective layer.
  • the test point of the pixel electrode is led to the surface of the array substrate through a via connection between the test portion and the test block of the second transparent conductive layer, and the test device can pass the specific test process. Testing the test block located in the test area in each pixel unit can obtain the semiconductor characteristics of the pixel electrode in the display area of the pixel unit.
  • the array substrate provided by the embodiment of the present invention can separately test the pixel electrodes of each pixel unit, and can improve the accuracy of the pixel electrode test in each individual pixel region.
  • FIG. 1 is a cross-sectional view showing a display area of one pixel unit in an ADS type array substrate in the prior art
  • FIG. 2 is a schematic plan view of a pixel unit in an array substrate in the prior art
  • FIG. 3 is a cross-sectional view showing a display area of a pixel unit in an ADS type array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic plan view of a pixel unit in an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a test area in a pixel unit in an array substrate according to an embodiment of the present invention. detailed description
  • the array substrate according to the embodiment of the present invention includes a plurality of pixel units.
  • each of the pixel units includes a first transparent conductive layer and a second transparent conductive layer, and the first transparent conductive layer forms a pixel electrode 1 .
  • the two transparent conductive layers 2 form a common electrode 201.
  • the second transparent conductive layer 2 is located on the surface of the pixel unit, and an insulating protective layer 131 is disposed between the first transparent conductive layer and the second transparent conductive layer to insulate therebetween.
  • the broken line indicates the occluded portion
  • the solid line indicates the viewable portion.
  • Each of the pixel units is provided with a test area, such as the test area A shown in FIG.
  • the pixel electrode 1 is provided with the test portion 102 extending to the test area A, and the second transparent conductive layer 2 is formed and tested in the test area A.
  • the test block 202 and the common electrode 201 are laterally separated from each other, and the portion of the insulating protective layer between the test block 202 and the test portion 102 is provided with at least one via 3, the test block. 202 is electrically connected to the test portion 102 through the via 3, as shown in FIG.
  • the common electrode 201 is a transparent electrode having a slit-like structure
  • the pixel electrode 1 is a plate-shaped transparent electrode.
  • the test points of the pixel electrodes 1 are led to the surface of the array substrate through the vias 3 between the test portion 102 and the test block 202 of the second transparent conductive layer 2.
  • the probe 81 of the testing device 8 can obtain the test area 202 located in the test area A in each pixel unit to obtain the display area D in the pixel unit (the area indicated by the dotted line in the figure).
  • the array substrate provided by the present invention can individually test the pixel electrodes 1 of each pixel unit, so that the accuracy of the test of the pixel electrodes 1 in each individual pixel region can be improved.
  • the test block 202 and the test portion 102 there are at least two via holes 3 in the insulating protective layer 13 between the test block 202 and the test portion 102 mentioned in the technical solution, and the test block 202 and the test portion 102 are electrically connected through each of the via holes 3.
  • the via holes 3 are disposed in at least two, which can prevent the electrical connection between the test block 202 and the test portion 102 from being defective, and the test block 202 and the test portion can be realized as long as at least one of the at least two via holes 3 is well connected. Electrical connection between 102.
  • the via hole 3 is filled with a connecting portion 21 made of a conductive material (for example, ITO), and the connecting portion 21 may be formed separately, or may be combined with the test portion 102 and the test block. 202 - body formation.
  • ITO a conductive material
  • the latter is preferred because the one-piece construction increases the stability of the electrical connection between the test portion 102 and the test block 202.
  • test area A preferably does not overlap display area D of each pixel unit.
  • the test area A and the display area D as shown in FIG. 4, that is, the test portion 102 and the test block 202 are located outside the display area D of the pixel unit; this can avoid the influence of the test area A on the display area D, thereby ensuring the array substrate The display effect of each pixel unit.
  • the pixel unit of the array substrate includes a thin film transistor, and the thin film transistor has a top gate structure.
  • an ADS array substrate is provided, the substrate includes a plurality of pixel units, wherein each of the pixel units includes:
  • a first insulating layer 14 formed on the substrate 9 and in the channel between the source 10 and the drain 11; an active layer 7 having a predetermined pattern structure formed on the source 10 and the drain 11;
  • the pixel electrode 1 is electrically connected to the drain 11 through a via hole in the second insulating layer 12, wherein the test portion 102 extending from the pixel electrode 1 is located above the data line 6;
  • first insulating protective layer 132 formed on the second insulating layer 12, and the first insulating protective layer 132 is disposed in the same layer as the pixel electrode 1;
  • the protective layer 131 has at least one via 3;
  • the common electrode 201 formed on the second insulating protection layer 131 and the test block 202, the test block 202 and the test portion 102 are electrically connected through a connection portion 21 provided in at least one of the via holes 3 in the second insulating protective layer 131.
  • the gate layer 5 is located at the first insulating protective layer 132 and the second insulating protective layer.
  • the insulation between the gate layer 5 and the pixel electrode 1, the data line 6, and the like is ensured, and the pixel electrode 1 formed by the first transparent conductive layer and the test portion 102 extended by the pixel electrode 1 are located at Below the two insulating protective layer 131, the common electrode 201 formed by the second transparent conductive layer 2 and the test block 202 opposite to the test portion 102 are located above the second insulating protective layer 131, and the test portion 102 and the test block 202 are filled in the second
  • the connection portion 21 in the via hole 3 formed by the insulating protection layer 131 is electrically connected.
  • the pixel electrode 1 passes through the via hole 3 between the test portion 102 and the test block 202 of the second transparent conductive layer 2 Connecting, the test point of the pixel electrode 1 is led to the surface of the array substrate.
  • the probe 81 of the test device 8 can obtain the pixel by testing the test block 202 located in the test area A in each pixel unit. The semiconductor characteristic of the pixel electrode 1 located in the display region D in the cell.
  • the first transparent conductive layer is made of the same material as the second transparent conductive layer 2.
  • the first transparent conductive layer and the second transparent metal layer 2 have the same material, so that the resistance between the test portion 102 of the pixel electrode 1 and the test block 202 formed by the second transparent insulating layer 2 is small, and the pixel electrode is further improved. 1 test accuracy.
  • the first transparent conductive layer has a plate-like structure made of indium tin oxide. That is, the first transparent conductive layer and the second transparent conductive layer 2 are made of indium tin oxide.
  • a display device comprising any of the above-mentioned array substrates.
  • the display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet, or the like.
  • a method for fabricating an array substrate including: fabricating a source/drain metal layer on a substrate 9, forming a source 10 and a drain 11 of a corresponding pattern, and forming a corresponding pattern.
  • a through hole is formed at a position corresponding to the second insulating layer 12 and the drain 11;
  • a first transparent conductive layer is formed on the second insulating layer 12, and a pixel electrode 1 of a corresponding pattern is formed, and the pixel electrode 1 and the drain electrode 11 are electrically connected through a via hole provided in the second insulating layer 12, and the pixel electrode 1 extends out of the test.
  • a gate layer 5 is formed on the first insulating protection layer 132, and a corresponding pattern of gate lines is formed; a second insulating protection layer 131 is deposited on the gate layer 5;
  • the second insulating protection layer 131 is formed with a via hole 3 at a position corresponding to the data line 6;
  • a second transparent conductive layer 2 is formed on the second insulating protective layer 131, and a common electrode 201 of a corresponding pattern is formed, and an elongated test block 202 is disposed.
  • the test block 202 and the test portion 102 are disposed through the second insulating protective layer 131.
  • the via 3 is electrically connected.
  • the gate layer 5 is located between the first insulating protective layer 132 and the second insulating protective layer 131, thereby ensuring insulation between the gate layer 5 and the pixel electrode 1, the data line 6, and the like.
  • the pixel electrode 1 formed by the first transparent conductive layer and the test portion 102 extended by the pixel electrode 1 are located under the second insulating protection layer 131, the common electrode 201 formed by the second transparent conductive layer 2, and the test portion 102 described above
  • the opposite test block 202 is located above the second insulating protective layer 131, and the test portion 102 is electrically connected to the test block 202 through the connecting portion 21 filled in the via hole 3 formed by the second insulating protective layer 131.
  • the array substrate of the above structure is
  • the pixel electrode 1 is connected to the via hole 3 between the test block 202 of the second transparent conductive layer 2 through the test portion 102, and the test point of the pixel electrode 1 is led to the surface of the array substrate.
  • the test device 8 is tested.
  • the probe 81 can be obtained by testing the test block 202 located in the test area A in each pixel unit to obtain the display area D in the pixel unit. 1, the pixel electrode semiconductor characteristics.

Abstract

一种阵列基板及其制备方法、显示装置。该阵列基板包括多个像素单元，每个像素单元包括第一透明导电层和第二透明导电层（2），第一透明导电层形成像素电极（1），第二透明导电层（2）形成公共电极（201），且第二透明导电层（2）位于像素单元表面，第一透明导电层与第二透明导电层（2）之间设有绝缘防护层（131）；其中，每一个像素单元的像素电极（1）延伸出测试部（102），第二透明导电层（2）还形成有与测试部（102）对应的测试块（202），测试块（202）与公共电极（201）横向隔离，绝缘防护层（131）位于测试块（202）与测试部（102）之间的部分设有至少一个过孔（3），测试块（202）与测试部（102）通过过孔（3）电连接。该阵列基板能够对每一个像素单元的像素电极（1）进行单独测试并提高测试的精确性。

Description

阵列基板及其制备方法、 显示装置 技术领域
本发明的实施例涉及液晶显示技术领域， 特别涉及一种阵列基板及其制 备方法、 显示装置。 背景技术
在液晶显示技术领域中， 因高级超维场转换技术 （ADvanced Super Dimension Switch, AD-SDS, 简称 ADS )型阵列基板具有视角宽等优点， 所 以得到广泛的使用。 ADS技术主要是通过同一平面内狭缝电极边缘所产生的 电场以及狭缝电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内 狭缝电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液 晶工作效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD产 品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低 色差、 无挤压水波紋（push Mura )等优点。
现有技术中， ADS型阵列基板包括多个像素单元， 如图 1和图 2所示， 每一个像素单元中， 在玻璃基板 09上制作有由栅极材料做出的栅极线 05, 在栅极线上方沉积有栅绝缘层 03, 栅绝缘层 03的上方设有具有预定图形的 有源层 07, 在有源层 07的上方设置有源漏极金属层用于制作具有预定图形 的源极 08和漏极 010, 在上述源漏极金属层上方设有用于制作像素电极 01 (即板状电极）的第一透明导电层，在第一透明导电层的上方沉积钝化层 04, 而在钝化层 04上方设有用于制作公共电极 02 (即狭缝电极） 的第二透明导 电层， 其中公共电极 02之间形成有多个狭缝。
一块液晶面板具有多个像素单元， 位于液晶面板成像区域的每一个像素 单元显示区域的像素电极 01被后来制作的多层结构覆盖，因此无法在切割基 板前进行 TFT半导体特性的测试， 为此， 现有技术中在整个液晶面板的边缘 部位（即， 非显示区域）设有专门用于测试的检测模块。 这些检测模块与显 示区域中的各层结构同时制作， 但仅仅生产至像素电极层， 位于像素电极上 方的多层结构并未制作，因此可以用测试装置测量这些检测模块的像素电极； 测试时， 对检测模块的像素电极与像素单元的像素电极施加相同的电压以及 电流等条件， 通过测试检测模块像素电极的半导体特性来推断其它像素单元 中像素电极的半导体特性。
但是， 由于检测模块与其它各个像素单元之间存在电阻等差异因素， 通 过测试检测模块的像素电极得出的测试结果与各个像素单元像素电极的实际 特性有很大差异， 不利于对薄膜晶体管 （TFT ) 的深入分析和研讨， 有时候 甚至无法确切掌握所设计 TFT的实际工作情况到底如何，造成很大的不确定
11^· 。
因此， 如何提供一种阵列基板， 以提高对每一个单独的像素单元中像素 电极测试的精确性， 是本领域技术人员需要解决的技术问题。 发明内容
本发明提供了一种阵列基板， 该阵列基板能够对每一个像素单元的像素 电极进行单独测试， 所以能够提高对每一个单独的像素区域中像素电极测试 的精确性。
为达到上述目的， 本发明的实施例提供以下技术方案：
根据本发明的第一方面， 提供一种阵列基板， 包括多个像素单元， 每一 个所述像素单元包括第一透明导电层和第二透明导电层， 所述第一透明导电 层形成像素电极， 所述第二透明导电层形成公共电极， 且所述第二透明导电 层位于所述像素单元表面， 所述第一透明导电层与所述第二透明导电层之间 设有绝缘防护层； 其中， 每一个所述像素单元的像素电极延伸出测试部， 所 述第二透明导电层还形成有与所述测试部对应的测试块， 所述测试块与所述 公共电极横向隔离， 所述绝缘防护层位于所述测试块与所述测试部之间的部 分设有至少一个过孔， 所述测试块与所述测试部通过所述过孔电连接。
根据本发明的第二方面， 提供一种阵列基板， 包括多个像素单元， 其中 每一个所述像素单元包括：
基板；
形成于基板上的数据线、源极和漏极，所述源极与相邻的数据线电连接； 形成于所述基板上、 以及所述源极和所述漏极之间的沟道内的第一绝缘 层； 形成于所述源极和漏极上的具有预定图形结构的有源层； 形成于所述数据线和所述有源层上的第二绝缘层， 所述第二绝缘层具有 通孔；
形成于所述第二绝缘层上的像素电极， 所述像素电极通过所述第二绝缘 层的通孔与所述漏极电连接， 其中所述像素电极延伸出的测试部位于所述数 据线的上方；
形成于所述第二绝缘层上的第一绝缘防护层， 所述第一绝缘防护层与所 述像素电极同层设置；
形成于所述第一绝缘防护层上的栅极层；
形成于所述栅极层以及所述像素电极上的第二绝缘防护层， 所述第二绝 缘防护层具有至少一个过孔；
形成于第二绝缘防护层上的公共电极以及所述测试块， 所述测试块与所 述测试部通过设置于所述第二绝缘防护层的至少一个过孔电连接。
根据本发明的第三方面， 还提供了一种显示装置， 包括以上任一种阵列 基板。
根据本发明的第四方面， 还提供了一种阵列基板的制作方法， 包括： 在基板上制作源漏极金属层， 并形成相应图形的源极和漏极， 以及形成 相应图形的数据线；
在源漏极金属层上制作第一绝缘层， 并形成相应的图形；
在源漏极金属层上制作有源层；
在有源层上制作第二绝缘层；
在所述第二绝缘层与所述漏极对应位置制作过孔；
在第二绝缘层上制作第一透明导电层， 并形成相应图形的像素电极， 所 述像素电极与所述漏极通过第二绝缘层设置的通孔电连接， 且所述像素电极 延伸出测试部；
在第二绝缘层上沉积第一绝缘防护层；
在第一绝缘防护层上制作栅极层， 并形成相应图形的栅线；
在栅极层上沉积第二绝缘防护层；
第二绝缘防护层与数据线对应位置制作至少一个过孔；
在第二绝缘防护层上制作第二透明导电层，并形成相应图形的公共电极， 以及长条状的测试块， 所述测试块与所述测试部通过第二绝缘防护层设置的 至少一个过孔电连接。
本发明实施例提供的阵列基板中， 通过测试部与第二透明导电层的测试 块之间的过孔连接将像素电极的测试点引至阵列基板表面， 在具体测试过程 中， 测试装置可以通过测试每一个像素单元中位于测试区域内的测试块便可 得到该像素单元中位于显示区域的像素电极的半导体特性。
所以， 本发明实施例提供的阵列基板能够对每一个像素单元的像素电极 进行单独测试，能够提高对每一个单独的像素区域中像素电极测试的精确性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中 ADS型阵列基板中一个像素单元的显示区域的截面 图；
图 2为现有技术中阵列基板中的像素单元的平面示意图；
图 3为本发明实施例的 ADS型阵列基板中的像素单元的显示区域的截 面图；
图 4为本发明实施例的阵列基板中的像素单元的平面示意图；
图 5为本发明实施例的阵列基板中的像素单元中测试区域的截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。
"上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
根据本发明实施例的阵列基板包括多个像素单元， 如图 3、 4所示，每一 个像素单元包括第一透明导电层和第二透明导电层， 第一透明导电层形成像 素电极 1 ,第二透明导电层 2形成公共电极 201。第二透明导电层 2位于像素 单元表面， 第一透明导电层与第二透明导电层之间设有绝缘防护层 131 , 以 使二者之间绝缘。 在本文的附图中， 虚线表示被遮挡部分， 实线表示可观看 的部分。 每一个像素单元均设有测试区域， 如图 4中所示的测试区域 A, 像 素电极 1设有延伸至测试区域 A的测试部 102, 同时第二透明导电层 2在测 试区域 A形成与测试部 102相对的长条状的测试块 202, 测试块 202与公共 电极 201横向上相互分离， 绝缘防护层的位于测试块 202与测试部 102之间 的部分设有至少一个过孔 3 , 测试块 202与测试部 102通过过孔 3电连接， 如图 4所示。
如图 3和图 4所示， 在本实施例中， 公共电极 201为具有狭缝状结构的 透明电极， 像素电极 1为板状的透明电极。
本发明实施例的阵列基板中， 通过测试部 102与第二透明导电层 2的测 试块 202之间的过孔 3将像素电极 1的测试点引至阵列基板表面。 在具体测 试过程中，测试装置 8的探针 81可以通过测试每一个像素单元中位于测试区 域 A内的测试块 202便可得到该像素单元中位于显示区域 D (图中虚线框所 示区域） 的像素电极 1的半导体特性。
所以， 本发明提供的阵列基板能够对每一个像素单元的像素电极 1进行 单独测试， 所以能够提高对每一个单独的像素区域中像素电极 1测试的精确 性。
进一步地， 为了保证测试块 202与测试部 102之间电连接的稳定性， 上 述技术方案中提到的位于测试块 202与测试部 102之间绝缘防护层 13中的过 孔 3为至少两个， 测试块 202与测试部 102之间通过每一个过孔 3电连接。 过孔 3设置为至少两个， 可以预防测试块 202与测试部 102之间的电连接出 现虚接的不良，只要至少两个过孔 3中的一个连接良好则可以实现测试块 202 与测试部 102之间的电连接。
如图 4和图 5所示，具体的，上述过孔 3内填充有由导电材料（例如 ITO ) 制成的连接部 21 , 该连接部 21可以单独形成 , 也可以与测试部 102和测试 块 202—体形成。 后者为优选， 因为一体式结构增加了测试部 102与测试块 202之间电连接的稳定性。
在一个实施例中，测试区域 A优选地与每一个像素单元的显示区域 D不 重叠。如图 4中所示的测试区域 A和显示区域 D ,即测试部 102与测试块 202 位于像素单元的显示区域 D之外； 这样能够避免测试区域 A对显示区域 D 的影响， 从而保证阵列基板中每一个像素单元的显示效果。
优选地， 上述阵列基板的像素单元内包含有薄膜晶体管， 且所述薄膜晶 体管釆用顶栅型结构。
参照图 3和图 4, 根据本发明另一实施例， 提供一种 ADS阵列基板， 该 基板包括多个像素单元， 其中每一个像素单元包括：
形成于基板 9上的数据线 6、 源极 10和漏极 11 , 源极 10与相邻的数据 线 6电连接；
形成于基板 9上、以及源极 10和漏极 11之间的沟道内的第一绝缘层 14; 形成于源极 10和漏极 11上的具有预定图形结构的有源层 7;
形成于数据线 6和有源层 7上的第二绝缘层 12, 第二绝缘 12层具有通 孔；
形成于第二绝缘层 12上的像素电极 1 , 像素电极 1通过第二绝缘层 12 上的通孔与漏极 11电连接，其中像素电极 1延伸出的测试部 102位于数据线 6的上方；
形成于第二绝缘层 12上的第一绝缘防护层 132,第一绝缘防护层 132与 像素电极 1同层设置；
形成于第一绝缘防护层 132上的栅极层 5;
形成于栅极层 5以及像素电极 1上的第二绝缘防护层 131 , 第二绝缘防 护层 131具有至少一个过孔 3;
形成于第二绝缘防护层 131上的公共电极 201 以及测试块 202, 测试块 202与测试部 102通过设置于第二绝缘防护层 131中的至少一个过孔 3内的 连接部 21电连接。
上述技术方案中， 栅极层 5位于第一绝缘防护层 132和第二绝缘防护层
131之间，从而保证栅极层 5与像素电极 1、数据线 6等之间的绝缘性， 且第 一透明导电层形成的像素电极 1、 以及由像素电极 1延伸出的测试部 102位 于第二绝缘防护层 131下方， 第二透明导电层 2形成的公共电极 201以及与 上述测试部 102相对的测试块 202位于第二绝缘防护层 131上方，测试部 102 与测试块 202通过填充于第二绝缘防护层 131形成的过孔 3中的连接部 21 电连接， 因此， 上述结构的阵列基板中， 像素电极 1通过测试部 102与第二 透明导电层 2的测试块 202之间的过孔 3连接， 将像素电极 1的测试点引至 阵列基板表面，在具体测试过程中，测试装置 8的探针 81可以通过测试每一 个像素单元中位于测试区域 A内的测试块 202便可得到该像素单元中位于显 示区域 D的像素电极 1的半导体特性。
优选地， 在一个实施例中， 第一透明导电层与第二透明导电层 2的制作 材料相同。 第一透明导电层与第二通明金属层 2具有相同的材料， 所以， 像 素电极 1的测试部 102与第二透明绝缘层 2形成的测试块 202之间的电阻较 小， 进一步提高了像素电极 1测试的精确性。
更优选地， 在一个实施例中， 第一透明导电层具有由氧化铟锡制作而成 的板状结构。 即第一透明导电层和第二透明导电层 2的制作材料均为氧化铟 锡。
根据本发明再一个实施例， 提供了一种显示装置， 包括以上提到的任一 种阵列基板。 该显示装置可以是： 液晶面板、 电子纸、 OLED面板、 液晶电 视、 液晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的产品或 部件。
根据本发明又一个实施例， 还提供了一种阵列基板的制作方法， 包括： 在基板 9上制作源漏极金属层， 并形成相应图形的源极 10和漏极 11 , 以及形成相应图形的数据线 6;
在源漏极金属层上制作第一绝缘层 14, 并形成相应的图形； 在源漏极金属层上制作有源层 7;
在有源层 7上制作第二绝缘层 12;
在第二绝缘层 12与漏极 11对应位置制作通孔；
在第二绝缘层 12上制作第一透明导电层，并形成相应图形的像素电极 1 , 像素电极 1与漏极 11通过第二绝缘层 12设置的通孔电连接， 且像素电极 1 延伸出测试部 102;
在第二绝缘层 12上沉积第一绝缘防护层 132;
在第一绝缘防护层 132上制作栅极层 5, 并形成相应图形的栅线； 在栅极层 5上均勾沉积第二绝缘防护层 131 ;
第二绝缘防护层 131与数据线 6对应位置制作过孔 3;
在第二绝缘防护层 131上制作第二透明导电层 2, 并形成相应图形的公 共电极 201 ,以及长条状的测试块 202,测试块 202与测试部 102通过第二绝 缘防护层 131设置的过孔 3电连接。
通过上述方法制作的阵列基板中， 栅极层 5位于第一绝缘防护层 132和 第二绝缘防护层 131之间， 从而保证栅极层 5与像素电极 1、 数据线 6等之 间的绝缘性， 且第一透明导电层形成的像素电极 1、 以及由像素电极 1延伸 出的测试部 102位于第二绝缘防护层 131下方， 第二透明导电层 2形成的公 共电极 201以及与上述测试部 102相对的测试块 202位于第二绝缘防护层 131 上方， 测试部 102与测试块 202通过填充于第二绝缘防护层 131形成的过孔 3中的连接部 21电连接， 因此， 上述结构的阵列基板中， 像素电极 1通过测 试部 102与第二透明导电层 2的测试块 202之间的过孔 3连接， 将像素电极 1的测试点引至阵列基板表面， 在具体测试过程中， 测试装置 8的探针 81可 以通过测试每一个像素单元中位于测试区域 A内的测试块 202便可得到该像 素单元中位于显示区域 D的像素电极 1的半导体特性。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括多个像素单元，每一个所述像素单元包括第一透 明导电层和第二透明导电层， 所述第一透明导电层形成像素电极， 所述第二 透明导电层形成公共电极， 且所述第二透明导电层位于所述像素单元表面， 所述第一透明导电层与所述第二透明导电层之间设有绝缘防护层； 其中， 每 一个所述像素单元的像素电极延伸出测试部， 所述第二透明导电层还形成有 与所述测试部对应的测试块， 所述测试块与所述公共电极横向隔离， 所述绝 缘防护层位于所述测试块与所述测试部之间的部分设有至少一个过孔， 所述 测试块与所述测试部通过所述过孔电连接。
2、 根据权利要求 1所述的阵列基板， 其中所述过孔为至少两个。
3、根据权利要求 2所述的阵列基板， 其中所述过孔内填充有连接部， 所 述连接部与所述测试块为一体的。
4、 根据权利要求 1-3中任一项所述的阵列基板， 其中， 所述测试部与测 试块位于像素单元的显示区域之外。
5、 根据权利要求 1-4中任一项所述的阵列基板， 其中， 所述像素单元中 包含有薄膜晶体管， 所述薄膜晶体管釆用顶栅型结构。
6、 根据权利要求 1-5中任一项所述的阵列基板， 其中， 所述公共电极为 具有狭缝状结构的透明电极； 所述像素电极为板状的透明电极。
7、 根据权利要求 1-6中任一项所述的阵列基板， 其中， 所述第一透明导 电层与所述第二透明导电层的制作材料相同。
8、 一种阵列基板， 包括多个像素单元， 其中每一个所述像素单元包括： 基板；
形成于基板上的数据线、源极和漏极，所述源极与相邻的数据线电连接； 形成于所述基板上、 以及所述源极和所述漏极之间的沟道内的第一绝缘 层；
形成于所述源极和漏极上的具有预定图形结构的有源层；
形成于所述数据线和所述有源层上的第二绝缘层， 所述第二绝缘层具有 通孔；
形成于所述第二绝缘层上的像素电极， 所述像素电极通过所述第二绝缘 层的通孔与所述漏极电连接 , 其中所述像素电极延伸出的测试部位于所述数 据线的上方；
形成于所述第二绝缘层上的第一绝缘防护层， 所述第一绝缘防护层与所 述像素电极同层设置；
形成于所述第一绝缘防护层上的栅极层；
形成于所述栅极层以及所述像素电极上的第二绝缘防护层， 所述第二绝 缘防护层具有至少一个过孔；
形成于第二绝缘防护层上的公共电极以及所述测试块， 所述测试块与所 述测试部通过设置于所述第二绝缘防护层的至少一个过孔电连接。
9、 根据权利要求 8所述的阵列基板， 其中所述过孔为至少两个。
10、 根据权利要求 9所述的阵列基板， 其中所述过孔内填充有连接部， 所述连接部与所述测试块为一体式的。
11、 根据权利要求 8-10中任一项所述的阵列基板， 其中， 所述测试部与 测试块所在区域位于像素单元的显示区域之外。
12、 一种显示装置， 包括权利要求 1-11中任一项所述的阵列基板。
13、 一种阵列基板的制作方法， 包括：
在基板上制作源漏极金属层， 并形成相应图形的源极和漏极， 以及形成 相应图形的数据线；
在源漏极金属层上制作第一绝缘层， 并形成相应的图形；
在源漏极金属层上制作有源层；
在有源层上制作第二绝缘层；
在所述第二绝缘层与所述漏极对应位置制作过孔；
在第二绝缘层上制作第一透明导电层， 并形成相应图形的像素电极， 所 述像素电极与所述漏极通过第二绝缘层设置的通孔电连接， 且所述像素电极 延伸出测试部；
在第二绝缘层上沉积第一绝缘防护层；
在第一绝缘防护层上制作栅极层， 并形成相应图形的栅线；
在栅极层上沉积第二绝缘防护层；
第二绝缘防护层与数据线对应位置制作至少一个过孔；
在第二绝缘防护层上制作第二透明导电层，并形成相应图形的公共电极， 以及长条状的测试块， 所述测试块与所述测试部通过第二绝缘防护层设置的 至少一个过孔电连接。
PCT/CN2012/087235 2012-07-27 2012-12-23 阵列基板及其制备方法、显示装置 WO2014015636A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/127,935 US8975631B2 (en) 2012-07-27 2012-12-23 Array substrate, manufacturing method, and display device thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210265530.X 2012-07-27
CN201210265530.XA CN102790051B (zh) 2012-07-27 2012-07-27 阵列基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2014015636A1 true WO2014015636A1 (zh) 2014-01-30

Family

ID=47155415

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/087235 WO2014015636A1 (zh) 2012-07-27 2012-12-23 阵列基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US8975631B2 (zh)
CN (1) CN102790051B (zh)
WO (1) WO2014015636A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790051B (zh) * 2012-07-27 2014-12-10 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
KR20150031917A (ko) * 2013-09-17 2015-03-25 엘지이노텍 주식회사 전극 플레이트와 이를 이용하는 전기변색 플레이트, 전기변색 미러 및 디스플레이 장치
CN103915451B (zh) * 2014-03-28 2016-05-18 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN104701327B (zh) * 2015-03-20 2018-03-02 京东方科技集团股份有限公司 阵列基板、阵列基板的制造方法和显示装置
CN104656307B (zh) * 2015-03-25 2017-12-08 京东方科技集团股份有限公司 双视场显示面板和双视场显示装置
CN104765215A (zh) * 2015-04-21 2015-07-08 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN105632959B (zh) * 2016-01-05 2019-01-22 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN112599578B (zh) * 2020-12-11 2023-10-17 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020051114A1 (en) * 2000-10-27 2002-05-02 Sang-Ki Kwak Liquid crystal display
CN100510913C (zh) * 2006-07-27 2009-07-08 爱普生映像元器件有限公司 液晶显示装置
CN100541282C (zh) * 2004-08-13 2009-09-16 三星电子株式会社 阵列基板及具有所述阵列基板的主基板和液晶显示装置
US20100123841A1 (en) * 2008-11-18 2010-05-20 Kyoung-Ju Shin Array substrate and liquid crystal display device having the same
CN102790051A (zh) * 2012-07-27 2012-11-21 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1139837C (zh) * 1998-10-01 2004-02-25 三星电子株式会社 液晶显示器用薄膜晶体管阵列基板及其制造方法
US6380559B1 (en) * 1999-06-03 2002-04-30 Samsung Electronics Co., Ltd. Thin film transistor array substrate for a liquid crystal display
CN101295717B (zh) * 2007-04-25 2010-07-14 北京京东方光电科技有限公司 薄膜晶体管面板及其制造方法
CN202948234U (zh) * 2012-07-27 2013-05-22 北京京东方光电科技有限公司 阵列基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020051114A1 (en) * 2000-10-27 2002-05-02 Sang-Ki Kwak Liquid crystal display
CN100541282C (zh) * 2004-08-13 2009-09-16 三星电子株式会社 阵列基板及具有所述阵列基板的主基板和液晶显示装置
CN100510913C (zh) * 2006-07-27 2009-07-08 爱普生映像元器件有限公司 液晶显示装置
US20100123841A1 (en) * 2008-11-18 2010-05-20 Kyoung-Ju Shin Array substrate and liquid crystal display device having the same
CN102790051A (zh) * 2012-07-27 2012-11-21 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN102790051B (zh) 2014-12-10
CN102790051A (zh) 2012-11-21
US20140346511A1 (en) 2014-11-27
US8975631B2 (en) 2015-03-10

Similar Documents

Publication Publication Date Title
WO2014015636A1 (zh) 阵列基板及其制备方法、显示装置
US9508751B2 (en) Array substrate, method for manufacturing the same and display device
CN102053415B (zh) 水平电场液晶显示设备
WO2016206452A1 (zh) 一种阵列基板及其制作方法、显示面板、显示装置
EP2518558B1 (en) Liquid crystal display and array substrate
WO2017008472A1 (zh) Ads阵列基板及其制作方法、显示器件
KR102007833B1 (ko) 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판
US10050061B2 (en) Array substrate and manufacturing method thereof, display device
US20140138685A1 (en) Array Substrate, Method for Fabricating and Testing Array Substrate, and Display Device
US10720450B2 (en) Array substrate and manufacturing method thereof, display panel and display device
CN106796947A (zh) 具有微盖层的显示装置及其制造方法
KR20100005883A (ko) 어레이 기판 및 이를 갖는 액정표시장치
US20170285430A1 (en) Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device
WO2013104300A1 (zh) 阵列基板及包括该阵列基板的显示装置
US9627585B2 (en) Wiring structure, thin film transistor array substrate including the same, and display device
US8575617B2 (en) Thin film transistor array having improved connectivity between shorting bar and data lines
KR20120107269A (ko) 액정 표시 장치 및 이의 제조 방법
WO2014146349A1 (zh) 阵列基板及显示装置
WO2013143291A1 (zh) 阵列基板及其制造方法、以及显示设备
KR20130104429A (ko) 액정 표시 장치 및 이의 제조 방법
WO2014183420A1 (zh) 一种阵列基板及其制作方法和显示面板
WO2013135125A1 (zh) Tft阵列基板及其制造方法和显示装置
WO2013123803A1 (zh) 阵列基板及其制造方法、显示装置
US8610858B2 (en) Thin film transistor array panel and method of manufacturing the same
WO2015003456A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14127935

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12881743

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12881743

Country of ref document: EP

Kind code of ref document: A1