WO2017008472A1 - Ads阵列基板及其制作方法、显示器件 - Google Patents

Ads阵列基板及其制作方法、显示器件 Download PDF

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Publication number
WO2017008472A1
WO2017008472A1 PCT/CN2016/070008 CN2016070008W WO2017008472A1 WO 2017008472 A1 WO2017008472 A1 WO 2017008472A1 CN 2016070008 W CN2016070008 W CN 2016070008W WO 2017008472 A1 WO2017008472 A1 WO 2017008472A1
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Prior art keywords
electrode
array substrate
gate
touch
forming
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PCT/CN2016/070008
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English (en)
French (fr)
Inventor
许睿
陈小川
王海生
董学
王磊
杨盛际
刘英明
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/109,212 priority Critical patent/US10198104B2/en
Publication of WO2017008472A1 publication Critical patent/WO2017008472A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
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    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • the present disclosure relates to the field of touch display technologies, and in particular, to an ADS array substrate, a method for fabricating the same, and a display device.
  • the capacitive touch screen In the touch screen technology, compared with the resistive touch screen, the capacitive touch screen has the advantages of long life, high light transmittance, and multi-touch support. Moreover, the capacitive touch screen also has a good suppression effect on noise and parasitic capacitance to the ground. Therefore, capacitive touch screens have become one of the hot spots in today's touch screen manufacturing.
  • the capacitive touch screen includes a self-capacitive touch screen and a mutual-capacitive touch screen. Since the self-capacitive touch screen requires only one layer of touch electrodes, it can be realized by detecting whether the self-capacitance of the touch electrodes changes. Touch detection has the advantages of simple structure and easy implementation.
  • the in-cell touch display device has the purpose of thinning the thickness of the display device by embedding the touch electrode of the touch screen in the display screen, and at the same time greatly reducing the thickness.
  • the manufacturing cost of the touch display device is favored by the major panel manufacturers.
  • the present disclosure provides an ADS array substrate, a manufacturing method thereof, and a display device for implementing an in-cell touch display.
  • an embodiment of the present disclosure provides an ADS array substrate, including a display area and a non-display area located around the display area, the display area of the array substrate includes a plurality of pixel units, and each pixel unit includes a common An electrode and a pixel electrode, wherein a frame display time of the array substrate includes a display time period and a touch time period, wherein the plurality of common electrodes are multiplexed into a plurality of touch electrodes, and each touch electrode corresponds to a plurality of electrical properties Connected common electrodes, the array substrate also includes include:
  • the signal lines are electrically connected to the touch electrodes in one-to-one correspondence, and a common voltage signal is transmitted to the touch electrodes through the corresponding signal lines during a display time period of one frame display time, and displayed on one frame During the touch time period of the time, whether the self-capacitance of the touch electrode changes is detected by the corresponding signal line.
  • the array substrate is a thin film transistor array substrate, and the array substrate includes horizontally and vertically intersecting gate lines and data lines for defining an area where the plurality of pixel units are located Each pixel unit further includes a thin film transistor;
  • the signal line is disposed in the same layer as the gate line and the gate electrode of the thin film transistor, or is disposed in the same material as the source line and the drain electrode of the data line and the thin film transistor.
  • the signal lines are overlapped on the corresponding touch electrodes and electrically contacted.
  • the array substrate as described above, optionally, the array substrate specifically includes:
  • a gate insulating layer covering the gate line, the signal line, and the gate electrode
  • the passivation layer including a via
  • a pixel electrode disposed on the passivation layer, the pixel electrode being electrically connected to the drain electrode through a via hole in the passivation layer.
  • an insulating layer is disposed between the signal line and the touch electrode, and the signal line is electrically connected to the corresponding touch electrode through a via hole in the insulating layer.
  • the portion of the signal line located in the display area is disposed in parallel with the gate line, or the portion of the signal line located in the display area is disposed in parallel with the data line.
  • the common electrode is a plate electrode
  • the pixel electrode is a slit electrode
  • the pixel electrode has a plurality of slits, the slit includes a plurality of first slits disposed in parallel and a plurality of second slits disposed in parallel, the first a slit and the second slit and the grid line have a certain angle; the first slit and the second slit are symmetrically distributed on the central axis of the pixel electrode parallel to the gate line side.
  • the signal line extends from the display area to the non-display area; the array substrate has a rectangular structure, and the signal line extends from the display area to the side of the long side of the array substrate.
  • the embodiment of the present disclosure further provides a method for fabricating an ADS array substrate, wherein the array substrate includes a display area and a non-display area located around the display area, and the manufacturing method includes forming a plurality of display areas on the array substrate.
  • a pixel unit step each pixel unit includes a common electrode and a pixel electrode
  • a frame display time of the array substrate includes a display time period and a touch time period
  • the plurality of common electrodes are multiplexed into multiple touches
  • Each of the touch electrodes corresponds to a plurality of electrically connected common electrodes
  • the manufacturing method further includes:
  • the signal lines are electrically connected to the touch electrodes one by one, and transmitting a common voltage signal to the touch electrodes through the corresponding signal lines in a display time period of one frame display time, in one frame
  • the touch time period of the display time is used to detect whether the self-capacitance of the touch electrode changes through the corresponding signal line.
  • the array substrate is a thin film transistor array substrate, and the array substrate includes horizontally and vertically intersecting gate lines and data lines for defining regions where the plurality of pixel units are located.
  • Each pixel unit further includes a thin film transistor;
  • the step of forming a plurality of pixel units comprises: forming a transparent conductive layer, and patterning the transparent conductive layer to form a plurality of common electrodes;
  • the step of forming a plurality of signal lines includes:
  • the step of forming a plurality of pixel units comprises:
  • the step of forming a plurality of signal lines includes:
  • a gate metal layer on the common electrode, and patterning the gate metal layer to form a plurality of gate lines, a plurality of signal lines, and a gate electrode of the thin film transistor, wherein the signal lines are overlapped on the corresponding touch electrodes on;
  • the manufacturing method further includes:
  • a source/drain metal layer on the active layer, and patterning the source/drain metal layer to form a plurality of data lines and a thin film transistor source electrode and a drain electrode, wherein the source electrode and the drain electrode overlap The opposite sides of the active layer;
  • a pixel electrode is formed on the passivation layer, and the pixel electrode is electrically connected to the drain electrode through a via hole in the passivation layer.
  • the step of forming a plurality of pixel units comprises:
  • the manufacturing method further includes: forming an insulating layer on the common electrode, performing a patterning process on the insulating layer to form a via hole;
  • the forming a plurality of signal lines includes: forming a gate metal layer on the insulating layer, and patterning the gate metal layer to form a gate electrode including the signal line, the gate line, and a thin film transistor a pattern, wherein the signal line is electrically connected to a corresponding touch electrode through a via hole in the insulating layer.
  • a display device is also provided in an embodiment of the present disclosure, using the ADS array substrate as described above.
  • the common electrode of the ADS array substrate is multiplexed into a touch electrode, which can realize in-cell touch and reduce the thickness of the touch display device. At the same time, it can overcome the ghost phenomenon that occurs in the self-capacitive touch detection in the related art, shorten the detection time, and improve the touch sensitivity.
  • FIG. 1 is a schematic structural view of an ADS array substrate in an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a pixel unit of the ADS array substrate of FIG. 1 , showing a connection relationship between a signal line and a corresponding touch electrode;
  • Figure 3 is a cross-sectional view along line A-A of Figure 2;
  • FIG. 4 and FIG. 5 are schematic diagrams showing a process of fabricating the pixel unit of FIG. 2;
  • Figure 6 is a cross-sectional view taken along line A-A of Figure 4.
  • Figure 7 is a cross-sectional view taken along line A-A of Figure 5;
  • FIG. 8 is a schematic structural view of another pixel unit of the ADS array substrate of FIG. 1 , showing a relationship between a signal line and a non-corresponding touch electrode;
  • Figure 9 is a cross-sectional view along line B-B of Figure 8.
  • FIG. 10 and FIG. 11 are schematic diagrams showing a process of fabricating the pixel unit of FIG. 8;
  • Figure 12 is a cross-sectional view taken along line B-B of Figure 10;
  • Figure 13 is a cross-sectional view taken along line B-B of Figure 11;
  • Figure 14 is a cross-sectional view of Figure 2 taken along line A-A;
  • Figure 15 is a cross-sectional view of Figure 8 taken along line B-B;
  • FIG. 16 is a schematic structural view of a pixel unit of the ADS array substrate of FIG. 1 , showing that the signal line is parallel to the data line;
  • Figure 17 is a cross-sectional view taken along line A-A of Figure 16;
  • the main structure of a Thin Film Transistor-Liquid Crystal Display is a liquid crystal panel.
  • the liquid crystal panel includes a thin film transistor array substrate and a color filter substrate, and the liquid crystal molecules are filled on the array substrate and the color filter substrate. between.
  • the array substrate includes a plurality of gate lines and a plurality of data lines for defining a region where the plurality of pixel units are located, each of the pixel units includes a thin film transistor, a pixel electrode, and a common electrode, and the thin film transistor is opened through the gate line, and the pixel on the data line
  • the voltage is transmitted to the pixel electrode through the thin film transistor, so that an electric field that drives the liquid crystal molecules to deflect a specific angle is formed between the common electrode and the pixel electrode, thereby realizing gray scale display.
  • the filter layer on the color filter substrate is used to achieve color display.
  • TFT-LCD has the characteristics of small size, low power consumption, no radiation, etc. It has been rapidly developed in recent years and is dominant in the current flat panel display market.
  • ADS Advanced Super Dimension Switch
  • the common electrode and the pixel electrode are formed on the array substrate, mainly through the electric field generated by the edge of the slit electrode in the same plane, and the slit electrode layer and the plate shape
  • the electric field generated between the electrode layers forms a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • ADS technology can improve the picture quality of TFT-LCD, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • a pixel structure of A-ADS is adopted, the pixel electrode is a slit electrode, the common electrode is a plate electrode, and the pixel electrode is located on a side of the common electrode close to the liquid crystal molecule, and the pixel electrode
  • the slit is parallel to the grid line and is a horizontal slit.
  • the pixel structure of A-ADS has good light efficiency, small coupling capacitance of gate line and data line, and small load, and is suitable for large-size ADS type TFT-LCD.
  • Capacitive touch detection including self-capacitive touch detection and mutual-capacitive touch detection. Since self-capacitive touch detection requires only one layer of touch electrodes, by detecting whether the self-capacitance of the touch electrodes changes, The realization of touch detection has the advantages of simple structure and easy implementation. The self-capacitance of the touch electrode is its capacitance to ground.
  • the self-capacitive touch screen of the related art has a touch electrode arranged in a two-dimensional array, and the touch detection side
  • the method can be: using a self-capacitance change of a single touch electrode itself to transfer charge, one end is grounded, and the other end is connected to an excitation or sampling circuit to detect a change in self-capacitance.
  • the horizontal and vertical touch electrode arrays are sequentially detected, and the lateral coordinates and the longitudinal coordinates of the touched points are respectively determined according to the change of the self-capacitance before and after the touch, and combined into planar coordinates to determine the touch position.
  • the combined coordinates are also the only one, which can be accurately positioned; however, when there are two touch points, there are two coordinates in the horizontal and vertical directions respectively, and four sets of coordinates appear after the combination of the two, only Two are real touch points, and the other two are commonly known as "ghost points", which cannot achieve true multi-touch.
  • FIG. 1 is a schematic structural view of an ADS array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a pixel unit of the ADS array substrate of FIG. 1
  • FIG. 3 is a cross-sectional view of FIG. 2 along A-A.
  • an embodiment of the present disclosure provides an ADS array substrate including a display area and a non-display area located around the display area.
  • the display area of the array substrate includes a plurality of pixel units, each pixel.
  • the unit includes a common electrode 1 and a pixel electrode 5.
  • the plurality of common electrodes 1 are multiplexed into a plurality of touch electrodes 10 , and each of the touch electrodes 10 corresponds to a plurality of electrically connected common electrodes 1 , so that the touch screen is embedded in the display panel, and the touch display device is thinned. thickness.
  • the array substrate further includes a plurality of signal lines 11 , and the signal lines 11 are electrically connected to the touch electrodes 10 in one-to-one correspondence, as shown in FIG. 1 .
  • the one frame display time of the array substrate includes a display time period and a touch time period. In a display period of one frame display time, a common voltage signal is transmitted to the touch electrode 10 through the corresponding signal line 11, a reference voltage is supplied to the common electrode 1, and a liquid crystal molecule deflection specific between the common electrode 1 and the pixel electrode 5 is formed.
  • the electric field of the angle is combined with FIG. 2 and FIG. 3; in the touch time period of displaying the time of one frame, the self-capacitance of the touch electrode 10 is detected by the corresponding signal line 11 to determine the touch position.
  • the signal lines 11 are in one-to-one correspondence with the touch electrodes 10, the detection signals obtained by each of the signal lines 11 uniquely correspond to one touch electrode 10, and even if the plurality of touch electrodes 10 are simultaneously touched, the same can be accurately determined.
  • Multiple touch positions overcome the ghost phenomenon that occurs in self-capacitive touch detection in the related art.
  • the self-capacitance of all the touch electrodes 10 can be simultaneously detected, and the horizontal and vertical touch electrode arrays are sequentially detected in the related art, which shortens the detection time and improves the touch sensitivity.
  • the shape of the common electrode 1 may be a regular shape, such as a rectangle, a diamond, a triangle, a circle, or an ellipse, or may be an irregular shape, and is not specifically limited.
  • the number of the common electrodes 1 corresponding to each of the touch electrodes 10 is not specifically limited to meet the accuracy requirements of the touch detection.
  • the ADS array substrate may specifically be a thin film transistor array substrate, and includes a plurality of gate lines 20 and a plurality of data lines 30 for defining a region where the plurality of pixel units are located, and each of the pixel units further includes a thin film transistor. Since each common electrode 1 is located only in the area where the pixel unit is located, and does not overlap the gate line 20 and the data line 30, the coupling capacitance of the common electrode 1 and the gate line 20 and the data line 30 is reduced, and when the common electrode 1 is multiplexed When the electrode 10 is touched, the response time of the touch detection is minimized.
  • the signal line 11 is disposed in the same layer as the gate electrode 2 of the thin film transistor, or is disposed in the same layer as the source electrode 3 and the drain electrode 4 of the thin film transistor. That is, the signal line 11 and the gate electrode 2 of the thin film transistor are simultaneously formed by a patterning process for the same gate metal layer, or the signal line 11 and the source electrode 3 and the drain electrode 4 of the thin film transistor pass through The patterning process of the same source/drain metal layer is simultaneously formed, and the process and material for separately forming the signal line 11 are defaulted, thereby reducing the production cost. Since the resistivity of the transparent conductive material is greater than the resistivity of the gate metal and the source/drain metal, the signal line 11 is generally not formed by the transparent conductive layer.
  • the signal line 11 needs to extend from the display area to the non-display area, in general, the signal lines 11 should be distributed as evenly as possible, and the traces should be as short as possible and as narrow as possible. Specifically, a portion of the signal line 11 located in the display area may be disposed in parallel with the gate line 20 or the data line 30. The portions located in the non-display area may be distributed in parallel or in a fan shape. When the array substrate is rectangular, the signal line 11 extends from the display area to the side of the long side of the array substrate to reduce the length of the signal line 11, as shown in FIG.
  • the signal line 11 is disposed in the same layer as the gate electrode 2 of the thin film transistor, and the portion of the signal line 11 located in the display region is disposed in parallel with the gate line 20, and the gate line 20 is disposed.
  • the insulation is achieved by being spaced apart from the signal line 11 by a certain distance.
  • the signal line 11 and the source electrode 3 and the drain electrode 4 of the thin film transistor are disposed in the same layer and the portion of the signal line 11 located in the display area and the
  • the data lines 30 are arranged in parallel, and the data lines 30 are spaced apart from the signal lines 11 by a certain distance to achieve insulation.
  • the technical solution of the present disclosure multiplexes the common electrode into a touch electrode of a self-capacitive touch screen, and realizes the inside In-line touch reduces the thickness of the display device. At the same time, it can overcome the problem that the self-contained touch screen will appear ghost phenomenon in the related art, shorten the touch detection time, and improve the touch sensitivity.
  • the ADS array substrate in the embodiment of the present disclosure is in particular an A-ADS array substrate used in a large-sized display device, the common electrode 1 is a plate electrode, and the pixel electrode 5 is a slit electrode having a plurality of slits.
  • the advantages of good light efficiency, small coupling capacitance and small load are shown in Figure 2 and Figure 3.
  • the slit of the pixel electrode 5 includes a plurality of first slits 51 arranged in parallel and a plurality of second slits 52 arranged in parallel.
  • the first slit 51 and the second slit 52 respectively form a certain angle d (normally, 2° ⁇
  • d normally, 2° ⁇
  • the touch electrode 10 corresponds to a plurality of electrically connected common electrodes 1
  • the signal line 11 is electrically connected to the touch electrode 10 and converted into at least one common electrode 1 corresponding to the touch line 10 of the signal line 11 .
  • the signal line 11 may be a common electrode 1 corresponding to the touch electrode 10 to simplify the circuit.
  • the plurality of common electrodes 1 corresponding to each of the touch electrodes 10 can be electrically connected through a connection line (not shown).
  • the connection lines can be formed while forming the common electrode 1 .
  • the electrode 1 is of a unitary structure.
  • a first film layer of the touch electrode 10 ie, a first film layer for forming the common electrode 1 and a portion for fabricating the signal line 11 are fabricated.
  • the two film layers are disposed adjacent to each other, and there is no other film layer between the first film layer and the second film layer.
  • the signal line 11 is connected to the corresponding touch electrode 10 and electrically connected. Specifically, the signal line 11 is overlapped on a common electrode 1 corresponding to the touch electrode 10, thereby implementing the signal line. 11 is electrically connected to the touch electrodes 10 one by one, and the specific manufacturing process is shown in FIG. 4 to FIG. 7 .
  • the signal line 11 extends from the display area to the non-display area, and the signal line 11 and the non-corresponding touch electrode 10 are in the extending direction of the signal line 11 .
  • the signal line 11 and the common electrode 1 corresponding to the touch electrode 10 are staggered, thereby realizing the signal line 11 or not.
  • the corresponding touch electrodes are not electrically connected, and the specific manufacturing process is shown in FIG. 10 to FIG.
  • the overlapping of the signal line 11 on the corresponding touch electrode 10 means that there is an overlapping area between the signal line 11 and the touch electrode 10, and the two portions are completely in contact with each other in the overlapping area.
  • a first film layer for forming the touch electrode 10 is formed, and the first film layer is patterned to form a pattern including the plurality of touch electrodes 10.
  • the material of the first film layer is a transparent conductive material, and the first film layer is patterned to form a pattern including a plurality of common electrodes 1 , and the plurality of common electrodes 1 are multiplexed into multiple contacts.
  • the control electrode 10, each touch electrode corresponds to a plurality of electrically connected common electrodes 1;
  • the material of the second film layer is a gate metal, and the second film layer is patterned, and a pattern of the gate electrode 2 including the plurality of signal lines 11, the plurality of gate lines 20, and the thin film transistor is formed.
  • the gate electrode 2 and the gate line 20 are of a unitary structure.
  • the signal line 11 may be formed first, and then the touch electrode 10 is formed.
  • the first film layer of the touch electrode 10 is not adjacent to the second film layer on which the signal line 11 is formed.
  • An insulating layer 103 is disposed between the first film layer and the second film layer.
  • An insulating layer 103 is disposed between the signal line 11 and the touch electrode 10 , and the signal line 11 is electrically connected to the corresponding touch electrode 10 through a via hole in the insulating layer 103 .
  • the corresponding production process can be:
  • first film layer Forming a first film layer on which the touch electrode 10 is formed, and patterning the first film layer to form a pattern including a plurality of touch electrodes.
  • the material of the first film layer is a transparent conductive material, and the first film layer is patterned to form a pattern including a plurality of common electrodes 1 , and the plurality of common electrodes 1 are multiplexed into multiple contacts.
  • the control electrode 10, each touch electrode corresponds to a plurality of electrically connected common electrodes 1;
  • the second film layer Forming a second film layer on which the signal line 11 is formed on the insulating layer 103, and patterning the second film layer to form a pattern including a plurality of signal lines 11 through which the signal line 11 passes
  • the hole is electrically connected to the corresponding touch electrode 10 .
  • the signal line 11 is electrically connected to a common electrode 1 of the touch electrode 10 through a via hole in the insulating layer 103 .
  • the material of the second film layer is a gate metal, and the second film layer is patterned, and a pattern of the gate electrode 2 including the plurality of signal lines 11, the plurality of gate lines 20, and the thin film transistor is formed.
  • the gate electrode 2 and the gate line 20 are of a unitary structure.
  • the signal line 11 extends from the display area to the non-display area, and the signal line 11 and the non-corresponding touch electrode 10 are in the extending direction of the signal line 11 .
  • An insulating layer 103 is disposed between them, and is electrically connected.
  • the structure shown in FIG. 15 does not need to displace the signal line 11 and the non-corresponding touch electrode 10, which reduces the influence of the signal line 11 on the pixel aperture ratio.
  • the signal line 11 may be formed first, and then the touch electrode 10 is formed.
  • the second film layer for forming the signal line 11 may also be a source/drain metal layer, specifically, the source electrode 3 and the drain electrode formed on the data line 30 and the thin film transistor.
  • the signal line 11 parallel to the data line 30 is simultaneously formed by the same source/drain metal layer, and the signal line 11 is disposed in the same material as the data line 30, the source electrode 3 and the drain electrode 4, and the signal line 11 is The data lines 30 are staggered at a certain distance to achieve insulation.
  • the A-ADS type thin film transistor array substrate in the embodiment of the present disclosure specifically includes:
  • a substrate substrate 100 such as a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate, which includes a plurality of pixel regions;
  • each of the common electrodes 1 being located in a corresponding pixel region, the plurality of common electrodes 1 being multiplexed into a plurality of touch electrodes 10, each of the touch electrodes 10 corresponds to a plurality of electrically connected common electrodes 1;
  • the signal line 11 is in one-to-one correspondence with the touch electrode 10, and the signal line 11 is overlapped on a common electrode 1 corresponding to the touch electrode 10;
  • a gate insulating layer 101 disposed on the base substrate 100;
  • An ohmic contact layer 7 disposed on the semiconductor layer 6;
  • a plurality of data lines 30, a thin film transistor source electrode 3 and a drain electrode 4 are disposed on the base substrate 100, and the gate lines 20 and the data lines 30 are laterally and vertically distributed to define the plurality of pixel regions.
  • the source electrode 3 and the drain electrode 4 are overlapped on opposite sides of the active layer 6 through the ohmic contact layer 7, and the ohmic contact layer 7 is used to reduce the source electrode 3 and the drain electrode 4 Contact resistance of the semiconductor layer 6;
  • a passivation layer 102 disposed on the thin film transistor, the passivation layer 102 including a via;
  • a pixel electrode 5 disposed on the passivation layer 102, the pixel electrode 5 being electrically connected to the drain electrode 4 of the thin film transistor through a via hole in the passivation layer 102.
  • the method for fabricating the A-ADS thin film transistor array substrate specifically includes:
  • Step S1 providing a substrate substrate 100, the substrate substrate 100 includes a plurality of pixel regions;
  • Step S2 forming a plurality of common electrodes 1 on the base substrate 100 of the step S1, each common electrode 1 is located in a corresponding pixel region, and the plurality of common electrodes 1 are multiplexed into a plurality of touch electrodes 10, each The touch electrodes 10 are electrically connected to the plurality of common electrodes 1 through a connection line, and the connection lines are integrated with the common electrode 1 , as shown in FIG. 4 and FIG. 6 ;
  • the common electrode 1 is made of a transparent conductive material such as indium zinc oxide or indium tin oxide.
  • a transparent conductive layer is formed on the base substrate 100 by physical deposition, chemical sputtering, or other film formation method;
  • a photoresist is coated on the transparent conductive film layer, and the photoresist is exposed and developed to form a photoresist retention region and a photoresist non-retention region, and the photoresist retention region corresponds to a common Where the electrode and the connecting line are located, the photoresist non-reserved area corresponds to other areas;
  • the remaining photoresist is removed to form a pattern including the common electrode 1 and the connecting lines, and the two ends of the connecting line are respectively connected to the two adjacent common electrodes 1 to electrically connect the plurality of corresponding touch electrodes 10 Common electrode 1.
  • Step S3 forming a gate metal layer on the base substrate 100 completing step S2, and patterning the gate metal layer to form a plurality of gate lines 20, signal lines 11 and gate electrodes 2 of the thin film transistors, the signal lines 11 is parallel to the gate line 20, and the signal line 11 extends from the display area to the non-display area, and one end of the signal line 11 is overlapped on a common electrode 1 corresponding to the touch electrode 10 to realize electrical connection with the corresponding touch electrode 10. See Figure 4 and Figure 6.
  • the signal line 11 is disposed at a distance from the non-corresponding touch electrode 10 to achieve insulation, that is, the common electrode 1 of the signal line 11 corresponding to the touch electrode 10 in the extending direction of the signal line 11 Staggered a certain distance setting, as shown in Figure 10 and Figure 12;
  • the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or a multilayer structure,
  • the layer structure is, for example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, and the like.
  • Step S4 forming a gate insulating layer 101 on the base substrate 100 completing step S3, as shown in FIGS. 5 and 7, and FIGS. 11 and 13;
  • the material of the gate insulating layer 101 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the material of the gate insulating layer 101 may be SiNx, SiOx or Si(ON)x.
  • Step S5 forming a thin film transistor active active layer pattern 6 on the base substrate 100 completing step S4, as shown in FIGS. 5 and 7, and FIGS. 11 and 13;
  • the material of the active layer 6 may be selected from a silicon semiconductor or a metal oxide semiconductor (eg, indium zinc oxide, indium tin oxide).
  • Step S6 sequentially forming an ohmic contact layer and a source/drain metal layer on the base substrate 100 completing step S5, applying a photoresist on the source/drain metal layer, exposing and developing the photoresist. a photoresist retention region and a photoresist non-retention region, etching away the source/drain metal layer and the ohmic contact layer of the photoresist non-retained region, stripping the remaining photoresist, forming the ohmic contact layer pattern 7 and the source electrode 3
  • the drain electrode 4, the source electrode 3 and the drain electrode 4 are overlapped by the ohmic contact layer 7 at the active
  • the source/drain metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the source/drain metal layer may be a single layer structure or a multilayer structure. , multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.
  • Step S7 forming a passivation layer 102 on the base substrate 100 completing step S6, patterning the passivation layer 103 to form via holes, as shown in FIGS. 2 and 3, and FIGS. 8 and 9.
  • the material of the passivation layer 102 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the material of the passivation layer 102 may be SiNx, SiOx or Si(ON)x.
  • Step S8 forming a pixel electrode 5 on the base substrate 100 of the step S7, the pixel electrode 5 being electrically connected to the drain electrode 4 of the thin film transistor through a via hole in the passivation layer 102, in combination with FIG. 2 and FIG. 3, and as shown in Figures 8 and 9.
  • the pixel electrode 5 is made of a transparent conductive material such as indium zinc oxide or indium tin oxide.
  • a display device which uses the ADS array substrate as described above to implement in-cell touch and reduce the thickness of the touch display device. And overcome the problem of ghost point phenomenon in the self-capacitive touch detection in the current related operation, shorten the touch detection time and improve the touch detection sensitivity.
  • the display device may be: a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • the technical solution of the present disclosure multiplexes the common electrode of the ADS array substrate into a touch electrode to realize in-cell touch, which can reduce the thickness of the touch display device. And setting a signal line electrically connected to the touch electrode one by one, and detecting whether the self-capacitance of the touch electrode changes by a corresponding signal line during a touch time period of displaying the time of one frame, and determining the touch position.
  • the signal lines are in one-to-one correspondence with the touch electrodes, when a plurality of touch electrodes are simultaneously touched, multiple touch positions can be accurately detected, thereby overcoming the ghost phenomenon that occurs in the self-capacitive touch detection in the related art. .
  • the self-capacitance of all the touch electrodes can be detected together, and the horizontal and vertical touch electrode arrays are sequentially detected in the related art, which shortens the detection time and improves the touch sensitivity.

Abstract

一种ADS阵列基板及其制作方法、显示器件。所述ADS阵列基板的公共电极（1）复用为触控电极（10），并设置与触控电极（10）一一对应电性连接的信号线（11），在一帧画面显示时间的触控时间段，通过对应的信号线（11）检测触控电极（10）的自电容是否发生变化，确定触摸位置。由于信号线（11）与触控电极（10）一一对应，通过每条信号线获得的检测信号唯一对应一个触控电极（10），即使多个触控电极（10）被同时触摸，也能够精确确定所述多个触摸位置。

Description

ADS阵列基板及其制作方法、显示器件
相关申请的交叉引用
本申请主张在2015年7月14日在中国提交的中国专利申请号No.201510412185.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及触控显示技术领域，特别是涉及一种ADS阵列基板及其制作方法、显示器件。
背景技术
在触控屏技术中，相对于电阻式触控屏，电容式触控屏具有寿命长、透光率高、可以支持多点触控等优点。并且，电容式触控屏对噪声和对地寄生电容也有很好的抑制作用。因此，电容式触控屏已成为如今触控屏制造的热点之一。电容式触控屏包括自容式触控屏和互容式触控屏，由于自容式触控屏只需一层触控电极，通过检测触控电极的自电容是否发生变化，即可实现触摸检测，具有结构简单、便于实现等优点。
近年来，显示器件的厚度越来越薄，内嵌式触控显示器件通过将触控屏的触控电极内嵌在显示屏内部，达到了减薄显示器件的厚度的目的，同时又大大降低了触控显示器件的制造成本，受到各大面板厂家的青睐。
发明内容
本公开提供一种ADS阵列基板及其制作方法、显示器件，用以实现内嵌式触控显示。
为解决上述技术问题，本公开实施例中提供一种ADS阵列基板，包括显示区域和位于显示区域周边的非显示区域，所述阵列基板的显示区域包括多个像素单元，每个像素单元包括公共电极和像素电极，所述阵列基板的一帧画面显示时间包括显示时间段和触控时间段，所述多个公共电极复用为多个触控电极，每个触控电极对应多个电性连接的公共电极，所述阵列基板还包 括：
多条信号线，所述信号线与触控电极一一对应电性连接，在一帧画面显示时间的显示时间段，通过对应的信号线向触控电极传递公共电压信号，在一帧画面显示时间的触控时间段，通过对应的信号线检测触控电极的自电容是否发生变化。
如上所述的阵列基板，可选的是，所述阵列基板为薄膜晶体管阵列基板，所述阵列基板包括横纵交叉分布的栅线和数据线，用于限定所述多个像素单元所在的区域，每个像素单元还包括薄膜晶体管；
所述信号线与所述栅线和所述薄膜晶体管的栅电极为同层同材料设置，或，与所述数据线和所述薄膜晶体管的源电极、漏电极为同层同材料设置。
如上所述的阵列基板，可选的是，所述信号线搭接在对应的触控电极上，电性接触。
如上所述的阵列基板，可选的是，所述阵列基板具体包括：
衬底基板；
设置在衬底基板上的多个公共电极；
同层同材料设置的多条栅线、多条信号线和薄膜晶体管的栅电极，所述信号线搭接在对应的触控电极上；
覆盖所述栅线、信号线和栅电极的栅绝缘层；
设置在所述栅绝缘层上的有源层图案；
同层同材料设置的多条数据线和薄膜晶体管源电极、漏电极，所述源电极和漏电极搭接在所述有源层的相对两侧；
覆盖所述薄膜晶体管的钝化层，所述钝化层包括过孔；
设置在所述钝化层上的像素电极，所述像素电极通过所述钝化层中的过孔与所述漏电极电性连接。
如上所述的阵列基板，可选的是，所述信号线与触控电极之间设置有绝缘层，所述信号线通过绝缘层中的过孔与对应的触控电极电性连接。
如上所述的阵列基板，可选的是，所述信号线位于显示区域的部分与所述栅线平行设置，或，所述信号线位于显示区域的部分与所述数据线平行设置。
如上所述的阵列基板，可选的是，所述公共电极为板状电极，所述像素电极为狭缝电极。
如上所述的阵列基板，可选的是，所述像素电极具有多个狭缝，所述狭缝包括多个平行设置的第一狭缝和多个平行设置的第二狭缝，所述第一狭缝和所述第二狭缝与所述栅线之间呈一定夹角；所述第一狭缝和第二狭缝对称分布在所述像素电极平行于所述栅线的中心轴两侧。
如上所述的阵列基板，可选的是，所述信号线从显示区域延伸至非显示区域；所述阵列基板为矩形结构，所述信号线从显示区域延伸至阵列基板的长边所在侧。
本公开实施例中还提供一种如上所述的ADS阵列基板的制作方法，所述阵列基板包括显示区域和位于显示区域周边的非显示区域，所述制作方法包括在阵列基板的显示区域形成多个像素单元的步骤，每个像素单元包括公共电极和像素电极，所述阵列基板的一帧画面显示时间包括显示时间段和触控时间段，所述多个公共电极复用为多个触控电极，每个触控电极对应多个电性连接的公共电极，所述制作方法还包括：
形成多条信号线，所述信号线与触控电极一一对应电性连接，在一帧画面显示时间的显示时间段，通过对应的信号线向触控电极传递公共电压信号，在一帧画面显示时间的触控时间段，通过对应的信号线检测触控电极的自电容是否发生变化。
如上所述的制作方法，可选的是，所述阵列基板为薄膜晶体管阵列基板，所述阵列基板包括横纵交叉分布的栅线和数据线，用于限定所述多个像素单元所在的区域，每个像素单元还包括薄膜晶体管；
形成多条信号线的步骤具体为：
通过对同一栅金属层的构图工艺形成所述信号线、所述栅线和所述薄膜晶体管的栅电极，或，通过对同一源漏金属层的构图工艺形成所述信号线、所述数据线和所述薄膜晶体管的源电极、漏电极。
如上所述的制作方法，可选的是，所述形成多个像素单元的步骤包括：形成透明导电层，对所述透明导电层进行构图工艺，形成多个公共电极；
所述形成多条信号线的步骤包括：
在公共电极上形成栅金属层，对所述栅金属层进行构图工艺，形成包括所述信号线、所述栅线和薄膜晶体管的栅电极的图案，其中，所述信号线搭接在对应的触控电极上，电性接触。
如上所述的制作方法，可选的是，所述形成多个像素单元的步骤包括：
提供一衬底基板；
在所述衬底基板上形成多个公共电极；
所述形成多条信号线的步骤包括：
在所述公共电极上形成栅金属层，对所述栅金属层进行构图工艺，形成多条栅线、多条信号线和薄膜晶体管的栅电极，所述信号线搭接在对应的触控电极上；
所述制作方法还包括：
形成覆盖所述栅线、信号线和栅电极的栅绝缘层；
在所述栅绝缘层上形成有源层图案；
在所述有源层上形成源漏金属层，对所述源漏金属层进行构图工艺，形成多条数据线和薄膜晶体管源电极、漏电极，所述源电极和漏电极搭接在所述有源层的相对两侧；
形成覆盖所述薄膜晶体管的钝化层，对所述钝化层进行构图工艺形成过孔；
在所述钝化层上形成像素电极，所述像素电极通过所述钝化层中的过孔与所述漏电极电性连接。
如上所述的制作方法，可选的是，所述形成多个像素单元的步骤包括：
形成透明导电层，对所述透明导电层进行构图工艺，形成多个公共电极；
所述制作方法还包括：在公共电极上形成绝缘层，对所述绝缘层进行构图工艺，形成过孔；
所述形成多条信号线的步骤包括：在所述绝缘层上形成栅金属层，对所述栅金属层进行构图工艺，形成包括所述信号线、所述栅线和薄膜晶体管的栅电极的图案，其中，所述信号线通过所述绝缘层中的过孔与对应的触控电极电性连接。
本公开实施例中还提供一种显示器件，采用如上所述的ADS阵列基板。
本公开的上述技术方案的有益效果如下：
上述技术方案中，将ADS阵列基板的公共电极复用为触控电极，能够实现内嵌式触控，减薄触摸显示器件的厚度。同时，还能够克服相关技术中自容式触控检测会出现的鬼点现象，缩短检测时间，提高触控灵敏度。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1表示本公开实施例中ADS阵列基板的结构示意图；
图2表示图1中ADS阵列基板的一个像素单元的结构示意图，显示信号线与对应的触控电极之间的连接关系；
图3表示图2沿A-A的剖视图一；
图4和图5表示图2中像素单元的制作过程示意图；
图6表示图4沿A-A的剖视图；
图7表示图5沿A-A的剖视图；
图8表示图1中ADS阵列基板的另一个像素单元的结构示意图，显示信号线与不对应的触控电极之间的关系；
图9表示图8沿B-B的剖视图一；
图10和图11表示图8中像素单元的制作过程示意图；
图12表示图10沿B-B的剖视图；
图13表示图11沿B-B的剖视图；
图14表示图2沿A-A的剖视图二；
图15表示图8沿B-B的剖视图二；
图16表示图1中ADS阵列基板的一个像素单元的结构示意图，显示信号线与数据线平行；
图17表示图16沿A-A的剖视图。
具体实施方式
在详细介绍本公开的技术方案之前，首先对本公开涉及的概念及工作原理进行如下解释：
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，简称TFT-LCD)的主体结构为液晶面板，液晶面板包括对盒的薄膜晶体管阵列基板和彩膜基板，液晶分子填充在阵列基板和彩膜基板之间。阵列基板包括多条栅线和多条数据线，用于限定多个像素单元所在的区域，每个像素单元包括薄膜晶体管、像素电极和公共电极，通过栅线打开薄膜晶体管，数据线上的像素电压通过薄膜晶体管传输至像素电极，从而公共电极与像素电极之间形成驱动液晶分子偏转特定角度的电场，实现灰阶显示。彩膜基板上的滤光层用于实现彩色显示。TFT-LCD具有体积小，功耗低，无辐射等特点，近年来得到迅速发展，在当前的平板显示器市场中占据主导地位。
高级超维场开关(ADS，Advanced Super Dimension Switch)显示模式：公共电极和像素电极均形成在阵列基板上，主要是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。ADS技术可以提高TFT-LCD的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。
对于大尺寸的ADS型TFT-LCD，采用A-ADS的像素结构，其像素电极为狭缝电极，公共电极为板状电极，像素电极位于公共电极靠近液晶分子的一侧，且像素电极上的狭缝与栅线平行，为水平狭缝。A-ADS的像素结构具有光效好，栅线和数据线的耦合电容小，负载小的优势，适用于大尺寸的ADS型TFT-LCD。
电容式触控检测：包括自容式触控检测和互容式触控检测，由于自容式触控检测只需一层触控电极，通过检测触控电极的自电容是否发生变化，即可实现触摸检测，具有结构简单、便于实现等优点。其中，触控电极的自电容为其对地电容。
相关技术中的自容式触控屏，其触控电极呈二维阵列分布，触摸检测方 法可以为：利用单个触控电极自身的自电容变化传输电荷，由一端接地，另一端接激励或采样电路来检测自电容的变化。具体为，依次检测横向和纵向触控电极阵列，根据触摸前后自电容的变化分别确定触摸点的横向坐标和纵向坐标，组合成平面坐标确定触摸位置。当触摸点只有一个时，组合后的坐标也是唯一的一个，可以准确定位；但是，当触摸点有两个时，横向和纵向分别有两个坐标，两两组合后出现四组坐标，其中只有两个是真实触摸点，另两个就是俗称的“鬼点”，无法实现真正的多点触摸。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
图1所示为本公开实施例中ADS阵列基板的结构示意图；图2所示为图1中ADS阵列基板的一个像素单元的结构示意图；图3所示为图2沿A-A的剖视图。
结合图1-图3所示，本公开实施例中提供一种ADS阵列基板，包括显示区域和位于显示区域周边的非显示区域，所述阵列基板的显示区域包括多个像素单元，每个像素单元包括公共电极1和像素电极5。所述多个公共电极1复用为多个触控电极10，每个触控电极10对应多个电性连接的公共电极1，实现触摸屏内嵌至显示面板内，减薄触控显示器件的厚度。
所述阵列基板还包括多条信号线11，所述信号线11与触控电极10一一对应电性连接，如图1所示。所述阵列基板的一帧画面显示时间包括显示时间段和触控时间段。在一帧画面显示时间的显示时间段，通过对应的信号线11向触控电极10传递公共电压信号，为公共电极1提供基准电压，公共电极1与像素电极5之间形成驱动液晶分子偏转特定角度的电场，结合图2和图3所示；在一帧画面显示时间的触控时间段，通过对应的信号线11检测触控电极10的自电容是否发生变化，确定触摸位置。另外，由于信号线11与触控电极10一一对应，通过每条信号线11获得的检测信号唯一对应一个触控电极10，即使多个触控电极10被同时触摸，也能够精确确定所述多个触摸位置，克服了相关技术中自容式触控检测会出现的鬼点现象。而且所有触控电极10的自电容能够同时进行检测，相对于相关技术中依次检测横向和纵向触控电极阵列，缩短了检测时间，提高了触控灵敏度。
其中，所述公共电极1的形状可以为规则形状，如：矩形、菱形、三角形、圆形或椭圆形，也可以为不规则形状，不作具体的限定。对于每个触控电极10对应的公共电极1的个数，也不作具体的限定，以满足触控检测的精度需求为准。
ADS阵列基板具体可以为薄膜晶体管阵列基板，包括多条栅线20和多条数据线30，用于限定多个像素单元所在的区域，每个像素单元还包括薄膜晶体管。由于每个公共电极1仅位于像素单元所在的区域，与栅线20、数据线30不交叠，减小了公共电极1与栅线20、数据线30的耦合电容，当公共电极1复用为触控电极10时，最大限度降低了触控检测的响应时间。
可选地，所述信号线11与所述薄膜晶体管的栅电极2为同层同材料设置，或，与所述薄膜晶体管的源电极3和漏电极4为同层同材料设置。即，所述信号线11与所述薄膜晶体管的栅电极2通过对同一栅金属层的构图工艺同时形成，或，所述信号线11与所述薄膜晶体管的源电极3和漏电极4通过对同一源漏金属层的构图工艺同时形成，缺省了单独制作信号线11的工艺和材料，降低生产成本。由于透明导电材料的电阻率大于栅金属和源漏金属的电阻率，因此，一般不通过透明导电层来制作所述信号线11。
由于所述信号线11需要从显示区域延伸至非显示区域，一般而言，信号线11应尽量均匀分布，且走线尽量短，尽量窄。具体可以设置所述信号线11位于显示区域的部分与所述栅线20或数据线30平行。而位于非显示区域的部分可以平行分布，也可以扇形分布。当阵列基板为矩形时，所述信号线11从显示区域延伸至阵列基板的长边所在侧，以减小信号线11的长度，参见图1所示。
本公开实施例中设置所述信号线11与所述薄膜晶体管的栅电极2为同层同材料设置，且所述信号线11位于显示区域的部分与所述栅线20平行设置，栅线20与信号线11错开间隔一定的距离，实现绝缘。或，如图16和图17所示，所述信号线11与所述薄膜晶体管的源电极3和漏电极4为同层同材料设置，且所述信号线11位于显示区域的部分与所述数据线30平行设置，数据线30与信号线11错开间隔一定的距离，实现绝缘。
本公开的技术方案将公共电极复用为自容式触控屏的触控电极，实现内 嵌式触控，减薄了显示器件的厚度。同时，还能够克服相关技术中自容式触控屏会出现鬼点现象的问题，缩短触控检测时间，提高触控灵敏度。
本公开实施例中的ADS阵列基板尤其为大尺寸显示器件采用的A-ADS阵列基板，所述公共电极1为板状电极，所述像素电极5为狭缝电极，具有多个狭缝，具有光效好、耦合电容小、负载小等优点，结合图2和图3所示。对于A-ADS型薄膜晶体管阵列基板，可选地，如图2所示，所述像素电极5的狭缝包括多个平行设置的第一狭缝51和多个平行设置的第二狭缝52，所述第一狭缝51和所述第二狭缝52分别与栅线20之间呈一定夹角d(通常，2°≤|α|≤5°)，且所述第一狭缝51和第二狭缝52对称地分布在像素电极5平行于栅线20的中心轴00’两侧；这样，像素电极5具有第一狭缝51的部分与公共电极1之间形成第一电场，像素电极5具有第二狭缝52的部分与公共电极1之间形成第二电场，且第一电场与第二电场的方向不同，增加显示器件的视角。
由于触控电极10对应多个电性连接的公共电极1，所述信号线11与触控电极10的电性连接，转换为所述信号线11与触控电极10对应的至少一个公共电极1电性连接。具体的，所述信号线11与触控电极10对应的一个公共电极1即可，以简化线路。而每个触控电极10对应的多个公共电极1可以通过连接线(图中未示出)电性连接，具体可以在形成公共电极1的同时形成所述连接线，所述连接线与公共电极1为一体结构。
下面以所述信号线11与触控电极10对应的一个公共电极1来介绍所述信号线11与触控电极10电性连接的具体方案。
在一个具体的实施方式中，结合图2和图3所示，制作所述触控电极10的第一膜层(即制作公共电极1的第一膜层)与制作所述信号线11的第二膜层相邻设置，所述第一膜层和第二膜层之间没有其他膜层。所述信号线11搭接在对应的触控电极10上，电性接触，具体为，所述信号线11搭接在该触控电极10对应的一个公共电极1上，从而实现所述信号线11与触控电极10的一一对应电性连接，具体的制作过程详见图4-图7所示。
结合图1、图8和图9所示，所述信号线11从显示区域延伸至非显示区域，在所述信号线11的延伸方向上，所述信号线11与不对应的触控电极10 错开设置，不电性连接，具体为，在所述信号线11的延伸方向上，所述信号线11与该触控电极10对应的公共电极1错开设置，从而实现所述信号线11与不对应的触控电极不电性连接，具体的制作过程详见图10-图13所示。
需要说明的是，所述信号线11搭接在对应的触控电极10上是指：所述信号线11和触控电极10之间存在交叠区域，两者位于交叠区域的部分完全接触设置。结合图4和图6所示，对应的制作工艺可以为：
形成制作触控电极10的第一膜层，对所述第一膜层进行构图工艺，形成包括多个触控电极10的图案。具体的，所述第一膜层的材料为透明导电材料，对所述第一膜层进行构图工艺，形成包括多个公共电极1的图案，所述多个公共电极1复用为多个触控电极10，每个触控电极对应多个电性连接的公共电极1；
在所述第一膜层上形成制作信号线11的第二膜层，对所述第二膜层进行构图工艺，形成包括多条信号线11的图案，其中，所述信号线11搭接在对应的触控电极10上，具体为，所述信号线11搭接在该触控电极10的一个公共电极1上。
具体的，所述第二膜层的材料为栅金属，对所述第二膜层进行构图工艺，同时形成包括多条信号线11、多条栅线20和薄膜晶体管的栅电极2的图案，栅电极2与栅线20为一体结构。
在上述步骤中，也可以先形成信号线11，然后再形成触控电极10。
在另一个具体的实施方式中，结合图2和图14所示，制作所述触控电极10的第一膜层与制作所述信号线11的第二膜层不相邻设置，所述第一膜层和第二膜层之间设置有绝缘层103。即所述信号线11与触控电极10之间设置有绝缘层103，所述信号线11通过绝缘层103中的过孔与对应的触控电极10电性连接。对应的制作工艺可以为：
形成制作触控电极10的第一膜层，对所述第一膜层进行构图工艺，形成包括多个触控电极的图案。具体的，所述第一膜层的材料为透明导电材料，对所述第一膜层进行构图工艺，形成包括多个公共电极1的图案，所述多个公共电极1复用为多个触控电极10，每个触控电极对应多个电性连接的公共电极1；
在所述第一膜层上形成绝缘层103，对所述绝缘层103进行构图工艺，在所述绝缘层103中形成过孔；
在所述绝缘层103上形成制作信号线11的第二膜层，对所述第二膜层进行构图工艺，形成包括多个信号线11的图案，其中，所述信号线11通过所述过孔与对应的触控电极10电性连接，具体为，所述信号线11通过所述绝缘层103中的过孔与该触控电极10的一个公共电极1电性连接。具体的，所述第二膜层的材料为栅金属，对所述第二膜层进行构图工艺，同时形成包括多条信号线11、多条栅线20和薄膜晶体管的栅电极2的图案，栅电极2与栅线20为一体结构。
结合图1、图8和图15所示，所述信号线11从显示区域延伸至非显示区域，在所述信号线11的延伸方向上，所述信号线11与不对应的触控电极10之间设置有绝缘层103，不电性连接。相对于图9所示结构而言，图15所示的结构不需要令信号线11与不对应的触控电极10错开设置，减少了信号线11对像素开口率的影响。
在上述步骤中，也可以先形成信号线11，然后再形成触控电极10。
在上述具体实施方式中，当ADS阵列基板为薄膜晶体管阵列基板，制作信号线11的第二膜层也可以为源漏金属层，具体可以在形成数据线30与薄膜晶体管的源电极3和漏电极4时，由同一源漏金属层同时形成与所述数据线30平行的信号线11，信号线11与数据线30、源电极3和漏电极4同层同材料设置，且信号线11与数据线30错开间隔一定距离设置，实现绝缘。
以底栅型薄膜晶体管为例，结合图1-图3、图8和图9所示，本公开实施例中A-ADS型薄膜晶体管阵列基板具体包括：
衬底基板100，如：玻璃基板、石英基板、有机树脂基板等透明基板，其包括多个像素区域；
设置在所述衬底基板100上的多个公共电极1，每个公共电极1位于对应的像素区域内，所述多个公共电极1复用为多个触控电极10，每个触控电极10对应多个电性连接的公共电极1；
设置在所述衬底基板100上的多条栅线20、多条信号线11和薄膜晶体管的栅电极2，所述栅线20、信号线11和栅电极2同层同材料设置，所述信 号线11与触控电极10一一对应，所述信号线11搭接在触控电极10对应的一个公共电极1上；
设置在所述衬底基板100上的栅绝缘层101；
设置在所述栅绝缘层101上的薄膜晶体管的有源层图案6，所述有源层6的材料为硅半导体或金属氧化物半导体；
设置在所述半导体层6上的欧姆接触层7；
设置在所述衬底基板100上的多条数据线30、薄膜晶体管源电极3和漏电极4，所述栅线20和数据线30横纵交叉分布，限定所述多个像素区域。所述源电极3和漏电极4通过所述欧姆接触层7搭接在所述有源层6的相对两侧，所述欧姆接触层7用于减小所述源电极3和漏电极4与半导体层6的接触电阻；
设置在所述薄膜晶体管上的钝化层102，所述钝化层102包括过孔；
设置在所述钝化层102上的像素电极5，所述像素电极5通过所述钝化层102中的过孔与薄膜晶体管的漏电极4电性连接。
结合图1、图2-图7，以及图8-图13所示，上述A-ADS型薄膜晶体管阵列基板制作方法具体包括：
步骤S1、提供一衬底基板100，所述衬底基板100包括多个像素区域；
步骤S2、在完成步骤S1的衬底基板100上形成多个公共电极1，每个公共电极1位于对应的像素区域内，所述多个公共电极1复用为多个触控电极10，每个触控电极10对应多个的公共电极1通过连接线电性连接，所述连接线与所述公共电极1为一体结构，参见图4和图6所示；
所述公共电极1由透明导电材料制作而成，如：铟锌氧化物或铟锡氧化物。
具体的：
首先，通过物理沉积、化学溅射或其他成膜方法在衬底基板100形成透明导电层；
之后，在所述透明导电膜层上涂覆光刻胶，对所述光刻胶进行曝光，显影，形成光刻胶保留区域和光刻胶不保留区域，所述光刻胶保留区域对应公共电极和连接线所在的区域，所述光刻胶不保留区域对应其他区域；
然后，以保留的光刻胶为阻挡去除光刻胶不保留区域的透明导电层；
最后，去除剩余的光刻胶，形成包括公共电极1和连接线的图案，所述连接线的两端分别连接相邻的两个公共电极1，从而电性连接触控电极10对应的多个公共电极1。
步骤S3、在完成步骤S2的衬底基板100上形成栅金属层，对所述栅金属层进行构图工艺，形成多条栅线20、信号线11和薄膜晶体管的栅电极2，所述信号线11与栅线20平行，所述信号线11从显示区域延伸至非显示区域，其一端搭接在触控电极10对应的一个公共电极1上，实现与对应的触控电极10的电性连接，参见图4和图6所示。而所述信号线11与不对应的触控电极10错开一定距离设置，实现绝缘，即，所述信号线11的延伸方向上，所述信号线11与该触控电极10对应的公共电极1错开一定距离设置，结合图10和图12所示；
所述栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤S4、在完成步骤S3的衬底基板100上形成栅绝缘层101，结合图5和图7，以及图11和图13所示；
栅绝缘层101的材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，栅绝缘层101的材料可以是SiNx，SiOx或Si(ON)x。
步骤S5、在完成步骤S4的衬底基板100上形成薄膜晶体管有源的有源层图案6，结合图5和图7，以及图11和图13所示；
所述有源层6的材料可以选择硅半导体或金属氧化物半导体(如：铟锌氧化物、铟锡氧化物)。
步骤S6、在完成步骤S5的衬底基板100上依次形成欧姆接触层和源漏金属层，在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影，形成光刻胶保留区域和光刻胶不保留区域，刻蚀掉光刻胶不保留区域的源漏金属层和欧姆接触层，剥离剩余的光刻胶，形成欧姆接触层的图案7和源电极3、漏电极4，所述源电极3和漏电极4通过欧姆接触层7搭接在所述有源 层6的相对两侧，结合图5和图7，以及图11和图13所示；
所述源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，源漏金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤S7、在完成步骤S6的衬底基板100上形成钝化层102，对所述钝化层103进行构图工艺，形成过孔，结合图2和图3，以及图8和图9所示；
钝化层102的材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，钝化层102的材料可以是SiNx，SiOx或Si(ON)x。
步骤S8、在完成步骤S7的衬底基板100上形成像素电极5，所述像素电极5通过所述钝化层102中的过孔与薄膜晶体管的漏电极4电性连接，结合图2和图3，以及图8和图9所示。
所述像素电极5由透明导电材料制作而成，如：铟锌氧化物或铟锡氧化物。
至此完成阵列基板的制作。
本公开实施例中还提供一种显示器件，采用如上所述的ADS阵列基板，用以实现内嵌式触控，减薄触控显示器件的厚度。并克服现相关术中自容式触控检测会出现鬼点现象的问题，缩短触控检测时间，提高触控检测灵敏度。
所述显示器件可以为：液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的技术方案将ADS阵列基板的公共电极复用为触控电极，实现内嵌式触控，能够减薄触摸显示器件的厚度。并设置与触控电极一一对应电性连接的信号线，在一帧画面显示时间的触控时间段，通过对应的信号线检测触控电极的自电容是否发生变化，确定触摸位置。另外，由于信号线与触控电极一一对应，当多个触控电极被同时触摸时，也可以精确检测多个触摸位置，克服了相关技术中自容式触控检测会出现的鬼点现象。而且所有触控电极的自电容能够一起进行检测，相对于相关技术中依次检测横向和纵向触控电极阵列，缩短了检测时间，提高了触控灵敏度。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进 和替换，这些改进和替换也应视为本公开的保护范围。

Claims (15)

  1. 一种ADS阵列基板，包括显示区域和位于显示区域周边的非显示区域，所述阵列基板的显示区域包括多个像素单元，每个像素单元包括公共电极和像素电极；其中，所述阵列基板的一帧画面显示时间包括显示时间段和触控时间段，所述多个公共电极复用为多个触控电极，每个触控电极对应多个电性连接的公共电极，所述阵列基板还包括：
    多条信号线，所述信号线与触控电极一一对应电性连接，在一帧画面显示时间的显示时间段，通过对应的信号线向触控电极传递公共电压信号，在一帧画面显示时间的触控时间段，通过对应的信号线检测触控电极的自电容是否发生变化。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板为薄膜晶体管阵列基板，所述阵列基板包括横纵交叉分布的栅线和数据线，用于限定所述多个像素单元所在的区域，每个像素单元还包括薄膜晶体管；
    所述信号线、所述栅线和所述薄膜晶体管的栅电极为同层同材料设置，或，与所述数据线和所述薄膜晶体管的源电极、漏电极为同层同材料设置。
  3. 根据权利要求2所述的阵列基板，其中，所述信号线搭接在对应的触控电极上，电性接触。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板具体包括：
    衬底基板；
    设置在衬底基板上的多个公共电极；
    同层同材料设置的多条栅线、多条信号线和薄膜晶体管的栅电极，所述信号线搭接在对应的触控电极上；
    覆盖所述栅线、信号线和栅电极的栅绝缘层；
    设置在所述栅绝缘层上的有源层图案；
    同层同材料设置的多条数据线和薄膜晶体管源电极、漏电极，所述源电极和漏电极搭接在所述有源层的相对两侧；
    覆盖所述薄膜晶体管的钝化层，所述钝化层包括过孔；
    设置在所述钝化层上的像素电极，所述像素电极通过所述钝化层中的过 孔与所述漏电极电性连接。
  5. 根据权利要求2所述的阵列基板，其中，所述信号线与触控电极之间设置有绝缘层，所述信号线通过所述绝缘层中的过孔与对应的触控电极电性连接。
  6. 根据权利要求2所述的阵列基板，其中，所述信号线位于显示区域的部分与所述栅线平行设置，或，所述信号线位于显示区域的部分与所述数据线平行设置。
  7. 根据权利要求2-6任一项所述的阵列基板，其中，所述公共电极为板状电极，所述像素电极为狭缝电极。
  8. 根据权利要求7所述的阵列基板，其中，所述像素电极具有多个狭缝；所述狭缝包括多个平行设置的第一狭缝和多个平行设置的第二狭缝，所述第一狭缝和所述第二狭缝与所述栅线之间呈一定夹角；
    所述第一狭缝和第二狭缝对称分布在所述像素电极平行于所述栅线的中心轴两侧。
  9. 根据权利要求1-5任一项所述的阵列基板，其中，所述信号线从显示区域延伸至非显示区域；所述阵列基板为矩形结构，所述信号线从显示区域延伸至阵列基板的长边所在侧。
  10. 一种权利要求1-9任一项所述的ADS阵列基板的制作方法，所述阵列基板包括显示区域和位于显示区域周边的非显示区域，所述制作方法包括在阵列基板的显示区域形成多个像素单元的步骤，每个像素单元包括公共电极和像素电极，其中，所述阵列基板的一帧画面显示时间包括显示时间段和触控时间段，所述多个公共电极复用为多个触控电极，每个触控电极对应多个电性连接的公共电极，所述制作方法还包括：
    形成多条信号线，所述信号线与触控电极一一对应电性连接，在一帧画面显示时间的显示时间段，通过对应的信号线向触控电极传递公共电压信号，在一帧画面显示时间的触控时间段，通过对应的信号线检测触控电极的自电容是否发生变化。
  11. 根据权利要求10所述的制作方法，其中，所述阵列基板为薄膜晶体管阵列基板，所述阵列基板包括横纵交叉分布的栅线和数据线，用于限定所 述多个像素单元所在的区域，每个像素单元还包括薄膜晶体管；
    形成多条信号线的步骤具体为：
    通过对同一栅金属层的构图工艺形成所述信号线、所述栅线和所述薄膜晶体管的栅电极，或，通过对同一源漏金属层的构图工艺形成所述信号线、所述数据线和所述薄膜晶体管的源电极、漏电极。
  12. 根据权利要求10所述的制作方法，其中，所述形成多个像素单元的步骤包括：形成透明导电层，对所述透明导电层进行构图工艺，形成多个公共电极；
    所述形成多条信号线的步骤包括：
    在公共电极上形成栅金属层，对所述栅金属层进行构图工艺，形成包括所述信号线、所述栅线和薄膜晶体管的栅电极的图案，其中，所述信号线搭接在对应的触控电极上，电性接触。
  13. 根据权利要求10所述的制作方法，其中，所述形成多个像素单元的步骤包括：
    提供一衬底基板；
    在所述衬底基板上形成多个公共电极；
    所述形成多条信号线的步骤包括：
    在所述公共电极上形成栅金属层，对所述栅金属层进行构图工艺，形成多条栅线、多条信号线和薄膜晶体管的栅电极，所述信号线搭接在对应的触控电极上；
    所述制作方法还包括：
    形成覆盖所述栅线、信号线和栅电极的栅绝缘层；
    在所述栅绝缘层上形成有源层图案；
    在所述有源层上形成源漏金属层，对所述源漏金属层进行构图工艺，形成多条数据线和薄膜晶体管源电极、漏电极，所述源电极和漏电极搭接在所述有源层的相对两侧；
    形成覆盖所述薄膜晶体管的钝化层，对所述钝化层进行构图工艺形成过孔；
    在所述钝化层上形成像素电极，所述像素电极通过所述钝化层中的过孔 与所述漏电极电性连接。
  14. 根据权利要求10所述的制作方法，其中，所述形成多个像素单元的步骤包括：形成透明导电层，对所述透明导电层进行构图工艺，形成多个公共电极；
    所述制作方法还包括：在公共电极上形成绝缘层，对所述绝缘层进行构图工艺，形成过孔；
    所述形成多条信号线的步骤包括：在所述绝缘层上形成栅金属层，对所述栅金属层进行构图工艺，形成包括所述信号线、所述栅线和薄膜晶体管的栅电极的图案，其中，所述信号线通过所述绝缘层中的过孔与对应的触控电极电性连接。
  15. 一种显示器件，包括权利要求1-9任一项所述的ADS阵列基板。
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