CN205229635U - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

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CN205229635U
CN205229635U CN201521064387.3U CN201521064387U CN205229635U CN 205229635 U CN205229635 U CN 205229635U CN 201521064387 U CN201521064387 U CN 201521064387U CN 205229635 U CN205229635 U CN 205229635U
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郝学光
先建波
李盼
吴新银
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BOE Technology Group Co Ltd
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Priority to PCT/CN2016/098049 priority patent/WO2017101524A1/zh
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Abstract

本实用新型提供了一种像素结构、阵列基板及显示装置，该像素结构包括衬底基板以及设置在所述衬底基板上的栅层和源漏层，所述栅层包括薄膜晶体管的栅极，所述源漏层包括所述薄膜晶体管的源极和漏极，所述栅层与所述源漏层之间存在交叠区域，其中，所述栅层和/或所述源漏层包括位于所述交叠区域的镂空结构。本实用新型提供的像素结构，通过在栅层上与源漏层交叠的位置和/或源漏层上与栅层交叠的位置设置镂空结构，从而有效减小源漏层与栅层之间的交叠面积，进而降低了栅层与源漏层的耦合电容，不仅增强了像素TFT的驱动能力，而且提升了像素的充放电能力。

Description

像素结构、阵列基板及显示装置
技术领域
本实用新型涉及显示领域，尤其涉及一种像素结构、阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示器(ThinFilmTransistorLiquidCrystalDisplay，TFT-LCD)具有体积小、功耗低、无辐射等特点，在当前平板显示器市场中占据了主导地位。TFT-LCD主要由对盒的阵列基板和彩膜基板构成，其中阵列基板上形成有栅层(包括栅极和栅线)、源漏层(包括源极、漏极和数据线)和像素电极。
然而，在现有的阵列基板中，由于栅层与源漏层存在交叠区域，使栅层与源漏层之间存在较大的耦合电容，造成像素的TFT驱动能力不足，像素充电速度较缓慢，容易产生较大的像素电压变化量(ΔVp)，使得数据线写入的所设定的像素电压在TFT关闭后有所变动，进而产生两个效应：1.使像素最后所显示的灰阶偏离原来写入电压所希望表现的灰阶；2.使原来数据线写入正负极性大小对称的电压向下偏离而产生直流残留。
实用新型内容
(一)要解决的技术问题
本实用新型要解决的技术问题是：如何降低阵列基板上栅层与源漏层之间的耦合电容。
(二)技术方案
为解决上述技术问题，本实用新型的技术方案提供了一种像素结构，包括衬底基板以及设置在所述衬底基板上的栅层和源漏层，所述栅层包括薄膜晶体管的栅极，所述源漏层包括所述薄膜晶体管的源极和漏极，所述栅层与所述源漏层之间存在交叠区域，其中，所述栅层和/或所述源漏层包括位于所述交叠区域的镂空结构。
可选地，所述镂空结构包括多个开口。
可选地，所述镂空结构中开口的形状为以下的任意一种：三角形、矩形、圆形。
可选地，所述交叠区域包括所述源极与所述栅极之间的交叠区域。
可选地，所述源漏层还包括与所述源极相连的数据线，所述源极的宽度小于所述数据线的宽度。
可选地，所述薄膜晶体管的沟道长度为2微米～8微米。
可选地，所述源漏层还包括设置在所述源极与所述漏极之间且与所述源极和所述漏极分隔的中间电极。
可选地，所述衬底基板上还设置有栅极绝缘层、有源层、保护层和像素电极。
为解决上述技术问题，本实用新型还提供了一种阵列基板，包括上述的像素结构。
为解决上述技术问题，本实用新型还提供了一种显示装置，包括上述的阵列基板。
(三)有益效果
本实用新型提供的像素结构，通过在栅层上与源漏层交叠的位置和/或源漏层上与栅层交叠的位置设置镂空结构，从而有效减小源漏层与栅层之间的交叠面积，进而降低了栅层与源漏层的耦合电容，不仅增强了像素TFT的驱动能力，而且提升了像素的充放电能力。
附图说明
图1是本实用新型实施方式提供的一种像素结构的示意图；
图2是图1中AA’方向的截面示意图；
图3是图1中BB’方向的截面示意图；
图4是本实用新型实施方式提供的另一种像素结构的示意图；
图5是本实用新型实施方式提供的又一种像素结构的示意图。
具体实施方式
下面结合附图和实施例，对本实用新型的具体实施方式作进一步详细描述。以下实施例用于说明本实用新型，但不用来限制本实用新型的范围。
本实用新型实施方式提供了一种像素结构，该像素结构包括衬底基板以及设置在所述衬底基板上的栅层和源漏层，所述栅层包括薄膜晶体管的栅极，所述源漏层包括所述薄膜晶体管的源极和漏极，所述栅层与所述源漏层之间存在交叠区域，其中，所述栅层和/或所述源漏层包括位于所述交叠区域的镂空结构。
本实用新型实施方式提供的像素结构，通过在栅层上与源漏层交叠的位置和/或源漏层上与栅层交叠的位置设置镂空结构，从而有效减小源漏层与栅层之间的交叠面积，进而降低了栅层与源漏层的耦合电容，不仅增强了像素TFT的驱动能力，而且提升了像素的充放电能力。
其中，在本实用新型中，镂空结构可以位于栅层上，也可以位于源漏层，也可以在栅层和源漏层上均设置镂空结构。
优选地，为了进一步地降低栅极与源漏极的耦合电容，栅层上的镂空结构和/或源漏层上的镂空结构可以包括多个开口，其中，开口的形状可以为三角形、矩形(如长方形、正方形)、圆形或者其他不规则形状。
参见图1，图1是本实用新型实施方式提供的一种像素结构的示意图，该像素结构包括衬底基板，衬底基板上设置有栅层、栅极绝缘层(GI层)、有源层、源漏层、保护层(PL层)、像素电极，其中，如图1所示，栅层10包括栅极12以及与栅极相连的栅线11，源漏层20包括薄膜晶体管的源极22、漏极23以及与源极22相连的数据线21，像素电极30通过保护层上的过孔(虚线框1内的区域)与漏极23相连，有源层位于虚线框2内的区域；
其中，栅层10与源漏层20之间存在交叠区域，其包括源极22与栅极12之间的交叠区域，源极22在与栅极交叠的位置设置有镂空结构，该镂空结构包括多个开口24；
图2是图1中AA’方向的截面示意图，如图2所示，栅层10、栅极绝缘层(GI层)40、有源层50、源漏层20、保护层(PL层)60依次设置在衬底基板100上，通过在源漏层20与栅层10交叠的位置处设置开口24，从而有效减小源漏层20与栅层10的交叠面积，进而降低了栅层与源漏层的耦合电容；
图3是图1中BB’方向的截面示意图，如图3所示，像素电极30通过保护层60上的过孔与源漏层20中的漏极23相连。
其中，栅层10的材料可以为钼(Mo)或铝(Al)，有源层50的材料可以为非晶硅、多晶硅或氧化物半导体材料。
具体地，对于上述的像素结构，其制作方法可以如下：
S1：在衬底基板上形成栅层。例如：在衬底基板(可以为玻璃基板)上沉积一层或多层金属薄膜，该金属薄膜的材料可以为Mo、Al或其合金等，通过对该金属薄膜进行掩膜版曝光、显影、刻蚀等处理，从而形成栅层。具体的，栅层可以包括栅线(栅极金属走线)及薄膜晶体管的栅极图形；
S2：在栅层上形成栅极绝缘层，有源层和源漏层。例如：在栅层上沉积栅极绝缘层(GI)，然后采用非晶硅、多晶硅、或者氧化物半导体等材料形成一层半导体薄膜，通过对该半导体薄膜进行掩膜版曝光、显影、刻蚀等工艺处理，从而形成薄膜晶体管的有源层(ActiveLayer)，然后沉积一层或多层金属薄膜，该金属薄膜的材料可以为Mo、Al或其合金等，通过对该金属薄膜进行曝光、显影、刻蚀等工艺处理，从而形成源漏层。具体的，栅层上依次设置栅极绝缘层(GI层)、有源层、源漏层，源漏层包括薄膜晶体管的源极、漏极、数据线以及源漏层与栅层交叠处的镂空结构；
S3：在源漏层上形成保护层。例如：采用树脂材料或其他无机材料在源漏层上形成保护层。当然，根据需要还可以通过曝光、显影等工艺在其上形成过孔(viahole)；
S4：在保护层上像素电极。例如：在保护层上沉积一层透明导电薄膜(如ITO材料)，通过曝光、显影、刻蚀等工艺形成像素电极或公共电极等透明导电图案。
可选的，为了进一步地减小源漏层与栅层的交叠面积，还可以适当减小源极的宽度。例如，可以如图4所示，源极22的宽度D可以小于源漏层在其他位置处的数据线21的宽度d；
可选的，薄膜晶体管的沟道长度L为2微米～8微米。较佳的为5微米，好处之一在于可以减小栅极的面积，进而可以避免由于源极宽度减小导致的薄膜晶体管漏电流增加。
此外，为避免由于减小源极宽度从而增加薄膜晶体管的漏电流，还可以在薄膜晶体管的源极与漏极之间设置中间电极，从而形成两个串联的薄膜晶体管，如图5所示，在像素结构中，源漏层20不仅包括薄膜晶体管的源极22、漏极23以及与源极22相连的数据线21，还包括设置在源极22与漏极23之间且与源极22和漏极23分隔的中间电极25，从而形成两个串联的薄膜晶体管(即源极22与中间电极25形成一个薄膜晶体管，中间电极25与漏极23形成另一个薄膜晶体管)，进而降低漏电流。
其中，本实用新型上述的像素结构可以为TN模式显示装置中的像素结构，也可以为VA，IPS或ADS模式显示装置中的像素结构，本实用新型对此不作具体限定。
本实用新型实施方式提供的像素结构，通过在栅层上与源漏层交叠的位置和/或源漏层上与栅层交叠的位置设置镂空结构，有效减小源漏层与栅层的交叠面积，从而降低了栅层与源漏层的耦合电容，进而避免了像素电压产生较大的变化量(ΔVp)，不会使像素最后所显示的灰阶严重偏离原来写入的电压所希望表现的灰阶，同时也避免了数据线写入的正负极性大小对称的电压向下偏离而产生直流残留。
此外，本实用新型实施方式还提供了一种阵列基板，包括上述的像素结构。
本实用新型实施方式还提供了一种显示装置，包括上述的阵列基板。其中，本实用新型实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本实用新型，而并非对本实用新型的限制，有关技术领域的普通技术人员，在不脱离本实用新型的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本实用新型的范畴，本实用新型的专利保护范围应由权利要求限定。

Claims (10)

1.一种像素结构，包括衬底基板以及设置在所述衬底基板上的栅层和源漏层，所述栅层包括薄膜晶体管的栅极，所述源漏层包括所述薄膜晶体管的源极和漏极，所述栅层与所述源漏层之间存在交叠区域，其特征在于，所述栅层和/或所述源漏层包括位于所述交叠区域的镂空结构。
2.根据权利要求1所述的像素结构，其特征在于，所述镂空结构包括多个开口。
3.根据权利要求1所述的像素结构，其特征在于，所述镂空结构中开口的形状为以下的任意一种：三角形、矩形、圆形。
4.根据权利要求1所述的像素结构，其特征在于，所述交叠区域包括所述源极与所述栅极之间的交叠区域。
5.根据权利要求4所述的像素结构，其特征在于，所述源漏层还包括与所述源极相连的数据线，所述源极的宽度小于所述数据线的宽度。
6.根据权利要求5所述的像素结构，其特征在于，所述薄膜晶体管的沟道长度为2微米～8微米。
7.根据权利要求5所述的像素结构，其特征在于，所述源漏层还包括设置在所述源极与所述漏极之间且与所述源极和所述漏极分隔的中间电极。
8.根据权利要求1-7任一所述的像素结构，其特征在于，所述衬底基板上还设置有栅极绝缘层、有源层、保护层和像素电极。
9.一种阵列基板，其特征在于，包括权利要求1-8任一所述的像素结构。
10.一种显示装置，其特征在于，包括权利要求9所述的阵列基板。
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