CN104267546A - 一种阵列基板和显示装置 - Google Patents
一种阵列基板和显示装置 Download PDFInfo
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Abstract
本发明涉及显示技术领域,尤其涉及一种阵列基板和显示装置,用以解决现有技术中存在的Cgc和/或Cdc的电容值比较大的问题。本发明实施例提供了一种阵列基板,包括:栅线、数据线、以及与栅线和数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域;而且,所述公共电极层包括位于至少一个所述交叠区域的镂空结构部,且位于所述交叠区域的镂空结构部包含至少一个镂空区域。本发明实施例能够减小Cgc和/或Cdc的电容值。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板和显示装置。
背景技术
当阵列基板不仅包括栅线和数据线,还包括与所述栅线和数据线电性绝缘的公共电极层时,所述公共电极层与所述栅线之间会形成有寄生电容Cgc,以及所述公共电极层与所述数据线之间会形成有寄生电容Cdc。
目前,电性绝缘的所述公共电极层与栅线之间可以存在交叠区域,也可以不存在交叠区域;其中,当所述公共电极层与栅线之间存在交叠区域时,Cgc的电容值比较大。类似地,当电性绝缘的所述公共电极层与数据线之间存在交叠区域时,Cdc的电容值比较大。
在Cgc的电容值比较大时,对Cgc进行充电所消耗的电量也比较大,导致所述阵列基板的功耗比较大;而且,在Cgc的电容值比较大时,所述栅线上传输的信号会与所述公共电极层上施加的信号发生串扰,从而会造成显示不良。类似地,在Cdc的电容值比较大时,也会出现功耗比较大和显示不良的问题。
综上所述,目前,当所述公共电极层与栅线之间存在交叠区域时,Cgc的电容值比较大;和/或,当所述公共电极层与数据线之间存在交叠区域时,Cdc的电容值比较大。
发明内容
本发明实施例提供了一种阵列基板和显示装置,用以解决现有技术中存在的Cgc和/或Cdc的电容值比较大的问题。
第一方面,本发明实施例提供了一种阵列基板,包括:栅线、数据线、以及与所述栅线和数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域;
所述公共电极层包括位于至少一个所述交叠区域的镂空结构部,且位于所述交叠区域的镂空结构部包含至少一个镂空区域。
较佳地,位于所述交叠区域的镂空结构部包含多个镂空区域;
所述多个镂空区域呈矩阵式排布。
较佳地,位于所述交叠区域的镂空结构部呈网格状结构。
较佳地,各所述镂空区域为圆形。
较佳地,位于所述交叠区域的镂空结构部包含一个镂空区域;
所述一个镂空区域为长方形。
较佳地,位于所述交叠区域的镂空结构部包含的镂空区域满足:对于所述镂空区域的边框上的任意一点,其距离所述交叠区域的边框的最小值不小于2微米。
较佳地,所述公共电极层、所述栅线与所述数据线分别位于不同层,所述阵列基板还包括:
位于所述栅线所在膜层和所述公共电极层之间、以及位于所述数据线所在膜层和所述公共电极层之间的中间层;其中,所述中间层包括钝化层和/或树脂层,所述钝化层的材料包括二氧化硅或氮化硅中的一种或多种。
较佳地,所述中间层的厚度的取值不小于2微米。
第二方面,本发明实施例提供了一种显示装置,包括:本发明实施例中所述的阵列基板。
本发明实施例的有益效果包括:
在本发明实施例中,阵列基板包括:栅线、数据线、以及与栅线和数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域;而且,所述公共电极层包括位于至少一个所述交叠区域的镂空结构部,且位于所述交叠区域的镂空结构部包含至少一个镂空区域;
与现有技术相比,由于本发明实施例的公共电极层在至少一个所述交叠区域设置具有镂空区域的镂空结构部,从而能够减小公共电极层与栅线和/或数据线之间的实际交叠面积,进而能够减小Cgc和/或Cdc的电容值。
附图说明
图1a~图1d为本发明实施例中位于交叠区域的镂空结构部的结构示意图;
图2为本发明实施例中HADS(High advanced dimension switch,高透过率高级维场开关)模式显示装置包括的阵列基板的俯视图。
具体实施方式
为了清楚说明本发明实施例的方案,下面结合说明书附图对本发明实施例作进一步详细描述。
需要说明的是,附图中各层膜层的厚度和形状不反映真实比例,目的只是示意说明本发明内容。
较佳地,本发明实施例提供一种阵列基板,包括:栅线、数据线、以及与栅线和数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域;
所述公共电极层包括位于至少一个所述交叠区域的镂空结构部,且位于所述交叠区域的镂空结构部包含至少一个镂空区域。
实施中,与现有技术相比,在本发明实施例中,由于本发明实施例的公共电极层在至少一个所述交叠区域设置具有镂空区域的镂空结构部,从而能够减小公共电极层与栅线和/或数据线之间的实际交叠面积;
因此,本发明实施例能够减小Cgc和/或Cdc的电容值;从而可以在一定程度上降低阵列基板的功耗、以及避免显示不良的发生。
较佳地,公共电极层包括位于各个所述交叠区域的镂空结构部。
实施中,在位于交叠区域的镂空结构部的具体结构不变的情况下,设置镂空结构部的交叠区域的个数越多,公共电极层与栅线和/或数据线之间的实际交叠面积越小,Cgc和/或Cdc的电容值越小;因此,在位于交叠区域的镂空结构部的具体结构不变的情况下,在公共电极层包括位于各个所述交叠区域的镂空结构部时,公共电极层与栅线和/或数据线之间的实际交叠面积最小,Cgc和/或Cdc的电容值最小。
较佳地,位于所述交叠区域的镂空结构部的大小,可以与对应的交叠区域大小相匹配;也可以与对应的交叠区域大小不匹配;
比如,以位于一个所述交叠区域的镂空结构部为例,如图1a所示,位于交叠区域1的镂空结构部2的大小,与对应的交叠区域1大小相匹配;如图1b所示,位于交叠区域1的镂空结构部2的大小,与对应的交叠区域1大小不匹配,此时,位于交叠区域1的镂空结构部2的大小略大于对应的交叠区域1大小。
需要说明的是,在本发明实施例中,位于交叠区域的镂空结构部只需要满足包含至少一个镂空区域即可;而位于交叠区域的镂空结构部包含的镂空区域的具体个数、形状、大小、以及排列方式等可以根据需要任意设定。
较佳地,位于交叠区域的镂空结构部可以包含一个镂空区域,也可以包含多个镂空区域。
实施中,在位于交叠区域的镂空结构部包含的镂空区域的大小不变的情况下,位于交叠区域的镂空结构部包含的镂空区域的个数越多,公共电极层与栅线和/或数据线之间的实际交叠面积越小,Cgc和/或Cdc的电容值越小。
较佳地,位于交叠区域的镂空结构部包含的镂空区域的形状可以为规则形状,也可以为不规则形状。
实施中,在位于交叠区域的镂空结构部包含的镂空区域的形状为规则形状时,其制作复杂度比较低。
较佳地,位于交叠区域的镂空结构部包含的镂空区域的大小可以根据需要任意设定。
实施中,在位于交叠区域的镂空结构部包含的镂空区域的个数不变的情况下,位于交叠区域的镂空结构部包含的镂空区域越大,公共电极层与栅线和/或数据线之间的实际交叠面积越小,Cgc和/或Cdc的电容值越小。
较佳地,在位于交叠区域的镂空结构部包含多个镂空区域时,该多个镂空区域可以规则排列,也可以杂乱排列。
实施中,在位于交叠区域的镂空结构部包含的多个镂空区域规则排列时,其制作复杂度比较低。
下面以位于交叠区域的镂空结构部包含的镂空区域的个数为分类依据,分别对位于交叠区域的镂空结构部包含的镂空区域的几种较佳的实施方式进行说明。
一、位于交叠区域的镂空结构部包含多个镂空区域。
较佳地,位于所述交叠区域的镂空结构部包含多个镂空区域;
所述多个镂空区域呈矩阵式排布。
实施中,在位于交叠区域的镂空结构部包含的多个镂空区域呈矩阵式排布时,其制作复杂度比较低。
较佳地,如图1a所示,位于交叠区域1的镂空结构部2呈网格状结构。
实施中,在位于交叠区域的镂空结构部呈网格状结构时,其制作复杂度比较低。
较佳地,如图1c所示,位于交叠区域1的镂空结构部2包含的各所述镂空区域3为圆形。
实施中,栅线和数据线一般为长条形,在公共电极层与栅线和/或数据线之间存在交叠区域时,公共电极层与栅线和/或数据线之间存在的交叠区域一般为长方形;因此,与所述镂空区域为其他形状相比,在各所述镂空区域为圆形时,可以保证公共电极层与栅线和/或数据线之间的实际交叠面积比较小,Cgc和/或Cdc的电容值比较小。
二、位于交叠区域的镂空结构部包含一个镂空区域。
较佳地,如图1d所示,位于所述交叠区域1的镂空结构部2包含一个镂空区域3;
所述一个镂空区域3为长方形。
实施中,栅线和数据线一般为长条形,在公共电极层与栅线和/或数据线之间存在交叠区域时,公共电极层与栅线和/或数据线之间存在的交叠区域一般为长方形;因此,与所述镂空区域为其他形状相比,在所述一个镂空区域为长方形时,可以保证公共电极层与栅线和/或数据线之间的实际交叠面积比较小,Cgc和/或Cdc的电容值比较小,另外,制作复杂度也比较低。
较佳地,位于所述交叠区域的镂空结构部包含的镂空区域满足:对于所述镂空区域的边框上的任意一点,其距离所述交叠区域的边框的最小值不小于2微米。
实施中,对于所述镂空区域的边框上的任意一点,其距离所述交叠区域的边框的最小值不小于2微米;可以在一定程度上避免漏光问题的发生。
较佳地,所述公共电极层、所述栅线与所述数据线分别位于不同层,所述阵列基板还包括:
位于所述栅线所在膜层和所述公共电极层之间、以及位于所述数据线所在膜层和所述公共电极层之间的中间层;其中,所述中间层包括钝化层和/或树脂层,所述钝化层的材料包括二氧化硅或氮化硅中的一种或多种。
实施中,通过在所述栅线所在膜层和所述公共电极层之间、以及在所述数据线所在膜层和所述公共电极层之间制作中间层,可以增大所述数据线所在膜层和所述公共电极层之间的距离,以及增大所述栅线所在膜层和所述公共电极层之间的距离;
而本案的发明人在发明过程中注意到:公共电极层与栅线所在膜层之间的距离越大,Cgc的电容值越小;类似地,公共电极层与数据线所在膜层之间的距离越大,Cdc的电容值越小;因此,本发明实施例能够减小Cgc和Cdc的电容值;从而可以在一定程度上降低阵列基板的功耗、以及避免显示不良的发生。
需要说明的是,根据所述公共电极层、所述栅线所在膜层与所述数据线所在膜层的膜层顺序不同,位于所述栅线所在膜层和所述公共电极层之间的中间层、以及位于所述数据线所在膜层和所述公共电极层之间的中间层可以为同一膜层,也可以为不同膜层;
比如,在所述公共电极层位于所述栅线所在膜层和所述数据线所在膜层之间时,位于所述栅线所在膜层和所述公共电极层之间的中间层(第一中间层)、以及位于所述数据线所在膜层和所述公共电极层之间的中间层(第二中间层)为不同膜层;
在所述栅线所在膜层位于所述公共电极层和所述数据线所在膜层之间,且在所述栅线所在膜层和所述公共电极层之间设置中间层时,位于所述栅线所在膜层和所述公共电极层之间的中间层、以及位于所述数据线所在膜层和所述公共电极层之间的中间层为同一膜层;
在所述数据线所在膜层位于所述公共电极层和所述栅线所在膜层之间,且在所述数据线所在膜层和所述公共电极层之间设置中间层时,位于所述栅线所在膜层和所述公共电极层之间的中间层、以及位于所述数据线所在膜层和所述公共电极层之间的中间层为同一膜层。
具体实施中,可以根据应用需要设定中间层的厚度;比如,在设定中间层的厚度时,综合考虑减小Cgc和Cdc的电容值的效果、以及阵列基板的厚度。
较佳地,可以通过增加或减少钝化层和/或树脂层的膜层数量,以获得具有设定厚度的中间层。
较佳地,所述中间层的厚度的取值不小于2微米。
实施中,所述中间层的厚度的取值不小于2微米,可以保证减小Cgc和Cdc的电容值的效果比较好。
需要说明的是,本发明实施例中的阵列基板可以为任一种满足如下条件的阵列基板:其包括:栅线、数据线、以及与栅线和数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域;
比如,HADS模式显示装置包括的阵列基板,或者,IADS(Innovativeadvanced dimension switch,创新高级维场开关)模式显示装置包括的阵列基板。
实施例
下面以HADS模式显示装置中阵列基板包括的一个像素单元的结构为例,对本发明实施例的方案进行说明。
如图2所示,HADS模式显示装置的阵列基板包括:相互交叉以界定像素单元的栅线10和数据线20,位于该像素单元内且相互电性连接的TFT(薄膜晶体管)30和像素电极40,与栅线10同层设置且相互绝缘的公共电极线50,以及通过过孔60与公共电极线50电性连接的公共电极层70;
电性绝缘的公共电极层70与栅线10之间存在交叠区域A,且电性绝缘的公共电极层70与数据线20之间存在交叠区域B;
公共电极层70包括位于像素电极40正上方的多个镂空区域71,以便公共电极层70与像素电极40之间能够形成边缘电场;以及公共电极层70包括位于TFT 30正上方的镂空区域72,以避免公共电极层70对TFT 30造成干扰;另外,公共电极层70还包括位于交叠区域A和交叠区域B的具有镂空区域的镂空结构部2,且位于交叠区域A和交叠区域B的镂空结构部2均呈网格状结构。
实施中,电性绝缘的公共电极层与栅线之间存在交叠区域,且电性绝缘的公共电极层与数据线之间存在交叠区域,因此,Cgc和Cdc的电容值均比较大;而由于公共电极层在该交叠区域设置呈网格状结构的镂空结构部,因此,能够减小公共电极层与栅线之间的实际交叠面积,以及减小公共电极层与数据线之间的实际交叠面积,进而能够减小Cgc和Cdc的电容值。
较佳地,基于同一发明构思,本发明实施例提供一种显示装置,包括:本发明实施例提供的所述阵列基板。
实施中,本发明实施例中的阵列基板中的Cgc和/或Cdc的电容值减小了,使得所述阵列基板的功耗、以及显示不良问题的发生概率在一定程度上降低了,因此,包括本发明实施例中的阵列基板的显示装置的功耗、以及显示不良问题的发生概率也在一定程度上降低了。
较佳地,所述显示装置可以为:液晶面板、电子纸、OLED(Organic LightEmitting Diode,有机发光二极管)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
尽管已描述了本发明的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例作出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (9)
1.一种阵列基板,包括:栅线、数据线、以及与所述栅线和所述数据线电性绝缘的公共电极层,其中,所述公共电极层与所述栅线之间存在至少一个交叠区域,和/或,所述公共电极层与所述数据线之间存在至少一个交叠区域,其特征在于,
所述公共电极层包括位于至少一个所述交叠区域的镂空结构部,且位于所述交叠区域的镂空结构部包含至少一个镂空区域。
2.如权利要求1所述的阵列基板,其特征在于,位于所述交叠区域的镂空结构部包含多个镂空区域;
所述多个镂空区域呈矩阵式排布。
3.如权利要求2所述的阵列基板,其特征在于,位于所述交叠区域的镂空结构部呈网格状结构。
4.如权利要求2所述的阵列基板,其特征在于,各所述镂空区域为圆形。
5.如权利要求1所述的阵列基板,其特征在于,位于所述交叠区域的镂空结构部包含一个镂空区域;
所述一个镂空区域为长方形。
6.如权利要求1所述的阵列基板,其特征在于,位于所述交叠区域的镂空结构部包含的镂空区域满足:对于所述镂空区域的边框上的任意一点,其距离所述交叠区域的边框的最小值不小于2微米。
7.如权利要求1所述的阵列基板,其特征在于,所述公共电极层、所述栅线与所述数据线分别位于不同层,所述阵列基板还包括:
位于所述栅线所在膜层和所述公共电极层之间、以及位于所述数据线所在膜层和所述公共电极层之间的中间层;其中,所述中间层包括钝化层和/或树脂层,所述钝化层的材料包括二氧化硅和氮化硅中的一种或多种。
8.如权利要求7所述的阵列基板,其特征在于,所述中间层的厚度的取值不小于2微米。
9.一种显示装置,其特征在于,包括如权利要求1~8任一项所述的阵列基板。
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CN111474776A (zh) * | 2020-05-11 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | 液晶显示面板及显示装置 |
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WO2021227100A1 (zh) * | 2020-05-11 | 2021-11-18 | 深圳市华星光电半导体显示技术有限公司 | 液晶显示面板及显示装置 |
CN112379552A (zh) * | 2020-12-03 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及其制作方法 |
WO2023024870A1 (zh) * | 2021-08-25 | 2023-03-02 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
CN115376416A (zh) * | 2022-09-15 | 2022-11-22 | 厦门天马微电子有限公司 | 一种显示面板及显示装置 |
Also Published As
Publication number | Publication date |
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EP3196692A1 (en) | 2017-07-26 |
WO2016041302A1 (zh) | 2016-03-24 |
EP3196692A4 (en) | 2018-04-18 |
US20170133402A1 (en) | 2017-05-11 |
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