CN202839610U - 一种阵列基板及显示装置 - Google Patents

一种阵列基板及显示装置 Download PDF

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CN202839610U
CN202839610U CN2012204455784U CN201220445578U CN202839610U CN 202839610 U CN202839610 U CN 202839610U CN 2012204455784 U CN2012204455784 U CN 2012204455784U CN 201220445578 U CN201220445578 U CN 201220445578U CN 202839610 U CN202839610 U CN 202839610U
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崔贤植
田正牧
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BOE Technology Group Co Ltd
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Abstract

本实用新型提供一种阵列基板，其包括基板、设置于基板上的栅线及像素电极、设置于栅线上方并将栅线覆盖的公共电极，其中，所述公共电极上设置有条形通孔，且该条形通孔至少有一部分位于栅线的正上方。相应地，提供一种包含上述阵列基板的显示装置。本实用新型所述阵列基板及显示装置能在减少栅线的线路负载的同时提高单元像素的开口率，并减小了对显示装置的充电率的影响。

Description

一种阵列基板及显示装置
技术领域
本实用新型涉及显示器制造技术领域，具体涉及一种阵列基板及包括所述阵列基板的显示装置。
背景技术
AD-SDS高级超维场转换技术（ADvanced Super DimensionSwitch，AD-SDS，简称ADS），其核心技术特性描述为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹（push Mura）等优点。
目前，ADS技术通过电动力学优化对液晶材料进行改良，在正性型液晶上获得了负性液晶90%左右的光效率，从而解决了由于负性液晶黏度大而导致的响应时间慢的问题，除此之外，ADS技术在透光率、对比度、亮度、可视角度、色差等方面也有显著的提高。
目前，ADS模式的显示装置中，用于遮挡栅线（gate line）漏光的黑矩阵（Black Matrix，BM）的最小宽度一般为32μm，以便在最大程度上减少栅线漏光（disinclination）的同时确保较佳的单元像素的开口率（aperture ratio）。而开口率是影响显示装置屏幕的亮度与功耗的重要因素，开口率越高，光透过率也越高，在相同的背光源条件下，屏幕的亮度就会越高。而在液晶显示器中，背光源的功耗占整个电源输出的60%左右，所以，在工艺条件许可的情况下，应尽可能采用高开口率的设计方案，使得在满足显示装置亮度的前提下将背光源的功耗降为最低，从而降低整个显示系统的功耗。但在ADS模式的显示装置中，若想提高单元像素的开口率就需减少黑矩阵的宽度，但黑矩阵宽度的减少会导致并加剧栅线的漏光。
为了能在提高单元像素的开口率的同时减少栅线的漏光，出现了一种I-ADS（高透过率-高级超维场转换技术）模式的显示装置，其与ADS模式的显示装置的区别在于：阵列基板中的像素电极（Vpixel）与公共电极（Vcom）的位置发生了翻转，即在I-ADS模式的阵列基板中，像素电极作为第一电极（1st ITO，即为板状电极）设置于基板上，公共电极作为第二电极（2nd ITO，即为狭缝电极）并位于像素电极的上方；而在ADS模式的阵列基板中，公共电极作为第一电极设置于基板上，像素电极作为第二电极并位于公共电极的上方。
图1（a）为现有技术中I-ADS模式的阵列基板的结构示意图，
图1（b）为图1（a）的A-A'截面示意图。如图1（b）所示，所述I-ADS模式的阵列基板包括基板104，设置于基板上的栅线103及像素电极101，设置于栅线103上方并将栅线103完全覆盖的公共电极102。这里，由于公共电极将栅线完全覆盖，产生了公共电极遮罩效应（Vcom shielding），使得栅线的漏光最小化，因此可以减小用于遮挡栅线漏光的黑矩阵的宽度，从而提高了单元像素的开口率。然而，正是由于公共电极将栅线完全覆盖，使得栅极电容（ratio of Cap gate）增大并导致栅线的线路负载（line load）增加，从而导致栅线产生延迟（delay），并影响显示装置的充电率。
实用新型内容
本实用新型所要解决的技术问题是针对现有技术中所存在的上述缺陷，提供一种能在减少栅线的线路负载的同时提高单元像素的开口率的阵列基板及包含所述阵列基板的显示装置。
解决本实用新型技术问题所采用的技术方案是：
一种阵列基板，包括基板、设置于基板上的栅线及像素电极、设置于栅线上方并将栅线覆盖的公共电极，所述公共电极上设置有条形通孔，且该条形通孔至少有一部分位于栅线的正上方。
进一步地，所述条形通孔全部位于栅线的正上方。
进一步地，所述条形通孔的宽度大于零且小于栅线的宽度。
进一步地，所述栅线的宽度小于条形通孔两侧的公共电极的宽度。
进一步地，所述像素电极与公共电极之间设置有绝缘层。
本实用新型同时提供一种显示装置，包括阵列基板，所述阵列基板采用上述的阵列基板。
有益效果：
1）本实用新型所述阵列基板与现有技术中ADS模式阵列基板相比，在相同的栅线漏光范围的情况下黑矩阵的宽度更小，现有ADS模式中栅线漏光范围一般为10-15μm，但不限定于此，从而极大的提高了单元像素的开口率；
2）本实用新型所述阵列基板与现有技术中I-ADS模式阵列基板相比，减小了栅极电容及栅线的线路负载，因而降低了栅线的延迟，并减小了对显示装置的充电率的影响。
附图说明
图1（a）为现有技术中I-ADS模式的阵列基板的结构示意图；
图1（b）为图1（a）的A-A'截面示意图；
图2为本实用新型所述阵列基板的结构示意图；
图3为本实用新型所述阵列基板中公共电极102上设置的条形通孔的宽度分别与黑矩阵的最小宽度、栅线漏光范围及栅极电容率的对应关系示意图；
图中：101－像素电极；102－公共电极；103－栅线；104－基板；105-数据线。
具体实施方式
为使本领域技术人员更好地理解本实用新型的技术方案，下面结合附图和具体实施方式对本实用新型阵列基板以及包括所述阵列基板的显示装置作进一步详细描述。
如图2所示，本实施例中，所述阵列基板包括基板104、设置于基板104上的栅线103及像素电极101、设置于栅线103上方并将栅线103覆盖的公共电极102。优选所述像素电极101与公共电极102之间设置有绝缘层。当然，所述阵列基板还包括数据线105、由栅线及数据线交叉定义的若干个像素单元（每个像素单元均包括薄膜晶体管）、公共电极线等，由于本实用新型所述阵列基板不涉及上述部件的改进，因此不再赘述。
其中，所述公共电极102上设置有条形通孔（宽度为d1），所述条形通孔沿与栅线103平行的方向贯穿公共电极102，且该条形通孔位于栅线103的正上方。优选所述条形通孔的宽度大于零且小于栅线103的宽度。
图3为所述公共电极102上设置的条形通孔的宽度分别与用于遮挡栅线漏光的黑矩阵的最小宽度、栅线漏光范围及栅极电容率的对应关系示意图，其中栅极电容率为本实用新型中阵列基板的栅极电容与现有技术中ADS模式阵列基板的栅极电容之比。可见，随着所述条形通孔宽度的增大，对应的黑矩阵的最小宽度与栅线漏光范围也逐渐增大，而栅极电容率则逐渐减小。
如图3所示，当所述条形通孔的宽度d1=0时，公共电极102上没有设置条形通孔，此种结构的阵列基板即现有技术中I-ADS模式的阵列基板，其对应的黑矩阵的最小宽度为9μm、栅线漏光范围为0、栅极电容率为620%；可见，虽然现有技术中I-ADS模式阵列基板的黑矩阵的最小宽度比现有技术中ADS模式阵列基板的黑矩阵的最小宽度相比大大减小了（减小约23μm），但是其栅线负载与现有技术中ADS模式阵列基板的栅线负载（栅线负载=栅极电容*栅极电阻）相比却增加了6.2倍，从而造成栅线的线路负载过大，加剧了栅线和数据线的延迟，并严重影响所述显示装置的充电率；
当所述条形通孔的宽度d1=4μm时，对应的黑矩阵的最小宽度为24.5μm、栅线漏光范围为6μm、栅极电容率为350%；可见，条形通孔的宽度d1=4μm时对应的黑矩阵的最小宽度及栅线漏光范围分别与现有技术中I-ADS模式阵列基板的黑矩阵的最小宽度及栅线漏光范围相比有所增加，但其栅极电容率与现有技术中I-ADS模式阵列基板的栅极电容率相比减小了约43.5％，因而有效地减少了栅线的线路负载，降低了栅线和数据线的延迟，减小了对所述显示装置的充电率的影响；所述条形通孔的宽度d1=4μm时对应的黑矩阵的最小宽度与现有技术中ADS模式阵列基板的黑矩阵的最小宽度相比减小约7.5μm，因而其开口率与现有技术中ADS模式阵列基板的开口率相比增加了约3%，极大的降低了整个显示系统的功耗。本实用新型所述阵列基板与现有技术中ADS模式阵列基板相比，虽然增加了栅极电容率（约3.5倍）从而造成栅线负载的增加，但也增加了开口率（约3%）并降低了整个显示系统的功耗，且对于所增加的栅极电容率来说，开口率的增加对整个显示系统来说更为重要，故增加的栅极电容率相对来说对整个显示系统的影响较小。
本实用新型还提供一种包括上述阵列基板的I-ADS模式的显示装置。
可以理解的是，以上实施方式仅仅是为了说明本实用新型的原理而采用的示例性实施方式，然而本实用新型并不局限于此。对于本领域内的普通技术人员而言，在不脱离本实用新型的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本实用新型的保护范围。

Claims (6)

1.一种阵列基板，包括基板、设置于基板上的栅线及像素电极、设置于栅线上方并将栅线覆盖的公共电极，其特征在于，所述公共电极上设置有条形通孔，且该条形通孔至少有一部分位于栅线的正上方。
2.根据权利要求1所述的阵列基板，其特征在于，所述条形通孔全部位于栅线的正上方。
3.根据权利要求1所述的阵列基板，其特征在于，所述条形通孔的宽度大于零且小于栅线的宽度。
4.根据权利要求3所述的阵列基板，其特征在于，所述栅线的宽度小于条形通孔两侧的公共电极的宽度。
5.根据权利要求1所述的阵列基板，其特征在于，所述像素电极与公共电极之间设置有绝缘层。
6.一种显示装置，包括阵列基板，其特征在于，所述阵列基板采用权利要求1-5中任一所述的阵列基板。
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CN104267546A (zh) * 2014-09-19 2015-01-07 京东方科技集团股份有限公司 一种阵列基板和显示装置
WO2017101524A1 (zh) * 2015-12-18 2017-06-22 京东方科技集团股份有限公司 像素结构及其制作方法、阵列基板及显示装置
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WO2017101524A1 (zh) * 2015-12-18 2017-06-22 京东方科技集团股份有限公司 像素结构及其制作方法、阵列基板及显示装置
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