CN103151359A - 一种显示装置、阵列基板及其制作方法 - Google Patents

一种显示装置、阵列基板及其制作方法 Download PDF

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CN103151359A
CN103151359A CN201310082081XA CN201310082081A CN103151359A CN 103151359 A CN103151359 A CN 103151359A CN 201310082081X A CN201310082081X A CN 201310082081XA CN 201310082081 A CN201310082081 A CN 201310082081A CN 103151359 A CN103151359 A CN 103151359A
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groove
electrode
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passivation layer
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CN103151359B (zh
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崔承镇
刘圣烈
宋泳锡
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BOE Technology Group Co Ltd
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Priority to PCT/CN2013/085103 priority patent/WO2014139283A1/zh
Priority to EP13857663.2A priority patent/EP2975642B1/en
Priority to US14/362,241 priority patent/US9465264B2/en
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Abstract

本发明涉及显示技术领域，特别是涉及一种显示装置、阵列基板及其制作方法。该阵列基板包括：基板，所述基板上依次设有薄膜晶体管、钝化层和透明电极层，所述树钝化层上形成凹槽，所述透明电极层设置于凹槽内。本发明提供的显示装置、阵列基板及其制作方法，制作工艺简单，采用具有凹槽的钝化层，利用光刻胶进行灰化工艺形成透明电极层，从而省略制备透明电极的掩模板，可最大程度降低制造成本。

Description

一种显示装置、阵列基板及其制作方法
技术领域
本发明涉及显示技术领域，特别是涉及一种显示装置、阵列基板及其制作方法。
背景技术
近年来，随着科技的发展，液晶显示器技术也随之不断完善。TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管-液晶显示器）以其图像显示品质好、能耗低、环保等优势占据着显示器领域的重要位置。TFT-LCD由彩膜基板和阵列基板对盒而成。其中，现有的阵列基板通常采用多次mask掩膜工艺形成特定的结构图形。
如图1所示，为现有技术中阵列基板结构示意图。该阵列基板包括基板1、该基板1上设有栅极、栅绝缘层2和半导体层，该绝缘层2上设有源电极3和漏电极4，该源电极3和漏电极4的上方和周围设有钝化层5，该钝化层5上设有像素电极层6。该像素电极层6通常采用掩模板进行曝光及后续工艺，进而形成电极层图形。在TFT-LCD的制作工艺中，掩模板的制作成本非常昂贵，每形成一种结构层都需要只有一次特定图形的掩模板进行曝光，工艺复杂，成本高，每多一次mask产能及良率均受到限制。
发明内容
（一）要解决的技术问题
本发明要解决的技术问题是提供一种显示装置、阵列基板及其制作方法，减少mask工艺制程，克服现有技术中采用掩模板制作透明电极层带来的生产成本较高的缺陷。
（二）技术方案
为了解决上述技术问题，本发明一方面提供一种阵列基板，包括：基板，所述基板上依次设有薄膜晶体管、钝化层和透明电极层，所述树钝化层上形成有凹槽，所述透明电极层设置于凹槽内。
进一步地，所述钝化层由感光树脂材料制成。
进一步地，所述凹槽的高度为0.5-3um。
进一步地，所述透明电极层为像素电极，所述像素电极位于凹槽内。
进一步地，所述凹槽为梳状，所述透明电极层为像素电极，所述像素电极位于梳状凹槽内，所述阵列基板还包括位于钝化层下方的公共电极；
或者，所述凹槽为梳状，所述透明电极层为公共电极，所述公共电极位于梳状凹槽内，所述阵列基板还包括位于钝化层下方的像素电极。
另一方面，本发明还提供一种阵列基板的制作方法，包括如下步骤：
在基板上形成包括薄膜晶体管和钝化层的图形，所述钝化层上形成凹槽；
在凹槽内形成透明电极的图形。
进一步地，在基板上形成薄膜晶体管，具体包括：
在基板上通过构图工艺形成栅极和栅线的图形；
在完成上述步骤的基板上形成栅绝缘层；
在完成上述步骤的基板上通过构图工艺形成有源层和源漏电极层的图形。
进一步地，所述形成具有凹槽的钝化层的图形包括：
在形成有所述薄膜晶体管的基板上形成钝化层；
在完成上述步骤的基板上涂覆光刻胶，通过双色调掩模板对光刻胶进行曝光，对应透明电极区域的光刻胶进行部分曝光，对应暴露出漏极的过孔区域的光刻胶进行完全曝光，其他区域的光刻胶不进行曝光；
通过显影处理后，对应所述完全曝光区域的钝化层暴露出来，利用刻蚀工艺形成所述漏极的过孔；
利用灰化工艺，将所述对应透明电极区域的光刻胶去除，以暴露出钝化层；
利用刻蚀工艺将暴漏出的钝化层进行部分去除，在钝化层上形成所述凹槽。
进一步地，所述形成具有凹槽的钝化层图形包括：
在形成有所述薄膜晶体管的基板上形成感光树脂层，通过双色调掩模板对感光树脂层进行曝光，使得对应透明电极区域的所述感光树脂层进行部分曝光，在对应暴露出漏极的过孔区域的所述感光树脂层进行完全曝光，其他区域的所述感光树脂层不进行曝光，通过显影工艺后，所述感光树脂层对应透明电极的区域形成凹槽的图形。
进一步地，所述在凹槽内形成透明电极的图形，具体包括：
在形成凹槽的基板上形成透明导电层；
在完成上述步骤的基板上涂覆光刻胶；
依据钝化层上具有的凹槽，形成在凹槽部分的光刻胶和凹槽以外的光刻胶的厚度差，对光刻胶进行灰化处理，保留凹槽区域的光刻胶，去除凹槽以外其他区域的光刻胶以暴露出透明导电层；
采用刻蚀工艺将暴露出的透明导电层去除，剥离所述凹槽部分的的光刻胶，形成透明电极的图形。
进一步地，所述透明电极为像素电极。
进一步地，所述形成的凹槽为梳状，所述透明电极层为像素电极，在形成钝化层之前，还包括形成公共电极的图形。
进一步地，所述形成的凹槽为梳状，所述透明电极层为公共电极，在形成钝化层之前，还包括形成像素电极的图形。
再一方面，本发明还提供一种显示装置，包括上述的阵列基板。
（三）有益效果
上述技术方案具有如下优点：本发明提供的显示装置、阵列基板及其制作方法，制作工艺简单，采用具有凹槽的钝化层，利用光刻胶进行灰化工艺形成透明电极层，从而省略制备透明电极的掩模板，可最大程度降低制造成本。
附图说明
图1为现有技术中阵列基板结构示意图；
图2a-2e为本发明实施例阵列基板结构制作步骤示意图，其中图2e为本发明实施例阵列基板其中一种结构示意图;
图3为本发明阵列基板另一种结构示意图;
图4为本发明实施例阵列基板的制作方法流程图。
其中，1：基板；2：栅绝缘层；3：源电极；4：漏电极；5：钝化层；51：凹槽；6：像素电极；7：光刻胶；8：公共电极。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
如图2e所示，本发明实施例中的阵列基板包括：基板，基板上依次设有薄膜晶体管、钝化层和透明电极层，树钝化层上形成有凹槽，所述透明电极层设置于凹槽内。
具体为：基板1（透明基板如，玻璃基板），在基板1上设有栅极和栅线，所述栅极和栅线之上设有栅绝缘层，栅绝缘层2上设有有源层，该有缘层可以采用氧化物半导体或非晶硅a-si等材料制成，在有源层之上设有源漏电极层（包括源电极3、漏电极4及之间的沟道）最终形成薄膜晶体管TFT。在源电极和漏电极之上设有钝化层5，该钝化层5上设有凹槽51，透明电极层设置于凹槽51内。该凹槽51的高度h为0.5-3um即可（参见图2a），所述凹槽的高度为钝化层凹槽的底部到钝化层最高处，即到达钝化层上表面的距离；较优地，该凹槽51的高度占钝化层5厚度的一半。透明电极层由ITO（Indium TinOxides，纳米铟锡）等材料制成。
对于TN（Twisted Nematic，扭曲向列显示）模式而言，该透明电极层为像素电极6，该像素电极设置于凹槽51内，在节省空间的前提下，可最大程度地保护像素电极。
而对于ADS（Advanced Super Dimension Switch）模式而言，ADS是平面电场宽视角核心技术-高级超维场转换技术，可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹（push Mura）等优点。高级超维场转换技术是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。参考图3，该凹槽51为梳状，所述透明电极层为像素电极，所述像素电极位于梳状凹槽内，所述阵列基板还包括位于钝化层下方的公共电极8。
或者，所述凹槽51为梳状，所述透明电极层为公共电极8，所述公共电极位于梳状凹槽51内，所述阵列基板还包括位于钝化层下方的像素电极。
如图4所示，本发明实施例阵列基板的制作方法具体包括如下步骤：
步骤S1、在基板上形成包括薄膜晶体管和钝化层的图形。
该步骤和现有的制作薄膜晶体管TFT和钝化层图形的步骤相似，以制作底栅型TFT为例进行说明，具体包括步骤：
其中，在基板上形成薄膜晶体管，具体包括：
在基板上通过沉积、曝光、显影、刻蚀及剥离等一系列构图工艺形成栅极和栅线的图形；在完成上述步骤的基板上形成栅绝缘层；在完成上述步骤的基板上通过构图工艺形成有源层和源漏电极层的图形；在形成有所述薄膜晶体管的基板上形成钝化层。
步骤S2、所述钝化层上形成凹槽。
具体为：在完成上述步骤的基板上涂覆光刻胶，通过双色调掩模板（灰调或半调掩膜板）对光刻胶进行曝光，对应透明电极区域的光刻胶进行部分曝光，对应暴露出漏极的过孔区域的光刻胶进行完全曝光，其他区域的光刻胶不进行曝光；
通过显影处理后，对应所述完全曝光区域的钝化层暴露出来，利用刻蚀工艺形成所述漏极的过孔；利用灰化工艺，将所述对应透明电极区域的光刻胶去除，以暴露出钝化层；利用刻蚀工艺将暴漏出的钝化层进行部分去除，在钝化层上形成所述凹槽，参考图2a。
另外，还可以采用如下方法形成具有凹槽的钝化层：在形成有所述薄膜晶体管的基板上形成感光树脂层，通过双色调掩模板对感光树脂层进行曝光，使得对应透明电极区域的所述感光树脂层进行部分曝光，在对应暴露出漏极的过孔区域的所述感光树脂层进行完全曝光，其他区域的所述感光树脂层不进行曝光，通过显影工艺后，所述感光树脂层对应透明电极的区域形成凹槽的图形。
步骤S3、在凹槽内形成透明电极的图形，具体步骤包括：在形成凹槽的基板上形成透明导电层6；在完成上述步骤的基板上涂覆光刻胶7；依据钝化层上具有的凹槽，形成在凹槽部分的光刻胶和凹槽以外的光刻胶的厚度差，对光刻胶进行灰化处理，保留凹槽区域的光刻胶，去除凹槽以外其他区域的光刻胶以暴露出透明导电层；采用刻蚀工艺将暴露出的透明导电层去除，剥离所述凹槽部分的的光刻胶，形成透明电极的图形，参考2b-2e。
其中，关于透明电极层对于不同模式的显示模式，有不同的制作方法，对于TN模式，透明电极层为像素电极，像素电极通过过孔，连接薄膜晶体管，具体连接薄膜晶体管的漏极。
对于ADS模式，该模式在形成钝化层之前还包括公共电极，该公共电极的图形通常与栅线在同一次构图工艺中形成），该公共电极为板状，像素电极形成在梳状的凹槽内，形成梳状像素电极，该梳状电极位于公共电极的上方。当然，该透明电极层可以为公共电极，该公共电极形成在梳状的凹槽内，形成梳状公共电极，而此时，在形成钝化层之前还包括像素电极，该像素电极位于公共电极的下方，为板状。
当然，还可以制作IPS模式的显示面板，即制作梳状的像素电极和梳状的公共电极，每条像素电极和公共电极交错排列即可。
由上述实施例中的阵列基板制作方法制作的阵列基板如图2e所示，与现有技术相比，由于未采用mask来制作透明电极层，从而减少了一次mask工艺，从而节省了制作工序和制作成本。
本发明还提供了一种显示装置，包括上述阵列基板，该显示装置可以是：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明提供的显示装置、阵列基板及其制作方法，制作工艺简单，采用具有凹槽的钝化层，利用光刻胶进行灰化工艺形成透明电极层，从而省略制备透明电极的掩模板，可最大程度降低制造成本。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本发明的保护范围。

Claims (14)

1.一种阵列基板，其特征在于，包括：
基板，所述基板上依次设有薄膜晶体管、钝化层和透明电极层，所述树钝化层上形成有凹槽，所述透明电极层设置于凹槽内。
2.如权利要求1所述的阵列基板，其特征在于，所述钝化层由感光树脂材料制成。
3.如权利要求1所述的阵列基板，其特征在于，所述凹槽的高度为0.5-3um。
4.如权利要求1所述的阵列基板，其特征在于，所述透明电极层为像素电极，所述像素电极位于凹槽内。
5.如权利要求1所述的阵列基板，其特征在于，所述凹槽为梳状，所述透明电极层为像素电极，所述像素电极位于梳状凹槽内，所述阵列基板还包括位于钝化层下方的公共电极；
或者，所述凹槽为梳状，所述透明电极层为公共电极，所述公共电极位于梳状凹槽内，所述阵列基板还包括位于钝化层下方的像素电极。
6.一种显示装置，其特征在于，包括权利要求1-5任一项所述的阵列基板。
7.一种阵列基板的制作方法，其特征在于，包括如下步骤：
在基板上形成包括薄膜晶体管和钝化层的图形，所述钝化层上形成凹槽；
在凹槽内形成透明电极的图形。
8.如权利要求7所述的阵列基板的制作方法，其特征在于，在基板上形成薄膜晶体管，具体包括：
在基板上通过构图工艺形成栅极和栅线的图形；
在完成上述步骤的基板上形成栅绝缘层；
在完成上述步骤的基板上通过构图工艺形成有源层和源漏电极层的图形。
9.如权利要求7所述的阵列基板的制作方法，其特征在于，所述形成具有凹槽的钝化层的图形包括：
在形成有所述薄膜晶体管的基板上形成钝化层；
在完成上述步骤的基板上涂覆光刻胶，通过双色调掩模板对光刻胶进行曝光，对应透明电极区域的光刻胶进行部分曝光，对应暴露出漏极的过孔区域的光刻胶进行完全曝光，其他区域的光刻胶不进行曝光；
通过显影处理后，对应所述完全曝光区域的钝化层暴露出来，利用刻蚀工艺形成所述漏极的过孔；
利用灰化工艺，将所述对应透明电极区域的光刻胶去除，以暴露出钝化层；
利用刻蚀工艺将暴漏出的钝化层进行部分去除，在钝化层上形成所述凹槽。
10.如权利要求7所述的阵列基板的制作方法，其特征在于，所述形成具有凹槽的钝化层图形包括：
在形成有所述薄膜晶体管的基板上形成感光树脂层，通过双色调掩模板掩模板对感光树脂层进行曝光，使得对应透明电极区域的所述感光树脂层进行部分曝光，在对应暴露出漏极的过孔区域的所述感光树脂层进行完全曝光，其他区域的所述感光树脂层不进行曝光，通过显影工艺后，所述感光树脂层对应透明电极的区域形成凹槽的图形。
11.如权利要求7所述的阵列基板的制作方法，其特征在于，所述在凹槽内形成透明电极的图形，具体包括：
在形成凹槽的基板上形成透明导电层；
在完成上述步骤的基板上涂覆光刻胶；
依据钝化层上具有的凹槽，形成在凹槽部分的光刻胶和凹槽以外的光刻胶的厚度差，对光刻胶进行灰化处理，保留凹槽区域的光刻胶，去除凹槽以外其他区域的光刻胶以暴露出透明导电层；
采用刻蚀工艺将暴露出的透明导电层去除，剥离所述凹槽部分的的光刻胶，形成透明电极的图形。
12.如权利要求7所述的阵列基板的制作方法，其特征在于，所述透明电极为像素电极。
13.如权利要求7所述的阵列基板的制作方法，其特征在于，所述形成的凹槽为梳状，所述透明电极为像素电极，在形成钝化层之前，还包括形成公共电极的图形。
14.如权利要求7所述的阵列基板的制作方法，其特征在于，所述形成的凹槽为梳状，所述透明电极为公共电极，在形成钝化层之前，还包括形成像素电极的图形。
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CN112309836B (zh) * 2019-08-01 2022-10-28 京东方科技集团股份有限公司 一种背板及其制备方法、背光模组和显示装置
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