WO2015043055A1 - 阵列基板及其制作方法、液晶面板及显示装置 - Google Patents

阵列基板及其制作方法、液晶面板及显示装置 Download PDF

Info

Publication number
WO2015043055A1
WO2015043055A1 PCT/CN2013/088248 CN2013088248W WO2015043055A1 WO 2015043055 A1 WO2015043055 A1 WO 2015043055A1 CN 2013088248 W CN2013088248 W CN 2013088248W WO 2015043055 A1 WO2015043055 A1 WO 2015043055A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
insulating layer
substrate
groove
sub
Prior art date
Application number
PCT/CN2013/088248
Other languages
English (en)
French (fr)
Inventor
王孝林
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/402,946 priority Critical patent/US10101615B2/en
Publication of WO2015043055A1 publication Critical patent/WO2015043055A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, a liquid crystal panel, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the liquid crystal display can be divided into: Twisted Nematic (TN) type, In Plane Switching (IPS) type and Advanced Super Dimension Switch (ADS) type.
  • the ADS mode liquid crystal display forms a multi-dimensional electric field by an electric field generated by the edge of the slit electrode in the same plane in the liquid crystal display and an electric field generated between the slit electrode layer and the planar common electrode layer provided by different layers, and the electric field is mainly a horizontal electric field.
  • the horizontal electric field enables rotation of all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the slit electrode, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
  • the conventional ADS mode liquid crystal panel various electrode structures are inevitably disposed in a non-display area around the sub-pixel region, for example, a structure such as a gate line or a data line is provided. Since the pixel electrode and the common electrode are located in different layers, the electric field formed between the two is affected by the structure of the electrode around the sub-pixel, especially by the insulating layer distributed above the gate line, the data line, etc., so that the electric field has a certain attenuation. In addition, since the area of the sub-pixel display region is limited, the common electrode has a planar structure, and the electric field strength between the common electrode and the pixel electrode is not ideal, especially the electric field strength between the common electrode edge and the pixel electrode is small. Attenuating the transmittance of light in the sub-pixel region is not conducive to realizing a liquid crystal panel and a display device having a high transmittance and a wide viewing angle. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a liquid crystal panel, and a display device for providing a A liquid crystal panel and a display device having a high light transmittance in a sub-pixel region.
  • An embodiment of the present invention provides an array substrate, including: a substrate substrate; a sub-pixel region on the substrate substrate, the sub-pixel region is provided with a first electrode and a second electrode; a first insulating layer between the electrode and the second electrode; one of the first electrode and the second electrode is a common electrode, and the other is a pixel electrode; a surface of at least one of the first electrode and the second electrode is Surface.
  • the array substrate may further include a second insulating layer between the substrate substrate and the second electrode, the second insulating layer has a groove region extending in a first direction, and the second electrode A groove shape is formed on the second insulating layer in accordance with the shape of the second insulating layer.
  • the substrate substrate has a groove region extending in the first direction, and the second electrode is disposed on the substrate to form a groove shape according to the shape of the substrate.
  • the longitudinal section of the groove region in the second direction perpendicular to the first direction is an inverted trapezoidal shape.
  • an angle between at least one side surface of the groove-shaped second electrode and the substrate of the substrate is not zero. And not 90. .
  • the two side surfaces of the groove-shaped second electrode, the angle between at least one side surface of the groove-shaped second electrode and the substrate of the substrate is 30° - 75°.
  • the depth of the groove region of the second insulating layer is equal to or smaller than the thickness of the region other than the groove region.
  • the first electrode is composed of one or more sub-electrodes extending in a first direction, and the shortest distance of the first electrode from the two side surfaces of the groove-shaped second electrode is 1 to 4.5 ⁇ m.
  • the array substrate may further include: a plurality of gate lines distributed along a first direction around each sub-pixel and a plurality of data lines distributed along a second direction perpendicular to the first direction, wherein the second insulating layer is located at the Or a plurality of data lines distributed along a first direction around each sub-pixel and a plurality of gate lines distributed along a second direction perpendicular to the first direction, wherein the second insulating layer is located at Said data line.
  • the second insulating layer is a transparent resin or a black light-shielding resin.
  • An embodiment of the present invention provides a method of fabricating an array substrate, including: forming a first electrode and a second electrode pattern in a region of a sub-pixel on a substrate, and a first electrode and a second electrode a first insulating layer; one of the first electrode and the second electrode is common And the other is a pixel electrode; wherein a surface of at least one of the first electrode and the second electrode is a curved surface.
  • a first electrode and a second electrode pattern in a region of the sub-pixel are formed on the substrate of the substrate, and the first insulating layer between the first electrode and the second electrode is specifically: on the substrate of the substrate Forming a second insulating layer of a set thickness, forming a recessed region extending in the first direction in a predetermined region of the second insulating layer; forming a surface on the substrate substrate on which the second insulating layer is formed a second conductive pattern formed on the second insulating layer, the second electrode is disposed on the second insulating layer to form a groove shape according to the shape of the second insulating layer; Forming the first insulating layer on the substrate of the electrode, the first insulating layer is for insulating the second electrode and the first electrode to be formed; on the substrate substrate on which the first insulating layer is formed A conductive film layer is formed to form a first electrode pattern over the first insulating layer.
  • the depth of the groove region of the second insulating layer is equal to or smaller than the thickness of the region of the second insulating layer other than the groove region.
  • a first electrode and a second electrode pattern in a region of the sub-pixel are formed on the substrate of the substrate, and the first insulating layer between the first electrode and the second electrode is specifically: on the substrate of the substrate
  • the predetermined area is formed with a groove area extending along the first direction; a conductive film layer is formed on the substrate substrate on which the grooved area is formed, and a second electrode pattern is formed on the substrate substrate,
  • the second electrode is disposed on the substrate in a shape of a groove according to the shape of the substrate;
  • the first insulating layer is formed on the substrate on which the second electrode is formed, and the first insulating layer is used for insulating a second electrode and a first electrode to be formed;
  • a conductive film layer is formed on the substrate substrate on which the first insulating layer is formed, and a first electrode pattern is formed over the first insulating layer.
  • One embodiment of the present invention provides a liquid crystal panel comprising the array substrate of any of the above.
  • One embodiment of the present invention provides a display device including the liquid crystal panel.
  • an area between the first electrode and the second electrode is increased in the array substrate, and an electric field strength formed between the two is larger, especially an edge of the sub-pixel region.
  • the electric field strength is greater, which increases the effective electric field applied to the liquid crystal at the edge of the sub-pixel region, and improves the transmittance of light in the sub-pixel region.
  • FIG. 1 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 2 is a second schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 3 is a third schematic structural view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a fourth schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 6 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a second flowchart of a method for fabricating an array substrate according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides an array substrate and a manufacturing method thereof, a liquid crystal panel and a display device, which are used to provide a liquid crystal panel and a display device with high light transmittance in a sub-pixel region, and provide a manufacturing process The method of fabricating the array substrate.
  • Embodiments of the present invention provide an improved array substrate and liquid crystal panel of an ADS display mode.
  • the array substrate includes a village substrate and sub-pixels on the substrate, and a region of the sub-pixel is provided with a first electrode and a second electrode.
  • the array substrate further includes a first insulating layer between the first electrode and the second electrode for insulating the first electrode and the second electrode; one of the first electrode and the second electrode is a common electrode, and the other is Pixel electrode.
  • the surface of at least one of the first electrode and the second electrode is curved, whereby the surface area of the pixel electrode and the common electrode is increased, and the electric field intensity formed between the pixel electrode and the common electrode is greater, and the sub-pixel region (eg, red, green)
  • the sub-pixel region eg, red, green
  • the intensity of the electric field formed by the edge of the blue sub-pixel region or the like is larger, which increases the effective electric field applied to the liquid crystal at the edge of the sub-pixel region, and improves the transmittance of light in the sub-pixel region.
  • the pixel electrode and the common electrode are stacked.
  • the pixel electrode and the common electrode are both curved; in another embodiment, one of the pixel electrode and the common electrode is curved; the above embodiments can improve the transmittance of light in the sub-pixel region. .
  • the pixel electrode (or the common electrode) located on the bottom substrate of the substrate is closer to the substrate substrate, and the common electrode (or the pixel electrode) located on the substrate of the substrate is far from the substrate of the substrate.
  • the intensity of the electric field formed between the pixel electrode and the common electrode is greater, and the electric field intensity formed by the edge of the sub-pixel region is greater, which increases the effective electric field applied to the liquid crystal at the edge of the sub-pixel region, and improves the light of the sub-pixel region. Transmittance.
  • the curved pixel electrode (or the common electrode) can be implemented in various ways.
  • the pixel electrode or the common electrode is disposed in a groove shape, and the groove-shaped electrode structure includes a side surface and a bottom surface, and the curved electrode structure is compared.
  • the planar electrode structure can increase the electrode area of the pixel electrode or the common electrode, increase the electric field strength between the pixel electrode and the common electrode, especially increase the electric field intensity of the edge of the pixel electrode, and improve the effective electric field applied to the liquid crystal at the edge of the sub-pixel region.
  • the curved pixel electrode or the common electrode is not limited to a groove-like structure, and may be any other uneven structure.
  • the second electrode having a groove shape is taken as an example.
  • the second electrode having a groove shape has at least the following two embodiments.
  • the second insulating layer is patterned to form an insulating layer having a recessed region, and the second electrode is disposed on the second insulating layer to form a corresponding recessed surface.
  • Two electrodes; The advantage of this embodiment is that the etching conditions of the second insulating layer are relatively simple, and the process difficulty is small.
  • the groove-shaped region is directly formed on the substrate of the village, and the second electrode is placed thereon to form a corresponding groove-shaped second electrode according to the shape of the substrate of the substrate.
  • the advantage of this embodiment is that the second insulation layer is not needed, directly in the village.
  • a groove region is formed on the base substrate, and the thickness of the array substrate is relatively thin.
  • the substrate substrate may be a glass substrate or a flexible substrate.
  • a partial schematic diagram of an array substrate including a sub-pixel region (e.g., a red, green, or blue sub-pixel region, etc.) will be exemplified, that is, a film structure in which only one sub-pixel region is embodied in the array substrate.
  • the array substrate including the second electrodes formed by the above two methods will be specifically described below with reference to the drawings.
  • the array substrate includes: a substrate substrate 1; a plurality of sub-pixels on the substrate 1; the sub-pixel region is provided with a first electrode 11, The second electrode 12, the first insulating layer 13 and the second insulating layer 14; the second insulating layer 14 is located on the substrate substrate 1; the second electrode 12 is located on the second insulating layer 14; the first insulating layer 13 is located at the second electrode 12; the first electrode 11 is located on the first insulating layer 13.
  • the second insulating layer 14 has a groove region extending in a first direction (such as a direction perpendicular to the plane of the paper), and the second electrode 12 is disposed on the second insulating layer 14 to form a second surface having a curved surface.
  • the electrode 12 has a shape of a groove.
  • the groove-shaped second electrode 12 is located on the bottom of the groove of the groove-shaped second insulating layer and on the side surface of the groove.
  • One of the first electrode 11 and the second electrode 12 is a common electrode, and the other is a pixel electrode;
  • the common electrode (or the pixel electrode) is a groove-shaped electrode structure, and the pixel electrode (or the common electrode) is located at the groove-shaped electrode
  • the lateral width of the groove-shaped common electrode (or pixel electrode) is constant, the surface area increases, and the electric field strength between the common electrode and the pixel electrode increases, especially the electric field strength at the edge of the sub-pixel region increases, which improves the sub-
  • the effective electric field applied to the liquid crystal at the edge of the pixel region improves the transmittance of the light in the sub-pixel region, and finally improves the display quality of the image.
  • the first electrode may be a groove-like structure similar to the second electrode, or may be a horizontal electrode structure, which is not limited herein.
  • the second electrode 12 may also form a second electrode 12 having a curved surface according to the groove-shaped first insulating layer 13, and the second electrode 12 has a groove shape.
  • the first electrode 11 is a horizontal electrode
  • the second electrode 12 is a groove-shaped electrode
  • the longitudinal section of the groove region along the second direction perpendicular to the first direction is an inverted ladder shape.
  • the bottom area of the groove is smaller than the opening area of the opposite groove of the bottom surface, the groove It is a structure that is wide and narrow. That is, the angle ⁇ between at least one of the side surfaces of the two side surfaces of the groove-shaped second electrode 12 and the substrate 1 is not 0. And not 90. (ie, the angle ⁇ is greater than 0° and less than 90.).
  • the angle ⁇ between the two side surfaces of the groove-shaped second electrode 12 and the substrate substrate 1 may be equal or unequal.
  • angle ⁇ between the two side surfaces of the groove-shaped second electrode 12 and the substrate substrate 1 may be 30. ⁇ 75. .
  • At least one of the two side surfaces of the groove-shaped second electrode 12 is equal to the angle ⁇ between the substrate and the substrate, and preferably, the value of ⁇ is 45°.
  • An angle ⁇ between the at least one of the two side surfaces extending in the first direction of the groove-shaped second electrode and the substrate of the substrate is not 90.
  • the two side surfaces of the groove have a certain slope angle with respect to the substrate of the substrate, so that the second electrode portion located at the bottom of the groove and the second electrode portion on the side surface are not easily broken, further improving the array substrate The yield rate.
  • the depth of the groove region of the second insulating layer is equal to or smaller than the thickness of the region other than the groove region.
  • the depth of the groove region of the second insulating layer is equal to the thickness of the region other than the groove region, it is indicated that the bottom portion of the groove region is not provided with the second insulating layer, and the arrangement manner can reduce the thickness of the array substrate. .
  • the second insulating layer may be, but not limited to, a film layer made of a transparent resin or a black resin.
  • the second insulating layer may be a transparent resin to achieve an aperture ratio that does not affect the pixel.
  • the second electrode When the second electrode is located in the sub-pixel non-display area, for example, when the first electrode is a pixel electrode, the first electrode occupies almost the entire sub-pixel display area, the area of the second electrode is larger than the area of the first electrode, and the second electrode The two sides of one direction are located in the non-display area between the sub-pixel regions.
  • the second insulating layer is a black resin layer, it is located in a region corresponding to the black matrix of the color filter substrate, and the black resin layer can further function as a black matrix to prevent light leakage of the liquid crystal panel.
  • the first electrode provided in the first embodiment may be composed of one sub-electrode or a plurality of sub-electrodes.
  • the first electrode 11 is composed of a plurality of sub-electrodes 111, and the plurality of sub-electrodes 111 may be arranged in parallel or partially in parallel with the sub-electrodes 111, and the arrangement of the plurality of sub-electrodes 111 is not limited.
  • the first electrode 11 is composed of one sub-electrode 111, and the sub-electrode 111 is a strip electrode, and both sides of the strip electrode (ie, the edge of the strip electrode extending in the first direction) and the groove-shaped region respectively
  • the shortest distance s between the two side surfaces may be approximately 1 ⁇ m to 4.5 ⁇ m.
  • the thickness of the second insulating layer can be ⁇ . ⁇
  • the width of the first electrode can be 2.5 ⁇ 6 ⁇ , and the efficiency of the liquid crystal is approximately doubled.
  • the efficiency of the liquid crystal is higher; preferably, when the distance s is 1.5 ⁇ m to 3.5 ⁇ m, the efficiency of the liquid crystal is higher.
  • the array substrate of the present invention is provided between adjacent sub-pixels with a plurality of gate lines distributed along a first direction and a plurality of data lines distributed along a second direction perpendicular to the first direction (ie, mutual
  • the crossed gate lines and data lines define sub-pixels
  • the second insulating layer is on the gate lines.
  • the second insulating layer can function as a recessed region on the one hand, and can reduce the parasitic capacitance between the gate line and some other electrodes on the other hand, or prevent the electric field around the gate line from being polarized on the black matrix film layer.
  • the surface of the black matrix is induced to generate electric charges, causing a problem of residual image of the liquid crystal panel.
  • a plurality of data lines 15 distributed along a first direction and a plurality of gate lines distributed along a second direction perpendicular to the first direction are disposed between adjacent sub-pixels (
  • the gate line is not shown in FIG. 4, and the second insulating layer 14 is located on the data line 15 to cover the entire data line 15.
  • the second insulating layer 14 can function as a recessed area on the one hand, and can reduce the parasitic capacitance between the data line and other electrodes on the other hand, or prevent the electric field around the data line from polarizing the black matrix film layer. , causing the surface of the black matrix to induce a charge, causing a problem of residual image of the liquid crystal panel.
  • the array substrate provided by the above embodiment of the present invention corresponds to a liquid crystal panel of an advanced super-dimensional field switch ADS mode, for example, corresponding to a super-fine single strip electrode pixel structure or a common electrode structure, and a second electrode edge close to the substrate substrate is formed.
  • the slope of the tilt angle can effectively increase the pixel penetration rate.
  • Embodiment 2 The array substrate of another embodiment provided in the second embodiment is different from the first embodiment in that the manner of forming the second electrode is different.
  • the array substrate provided in the first embodiment, the second electrode is implemented in the above manner; the array substrate provided in the second embodiment, the second electrode is implemented in the above manner.
  • the other preferred embodiments are applicable to the second embodiment, for example, the arrangement of the first electrode, the clamping between the groove side surface and the substrate substrate.
  • the angle, the distance of the first electrode from the side surface of the second electrode, and the arrangement and advantageous effects of the data lines and the grid lines are all applicable to the second embodiment.
  • the array substrate of this embodiment includes: a substrate substrate 1; a plurality of sub-pixel regions on the substrate 1; the sub-pixel region is provided with a first electrode 11, a second electrode 12, and a first
  • the second electrode 12 is located on the substrate 1; the first insulating layer 13 is located on the second electrode 12; the first electrode 11 is located on the first insulating layer 13.
  • the bottom substrate 1 has a groove region extending in a first direction, and the second electrode 12 is disposed thereon to form a second electrode 12 having a curved surface according to the shape of the substrate 1 , and the shape of the second electrode 12 is concave. Grooved.
  • the common electrode (or the pixel electrode) is a groove-shaped electrode structure, and the pixel electrode (or the common electrode) is located above the groove-shaped electrode, and when the lateral width of the groove-shaped common electrode (or the pixel electrode) is constant, the surface area is increased, and the common
  • the electric field strength between the electrode and the pixel electrode increases, especially the electric field intensity at the edge of the sub-pixel region increases, and the effective electric field applied to the liquid crystal at the edge of the sub-pixel region is improved, thereby improving the transmittance of light in the sub-pixel region, and finally Improve the display quality of the image.
  • the first electrode and the second electrode provided in the first embodiment and the second embodiment are transparent conductive electrodes, and may be, for example, indium tin oxide (ITO) or indium oxide (IZO).
  • ITO indium tin oxide
  • IZO indium oxide
  • the array substrate is not limited to the above two embodiments, for example, the first electrode and the second electrode are curved surfaces or the first electrode is curved.
  • the curved surface is not limited to a groove shape, and may be other structures.
  • a common electrode having a curved shape may be provided in a region corresponding to each of the sub-electrodes, or a curved electrode may be provided in a region corresponding to the sub-electrodes near the edge, which is not specifically limited.
  • This embodiment provides a method for fabricating an array substrate.
  • the method of fabricating the array substrate can be carried out as follows. Forming a first electrode and a second electrode pattern in a region of the sub-pixel and a first insulating layer between the first electrode and the second electrode on the substrate of the submount; one of the first electrode and the second electrode A common electrode and a pixel electrode; a surface of at least one of the first electrode and the second electrode is a curved surface.
  • a first electrode and a second electrode pattern in a sub-pixel region and a first insulating layer between the first electrode and the second electrode are formed on the substrate substrate.
  • a specific example is:
  • insulating layer on the substrate substrate on which the second electrode is formed, the insulating layer being a first insulating layer for insulating the second electrode and the first electrode to be formed;
  • the depth of the groove region of the second insulating layer is equal to or smaller than the thickness of the region other than the groove region.
  • the depth of the groove region of the second insulating layer is equal to the thickness of the region other than the groove region, it is indicated that the bottom portion of the groove region is not provided with the second insulating layer, and the arrangement manner can reduce the thickness of the array substrate. .
  • the first electrode and the second electrode pattern in the region of the sub-pixel and the first insulating layer between the first electrode and the second electrode are formed on the substrate.
  • a specific example is:
  • a predetermined area on the substrate of the village is formed with a groove area extending in the first direction;
  • the angle between at least one of the two side surfaces of the groove-shaped second electrode and the substrate of the substrate is not zero. And not 90°.
  • an angle between at least one of the two side surfaces of the groove-shaped second electrode and the substrate of the substrate is 45°.
  • the first electrode is composed of a sub-electrode extending in a first direction, and the shortest distance of the sub-electrodes from the two side surfaces of the groove-shaped second electrode is ⁇ ⁇ 4.5 ⁇ .
  • the method for implementing any of the above array substrates further includes a process of fabricating a thin film transistor, a gate line, and a data line.
  • the embodiment of the invention further provides a liquid crystal panel comprising the array substrate of any of the above modes.
  • the liquid crystal panel may further include a color filter substrate disposed opposite to each other; or the array substrate includes a color film layer disposed on the array substrate, and the opposite substrate disposed opposite to the array substrate does not need to include color Membrane layer.
  • the liquid crystal display panel of the embodiment of the present invention is only required to include the array substrate provided in the above embodiments, and the arrangement of the color film is not limited.
  • the "patterning process" referred to in the present disclosure may include some or all of the steps of film formation, exposure, development, photolithography etching, and the like.
  • the film formation process can be achieved by deposition, spin coating, coating, and the like.
  • Embodiments of the present invention provide a display device including the above liquid crystal panel, and the display device may be a liquid crystal panel, a liquid crystal display, or a liquid crystal television.
  • an embodiment of the present invention provides an array substrate, including: a substrate substrate; a sub-pixel region on the substrate of the village, the sub-pixel region is provided with a first electrode and a second electrode; A first insulating layer for insulating the first electrode and the second electrode between the one electrode and the second electrode.
  • One of the first electrode and the second electrode is a common electrode, and the other is a pixel electrode; a surface of at least one of the first electrode and the second electrode is a curved surface.
  • the surface area of the pixel electrode and the common electrode is increased, the electric field intensity formed between the pixel electrode and the common electrode is greater, and the electric field intensity formed by the edge of the sub-pixel region (such as a red, green or blue sub-pixel region, etc.) is greater.
  • the effective electric field applied to the liquid crystal at the edge of the sub-pixel region is improved, and the transmittance of light in the sub-pixel region is improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括：衬底基板（1）；位于衬底基板（1）上的亚像素区域，亚像素区域设置有第一电极（11）和第二电极（12）；位于第一电极（11）和第二电极（12）之间的第一绝缘层（13）；第一电极（11）和第二电极（12）其中之一为公共电极，另一为像素电极；第一电极（11）和第二电极（12）至少之一的表面为曲面。该阵列基板可提高亚像素区域的光线透过率。

Description

阵列基板及其制作方法、 液晶面板及显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、液晶面板及显示装置。 背景技术
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗低、 无辐射等特点， 在当前的平板显示器市场 中占据了主导地位。
液晶显示器按照显示模式可以分为： 扭曲向列 （ Twisted Nematic, TN ) 型，平面转换（ In Plane Switching, IPS )型和高级超维场开关（ AdvancedSuper Dimension Switch, ADS )型等。 ADS模式液晶显示器通过液晶显示器中同 一平面内狭缝电极边缘所产生的电场以及狭缝电极层与不同层设置的面状公 共电极层间产生的电场形成多维电场， 该电场主要为水平电场， 该水平电场 使液晶盒内狭缝电极间、狭缝电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。
针对不同应用， ADS技术的改进技术有高透过率 I-ADS技术、 高开口率 H-ADS和高分辨率 S-ADS技术等。
现有 ADS模式液晶面板， 在亚像素区域周围的非显示区域不可避免地 设置各种电极结构， 例如设置有栅线或数据线等结构。 由于像素电极和公共 电极位于不同层， 二者之间形成的电场受亚像素周围电极结构的影响， 尤其 是受栅线、 数据线等上方分布的绝缘层的影响， 使得电场具有一定衰减。 另 夕卜， 由于亚像素显示区域的面积有限， 公共电极的为平面状结构， 公共电极 和像素电极之间的电场强度不够理想， 尤其是公共电极边缘与像素电极之间 的电场强度较小， 影响亚像素区域光线的穿透率， 不利于实现高透过率、 广 视角的液晶面板和显示装置。 发明内容
本发明实施例提供一种阵列基板、 液晶面板及显示装置， 用以提供一种 亚像素区域光线透过率较高的液晶面板和显示装置。
本发明的一个实施例提供了一种阵列基板， 其包括： 村底基板； 位于所 述村底基板上的亚像素区域， 所述亚像素区域设置有第一电极和第二电极； 位于第一电极和第二电极之间的第一绝缘层； 所述第一电极和第二电极其中 之一为公共电极， 另一为像素电极； 所述第一电极和第二电极至少之一的表 面为曲面。
例如， 该阵列基板还可以包括位于所述村底基板与所述第二电极之间的 第二绝缘层， 所述第二绝缘层具有沿第一方向延伸的凹槽区域， 所述第二电 极依照所述第二绝缘层的形状设置于其上形成凹槽状。
例如， 所述村底基板具有沿第一方向延伸的凹槽区域， 所述第二电极依 照所述村底基板的形状设置于其上形成凹槽状。
例如， 所述凹槽区域沿与所述第一方向垂直的第二方向的纵截面为倒立 的梯形状。
例如， 所述凹槽状第二电极的至少一个侧表面与所述村底基板之间的夹 角非 0。 且非 90。 。
例如， 所述凹槽状第二电极的两个侧表面， 所述凹槽状第二电极的至少 一个侧表面与所述村底基板之间的夹角为 30° -75° 。
例如， 所述第二绝缘层的凹槽区域的深度等于或小于除所述凹槽区域之 外的区域的厚度。
例如， 所述第一电极由一个或多个沿第一方向延伸的子电极组成， 所述 第一电极距离所述凹槽状第二电极的两个侧表面的最短距离为 1 ~4.5μιη。
例如， 该阵列基板还可以包括： 位于各亚像素周围沿第一方向分布的多 条栅线和沿与第一方向垂直的第二方向分布的多条数据线， 所述第二绝缘层 位于所述栅线上； 或者还包括： 位于各亚像素周围沿第一方向分布的多条数 据线和沿与第一方向垂直的第二方向分布的多条栅线， 所述第二绝缘层位于 所述数据线上。
例如， 所述第二绝缘层为透明树脂或黑色遮光树脂。
本发明的一个实施例提供一种阵列基板的制作方法， 其包括： 在村底基 板上形成位于亚像素的区域中的第一电极和第二电极图形， 以及位于第一电 极和第二电极之间的第一绝缘层； 所述第一电极和第二电极其中之一为公共 电极， 另一为像素电极； 其中， 所述第一电极和第二电极至少之一的表面为 曲面。
例如， 在村底基板上形成位于亚像素的区域中的第一电极和第二电极图 形， 以及位于第一电极和第二电极之间的第一绝缘层具体为： 在所述村底基 板上形成一层设定厚度的第二绝缘层， 在该第二绝缘层的预设区域形成具有 沿第一方向延伸的凹槽区域； 在形成有所述第二绝缘层的村底基板上形成一 层导电膜层， 形成位于所述第二绝缘层上的第二电极图形， 所述第二电极依 照所述第二绝缘层的形状设置于其上形成凹槽状； 在形成有所述第二电极的 村底基板上形成所述第一绝缘层， 该第一绝缘层为用于绝缘所述第二电极和 待形成的第一电极； 在形成有所述第一绝缘层的村底基板上形成一层导电膜 层， 形成位于所述第一绝缘层上方的第一电极图形。
例如， 所述第二绝缘层的凹槽区域的深度等于或小于第二绝缘层中除所 述凹槽区域之外的区域的厚度。
例如， 在村底基板上形成位于亚像素的区域中的第一电极和第二电极图 形， 以及位于第一电极和第二电极之间的第一绝缘层具体为： 在所述村底基 板上的预设区域形成具有沿第一方向延伸的凹槽区域； 在形成有凹槽区域的 村底基板上形成一层导电膜层， 形成位于所述村底基板上的第二电极图形， 所述第二电极依照所述村底基板的形状设置于其上形成凹槽状； 在形成有所 述第二电极的基板上形成所述第一绝缘层， 该第一绝缘层为用于绝缘所述第 二电极和待形成的第一电极； 在形成有所述第一绝缘层的村底基板上形成一 层导电膜层， 形成位于所述第一绝缘层上方的第一电极图形。
本发明的一个实施例提供的一种液晶面板， 其包括上述任一方式的阵列 基板。
本发明的一个实施例提供的一种显示装置， 其包括所述液晶面板。 综上所述， 在本发明实施例提供一种阵列基板中， 第一电极和第二电极 之间的面积增加， 二者之间形成的电场强度更大， 尤其是亚像素区域的边缘 形成的电场强度更大， 这提高了亚像素区域边缘加在液晶上的有效电场， 提 高了亚像素区域光线的透过率。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例一提供的阵列基板结构示意图之一；
图 2为本发明实施例一提供的阵列基板结构示意图之二；
图 3为本发明实施例一提供的阵列基板结构示意图之三；
图 4为本发明实施例一提供的阵列基板结构示意图之四；
图 5为本发明实施例二提供的阵列基板结构示意图；
图 6为本发明实施例提供的阵列基板制作方法流程图之一；
图 7为本发明实施例提供的阵列基板制作方法流程图之二。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的 "第一"、 "第 二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分 不同的组成部分。 同样， "一个" 、 "一" 或者 "该" 等类似词语也不表示 数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意 指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及 其等同， 而不排除其他元件或者物件。 "上" 、 "下" 、 "左" 、 "右" 等 仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置 关系也可能相应地改变。
本发明实施例提供一种阵列基板及其制作方法、 液晶面板及显示装置， 用以提供一种亚像素区域光线透过率较高的液晶面板和显示装置， 以及提供 一种制作工艺较筒单的阵列基板的制作方法。
本发明实施例提供一种改进的 ADS 显示模式的阵列基板和液晶面板。 所述阵列基板包括村底基板和位于所述村底基板上的亚像素， 所述亚像素所 在区域设置有第一电极和第二电极。 该阵列基板还包括位于第一电极和第二 电极之间用于绝缘第一电极和第二电极的第一绝缘层； 所述第一电极和第二 电极其中之一为公共电极， 另一为像素电极。 所述第一电极和第二电极至少 之一的表面为曲面， 由此像素电极和公共电极的表面积增加， 像素电极和公 共电极之间形成的电场强度更大， 亚像素区域（如红色、 绿色或蓝色亚像素 区域等） 的边缘形成的电场强度更大， 这提高了亚像素区域边缘加在液晶上 的有效电场， 提高了亚像素区域光线的透过率。
优选地， 像素电极和公共电极叠层设置。 本发明的一个实施例中， 像素 电极和公共电极均为曲面状； 另一个实施例中， 像素电极和公共电极其中之 一为曲面状； 上述实施例均可以提高亚像素区域光线的透过率。
更优选地，位于村底基板上距离村底基板较近的像素电极（或公共电极） 为曲面状， 位于村底基板上距离村底基板较远的公共电极（或像素电极） 为 平面状， 由此像素电极和公共电极之间形成的电场强度更大， 亚像素区域的 边缘形成的电场强度更大，这提高了亚像素区域边缘加在液晶上的有效电场， 提高了亚像素区域光线的透过率。
曲面状的像素电极（或公共电极）可以有多种实现方式， 较佳地， 像素 电极或公共电极设置为凹槽状， 凹槽状的电极结构包括侧表面和底面， 曲面 状电极结构相比较平面状电极结构可以增加像素电极或公共电极的电极面 积， 增加像素电极和公共电极之间的电场强度， 尤其增加像素电极边缘电场 强度， 提高亚像素区域边缘加在液晶上的有效电场。 当然， 曲面状的像素电 极或公共电极不限于为凹槽状结构， 也可以为其他任何凹凸不平状结构。
需要说明的是， 本发明实施例附图中的各功能膜层的厚度不代表真实的 厚度， 各膜层之间的相对厚度也不代表真实的相对厚度， 本发明实施例提供 的附图仅用于示意性地说明本发明。
以下将结合附图具体说明本发明实施例提供的阵列基板及其制作方法、 液晶面板及显示装置。
下面以凹槽状第二电极为例说明， 形成凹槽状第二电极至少有以下两种 实施方式。
方式一 在表面平整的村底基板上设置第二绝缘层， 对第二绝缘层进行构图工艺 形成具有凹槽区域的绝缘层， 第二电极依照第二绝缘层置于其上形成对应的 凹槽状第二电极； 该实施方式的优点在于第二绝缘层的刻蚀条件较筒单， 实 现工艺难度较小。
方式二
直接在村底基板上制作凹槽状区域， 第二电极依照村底基板的形状置于 其上形成对应的凹槽状第二电极， 该实施方式的优点在于无需第二绝缘层， 直接在村底基板上制作凹槽区域， 阵列基板的厚度相对较薄。
本发明实施例中， 村底基板可以选用玻璃基板或柔性基板等。
下面将以包括一个亚像素区域（如红色、 绿色或蓝色亚像素区域等） 的 阵列基板局部示意图为例说明， 即在阵列基板中仅体现一个亚像素区域的膜 层结构。 以下将通过附图分别具体说明包括上述两种方式形成的第二电极的 阵列基板。
实施例一
图 1为本发明实施例提供的阵列基板的截面示意图， 该阵列基板包括： 村底基板 1; 位于村底基板 1上的多个亚像素， 所述亚像素的区域设置有第 一电极 11、 第二电极 12、 第一绝缘层 13和第二绝缘层 14; 第二绝缘层 14 位于村底基板 1上；第二电极 12位于第二绝缘层 14上；第一绝缘层 13位于 第二电极 12上； 第一电极 11位于第一绝缘层 13上。 第二绝缘层 14具有沿 第一方向（如图 1垂直于纸面的方向）延伸的凹槽区域， 第二电极 12依照第 二绝缘层 14的形状设置于其上形成表面为曲面的第二电极 12, 该第二电极 12的形状为凹槽状。
凹槽状的第二电极 12位于凹槽状第二绝缘层的凹槽的底部和凹槽的侧 表面上。
第一电极 11和第二电极 12其中之一为公共电极， 另一为像素电极； 公 共电极（或像素电极） 为凹槽状的电极结构， 像素电极（或公共电极）位于 凹槽状的电极上方， 凹槽状的公共电极（或像素电极） 的横向宽度一定时， 表面积增加， 公共电极和像素电极之间的电场强度增加， 尤其是位于亚像素 区域边缘的电场强度增加，这提高了亚像素区域边缘加在液晶上的有效电场， 从而提高了亚像素区域光线的穿透率， 最终提高了图像的显示品质。 所述第一电极可以为类似于第二电极的凹槽状结构， 也可以为水平状电 极结构， 这里不做限制。 例如： 第二电极 12也可以根据依照凹槽状的第一绝 缘层 13, 形成表面为曲面的第二电极 12, 该第二电极 12的形状为凹槽状。
优选地， 参见图 1 , 第一电极 11为水平状电极， 第二电极 12为凹槽状 电极。
优选地， 参见图 1 , 凹槽区域沿与第一方向垂直的第二方向的纵截面为 倒立的梯形状， 换句话说， 凹槽的底面积小于底面相对的凹槽的开口面积， 凹槽为上宽下窄的结构。即凹槽状第二电极 12的两个侧表面至少其中一个侧 表面与村底基板 1之间的夹角 α非 0。 且非 90。 （也即夹角 α大于 0° 且小于 90。 ）。 当然， 凹槽状第二电极 12的两个侧表面与村底基板 1之间的夹角 α 可以相等或不相等。
进一步地，凹槽状第二电极 12的两个侧表面分别与村底基板 1之间的夹 角 α可以为 30。 ~75。 。
更进一步地，凹槽状第二电极 12的两个侧表面至少之一与村底基板之间 的夹角 α相等， 优选地， α值为 45° 。
上述凹槽状第二电极沿第一方向延伸的两个侧表面至少之一与村底基板 之间的夹角 α非 90。 ， 凹槽的两个侧表面相对于村底基板具有一定坡度角， 因此位于凹槽底部的第二电极部分和位于侧表面上的第二电极部分之间不容 易形成断裂， 进一步提高了阵列基板的良品率。
较佳地， 所述第二绝缘层的凹槽区域的深度等于或小于除所述凹槽区域 之外的区域的厚度。 当第二绝缘层的凹槽区域的深度等于除所述凹槽区域之 外的区域的厚度， 则说明凹槽区域的底部不设置有第二绝缘层， 这样的设置 方式可以降低阵列基板的厚度。
较佳地， 所述第二绝缘层可以但不限于为透明树脂或黑色树脂等制作的 膜层。
当第二电极位于亚像素显示区域时， 第二绝缘层可以为透明树脂， 以实 现不影响像素的开口率。
当第二电极位于亚像素非显示区域时， 例如当第一电极为像素电极时， 第一电极几乎占据整个亚像素显示区域， 第二电极的面积大于第一电极的面 积， 第二电极沿第一方向的两个侧面位于亚像素区域之间的非显示区域。 因 此， 第二绝缘层为黑色树脂层时， 位于与彩膜基板黑矩阵相对应的区域， 黑 色树脂层还可以进一步起到黑矩阵的作用， 防止液晶面板漏光的现象。
实施例一提供的第一电极可以由一个子电极组成， 也可以由多个子电极 组成。
参见图 2, 第一电极 11由多个子电极 111组成， 多个子电极 111的排列 方式可以平行或部分子电极 111平行，多个子电极 111的设置方式不做限制。
如图 3所示，第一电极 11由一个子电极 111组成，子电极 111为条状电 极， 条状电极的两侧（即条状电极沿第一方向延伸的边缘）分别与凹槽状区 域的两个侧表面之间的最短距离 s可以大约为 1μιη ~4.5μιη。
通过液晶光学模拟软件模拟发现， 第二绝缘层的厚度可以为 Ι.ΐμιη
~3.6μιη, 第一电极的宽度可以为 2.5μιη~6μιη, 液晶的效率约提高一倍。距离 s大约为 1μιη ~4.5μιη时， 液晶的效率更高； 较佳地，距离 s为 1.5μιη ~3.5μιη 时， 液晶的效率更高。
较佳地， 本发明所述阵列基板在相邻亚像素之间设置有沿第一方向分布 的多条栅线和沿与第一方向垂直的第二方向分布的多条数据线（也即相互交 叉的栅线和数据线限定出亚像素） ， 所述第二绝缘层位于所述栅线上。 该第 二绝缘层一方面可以起到凹陷区域的作用， 另一方面还可以减小栅线和其它 一些电极之间的寄生电容， 或者避免栅线周围的电场对黑矩阵膜层造成电极 化， 使得黑矩阵表面感应出电荷， 造成液晶面板残像的问题。
参见图 4, 或者， 本发明所述阵列基板在相邻亚像素之间设置有沿第一 方向分布的多条数据线 15 和沿与第一方向垂直的第二方向分布的多条栅线 (图 4中未体现栅线 ) ,第二绝缘层 14位于数据线 15上覆盖整条数据线 15。 该第二绝缘层 14一方面可以起到凹陷区域的作用，另一方面还可以减小数据 线和其它一些电极之间的寄生电容， 或者避免数据线周围的电场对黑矩阵膜 层造成电极化， 使得黑矩阵表面感应出电荷， 造成液晶面板残像的问题。
本发明上述实施例提供的阵列基板， 对应于高级超维场开关 ADS模式 的液晶面板， 例如对应超精细的单一条状电极像素结构或公共电极结构， 靠 近村底基板的第二电极边缘形成一定倾斜角度的斜坡， 可以有效提高像素的 穿透率。
实施例二 实施例二提供的另一方式的阵列基板， 与实施例一不同之处在于， 形成 第二电极的方式不同。 实施例一提供的阵列基板， 第二电极按照上述方式一 实现； 实施例二提供的阵列基板， 第二电极按照上述方式二实现。 实施例一 中除第二电极的形成方式不同于实施例二， 其他较佳的实施方式均适用于实 施例二， 例如第一电极的设置方式、 凹槽侧表面与村底基板之间的夹角、 第 一电极距离第二电极侧表面的距离， 以及数据线和栅线的设置方式和有益效 果等均适用于实施二。
参见图 5, 本实施例的阵列基板包括： 村底基板 1; 位于村底基板 1上的 多个亚像素区域， 所述亚像素的区域设置有第一电极 11、 第二电极 12和第 一绝缘层 13; 第二电极 12位于村底基板 1上； 第一绝缘层 13位于第二电极 12上； 第一电极 11位于第一绝缘层 13上。 村底基板 1上具有沿第一方向延 伸的凹槽区域，第二电极 12依照村底基板 1的形状设置于其上形成表面为曲 面的第二电极 12, 该第二电极 12的形状为凹槽状。
公共电极（或像素电极）为 槽状的电极结构， 像素电极（或公共电极） 位于凹槽状的电极上方， 凹槽状的公共电极（或像素电极） 的横向宽度一定 时， 表面积增加， 公共电极和像素电极之间的电场强度增加， 尤其是位于亚 像素区域边缘的电场强度增加， 提高了亚像素区域边缘加在液晶上的有效电 场， 从而提高了亚像素区域光线的穿透率， 最终提高了图像的显示品质。
较佳地， 实施例一和实施例二提供的所述第一电极和第二电极为透明导 电电极， 例如可以为铟锡氧化物（ITO )或铟辞氧化物 （IZO )等。
上述两个实施例仅是本发明提供的较优选的实施方式， 在具体实施过程 中阵列基板不限于上述两种实施方式， 例如第一电极和第二电极均为曲面或 第一电极为曲面的情况。 所述曲面不限于为凹槽状， 也可以为其他结构。 对 于多个子电极构成的第一电极， 可以在每一个子电极对应的区域设置具曲面 状的公共电极， 也可以在靠近边缘的子电极对应的区域设置曲面状电极， 这 里不做具体限定。
以下将具体说明上述实施例提供的阵列基板的制作方法：
实施例三
本实施例提供了一种阵列基板的制作方法。 该阵列基板的制作方法可如 下进行。 在村底基板上形成位于亚像素的区域中的第一电极和第二电极图形以及 位于第一电极和第二电极之间的第一绝缘层； 所述第一电极和第二电极其中 之一为公共电极， 另一为像素电极； 所述第一电极和第二电极至少之一的表 面为曲面。
针对第一实施例提供的阵列基板， 参见图 6, 在村底基板上形成位于亚 像素区域中的第一电极和第二电极图形以及位于第一电极和第二电极之间的 第一绝缘层的一个具体示例为：
511、 在所述村底基板上形成一层设定厚度的绝缘层， 采用构图工艺在 该绝缘层上预设区域形成具有沿第一方向延伸的凹槽区域， 具有凹槽区域的 绝缘层为第二绝缘层；
512、 在形成有所述第二绝缘层的村底基板上形成一层导电膜层， 通过 构图工艺形成位于所述第二绝缘层上的第二电极图形， 所述第二电极依照所 述第二绝缘层的形状设置于其上形成凹槽状；
513、 在形成有所述第二电极的村底基板上形成一层绝缘层， 该绝缘层 为用于绝缘所述第二电极和待形成的第一电极的第一绝缘层；
514、 在形成有所述第一绝缘层的村底基板上形成一层导电膜层， 通过 构图工艺形成位于所述第一绝缘层上方的第一电极图形。
较佳地， 所述第二绝缘层的凹槽区域的深度等于或小于除所述凹槽区域 之外的区域的厚度。 当第二绝缘层的凹槽区域的深度等于除所述凹槽区域之 外的区域的厚度， 则说明凹槽区域的底部不设置有第二绝缘层， 这样的设置 方式可以降低阵列基板的厚度。
针对第二实施例提供的阵列基板， 参见图 7, 在基板上形成位于亚像素 的区域中的第一电极和第二电极图形以及位于第一电极和第二电极之间的第 一绝缘层的一个具体示例为：
S21、 在所述村底基板上的预设区域形成具有沿第一方向延伸的凹槽区 域；
S22、 在形成有凹槽区域的村底基板上形成一层导电膜层， 通过构图工 艺形成位于所述村底基板上的第二电极图形， 所述第二电极依照所述村底基 板的形状设置于其上形成凹槽状；
S23、 在形成有所述第二电极的村底基板上形成一层绝缘层， 该绝缘层 为用于绝缘所述第二电极和待形成的第一电极的第一绝缘层；
S24、 在形成有所述第一绝缘层的村底基板上形成一层导电膜层， 通过 构图工艺形成位于所述第一绝缘层上方的第一电极图形。
优选地， 上述任一种阵列基板的实现方法， 所述凹槽状第二电极的两个 侧表面至少之一与所述村底基板之间的夹角非 0。 且非 90° 。
进一步地， 所述凹槽状第二电极的两个侧表面至少之一与所述村底基板 之间的夹角为 45° 。
优选地， 所述第一电极由一个沿第一方向延伸的子电极组成， 所述子电 极距离所述凹槽状第二电极的两个侧表面的最短距离为 Ιμιη ~4.5μιη。
优选地， 上述任一种阵列基板的实现方法， 还包括制作薄膜晶体管、 栅 线和数据线的过程。
本发明实施例还提供一种液晶面板， 包括上述任一种方式的阵列基板。 所述液晶面板还可以包括彩膜基板， 二者彼此相对设置； 或者， 该阵列基板 包括设置在阵列基板上的彩膜层， 而与该阵列基板相对设置的对置基板上则 无需再包括彩膜层。 本发明实施例的液晶显示面板只要包括上述实施例提供 的阵列基板即可， 彩膜的设置不做限制。
本公开所称的 "构图工艺" 可以包括成膜、 曝光、 显影、 光刻刻蚀等部 分或全部步骤。 成膜工艺可以采用沉积、 旋涂、 涂覆等方式等实现。
本发明实施例提供一种显示装置， 包括上述液晶面板， 所述显示装置可 以为液晶面板、 液晶显示器， 或液晶电视等。
综上所述， 本发明实施例提供一种阵列基板， 包括： 村底基板； 位于所 述村底基板上的亚像素区域， 所述亚像素区域设置有第一电极和第二电极； 位于第一电极和第二电极之间用于绝缘第一电极和第二电极的第一绝缘层。 所述第一电极和第二电极其中之一为公共电极， 另一为像素电极； 所述第一 电极和第二电极至少之一的表面为曲面。 由此像素电极和公共电极的表面积 增加，像素电极和公共电极之间形成的电场强度更大， 亚像素区域（如红色、 绿色或蓝色亚像素区域等） 的边缘形成的电场强度更大， 提高了亚像素区域 边缘加在液晶上的有效电场， 提高了亚像素区域光线的透过率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括：
村底基板；
位于所述村底基板上的亚像素区域， 所述亚像素区域设置有第一电极和 第二电极；
位于第一电极和第二电极之间的第一绝缘层；
其中， 所述第一电极和第二电极至少之一的表面为曲面。
2、根据权利要求 1所述的阵列基板，还包括位于所述村底基板与所述第 二电极之间的第二绝缘层， 其中， 所述第二绝缘层具有沿第一方向延伸的凹 槽区域， 所述第二电极依照所述第二绝缘层的形状设置于其上形成凹槽状。
3、根据权利要求 1所述的阵列基板， 其中， 所述村底基板具有沿第一方 向延伸的凹槽区域， 所述第二电极依照所述村底基板的形状设置于其上形成 凹槽状。
4、根据权利要求 2或 3所述的阵列基板， 其中， 所述凹槽区域沿与所述 第一方向垂直的第二方向的纵截面为倒立的梯形状。
5、根据权利要求 4所述的阵列基板， 其中， 所述凹槽状第二电极的至少 一个侧表面与所述村底基板之间的夹角非 0° 且非 90。 。
6、根据权利要求 2所述的阵列基板， 其中， 所述第二绝缘层的凹槽区域 的深度等于或小于除所述凹槽区域之外的区域的厚度。
7、根据权利要求 2或 3所述的阵列基板， 其中， 所述第一电极由一个或 多个沿第一方向延伸的子电极组成， 所述第一电极距离所述凹槽状第二电极 的两个侧表面的最短距离为 1~4.5μιη。
8、 根据权利要求 1-7任一所述的阵列基板， 还包括： 位于各亚像素周围 沿第一方向分布的多条栅线和沿与第一方向垂直的第二方向分布的多条数据 线， 所述第二绝缘层位于所述栅线上； 或者
还包括： 位于各亚像素周围沿第一方向分布的多条数据线和沿与第一方 向垂直的第二方向分布的多条栅线， 所述第二绝缘层位于所述数据线上。
9、根据权利要求 8所述的阵列基板， 其中， 所述第二绝缘层为透明树脂 或黑色遮光树脂。
10、 一种阵列基板的制作方法， 包括：
在村底基板上形成位于亚像素的区域中的第一电极和第二电极图形， 以 及位于第一电极和第二电极之间的第一绝缘层； 其中， 所述第一电极和第二 电极至少之一的表面为曲面。
11、根据权利要求 10所述的方法， 其中， 在所述村底基板上形成一层设 定厚度的第二绝缘层， 在该第二绝缘层的预设区域形成具有沿第一方向延伸 的凹槽区域；
在形成有所述第二绝缘层的村底基板上形成一层导电膜层， 形成位于所 述第二绝缘层上的第二电极图形， 所述第二电极依照所述第二绝缘层的形状 设置于其上形成凹槽状；
在形成有所述第二电极的村底基板上形成所述第一绝缘层， 该第一绝缘 层为用于绝缘所述第二电极和待形成的第一电极；
在形成有所述第一绝缘层的村底基板上形成一层导电膜层， 形成位于所 述第一绝缘层上方的第一电极图形。
12、根据权利要求 11所述的方法， 其中， 所述第二绝缘层的凹槽区域的 深度等于或小于第二绝缘层中除所述凹槽区域之外的区域的厚度。
13、 根据权利要求 10所述的方法， 其中，
在所述村底基板上的预设区域形成具有沿第一方向延伸的凹槽区域； 在形成有凹槽区域的村底基板上形成一层导电膜层， 形成位于所述村底 基板上的第二电极图形， 所述第二电极依照所述村底基板的形状设置于其上 形成凹槽状；
在形成有所述第二电极的村底基板上形成所述第一绝缘层， 该第一绝缘 层为用于绝缘所述第二电极和待形成的第一电极；
在形成有所述第一绝缘层的村底基板上形成一层导电膜层， 形成位于所 述第一绝缘层上方的第一电极图形。
14、 一种液晶面板， 包括权利要求 1-9任一权项所述的阵列基板。
15、 一种显示装置， 包括权利要求 14所述的液晶面板。
PCT/CN2013/088248 2013-09-26 2013-11-30 阵列基板及其制作方法、液晶面板及显示装置 WO2015043055A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/402,946 US10101615B2 (en) 2013-09-26 2013-11-30 Array substrate and manufacturing method thereof, liquid crystal panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310446572.8 2013-09-26
CN201310446572.8A CN103488003B (zh) 2013-09-26 2013-09-26 一种阵列基板及其制作方法、液晶面板及显示装置

Publications (1)

Publication Number Publication Date
WO2015043055A1 true WO2015043055A1 (zh) 2015-04-02

Family

ID=49828341

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/088248 WO2015043055A1 (zh) 2013-09-26 2013-11-30 阵列基板及其制作方法、液晶面板及显示装置

Country Status (3)

Country Link
US (1) US10101615B2 (zh)
CN (1) CN103488003B (zh)
WO (1) WO2015043055A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103838044B (zh) * 2014-02-26 2017-08-29 京东方科技集团股份有限公司 基板及其制造方法、显示装置
CN105957870A (zh) * 2016-06-29 2016-09-21 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板制备方法
CN106773335A (zh) * 2016-12-30 2017-05-31 深圳市华星光电技术有限公司 一种液晶显示面板
US10394093B2 (en) 2017-07-07 2019-08-27 HKC Corporation Limited Array substrate, manufacturing method thereof, and applied display panel thereof
CN107167974A (zh) * 2017-07-07 2017-09-15 惠科股份有限公司 阵列基板及其制造方法与应用的显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070002236A1 (en) * 2005-06-30 2007-01-04 Lg.Philips Lcd Co., Ltd. Multi-domain LCD device and method of fabricating the same
CN101900913A (zh) * 2009-05-29 2010-12-01 株式会社半导体能源研究所 液晶显示装置及其制造方法
JP2011237836A (ja) * 2011-08-31 2011-11-24 Sony Corp 液晶装置及び電子機器
CN102629055A (zh) * 2011-10-24 2012-08-08 北京京东方光电科技有限公司 显示器件的阵列基板、彩膜基板及其制备方法
CN103151359A (zh) * 2013-03-14 2013-06-12 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN103293811A (zh) * 2013-05-30 2013-09-11 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103323993A (zh) * 2012-03-19 2013-09-25 群康科技(深圳)有限公司 液晶显示装置及导电基板的制作方法
CN203480176U (zh) * 2013-09-26 2014-03-12 京东方科技集团股份有限公司 一种阵列基板、液晶面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642984B1 (en) * 1998-12-08 2003-11-04 Fujitsu Display Technologies Corporation Liquid crystal display apparatus having wide transparent electrode and stripe electrodes
US7863612B2 (en) * 2006-07-21 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Display device and semiconductor device
KR101802137B1 (ko) * 2008-07-10 2017-11-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치 및 전자 기기
CN202256974U (zh) 2011-10-25 2012-05-30 京东方科技集团股份有限公司 一种边缘场开关模式的液晶显示面板
KR20140046331A (ko) * 2012-10-10 2014-04-18 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치 제조 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070002236A1 (en) * 2005-06-30 2007-01-04 Lg.Philips Lcd Co., Ltd. Multi-domain LCD device and method of fabricating the same
CN101900913A (zh) * 2009-05-29 2010-12-01 株式会社半导体能源研究所 液晶显示装置及其制造方法
JP2011237836A (ja) * 2011-08-31 2011-11-24 Sony Corp 液晶装置及び電子機器
CN102629055A (zh) * 2011-10-24 2012-08-08 北京京东方光电科技有限公司 显示器件的阵列基板、彩膜基板及其制备方法
CN103323993A (zh) * 2012-03-19 2013-09-25 群康科技(深圳)有限公司 液晶显示装置及导电基板的制作方法
CN103151359A (zh) * 2013-03-14 2013-06-12 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN103293811A (zh) * 2013-05-30 2013-09-11 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN203480176U (zh) * 2013-09-26 2014-03-12 京东方科技集团股份有限公司 一种阵列基板、液晶面板及显示装置

Also Published As

Publication number Publication date
CN103488003B (zh) 2017-02-01
CN103488003A (zh) 2014-01-01
US20160252787A1 (en) 2016-09-01
US10101615B2 (en) 2018-10-16

Similar Documents

Publication Publication Date Title
JP4543006B2 (ja) 液晶表示素子及びその製造方法
KR101925983B1 (ko) 액정표시소자 및 그 제조방법
KR101779510B1 (ko) 액정 표시 장치 및 그 제조 방법
US9606392B2 (en) Display panel and liquid crystal display including the same
WO2013071840A1 (zh) Tft阵列基板及显示设备
TWI518424B (zh) 藍相液晶顯示面板
WO2015085704A1 (zh) 阵列基板及其制备方法、液晶显示装置
JP5526085B2 (ja) 液晶表示装置
US10114250B2 (en) Liquid crystal display and manufacturing method thereof
US9664962B2 (en) Liquid crystal display device
WO2017070996A1 (zh) 一种视角可调控的液晶显示面板及其视角调控方法
JP2006031022A (ja) 液晶表示器
WO2016095302A1 (zh) 液晶显示面板
WO2015103870A1 (zh) 显示基板和显示装置
WO2015085690A1 (zh) 显示装置、阵列基板及其制作方法
WO2015043055A1 (zh) 阵列基板及其制作方法、液晶面板及显示装置
WO2014187104A1 (zh) 显示面板及其制造方法、显示装置
KR102122538B1 (ko) 액정표시장치
WO2019062320A1 (zh) 阵列基板及其制备方法、显示装置
JP2007133409A (ja) 垂直配向モード液晶表示装置
WO2018113061A1 (zh) 阵列基板、彩膜基板及液晶面板
KR20150105597A (ko) 액정 디스플레이 장치
JP2015102684A (ja) 液晶表示装置及び３次元表示装置
KR101146490B1 (ko) 횡전계 방식 액정 표시 장치용 어레이 기판 및 그 제조 방법
JP2008152157A (ja) 液晶表示装置およびその製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14402946

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13894330

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 23.08.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13894330

Country of ref document: EP

Kind code of ref document: A1