WO2014139283A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2014139283A1
WO2014139283A1 PCT/CN2013/085103 CN2013085103W WO2014139283A1 WO 2014139283 A1 WO2014139283 A1 WO 2014139283A1 CN 2013085103 W CN2013085103 W CN 2013085103W WO 2014139283 A1 WO2014139283 A1 WO 2014139283A1
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WIPO (PCT)
Prior art keywords
array substrate
electrode
groove
passivation layer
forming
Prior art date
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PCT/CN2013/085103
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English (en)
French (fr)
Inventor
崔承镇
刘圣烈
宋泳锡
Original Assignee
京东方科技集团股份有限公司
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Filing date
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/362,241 priority Critical patent/US9465264B2/en
Priority to EP13857663.2A priority patent/EP2975642B1/en
Publication of WO2014139283A1 publication Critical patent/WO2014139283A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the TFT-LCD is formed by pairing a color filter substrate and an array substrate, and the existing array substrate is usually formed by a multiple mask process.
  • the array substrate includes: a substrate 1; a gate electrode, a gate insulating layer 2, and a semiconductor layer, which are disposed on the substrate 1; and a source electrode 3
  • the drain electrode 4 is provided on the insulating layer 2; the passivation layer 5 is provided above and around the source electrode 3 and the drain electrode 4; and the pixel electrode 6 is provided on the passivation layer 5.
  • the pixel electrode 6 is usually formed by a patterning process using a mask. In the fabrication process of TFT-LCD, the fabrication cost of the mask is very expensive, and more than one mask process will have a great impact on the productivity and yield. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which do not use a mask template to form a transparent electrode, thereby reducing the mask process process and reducing the production cost.
  • an embodiment of the present invention provides an array substrate, including: a substrate; a thin film transistor, a passivation layer, and a transparent electrode, which are sequentially formed on the substrate, wherein an upper surface of the passivation layer is formed with a groove, The transparent electrode is disposed in the groove.
  • the passivation layer is made of a photosensitive resin material.
  • the groove has a depth of 0.5 - 3 ⁇ m.
  • the transparent electrode functions as a pixel electrode, and the pixel electrode is located in the recess.
  • the groove is formed in a comb shape, the transparent electrode is a pixel electrode, the pixel electrode is formed in a comb shape, and the array substrate further includes a common electrode disposed with the passivation layer through the pixel electrode .
  • the groove is formed in a comb shape, the transparent electrode is a common electrode, the common electrode is formed in a comb shape, and the array substrate further includes a pixel electrode disposed with the passivation layer via the common electrode .
  • an embodiment of the present invention further provides a method of fabricating an array substrate, comprising: forming a thin film transistor and a passivation layer on a substrate, the passivation layer covering the thin film transistor and the passivation layer a surface is formed with a groove; and a transparent electrode is formed in the groove.
  • the forming a thin film transistor on the substrate includes: forming a gate and a gate line by a patterning process on the substrate; forming a gate insulating layer on the gate and the gate line; and passing on the gate insulating layer
  • the patterning process forms an active layer and source and drain electrodes.
  • forming a recess on an upper surface of the passivation layer includes: forming the passivation layer on a substrate on which the thin film transistor is formed; coating a photoresist on the passivation layer, through The photomask is exposed by a tone mask, wherein the photoresist corresponding to the region where the transparent electrode is located is partially exposed, and the photoresist corresponding to the region where the via of the drain is exposed is completely exposed, and photolithography is performed in other regions.
  • the glue is not exposed; after the development process, the fully exposed photoresist is removed to expose a passivation layer corresponding to a region of the via where the drain is exposed, and then an etching process is used to form the exposed drain.
  • the partially exposed photoresist is removed by an ashing process to expose a passivation layer corresponding to a region where the transparent electrode is located; and the exposed passivation layer is partially removed by an etching process, thereby being blunt
  • the upper surface of the layer forms the groove.
  • forming a recess on an upper surface of the passivation layer includes: forming a photosensitive resin layer on a substrate on which the thin film transistor is formed; exposing the photosensitive resin layer through a two-tone mask to correspond to The photosensitive resin layer in the region where the transparent electrode is located is partially exposed, the photosensitive resin layer corresponding to the region where the via hole exposing the drain is completely exposed, and the photosensitive resin layer in other regions is not exposed; using a developing process, corresponding The photosensitive resin layer in the region where the transparent electrode is located is partially removed to form a groove, and the photosensitive resin layer corresponding to the region where the via hole exposing the drain is completely removed to form a via hole.
  • the forming the transparent electrode in the groove comprises: forming a transparent conductive layer on the substrate on which the groove is formed; coating a photoresist on the transparent conductive layer; ashing the photoresist Processing, the electrical layer; removing the exposed transparent conductive layer by an etching process, and stripping the photoresist in the groove to form a transparent electrode.
  • the transparent electrode is a pixel electrode.
  • the groove is formed in a comb shape, and the transparent electrode functions as a pixel electrode.
  • the method further comprises: forming a common electrode.
  • the recess is formed in a comb shape, and the transparent electrode serves as a common electrode.
  • the method further includes: forming a pixel electrode.
  • an embodiment of the present invention further provides a display device including the above array substrate and an opposite substrate opposite to the array substrate.
  • FIG. 1 is a cross-sectional view showing the structure of a prior art array substrate
  • FIG. 2a-2e are structural cross-sectional views of an array substrate fabricated by using the steps of the method for fabricating an array substrate according to an embodiment of the present invention, wherein FIG. 2e is an array substrate according to an embodiment of the present invention applied to a vertical alignment type display device Structural section view;
  • Fig. 3 is a cross-sectional view showing the structure of an array substrate according to an embodiment of the present invention applied to a display device of the FFS mode. detailed description
  • Embodiment 1 of the present invention provides an array substrate, the array substrate includes: a substrate; a thin film transistor, a passivation layer, and a transparent electrode sequentially disposed on the substrate, wherein an upper surface of the passivation layer is formed with a groove The transparent electrode is disposed in the recess.
  • the array substrate of the embodiment of the present invention includes: a substrate 1 (a transparent substrate, for example, a glass substrate); a gate and a gate line (not shown in a cross-sectional view) formed on the substrate 1; and a gate insulating layer 2 formed in the Above the gate and the gate line; an active layer (not shown) formed on the gate insulating layer 2, the active layer may be made of a material such as an oxide semiconductor or an amorphous silicon a-si; the source electrode 3 and The drain electrode 4 is formed on the active layer; the passivation layer 5 is formed on the source electrode 3 and the drain electrode 4, wherein the upper surface of the passivation layer 5 is formed with a groove 51, and the transparent electrode 6 is disposed in the groove 51.
  • a substrate 1 a transparent substrate, for example, a glass substrate
  • a gate and a gate line not shown in a cross-sectional view
  • a gate insulating layer 2 formed in the Above the gate and the gate line
  • an active layer (not shown) formed
  • the depth h of the groove 51 is 0.5 ⁇ m - 3 ⁇ (see Fig. 2a), wherein the depth of the groove is the highest point of the bottom of the groove to the passivation layer, that is, the distance to the highest point on the upper surface of the passivation layer Alternatively, the depth of the groove 51 may be half the thickness of the passivation layer 5.
  • the transparent electrode may be made of a material such as ITO (Indium Tin Oxides).
  • the transparent electrode 6 can be used as the pixel electrode 6, and the pixel electrode 6 is disposed in the recess 51, thereby maximally protecting the pixel electrode 6 while saving space.
  • a common electrode is formed on a color filter substrate opposed to the array substrate.
  • a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer. All the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • 3 is a cross-sectional view showing the structure of an array substrate of a display device for an ADS mode according to an embodiment of the present invention. As shown in FIG.
  • the groove 51 is formed in a comb shape, and the transparent electrode 6 serves as a pixel electrode 6,
  • the pixel electrode 6 is located in the comb-shaped recess, and the array substrate further includes a common electrode 8 located below the pixel electrode 6 via an insulating layer.
  • the common electrode 8 is formed as a plate electrode.
  • the groove 51 is formed in a comb shape
  • the transparent electrode 6 can serve as the common electrode 8
  • the common electrode 8 is located in the comb-shaped groove 51
  • the array substrate further includes a common layer via the insulating layer.
  • the pixel electrode under the electrode 8 is exemplarily formed in a plate shape.
  • the pixel electrode may also be a comb electrode with a slit, which is not limited herein.
  • the passivation layer is formed to have a recess, and the transparent electrode is formed in the recess, so that the transparent electrode can be formed in the recess by using an ashing process of the photoresist.
  • the mask used for preparing the transparent electrode can be omitted, thereby reducing the manufacturing cost.
  • Embodiment 2 of the present invention provides a method of manufacturing an array substrate according to the above embodiment, the manufacturing method comprising the following steps:
  • Step S1 forming a thin film transistor and a passivation layer on the substrate 1, wherein the passivation layer covers the thin film transistor.
  • a thin film transistor and a passivation layer can be formed by a known method.
  • Step S1 includes: forming a gate and a gate line on a substrate by a patterning process including deposition, exposure, development, etching, and lift-off; Forming a gate insulating layer 2 on the substrate 1; forming an active layer and source-drain electrodes 3 and 4 by a patterning process on the substrate on which the above steps are performed, thereby forming a thin film transistor; and then forming a passivation on the substrate on which the thin film transistor is formed Layer 5.
  • the material forming the passivation layer is a commonly used insulating material such as a photosensitive resin material. It should be noted that, for other types of thin film transistors, they may be formed by a known method, and are not described herein for the sake of cleaning.
  • Step S2 forming a groove 51 on the upper surface of the passivation layer.
  • the step S2 includes:
  • a photoresist on the substrate obtained by the step S1 exposing the photoresist through a two-tone mask (gray or halftone mask), wherein the photoresist corresponding to the region where the transparent electrode is located is partially exposed , the photoresist corresponding to the region where the via of the exposed drain is located is completely exposed, and the photoresist of other regions is not exposed;
  • the passivation layer of the region where the photoresist is completely exposed is exposed, and a via hole exposing the drain is formed by an etching process;
  • the partially exposed photoresist is removed by an ashing process, that is, the photoresist corresponding to the transparent electrode region is removed to expose the passivation layer;
  • the exposed passivation layer is partially removed by an etching process to form a recess 51 on the upper surface of the passivation layer as shown in Fig. 2a.
  • the passivation layer having the recess may be formed by the following method, and the step S2 includes:
  • Step S3 forming a transparent electrode in the recess 51.
  • step S3 comprises: forming a transparent conductive layer 16 on the substrate on which the groove is formed; then coating the photoresist 7; since the upper surface of the passivation layer has a groove, the photolithography formed in the groove
  • the glue has a thickness difference between the photoresist formed outside the groove, and the photoresist is ashed according to the difference in thickness, the photoresist in the groove is retained, and the photoresist in other regions except the groove is removed.
  • the transparent conductive layer is exposed; the exposed transparent conductive layer is removed by an etching process, and the photoresist in the recess 51 is peeled off to form a transparent electrode, as shown in FIGS. 2b to 2e.
  • the transparent electrodes are fabricated using different manufacturing methods.
  • the transparent electrode can function as a pixel electrode, and the pixel electrode is connected to the thin film transistor through a via, for example, to the drain of the thin film transistor.
  • the common electrode is generally formed in the same patterning process as the gate line, and the common electrode is formed in a plate shape, and the pixel electrode is formed in a comb shape In the recess, a comb-shaped pixel electrode is formed, the comb electrode being located above the common electrode and spaced apart by an insulating layer.
  • the transparent electrode may also serve as a common electrode, and the common electrode is formed in the comb-shaped recess to form a comb-shaped common electrode, and at this time, before forming the passivation layer, forming a pixel electrode, the pixel electrode is located The lower side of the common electrode is formed in a plate shape.
  • an IPS mode display device in which a comb-shaped pixel electrode and a comb-shaped common electrode are formed, and each of the pixel electrodes and the common electrode may be alternately arranged.
  • the array substrate produced by the array substrate manufacturing method of the above embodiment is as shown in FIG. 2e or 3.
  • the transparent electrode is not formed by using a mask, the mask process is reduced, and the fabrication is saved. Process and production costs.
  • Embodiments of the present invention also provide a display device including the array substrate according to the above embodiment.
  • An example of the display device is a liquid crystal display device in which an array substrate and an opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which each operation of the array substrate is performed.
  • a mask for preparing a transparent electrode can further reduce the manufacturing cost.

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Abstract

一种阵列基板及其制作方法、显示装置。阵列基板包括：基板（1）；薄膜晶体管、钝化层（5）和透明电极（6），依次形成在基板上，其中钝化层（5）的上表面形成有凹槽（51），透明电极（6）设置于凹槽（51）内。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
近年来, TFT-LCD ( Thin Film Transistor-Liquid Crystal Display, 薄膜晶 体管-液晶显示器）因其图像品质好、 能耗低、 环保等优势占据着显示器领域 的重要位置。 TFT-LCD由彩膜基板和阵列基板对盒而成， 其中， 现有的阵列 基板通常采用多次掩模工艺形成。
图 1示出了现有技术的阵列基板的结构截面图， 如图 1所示， 该阵列基 板包括： 基板 1; 栅极、 栅绝缘层 2和半导体层， 设在基板 1上； 源电极 3 和漏电极 4, 设在绝缘层 2; 钝化层 5, 设在源电极 3和漏电极 4的上方及周 围； 以及像素电极 6, 设在钝化层 5上。 像素电极 6通常通过采用掩模板的 构图工艺形成。 在 TFT-LCD的制作工艺中， 掩模板的制作成本非常昂贵， 多一次掩模工艺就会对产能及良率产生很大的影响。 发明内容
本发明的实施例提供一种阵列基板及其制作方法、 显示装置， 不采用掩 模板来制作透明电极， 从而减少了掩模工艺制程， 降低了生产成本。
一方面， 本发明的实施例提供一种阵列基板， 包括： 基板； 薄膜晶体管、 钝化层和透明电极， 依次形成在所述基板上， 其中所述钝化层的上表面形成 有凹槽， 所述透明电极设置于所述凹槽内。
备选地， 所述钝化层由感光树脂材料制成。
备选地， 所述凹槽的深度为 0.5-3μιη。
备选地， 所述透明电极作为像素电极， 所述像素电极位于所述凹槽内。 备选地， 所述凹槽形成为梳状， 所述透明电极作为像素电极， 所述像素 电极形成为梳状， 所述阵列基板还包括与所述像素电极隔着钝化层设置的公 共电极。 备选地， 所述凹槽形成为梳状， 所述透明电极作为公共电极， 所述公共 电极形成为梳状， 所述阵列基板还包括与所述公共电极隔着钝化层设置的像 素电极。
另一方面， 本发明的实施例还提供一种阵列基板的制作方法， 包括： 在 基板上形成薄膜晶体管和钝化层， 所述钝化层覆盖所述薄膜晶体管且所述钝 化层的上表面形成有凹槽； 以及在所述凹槽内形成透明电极。
备选地， 所述在基板上形成薄膜晶体管包括： 在基板上通过构图工艺形 成栅极和栅线； 在所述栅极和栅线上形成栅绝缘层； 以及在所述栅绝缘层上 通过构图工艺形成有源层和源漏电极。
备选地， 在所述钝化层的上表面形成凹槽包括： 在形成有所述薄膜晶体 管的基板上形成所述钝化层； 在所述钝化层上涂覆光刻胶， 通过双色调掩模 板对所述光刻胶进行曝光， 其中对应于透明电极所在区域的光刻胶被部分曝 光， 对应于暴露漏极的过孔所在区域的光刻胶被完全曝光， 其他区域的光刻 胶未曝光； 通过显影处理后， 被完全曝光的所述光刻胶被去除从而暴露出对 应于暴露漏极的过孔所在区域的钝化层， 然后利用刻蚀工艺形成暴露所述漏 极的过孔； 利用灰化工艺， 将被部分曝光的所述光刻胶去除， 从而暴露对应 于透明电极所在区域的钝化层； 利用刻蚀工艺将被暴露的钝化层部分去除， 从而在钝化层的上表面形成所述凹槽。
备选地， 在所述钝化层的上表面形成凹槽包括： 在形成有所述薄膜晶体 管的基板上形成感光树脂层；通过双色调掩模板对所述感光树脂层进行曝光， 使得对应于透明电极所在区域的所述感光树脂层被部分曝光， 对应于暴露漏 极的过孔所在区域的所述感光树脂层被完全曝光， 其他区域的所述感光树脂 层未曝光； 利用显影工艺， 对应于所述透明电极所在区域的所述感光树脂层 被部分去除从而形成凹槽， 对应于暴露所述漏极的过孔所在区域的所述感光 树脂层被完全去除从而形成过孔。
备选地， 所述在凹槽内形成透明电极包括： 在形成有凹槽的基板上形成 透明导电层；在所述透明导电层上涂覆光刻胶；对所述光刻胶进行灰化处理， 电层；采用刻蚀工艺将暴露出的透明导电层去除，剥离所述凹槽内的光刻胶， 从而形成透明电极。 备选地， 所述透明电极为像素电极。
备选地， 所述凹槽形成为梳状， 所述透明电极作为像素电极， 在形成所 述钝化层之前， 所述方法还包括： 形成公共电极。
备选地， 所述凹槽形成为梳状， 所述透明电极作为公共电极， 在形成所 述钝化层之前， 所述方法还包括： 形成像素电极。
再一方面， 本发明的实施例还提供一种显示装置， 包括上述的阵列基板 以及与所述阵列基板对置的相对基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的阵列基板的结构截面图；
图 2a-2e为利用根据本发明实施例的阵列基板制作方法的各步骤制作得 到的阵列基板的结构截面图，其中图 2e为应用于垂直取向型显示装置的根据 本发明实施例的阵列基板的结构截面图； 以及
图 3为应用于 FFS模式的显示装置的根据本发明实施例的阵列基板的结 构截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例 1
本发明的实施例 1提供了一种阵列基板， 该阵列基板包括： 基板； 依次 设置在该基板上的薄膜晶体管、 钝化层和透明电极， 其中钝化层的上表面形 成有凹槽， 所述透明电极设置于凹槽内。
图 2e示出了根据本发明实施例的阵列基板的结构截面图，如图 2e所示， 本发明实施例的阵列基板包括： 基板 1 (透明基板， 例如， 玻璃基板） ； 栅 极和栅线（截面图中未示出） ， 形成在基板 1上； 栅绝缘层 2, 形成在所述 栅极和栅线之上； 有源层（未示出） ， 形成在栅绝缘层 2上， 该有源层可以 采用氧化物半导体或非晶硅 a-si等材料制成； 源电极 3和漏电极 4, 形成在 有源层之上； 钝化层 5, 形成在源电极 3和漏电极 4上， 其中钝化层 5的上 表面形成有凹槽 51 , 透明电极 6设置于凹槽 51内。
示例性地， 凹槽 51的深度 h为 0.5μιη-3μιη (参见图 2a ) , 其中凹槽的 深度为凹槽的底部到钝化层最高处， 即到达钝化层上表面最高点处的距离； 备选地， 凹槽 51的深度可为钝化层 5厚度的一半。
示例性地， 透明电极可以由 ITO ( Indium Tin Oxides, 氧化铟锡）等材 料制成。
对于垂直取向模式的液晶显示装置而言， 该透明电极 6可作为像素电极 6, 像素电极 6设置于凹槽 51内， 从而在节省空间的前提下， 可最大程度地 保护像素电极 6。 对于这种类型的液晶显示装置， 公共电极形成在与阵列基 板对置的彩膜基板上。
而对于 ADS ( Advanced Super Dimension Switch )模式的液晶显示装置 而言， 其是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板 状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方 所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大透光效 率的。 图 3示出了根据本发明实施例的用于 ADS模式的显示装置的阵列基 板的结构截面图，如图 3所示， 凹槽 51形成为梳状， 所述透明电极 6作为像 素电极 6, 像素电极 6位于梳状凹槽内， 而且所述阵列基板还包括隔着绝缘 层位于像素电极 6下方的公共电极 8。 示例性地， 该公共电极 8形成为板状 电极。
备选地， 对于 ADS模式的阵列基板， 凹槽 51形成为梳状， 透明电极 6 可作为公共电极 8, 公共电极 8位于梳状凹槽 51内， 而且阵列基板还包括隔 着绝缘层位于公共电极 8下方的像素电极，示例性地，像素电极形成为板状， 当然像素电极还可以是带有狭缝的梳状电极， 在此不做限制。
在本发明实施例提供的阵列基板中， 钝化层形成为具有凹槽， 而透明电 极形成在凹槽中， 这样可以通过利用光刻胶的灰化工艺将透明电极形成在凹 槽中， 从而可以省略制备透明电极所采用的掩模板， 进而降低制造成本。 实施例 2
本发明的实施例 2提供一种上述实施例的阵列基板的制造方法， 该制造 方法包括以下步骤：
步骤 Sl、在基板 1上形成薄膜晶体管和钝化层， 其中所述钝化层覆盖所 述薄膜晶体管。
在该步骤中， 可采用已知的方法形成薄膜晶体管和钝化层。
下面以制作底栅型薄膜晶体管为例给出详细说明， 步骤 S1包括： 在基板上通过包括沉积、 曝光、 显影、 刻蚀及剥离等的构图工艺形成栅极和 栅线； 在完成上述步骤的基板 1上形成栅绝缘层 2; 在完成上述步骤的基板 上通过构图工艺形成有源层和源漏电极 3和 4, 从而形成薄膜晶体管； 然后， 在形成有上述薄膜晶体管的基板上形成钝化层 5。
备选地， 形成钝化层的材料为常用的绝缘材料， 例如感光树脂材料。 需要说明的是，对于其他类型的薄膜晶体管，可以采用已知的方法形成， 为了筒洁， 这里不做赘述。
步骤 S2、 在所述钝化层的上表面形成凹槽 51。
示例性地， 所述步骤 S2包括：
在通过步骤 S1得到的基板上涂覆光刻胶， 通过双色调掩模板（灰调或 半调掩膜板）对光刻胶进行曝光， 其中对应于透明电极所在区域的光刻胶被 部分曝光， 对应于暴露漏极的过孔所在区域的光刻胶被完全曝光， 其他区域 的光刻胶未曝光；
通过显影处理后， 光刻胶被完全曝光的区域的钝化层被暴露， 利用刻蚀 工艺形成暴露所述漏极的过孔；
利用灰化工艺， 去除被部分曝光的光刻胶， 即， 去除对应于透明电极区 域的光刻胶， 从而暴露出钝化层； 以及
利用刻蚀工艺部分去除被暴露的钝化层， 从而在钝化层的上表面形成凹 槽 51 , 如图 2a所示。
备选地， 还可以采用如下方法形成具有凹槽的钝化层， 所述步骤 S2 包 括：
在形成有所述薄膜晶体管的基板上形成感光树脂层， 通过双色调掩模板 对感光树脂层进行曝光， 使得对应于透明电极所在区域的感光树脂层被部分 曝光， 对应于暴露漏极的过孔所在区域的感光树脂层被完全曝光， 其他区域 的所述感光树脂层未曝光， 在显影工艺后， 对应于透明电极所在区域的感光 树脂层被部分去除从而形成凹槽且对应于暴露漏极的过孔所在区域的感光树 脂层被完全去除从而形成过孔。
步骤 S3、 在凹槽 51内形成透明电极。
示例性地， 步骤 S3包括： 在形成有凹槽的基板上形成透明导电层 16; 然后涂覆光刻胶 7; 因钝化层的上表面具有凹槽， 所以形成在凹槽内的光刻 胶和形成在凹槽外的光刻胶之间具有厚度差， 根据该厚度差对光刻胶进行灰 化处理， 保留凹槽内的光刻胶， 去除凹槽以外其他区域的光刻胶以暴露出透 明导电层；采用刻蚀工艺将暴露出的透明导电层去除，剥离凹槽 51内的光刻 胶从而形成透明电极， 如图 2b到 2e所示。
备选地， 对于不同显示模式的显示装置， 透明电极的制作采用不同的制 作方法。
示例性地， 对于垂直取向模式， 透明电极可作为像素电极， 像素电极通 过过孔连接到薄膜晶体管， 例如， 连接到薄膜晶体管的漏极。
示例性地， 对于 ADS模式， 在形成钝化层之前还包括形成公共电极， 例如， 公共电极通常与栅线在同一次构图工艺中形成， 且公共电极形成为板 状， 像素电极形成在梳状的凹槽内， 形成梳状像素电极， 该梳状电极位于公 共电极的上方且二者之间隔着绝缘层。备选地，透明电极也可作为公共电极， 则公共电极形成在梳状的凹槽内， 形成梳状公共电极， 而此时， 在形成钝化 层之前还包括形成像素电极，该像素电极位于公共电极的下方且形成为板状。
除此以外， 还可以制作 IPS模式的显示装置， 即制作梳状的像素电极和 梳状的公共电极， 每条像素电极和公共电极交错排列即可。
由上述实施例的阵列基板制作方法制作得到的阵列基板如图 2e或 3所 示， 与现有技术相比， 由于未采用掩模来制作透明电极， 从而减少了一次掩 模工艺， 节省了制作工序和制作成本。
实施例 3
本发明的实施例还提供了一种显示装置， 其包括根据上述实施例的阵列 基板。 该显示装置的一个示例为液晶显示装置， 其中阵列基板与对置基板彼此 对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜基 板。 TFT阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋 转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示器还包括 为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置， 其中阵列基板的每 示操作。
本发明实施例提供的阵列基板及其制作方法、显示装置，制作工艺筒单， 采用具有凹槽的钝化层，利用光刻胶进行灰化工艺而在凹槽内形成透明电极， 从而省略了制备透明电极的掩模板， 进而可降低制造成本。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明技术原理的前提下， 还可以做出若干改进 和替换， 这些改进和替换也应视为本发明的保护范围。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板；
薄膜晶体管、 钝化层和透明电极， 依次形成在所述基板上，
其中所述钝化层的上表面形成有凹槽，所述透明电极设置于所述凹槽内。
2、如权利要求 1所述的阵列基板,其中所述钝化层由感光树脂材料制成。
3、 如权利要求 1所述的阵列基板， 其中所述凹槽的深度为 0.5-3μιη。
4、如权利要求 1所述的阵列基板， 其中所述透明电极作为像素电极， 所 述像素电极位于所述凹槽内。
5、如权利要求 1所述的阵列基板， 其中所述凹槽形成为梳状， 所述透明 电极作为像素电极， 所述像素电极形成为梳状， 所述阵列基板还包括与所述 像素电极隔着钝化层设置的公共电极。
6、如权利要求 1所述的阵列基板， 其中所述凹槽形成为梳状， 所述透明 电极作为公共电极， 所述公共电极形成为梳状， 所述阵列基板还包括与所述 公共电极隔着钝化层设置的像素电极。
7、 如权利要求 1-6之一所述的阵列基板， 其中所述薄膜晶体管包括： 栅线和栅极， 形成在基板上；
栅绝缘层， 形成在栅线和栅极上；
有源层， 形成在栅绝缘层上；
源漏电极， 形成在有源层上。
8、如权利要求 1-6之一所述的阵列基板， 其中所述凹槽的深度为所述钝 化层厚度的一半。
9、 一种阵列基板的制作方法， 包括：
在基板上形成薄膜晶体管和钝化层， 所述钝化层覆盖所述薄膜晶体管且 所述钝化层的上表面形成有凹槽； 以及
在所述凹槽内形成透明电极。
10、 如权利要求 9所述的阵列基板的制作方法， 其中所述在基板上形成 薄膜晶体管包括：
在基板上通过构图工艺形成栅极和栅线； 在所述栅极和栅线上形成栅绝缘层； 以及
在所述栅绝缘层上通过构图工艺形成有源层和源漏电极。
11、 如权利要求 9所述的阵列基板的制作方法， 其中在所述钝化层的上 表面形成凹槽包括：
在形成有所述薄膜晶体管的基板上形成所述钝化层；
在所述钝化层上涂覆光刻胶,通过双色调掩模板对所述光刻胶进行曝光， 其中对应于透明电极所在区域的光刻胶被部分曝光， 对应于暴露漏极的过孔 所在区域的光刻胶被完全曝光， 其他区域的光刻胶未曝光；
通过显影处理后， 被完全曝光的所述光刻胶被去除从而暴露出对应于暴 露漏极的过孔所在区域的钝化层， 然后利用刻蚀工艺形成暴露所述漏极的过 孔；
利用灰化工艺， 将被部分曝光的所述光刻胶去除， 从而暴露对应于透明 电极所在区域的钝化层；
利用刻蚀工艺将被暴露的钝化层部分去除， 从而在钝化层的上表面形成 所述凹槽。
12、 如权利要求 9所述的阵列基板的制作方法， 其中在所述钝化层的上 表面形成凹槽包括：
在形成有所述薄膜晶体管的基板上形成感光树脂层；
通过双色调掩模板对所述感光树脂层进行曝光， 使得对应于透明电极所 在区域的所述感光树脂层被部分曝光， 对应于暴露漏极的过孔所在区域的所 述感光树脂层被完全曝光， 其他区域的所述感光树脂层未曝光；
利用显影工艺， 对应于所述透明电极所在区域的所述感光树脂层被部分 去除从而形成凹槽， 对应于暴露所述漏极的过孔所在区域的所述感光树脂层 被完全去除从而形成过孔。
13、 如权利要求 9所述的阵列基板的制作方法， 其中所述在凹槽内形成 透明电极包括：
在形成有凹槽的基板上形成透明导电层；
在所述透明导电层上涂覆光刻胶；
对所述光刻胶进行灰化处理， 保留所述凹槽内的光刻胶且去除凹槽以外 区域的光刻胶以暴露出所述透明导电层； 采用刻蚀工艺将暴露出的透明导电层去除， 剥离所述凹槽内的光刻胶， 从而形成透明电极。
14、 如权利要求 9所述的阵列基板的制作方法， 其中所述透明电极作为 像素电极。
15、 如权利要求 9所述的阵列基板的制作方法， 其中所述 槽形成为梳 状， 所述透明电极作为像素电极， 在形成所述钝化层之前， 所述方法还包括： 形成公共电极。
16、 如权利要求 9所述的阵列基板的制作方法， 其中所述 槽形成为梳 状， 所述透明电极作为公共电极， 在形成所述钝化层之前， 所述方法还包括： 形成像素电极。
17、 一种显示装置， 包括：
权利要求 1-8所述的阵列基板； 以及
相对基板， 与所述阵列基板对置。
PCT/CN2013/085103 2013-03-14 2013-10-12 阵列基板及其制作方法、显示装置 WO2014139283A1 (zh)

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