WO2017054384A1 - 一种阵列基板及其制作方法、显示面板 - Google Patents

一种阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2017054384A1
WO2017054384A1 PCT/CN2016/072752 CN2016072752W WO2017054384A1 WO 2017054384 A1 WO2017054384 A1 WO 2017054384A1 CN 2016072752 W CN2016072752 W CN 2016072752W WO 2017054384 A1 WO2017054384 A1 WO 2017054384A1
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Prior art keywords
electrode
layer
insulating layer
signal transmission
forming
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PCT/CN2016/072752
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English (en)
French (fr)
Inventor
王守坤
袁剑峰
郭会斌
冯玉春
李梁梁
郭总杰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/326,383 priority Critical patent/US10304861B2/en
Publication of WO2017054384A1 publication Critical patent/WO2017054384A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel.
  • a TFT-LCD display generally includes an array substrate, a color filter substrate, and a liquid crystal disposed between the array substrate and the color filter substrate.
  • the TFT-LCD display panel is formed with display units arranged in the order of hundreds of thousands to millions of arrays, and each display unit displays an image by control of the TFT.
  • FIG. 1 it is a schematic diagram of a display unit corresponding to a display unit on a conventional TFT-LCD display array substrate.
  • a plurality of gate lines 121 and data lines 16 are formed on the array substrate, and the gate lines 121 and the data lines 16 are formed.
  • Cross defines a display unit.
  • 2 is a schematic view of aa' shown in FIG. 1, as shown in FIG.
  • the array substrate includes: a substrate substrate 11, a gate formed on the substrate substrate 11 (portion of the gate line 121), a common electrode line 122; a gate insulating layer 13 covering the gate electrode 121 and the common electrode line 122; an active layer 14 formed on the gate insulating layer 13 and a source electrode 161 and a drain electrode 162; a passivation layer 15 and pixels formed on the passivation layer 15
  • the common electrode 19 is connected to the common electrode line 122 through the via layer 1 on the flat layer 18, the passivation layer 15 and the gate insulating layer 13, and the pixel electrode 17 is connected to the drain electrode 162 through the via 2 on the passivation layer 15.
  • the inventors have found that, on the existing array substrate, as shown in FIG. 2, since the via 1 penetrates through the flat layer 18, the passivation layer 15, and the gate insulating layer 13, the via 1 is deep, and the common electrode 19 and the common electrode line 122 are The connection is prone to breakage, poor display, and reduced product yield.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display panel.
  • the common electrode on the array substrate is connected to the common electrode line through a plurality of conductive layers to prevent the via from being too deep to cause poor connection.
  • an array substrate including:
  • the first signal transmission layer comprising: a common electrode line;
  • a first insulating layer covering the first signal transmission layer and having a first via at a position corresponding to the common electrode line;
  • the first electrode layer is located on the first insulating layer, and includes: a connecting electrode, wherein the connecting electrode is located at the first via position;
  • a second insulating layer covering the first electrode layer and having a second via at a position corresponding to the connection electrode
  • the second electrode layer includes a common electrode, and the common electrode covers the second via hole;
  • connection electrodes are in contact with the common electrode line and the common electrode, respectively.
  • the second via hole is located at a position corresponding to the first via hole
  • connection electrode extends from the first via and extends over at least a portion of an upper surface of the first insulating layer; the second insulating layer extends from the first via corresponding to the connection electrode And a second via hole at a position extending over at least a portion of the upper surface of the first insulating layer.
  • the first electrode layer includes:
  • first electrode sublayer comprising a pixel electrode, and a first connection electrode at the first via location
  • the second electrode sub-layer comprising a second connection electrode at the first via location, and the second electrode sub-layer being on the first electrode sub-layer.
  • the material forming the first electrode sub-layer is indium tin oxide, and the material forming the second electrode sub-layer is metal.
  • the second sub-layer comprises two layers of molybdenum metal and an aluminum metal layer between the two layers of molybdenum metal.
  • the first signal transmission layer further includes: a gate line and a gate; the array
  • the substrate also includes:
  • a gate insulating layer covering the first signal transmission layer, wherein the gate insulating layer has a first sub via at a position corresponding to the common electrode line;
  • An active layer the active layer being on the gate insulating layer
  • the second signal transmission layer including a data line, a source and a drain;
  • a passivation layer having a second sub via at a position corresponding to the first sub via and a third via at a position corresponding to the drain, the pixel electrode being Connecting the drain to the third via;
  • the first electrode layer is located on the passivation layer, the first insulating layer includes a gate insulating layer and a passivation layer, and the second electrode sublayer further includes an auxiliary electrode, the auxiliary electrode at least corresponding to the The position of the third via is connected to the pixel electrode.
  • the array substrate includes a light transmissive area and an opaque area, and the auxiliary electrode is connected to the pixel electrode in the opaque area.
  • the second signal transmission layer further includes a third connection electrode at the first via location.
  • an embodiment of the present invention provides a method for fabricating an array substrate, including:
  • the first signal transmission layer comprising: a common electrode line;
  • first insulating layer on the base substrate, the first insulating layer covering the first signal transmission layer, and having a first via at a position corresponding to the common electrode line;
  • first electrode layer Forming a first electrode layer on the substrate, the first electrode layer is located on the first insulating layer, comprising: a connecting electrode, the connecting electrode is located at the first via position;
  • the second electrode layer including a common electrode, the common electrode covering the second via hole;
  • connection electrodes are in contact with the common electrode line and the common electrode, respectively.
  • the step of the second insulating layer having the second via hole corresponding to the position of the connecting electrode further comprises:
  • connection electrode layer has a second via at a position corresponding to the first via
  • connection electrode extends from the first via and extends over at least a portion of an upper surface of the first insulating layer, the second insulating layer extending from the first via corresponding to the connection electrode And a second via hole at a position extending over at least a portion of the upper surface of the first insulating layer.
  • the step of forming the first electrode layer on the base substrate further includes:
  • first conductive film Forming a first conductive film, a second conductive film, and a photoresist covering the first electrode layer on the base substrate; wherein the first conductive film and the second conductive film cover the first Via hole
  • the semi-gray mask comprises a light transmissive region, a semi-transmissive region and an opaque region, wherein the opaque region corresponds to The first via hole corresponds to the pixel electrode; after the development, the photoresist corresponding to the light-transmitting region is completely removed to expose the second conductive film, and the photoresist portion corresponding to the semi-transmissive region is removed; Etching the second conductive film corresponding to the light-transmitting region and the first conductive film; ashing the photoresist, completely removing the photoresist corresponding to the semi-transmissive region to expose the second conductive film, corresponding to opaque The photoresist portion of the region is retained; the second conductive film corresponding to the semi-transmissive region is etched; and the photoresist is stripped.
  • the material forming the first conductive film is indium tin oxide
  • the material forming the second conductive film is metal
  • the step of forming a first conductive film, a second conductive film, and a photoresist covering the first electrode layer on the base substrate further includes:
  • Forming a second conductive film on the first conductive film comprising: sequentially forming a molybdenum metal film, an aluminum metal film, and a molybdenum metal film;
  • a photoresist is formed on the second conductive film.
  • the first signal transmission layer further includes a gate line and a gate; and the step of forming a first insulating layer covering the first signal transmission layer on the substrate substrate further includes:
  • the second signal transmission layer including a data line, a source and a drain;
  • the passivation layer Forming a passivation layer on the base substrate, the passivation layer having a second sub via at a position corresponding to the common electrode line, and a third via at a position corresponding to the drain, The pixel electrode is connected to the drain at the third via;
  • the first insulating layer includes a gate insulating layer and a passivation layer
  • the second electrode sublayer further includes an auxiliary electrode
  • the auxiliary electrode is connected to the pixel electrode at least at a position corresponding to the third via.
  • the method further includes:
  • a plasma surface treatment is performed on a region between the source and the drain.
  • an embodiment of the present invention provides a display panel, including any of the array substrates provided by the embodiments of the present invention.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display panel, wherein a common electrode on the array substrate passes through a first via on the first insulating layer and a second via on the second insulating layer and a common electrode line
  • the connection is made, but a connection electrode is also formed at the first via hole, and the common electrode is connected to the common electrode line through the connection electrode.
  • Directly connecting to the common electrode line with respect to the common electrode can reduce the connection depth of the common electrode and the common electrode line, thereby preventing the first via hole and the second via hole from being too deep, resulting in a problem that the common electrode and the common electrode line are easily disconnected.
  • 1 is a schematic view of a conventional array substrate
  • Figure 2 is a schematic view of a-a' shown in Figure 1;
  • FIG. 3 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a method for forming a first insulating layer according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of another method for forming a first insulating layer according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention.
  • the “film” refers to a film formed by deposition or other processes on a substrate using a certain material. If the “film” does not require a patterning process throughout the manufacturing process, the “film” may also be referred to as a “layer”; if the “film” requires a patterning process throughout the manufacturing process, it is referred to as "before the patterning process”.
  • the film is called a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one film "pattern”.
  • the gate insulating layer can be made by depositing SiNx (silicon nitride) on a transparent substrate.
  • the gate insulating layer generally does not require a patterning process.
  • the active layer is formed by an oxide semiconductor film after a patterning process.
  • the gate metal layer includes a gate and a gate line, and the gate and the gate line are referred to as a pattern.
  • the so-called "patterning process” is a process of forming a film into a layer comprising at least one pattern; and the patterning process generally comprises: applying a glue on the film, exposing the photoresist with a mask, and then removing the developer The photoresist is etched away, the portion of the film that is not covered with the photoresist is etched away, and the remaining photoresist is finally stripped.
  • the "primary patterning process” refers to a layer structure process required for formation by one exposure.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3, including:
  • the first signal transmission layer includes: a common electrode line 122;
  • a first insulating layer 31 covering the first signal transmission layer and having a first via at a position corresponding to the common electrode line 122; the first via removing the first insulating layer 31 at the corresponding common electrode line A portion at the position of 122 is formed, and by forming the first via, the upper surface of the common electrode line 122 located under the first insulating layer 31 is exposed.
  • the first electrode layer is located on the first insulating layer 31, and includes: a connecting electrode 41, the connecting electrode 41 is located at the first via hole position, in other words, the common electrode exposed at the first via hole
  • the upper surface of the electrode line 122 is in direct contact.
  • the electrode 41 has a second via at a position where the second via is removed by removing a portion of the second insulating layer 32 at a position corresponding to the common electrode line 122, and forming a second via, under the second insulating layer 32. The upper surface of the electrode 41 is exposed.
  • the second electrode layer includes a common electrode 19, and the common electrode 19 covers the second via hole.
  • the common electrode 19 is in direct contact with the upper surface of the connection electrode 41 exposed at the second via hole; 41 is in contact with the common electrode line 122 and the common electrode 19, respectively, in other words, the common electrode 19 is connected to the common electrode line 122 through the connection electrode 41.
  • the array substrate may be formed with other thin film or layer structures.
  • the array substrate is described by taking only the connection between the common electrode and the common electrode line on the array substrate as an example. Other films or layer structures may not be provided at the locations corresponding to the common electrodes, or other film or layer structures may be included in the layer structures described above.
  • the array substrate includes a thin film transistor, and the active layer of the thin film transistor is located only at the position of the corresponding gate, and the pattern of the active layer is not included at the position corresponding to the common electrode line; the thin film transistor can also Including the source/drain metal layer, the source/drain metal layer may be a connection electrode including the above.
  • An embodiment of the present invention provides an array substrate, wherein the common electrode is connected to the common electrode line through the first via hole on the first insulating layer and the second via hole on the second insulating layer, wherein the first via hole is further A connection electrode is formed, and the common electrode is connected to the common electrode line through the connection electrode.
  • the embodiment of the present invention can reduce the connection depth of the common electrode and the common electrode line with respect to the common electrode directly connected to the common electrode line, thereby preventing the first via hole and the second via hole from being too deep, and the common electrode and the common electrode line are easily broken. Open question.
  • the second via is located at a position corresponding to the first via.
  • the connection depth of the common electrode 19 and the common electrode line 122 is the sum of the depths of the first via hole and the second via hole.
  • the connection depth of the common electrode 19 and the common electrode line 122 is such that the first via hole and the second via hole are prevented from being too deep, thereby avoiding the problem that the common electrode and the common electrode line are easily disconnected.
  • connection electrode 41 extends from the first via hole and extends over at least a portion of the upper surface of the first insulating layer 31;
  • the corresponding connection electrode 41 of the edge layer 32 has a second via hole extending from the first via hole and extending over at least a portion of the upper surface of the first insulating layer 31.
  • the first via hole may be staggered from the second via hole, and the common electrode 19 is connected to the common electrode line 122 through the connection electrode 41, thereby preventing the via hole formed corresponding to the first via hole and the second via hole position from being too deep. A problem that causes the common electrode and the common electrode line to be easily disconnected.
  • the first electrode layer comprises:
  • the first electrode sub-layer includes a pixel electrode 17 and a first connection electrode 411 at a first via position;
  • the second electrode sub-layer includes a second connection electrode 412 at the first via location, and the second electrode sub-layer 412 is located on the first electrode sub-layer 411.
  • the first electrode layer may include a plurality of conductive layers, which are not limited to the first electrode sublayer and the second electrode sublayer.
  • the first electrode layer may further include a third electrode sublayer or the like. Since the pixel electrode is formed on the array substrate, the first electrode sub-layer includes the pixel electrode and the first connection electrode. In other words, the pixel electrode and the first connection electrode are formed by one patterning, thereby avoiding forming the first electrode sub-layer separately. One exposure and other processes.
  • the material forming the first electrode sub-layer is indium tin oxide
  • the material forming the second electrode sub-layer is metal.
  • the pixel electrode is generally a transparent electrode
  • the material forming the first electrode sub-layer is indium tin oxide.
  • the conductivity of the metal is better relative to the metal oxide.
  • the material forming the second electrode sub-layer is a metal.
  • the material of the exemplary second electrode sub-layer may be metal molybdenum, metal aluminum or the like.
  • the second electrode sub-layer may comprise two layers of molybdenum metal and an aluminum metal layer between the two layers of molybdenum metal.
  • the material of the second electrode sub-layer is aluminum. Since the aluminum metality is relatively active, when other film or layer structures are formed after the second electrode sub-layer, for example, when the second electrode layer is formed, in a high temperature environment The aluminum metal is easily grown again to form small protrusions, which may cause contact with the second electrode layer to cause a short circuit.
  • a molybdenum metal layer is formed on both sides of the aluminum metal layer, and the molybdenum metal layer is more stable than the aluminum metal layer, thereby avoiding the second electrode sublayer and other electrode layers at a high temperature. contact.
  • the first signal transmission layer further includes: a gate line and a gate 121; the array substrate further includes:
  • the gate insulating layer 13 covers the first signal transmission layer, wherein the gate insulating layer 13 has a first sub via at a position corresponding to the common electrode line 122.
  • the active layer 14 is provided on the gate insulating layer 13.
  • the second signal transmission layer includes a data line, a source 161, and a drain 162.
  • the passivation layer 15 has a second sub via at a position corresponding to the first sub via, and has a third via at a position corresponding to the drain 162, and the pixel electrode 17 is at the third via Connected to the drain 162.
  • the first electrode layer is on the passivation layer 15, the first insulating layer includes a gate insulating layer 13 and a passivation layer 15, and the second electrode sublayer further includes an auxiliary electrode 50 at least at a position corresponding to the third via hole It is connected to the pixel electrode 17.
  • the first insulating layer includes a gate insulating layer 13 and a passivation layer 15, and the first via hole includes a first sub via hole on the gate insulating layer 13 and a second sub via hole on the passivation layer 15.
  • the array substrate further includes a thin film transistor including a gate, a source and a drain, wherein the passivation layer has a third via at a position corresponding to the drain, and the pixel electrode is connected to the drain at the third via, and Since the second electrode sublayer is located above the first electrode sublayer, the second electrode sublayer includes an auxiliary electrode connected to the pixel electrode at a position corresponding to the third via.
  • the second electrode sub-layer is two layers of molybdenum metal, and the aluminum metal layer is between the two molybdenum metal layers, and the stability of the molybdenum metal layer is good, and the pixel electrode is connected to the drain.
  • the second electrode sub-layer is located above the pixel electrode, which can further prevent the pixel electrode at the position from contacting the air, and further protect the normal connection between the pixel electrode and the drain.
  • the array substrate comprises a light transmitting region and an opaque region
  • the auxiliary electrode is connected to the pixel electrode in the opaque region. Since the pixel electrode is formed in the light-transmitting region mainly for light transmission for display, an auxiliary electrode is disposed in the opaque region to be connected to the pixel electrode to further protect the normal connection between the pixel electrode and the drain.
  • the second signal transmission layer further includes a third connection electrode 413 at the first via position. That is, between the common electrode 19 and the common electrode line 122, a third connection electrode 413 is further included to further reduce the common electrode 19 and the common electrode line 122. The depth of the connection. And the third connection is formed simultaneously with the source and the drain, reducing one patterning process.
  • An embodiment of the present invention provides a method for fabricating an array substrate. As shown in FIG. 8, the method includes the following steps: Step 101: Form a first signal transmission layer on a substrate.
  • the first signal transmission layer includes: a common electrode line.
  • the step 101 includes forming a metal thin film on the base substrate, exposing and etching the metal thin film to form a first signal transmission layer, wherein the first signal transmission layer includes a common electrode line.
  • the exposure and etching may be formed by patterning a mask.
  • the method further includes a step 102 of forming a first insulating layer on the base substrate, the first insulating layer covering the first signal transmission layer and having a first via at a position corresponding to the common electrode line.
  • the step 102 includes forming a first insulating film covering the first signal transmission layer on the base substrate, exposing and etching the first insulating film, and forming at a position of the corresponding common electrode line of the first insulating film.
  • the via hole is thereby exposed at the via of the first insulating film at the upper surface of the common electrode line.
  • the method further includes a step 103 of forming a first electrode layer on the base substrate, the first electrode layer being on the first insulating layer, the first electrode layer comprising a connection electrode, and the connection electrode being located at the first via position.
  • the step 103 includes: forming a first conductive film, a second conductive film and a photoresist covering the first electrode layer on the base substrate; wherein the first conductive film and the second conductive film cover the first via.
  • the photoresist is exposed and developed by using a half-gray mask;
  • the half-gray mask comprises a light-transmitting region, a semi-transmissive region and an opaque region, wherein the opaque region The region corresponds to the first via hole, and the semi-transmissive region corresponds to the pixel electrode; after the development, the photoresist corresponding to the light-transmitting region is completely removed to expose the second conductive film, and the photoresist portion corresponding to the semi-transmissive region is removed; a second conductive film of the region and the first conductive film; the photoresist is ashed, the photoresist corresponding to the semi-transmissive region is completely removed to expose the second conductive film, and the photoresist portion corresponding to the opaque region is retained; Etching a second conductive film corresponding to the semi-transmissive region; peeling off the photoresist.
  • the material forming the second conductive film is metal, that is, the material forming the second electrode sub-layer is metal.
  • the conductivity of the metal is better relative to the metal oxide.
  • a material for forming the second electrode sublayer is preferred.
  • the material of the second electrode sub-layer may be metal molybdenum, metal aluminum or the like.
  • the second electrode sub-layer is generally metal, and the second electrode sub-layer is generally dry-etched, and the first electrode sub-layer is wet etched. If the material of the second electrode sub-layer is metallic molybdenum, both the second electrode sub-layer and the first electrode sub-layer may be wet etched to simplify the process steps.
  • forming the first conductive film, the second conductive film, and the photoresist covering the first electrode layer on the substrate substrate specifically includes:
  • Forming a second conductive film on the first conductive film comprising: sequentially forming a molybdenum metal film, an aluminum metal film, and a molybdenum metal film;
  • a photoresist is formed on the second conductive film.
  • the second electrode sub-layer includes two layers of molybdenum metal and an aluminum metal layer between the two layers of molybdenum metal.
  • the aluminum metality is relatively active, and when other film or layer structures are formed after the second electrode sub-layer, for example, when the second electrode layer is formed, the aluminum metal is easy to be again in a high temperature environment. Growth causes the formation of small bumps which can cause contact with the second electrode layer to cause a short circuit.
  • a molybdenum metal layer is formed on both sides of the aluminum metal layer, and the molybdenum metal layer is more stable than the aluminum metal layer, so that the second electrode sublayer can be prevented from contacting other electrode layers at a high temperature. .
  • the second electrode material comprises a molybdenum aluminum molybdenum three-layer material layer
  • the second electrode sub-layer is dry-etched, and the first electrode material is wet-etched.
  • the material forming the first conductive film is indium tin oxide.
  • the pixel electrode is generally a transparent electrode, and the material forming the first electrode sub-layer is indium tin oxide.
  • the method further includes a step 104 of forming a second insulating layer on the base substrate, the second insulating layer covering the first electrode layer, and having a second via at a position corresponding to the connecting electrode.
  • the step 104 includes: forming a second insulating film covering the first electrode layer on the first electrode layer; exposing and etching the second insulating film to remove the second insulating film corresponding to the via hole of the first insulating layer The upper surface of the connection electrode is exposed.
  • the second insulating layer has the second via hole at the position of the corresponding connection electrode, and specifically includes: the connection electrode layer has the second via hole at a position corresponding to the first via hole.
  • Second via Located at a position corresponding to the first via hole, as shown in FIG. 3, the connection depth of the common electrode 19 and the common electrode line 122 is the sum of the depths of the first via hole and the second via hole.
  • connection electrode extends from the first via hole and extends over at least a portion of the upper surface of the first insulating layer, and the second insulating layer has the second via hole at the position of the corresponding connection electrode, specifically including: the second insulating layer is corresponding
  • the connection electrode has a second via at a position extending from the first via.
  • connection electrode 19 extends from the first via hole and extends over at least a portion of the upper surface of the first insulating layer 31; the second insulating layer 31 extends from the first via hole at the corresponding connection electrode 41.
  • the problem that the electrode wire is easy to disconnect.
  • the method may further include the step 105 of forming a second electrode layer on the base substrate, the second electrode layer including the common electrode, and the common electrode covering the second via hole.
  • the connection electrodes are in contact with the common electrode line and the common electrode, respectively.
  • the first signal transmission layer further includes a gate line and a gate; as shown in FIG. 9, the step of forming a first insulating layer covering the first signal transmission layer on the substrate substrate comprises:
  • Step 1021 forming a gate insulating layer on the base substrate, the gate insulating layer covering the first signal transmission layer, and having a first sub via hole at a position corresponding to the common electrode line.
  • the step 201 includes: forming an insulating film on the base substrate, exposing and etching the insulating film to form a gate insulating layer, and having a first sub-via at a position corresponding to the common electrode line.
  • the step of forming a first insulating layer covering the first signal transmission layer on the base substrate may further include a step 1022 of forming an active layer on the base substrate.
  • the semiconductor thin film is formed on the base substrate, and the semiconductor thin film is exposed and etched to form an active layer.
  • the step of forming a first insulating layer covering the first signal transmission layer on the base substrate may further include the step 1023 of forming a second signal transmission layer on the base substrate, the second signal transmission layer including the data line, the source and the drain pole.
  • the method comprises: forming a metal thin film and a photoresist on the active layer; exposing and developing the photoresist by using the mask, the mask comprises a light transmitting region and an opaque region, and the light is opaque.
  • the region corresponds to the data line, the source and the drain, and the photoresist corresponding to the light-transmitting region is completely removed to expose the metal film after development; the metal film corresponding to the light-transmitting region is etched; and the photoresist is stripped.
  • the step of forming a first insulating layer covering the first signal transmission layer on the base substrate may further include the step 1024: forming a passivation layer on the base substrate, the passivation layer having the second sub-position at a position corresponding to the common electrode line
  • the via hole has a third via at a position corresponding to the drain, and the pixel electrode is connected to the drain at the third via.
  • the method comprises: forming an insulating film on the second signal transmission layer, exposing and etching the insulating film, respectively forming a via hole at a position corresponding to the drain and the common electrode line, an upper surface of the drain, and a common electrode line. The upper surface is exposed.
  • the first insulating layer includes a gate insulating layer and a passivation layer
  • the second electrode sublayer further includes an auxiliary electrode
  • the auxiliary electrode is connected to the pixel electrode at least at a position corresponding to the third via.
  • the array substrate is formed as shown in FIG. 6.
  • the array substrate further includes a thin film transistor including a gate, a source and a drain, wherein the passivation layer has a third via at a position corresponding to the drain, and the pixel electrode is The third via is connected to the drain, and since the second electrode sublayer is located above the first electrode sublayer, the second electrode sublayer includes an auxiliary electrode connected to the pixel electrode at a position corresponding to the third via.
  • the stability of the molybdenum metal layer is good, at the position where the pixel electrode is connected to the drain, and the second The electrode sub-layer is located above the pixel electrode, which can further prevent the pixel electrode at the position from contacting with the air, and further protect the normal connection between the pixel electrode and the drain.
  • the first insulating layer includes a gate insulating layer 13 and a passivation layer 15, and the first via includes a first sub via on the gate insulating layer 13 and a second sub via passivation layer 15. Through hole.
  • the second signal transmission layer further comprises a third connection electrode at the first via location. That is, as shown in FIG. 7, between the common electrode 19 and the common electrode line 122, a third connection electrode 413 is further included to further reduce the connection depth of the common electrode 19 and the common electrode line 122. And the third connection is formed simultaneously with the source and the drain, reducing one patterning process.
  • the opaque region of the mask further corresponds to the common electrode line, that is, the source, the drain, and the third connection electrode are formed by one patterning process.
  • the method further includes:
  • Step 1025 Perform plasma surface treatment on the region between the source and the drain.
  • it may be plasma treatment using a gas such as (SF 6 + O 2 ) or H 2 for the purpose of sweeping impurity ions in the conductive channel and improving the defect of the conductive channel film layer.
  • a gas such as (SF 6 + O 2 ) or H 2
  • the plasma surface treatment may be performed on the region between the source and the drain by using other gases.
  • the method for fabricating an array substrate performs plasma processing on the channel region before the formation of the passivation layer, and corrects and improves the bombardment damage to the conductive channel during the channel etching process, and can
  • the gas treatment is performed to clean the impurity ions in the conductive channel, and the defect of the conductive channel film layer is improved, thereby improving the performance of the thin film transistor.
  • the method includes:
  • Step 201 Form a first signal transmission layer on the base substrate.
  • the first signal transmission layer includes a gate line, a gate, and a common electrode line.
  • Step 202 Form a gate insulating layer on the base substrate, the gate insulating layer covering the first signal transmission layer and having a first sub via at a position corresponding to the common electrode line.
  • Step 203 forming an active layer on the base substrate.
  • Step 204 Form a second signal transmission layer on the base substrate, where the second signal transmission layer includes a data line, a source, a drain, and a third connection electrode.
  • Step 205 Perform plasma surface treatment on the region between the source and the drain.
  • Step 206 Form a passivation layer on the base substrate, the passivation layer having a second sub via at a position corresponding to the common electrode line and a third via at a position corresponding to the drain.
  • Step 207 forming a first electrode layer on the base substrate by one patterning process.
  • the first electrode layer comprises a first electrode sublayer and a second electrode sublayer.
  • the first electrode sublayer includes a pixel electrode and a first connection electrode
  • the second electrode sublayer includes a second connection electrode.
  • Step 208 forming a flat layer on the base substrate.
  • the flat layer covers the first electrode layer and has a second via at a position corresponding to the connection electrode.
  • Step 209 forming a second electrode layer on the base substrate, the second electrode layer including the common The electrode, the common electrode covers the second via, wherein the connection electrode is in contact with the common electrode line and the common electrode, respectively.
  • the method of fabricating the array substrate as shown in FIG. 7 is not limited to the specific steps described above.
  • the first electrode sub-layer and the second electrode sub-layer may also be separately formed by two patterning processes, respectively.
  • the embodiments of the present invention are described by way of example only.

Abstract

一种阵列基板，包括：衬底基板（11）；第一信号传输层，第一信号传输层包括公共电极线（122）；第一绝缘层（31），第一绝缘层（31）覆盖第一信号传输层，且在对应公共电极线（122）的位置处具有第一过孔；第一电极层，第一电极层位于第一绝缘层（31）上，包括：连接电极（41），连接电极（41）位于第一过孔位置处；第二绝缘层（32），第二绝缘层（32）覆盖第一电极层，且在对应连接电极（41）的位置处具有第二过孔；第二电极层，第二电极层包括公共电极（19），公共电极（19）覆盖第二过孔；其中，连接电极（41）分别与公共电极线（122）、公共电极（19）接触。以及一种阵列基板的制作方法和使用该阵列基板的显示面板，解决了现有的公共电极和公共电极线连接的过孔深，公共电极与公共电极线的连接容易断裂的问题。

Description

一种阵列基板及其制作方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板。
背景技术
TFT-LCD因其体积小、重量轻、功耗低且无辐射等优点，在当前的平板显示器市场占据主导地位。TFT-LCD显示屏一般包括阵列基板、彩膜基板以及设置在阵列基板和彩膜基板之间的液晶。TFT-LCD显示屏形成有几十万到上百万阵列排布的显示单元，每个显示单元通过TFT的控制来显示图像。
示例的，如图1所示，为现有的TFT-LCD显示屏阵列基板上对应一个显示单元的示意图，阵列基板上形成有多条栅线121和数据线16，栅线121和数据线16交叉定义一个显示单元。图2为图1所示的a-a′示意图，如图2所示，阵列基板包括：衬底基板11；形成在衬底基板11上的栅极(栅线121的部分)、公共电极线122；覆盖栅极121和公共电极线122的栅绝缘层13；形成在栅绝缘层13上的有源层14以及源极161和漏极162；钝化层15以及形成在钝化层15上的像素电极17；平坦层18以及形成在平坦层18上的公共电极19。其中，公共电极19通过平坦层18、钝化层15以及栅绝缘层13上的过孔1与公共电极线122连接，像素电极17通过钝化层15上的过孔2与漏极162连接。
发明人发现，现有的阵列基板上，如图2所示，由于过孔1贯穿平坦层18、钝化层15以及栅绝缘层13，过孔1较深，公共电极19与公共电极线122的连接容易出现断裂，出现显示不良，降低产品良率。
发明内容
本发明的实施例提供一种阵列基板及其制作方法、显示面板，阵列基板上的公共电极通过多层导电层与公共电极线连接，避免过孔太深导致连接不良。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，本发明实施例提供了一种阵列基板，包括：
衬底基板；
第一信号传输层，所述第一信号传输层包括：公共电极线；
第一绝缘层，所述第一绝缘层覆盖所述第一信号传输层，且在对应所述公共电极线的位置处具有第一过孔；
第一电极层，所述第一电极层位于所述第一绝缘层上，包括：连接电极，所述连接电极位于所述第一过孔位置处；
第二绝缘层，所述第二绝缘层覆盖所述第一电极层，且在对应所述连接电极的位置处具有第二过孔；
第二电极层，所述第二电极层包括公共电极，所述公共电极覆盖所述第二过孔；
其中，所述连接电极分别与所述公共电极线、公共电极接触。
可选的，所述第二过孔位于对应所述第一过孔的位置处；或者，
所述连接电极从所述第一过孔延伸出并在所述第一绝缘层的上表面的至少部分上延伸；所述第二绝缘层在对应所述连接电极从所述第一过孔延伸出并在第一绝缘层的上表面的至少部分上延伸的位置处具有第二过孔。
可选的，所述第一电极层包括：
第一电极子层，所述第一电极子层包括像素电极，以及位于所述第一过孔位置处的第一连接电极；
第二电极子层，所述第二电极子层包括位于所述第一过孔位置处的第二连接电极，且所述第二电极子层位于所述第一电极子层上。
可选的，形成所述第一电极子层的材料为铟氧化锡，形成所述第二电极子层的材料为金属。
可选的，所述第二子层包括两层钼金属层以及位于所述两层钼金属层之间的铝金属层。
可选的，所述第一信号传输层还包括：栅线以及栅极；所述阵列 基板还包括：
栅绝缘层，所述栅绝缘层覆盖所述第一信号传输层，其中，所述栅绝缘层在对应所述公共电极线的位置处具有第一子过孔；
有源层，所述有源层位于所述栅绝缘层上；
第二信号传输层，所述第二信号传输层包括数据线、源极和漏极；
钝化层，所述钝化层在对应所述第一子过孔的位置处具有第二子过孔，且在对应所述漏极的位置处具有第三过孔，所述像素电极在所述第三过孔处与所述漏极连接；
所述第一电极层位于所述钝化层上，所述第一绝缘层包括栅绝缘层以及钝化层，所述第二电极子层还包括辅助电极，所述辅助电极至少在对应所述第三过孔的位置处与所述像素电极连接。
可选的，所述阵列基板包括透光区域和不透光区域，所述辅助电极在所述不透光区域与所述像素电极连接。
可选的，所述第二信号传输层还包括位于所述第一过孔位置处的第三连接电极。
另一方面，本发明实施例提供了一种制作阵列基板的方法，包括：
在衬底基板上形成第一信号传输层，所述第一信号传输层包括：公共电极线；
在所述衬底基板上形成第一绝缘层，所述第一绝缘层覆盖所述第一信号传输层，且在对应所述公共电极线的位置处具有第一过孔；
在所述衬底基板上形成第一电极层，所述第一电极层位于所述第一绝缘层上，包括：连接电极，所述连接电极位于所述第一过孔位置处；
在所述衬底基板上形成第二绝缘层，所述第二绝缘层覆盖所述第一电极层，且在对应所述连接电极的位置处具有第二过孔；
在所述衬底基板上形成第二电极层，所述第二电极层包括公共电极，所述公共电极覆盖所述第二过孔；
其中，所述连接电极分别与所述公共电极线、公共电极接触。
可选的，所述第二绝缘层在对应所述连接电极位置处具有第二过孔的步骤进一步包括：
所述连接电极层在对应所述第一过孔的位置处具有第二过孔；或者，
所述连接电极从所述第一过孔延伸出并在所述第一绝缘层的上表面的至少部分上延伸，所述第二绝缘层在对应所述连接电极从所述第一过孔延伸出并在第一绝缘层的上表面的至少部分上延伸的位置处具有第二过孔。
可选的，所述在所述衬底基板上形成第一电极层的步骤进一步包括：
在所述衬底基板上形成覆盖所述第一电极层的第一导电薄膜、第二导电薄膜和光刻胶；其中，所述第一导电薄膜和所述第二导电薄膜覆盖所述第一过孔；
利用半灰阶掩膜板对所述光刻胶进行曝光和显影；所述半灰阶掩膜板包括透光区域、半透光区域和不透光区域，其中，所述不透光区域对应所述第一过孔，所述半透光区域对应像素电极；显影后对应透光区域的光刻胶完全去除露出所述第二导电薄膜，对应半透光区域的光刻胶部分去除；刻蚀对应透光区域的第二导电薄膜以及第一导电薄膜；对所述光刻胶进行灰化处理，对应半透光区域的光刻胶完全去除露出所述第二导电薄膜，对应不透光区域的光刻胶部分保留；刻蚀对应半透光区域的第二导电薄膜；将所述光刻胶剥离。
可选的，形成所述第一导电薄膜的材料为铟氧化锡，形成所述第二导电薄膜的材料为金属。
可选的，所述在所述衬底基板上形成覆盖所述第一电极层的第一导电薄膜、第二导电薄膜和光刻胶的步骤进一步包括：
在所述第一绝缘层上形成第一导电薄膜；
在所述第一导电薄膜上形成第二导电薄膜，包括：依次形成钼金属薄膜、铝金属薄膜以及钼金属薄膜；
在所述第二导电薄膜上形成光刻胶。
可选的，所述第一信号传输层还包括栅线和栅极；所述在所述衬底基板上形成覆盖所述第一信号传输层的第一绝缘层的步骤进一步包括：
在所述衬底基板上形成栅绝缘层，所述栅绝缘层覆盖所述第一信号传输层，且在对应所述公共电极线的位置处具有第一子过孔；
在所述衬底基板上形成有源层；
在所述衬底基板上形成第二信号传输层，所述第二信号传输层包括数据线、源极和漏极；
在所述衬底基板上形成钝化层，所述钝化层在对应所述公共电极线的位置处具有第二子过孔，且在对应所述漏极的位置处具有第三过孔，所述像素电极在所述第三过孔处与所述漏极连接；
所述第一绝缘层包括栅绝缘层以及钝化层，所述第二电极子层还包括辅助电极，所述辅助电极至少在对应所述第三过孔的位置处与所述像素电极连接。
可选的，在所述栅绝缘层上形成第二信号传输层之后，且在所述第二信号传输层上形成钝化层之前，所述方法还包括：
对所述源极和漏极之间的区域进行等离子体表面处理。
另一方面，本发明实施例提供了一种显示面板，包括本发明实施例提供的任一所述的阵列基板。
本发明的实施例提供一种阵列基板及其制作方法、显示面板，阵列基板上的公共电极通过第一绝缘层上的第一过孔以及第二绝缘层上的第二过孔与公共电极线连接，但在第一过孔处还形成有连接电极，则公共电极通过连接电极与公共电极线连接。相对于公共电极直接与公共电极线连接，能够减小公共电极与公共电极线的连接深度，从而避免第一过孔和第二过孔太深，导致公共电极与公共电极线容易断开的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地， 下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有的一种阵列基板示意图；
图2为图1所示的a-a′示意图；
图3为本发明实施例提供的一种阵列基板示意图；
图4为本发明实施例提供的另一种阵列基板示意图；
图5为本发明实施例提供的另一种阵列基板示意图；
图6为本发明实施例提供的另一种阵列基板示意图；
图7为本发明实施例提供的另一种阵列基板示意图；
图8为本发明实施例提供的一种阵列基板的制作方法示意图；
图9为本发明实施例提供的一种形成第一绝缘层的方法示意图；
图10为本发明实施例提供的另一种形成第一绝缘层的方法示意图；
图11为本发明实施例提供的另一种阵列基板上制作方法示意图。
附图标记：
11-衬底基板；13-栅绝缘层；14-有源层；15-钝化层；161-源极；162-漏极；17-像素电极；18-平坦层；31-第一绝缘层；32-第二绝缘层；41-连接电极；50-辅助电极；121-栅线；122-公共电极线；411-第一连接电极；412-第二连接电极；413-第三连接电极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，本文中“上”和“下”等方位术语是相对于附图 中的阵列基板示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据阵列基板所放置的方位的变化而相应地发生变化。
在本发明所有实施例中，需要阐明“薄膜”、“层”以及“图案”的定义，以及之间的关系。其中，“薄膜”是指利用某一种材料在基板上利用沉积或其他工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”；若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个薄膜“图案”。
示例的，栅绝缘层可以是在透明基板上沉积SiNx(氮化硅)所制得的。栅绝缘层一般无需构图工艺。又示例的，有源层是氧化物半导体薄膜经构图工艺后形成的。栅金属层包括栅极、栅线，则栅极和栅线称为图案。
所谓“构图工艺”是将薄膜形成包含至少一个图案的层的工艺；而构图工艺通常包含：在薄膜上涂胶，利用掩膜板对所述光刻胶进行曝光，再利用显影液将需去除的光刻胶冲蚀掉，再刻蚀掉未覆盖光刻胶的薄膜部分，最后将剩下的光刻胶剥离。而在本发明所有实施例中，“一次构图工艺”是指经过一次曝光形成所需要的层结构工艺。
本发明实施例提供了一种阵列基板，如图3所示，包括：
衬底基板11；
第一信号传输层，第一信号传输层包括：公共电极线122；
第一绝缘层31，第一绝缘层31覆盖第一信号传输层，且在对应公共电极线122的位置处具有第一过孔；第一过孔通过去除第一绝缘层31在对应公共电极线122的位置处的部分形成，通过形成第一过孔，位于第一绝缘层31下面的公共电极线122的上表面被露出。
第一电极层，第一电极层位于第一绝缘层31上，包括：连接电极41，连接电极41位于第一过孔位置处，换句话说，连接电极41与第一过孔处露出的公共电极线122的上表面直接接触。
第二绝缘层32，第二绝缘层32覆盖第一电极层，且在对应连接 电极41的位置处具有第二过孔；第二过孔通过去除第二绝缘层32在对应公共电极线122的位置处的部分，通过形成第二过孔，位于第二绝缘层32下面的连接电极41的上表面被露出。
第二电极层，第二电极层包括公共电极19，公共电极19覆盖第二过孔，换句话说，公共电极19与第二过孔处露出的连接电极41的上表面直接接触；则连接电极41分别与公共电极线122、公共电极19接触，换句话说，公共电极19通过连接电极41与公共电极线122连接。
需要说明的是，阵列基板还可以形成有其他薄膜或层结构，上述仅以阵列基板上对应公共电极和公共电极线的连接处为例对阵列基板进行说明。在对应公共电极的位置处可以不设置其他薄膜或层结构，或者在上述的层结构中包括其他薄膜或层结构。例如，在一个实施例中，阵列基板包括薄膜晶体管，薄膜晶体管的有源层仅位于对应栅极的位置处，则在对应公共电极线的位置处不包括有源层的图案；薄膜晶体管还可以包括源漏金属层，源漏金属层可以是包括上述的连接电极。
本发明实施例提供的一种阵列基板，公共电极通过第一绝缘层上的第一过孔以及第二绝缘层上的第二过孔与公共电极线连接，其中，在第一过孔处还形成有连接电极，公共电极通过连接电极与公共电极线连接。相对于公共电极直接与公共电极线连接，本发明的实施例能够减小公共电极与公共电极线的连接深度，从而避免第一过孔和第二过孔太深，导致公共电极与公共电极线容易断开的问题。
可选的，第二过孔位于对应第一过孔的位置处。例如，如图3所示，公共电极19与公共电极线122的连接深度为第一过孔和第二过孔的深度之和。相对于现有的公共电极直接在第一过孔以及第二过孔与公共电极线连接，本发明实施例中的阵列基板，如图3所示，连接电极41位于第一过孔能够减小公共电极19与公共电极线122的连接深度，从而避免第一过孔和第二过孔太深，进而避免公共电极与公共电极线容易断开的问题。
在本发明的一个实施例中，如图4所示，连接电极41从第一过孔延伸出并在第一绝缘层31的上表面的至少部分上延伸；在第二绝 缘层32的对应连接电极41从第一过孔延伸出并在第一绝缘层31的上表面的至少部分上延伸的位置处具有第二过孔。换句话说，第一过孔可以与第二过孔错开，公共电极19通过连接电极41与公共电极线122连接，从而避免第一过孔和第二过孔位置对应形成的过孔过深，导致公共电极与公共电极线容易断开的问题。
在本发明的一个实施例中，如图5所示，第一电极层包括：
第一电极子层，第一电极子层包括像素电极17以及位于第一过孔位置处的第一连接电极411；
第二电极子层，第二电极子层包括位于第一过孔位置处的第二连接电极412，且第二电极子层412位于第一电极子层411上。
需要说明的是，第一电极层可以是包括多层导电层，其不限定于上述第一电极子层和第二电极子层。在本发明的实施例中，第一电极层还可以包括第三电极子层等。由于阵列基板上形成有像素电极，第一电极子层包括像素电极以及第一连接电极，换句话说，像素电极和第一连接电极通过一次构图形成，从而可以避免单独形成第一电极子层多一次曝光等工艺。
在本发明的一个实施例中，形成第一电极子层的材料为铟氧化锡，形成第二电极子层的材料为金属。像素电极一般为透明电极，则形成第一电极子层的材料为铟氧化锡。相对于金属氧化物，金属的导电性更好。为了提高连接电极的导电性，优选地，形成第二电极子层的材料为金属。示例的的第二电极子层的材料可以为金属钼、金属铝等。
在本发明的一个实施例中，第二电极子层可以包括两层钼金属层以及位于两层钼金属层之间的铝金属层。在现有技术中，第二电极子层的材料为铝，由于铝金属性比较活泼，在第二电极子层后形成其他薄膜或层结构时，例如形成第二电极层时，在高温环境下铝金属容易再次生长即形成小的凸起，会导致与第二电极层接触从而造成短路。因此，本发明优选的实施例中，在铝金属层的两侧分别形成钼金属层，钼金属层相对于铝金属层稳定性更好，从而可以避免高温下第二电极子层与其他电极层接触。
优选的，如图6所示，第一信号传输层还包括：栅线以及栅极 121；阵列基板还包括：
栅绝缘层13，栅绝缘层13覆盖第一信号传输层，其中，栅绝缘层13在对应公共电极线122的位置处具有第一子过孔。
有源层14，有源层14位于栅绝缘层13上。
第二信号传输层，第二信号传输层包括数据线、源极161和漏极162。
钝化层15，钝化层15在对应第一子过孔的位置处具有第二子过孔，且在对应漏极162的位置处具有第三过孔，像素电极17在第三过孔处与漏极162连接。
第一电极层位于钝化层15上，第一绝缘层包括栅绝缘层13以及钝化层15，第二电极子层还包括辅助电极50，辅助电极50至少在对应第三过孔的位置处与像素电极17连接。
即第一绝缘层包括栅绝缘层13和钝化层15，第一过孔包括栅绝缘层13上的第一子过孔以及钝化层15上的第二子过孔。
阵列基板还包括薄膜晶体管，薄膜晶体管包括栅极、源极和漏极，其中，钝化层在对应漏极的位置处具有第三过孔，像素电极在第三过孔与漏极连接，且由于第二电极子层位于第一电极子层的上面，则第二电极子层在对应第三过孔的位置处包括与像素电极连接的辅助电极。在一个实施例中，第二电极子层为两层钼金属层，位于两层钼金属层之间是铝金属层，钼金属层的稳定性较好，在像素电极与漏极连接的位置处，第二电极子层位于像素电极的上面，可以进一步避免该位置处的像素电极与空气接触，进一步保护像素电极与漏极的正常连接。
优选的，阵列基板包括透光区域和不透光区域，辅助电极在不透光区域与像素电极连接。由于像素电极形成在透光区域主要用于透光实现显示，则在不透光区域均设置有辅助电极使其与像素电极连接，以进一步保护像素电极与漏极的正常连接。
优选的，如图7所示，第二信号传输层还包括位于第一过孔位置处的第三连接电极413。即在公共电极19与公共电极线122之间，还包括第三连接电极413，进一步减小公共电极19与公共电极线122 的连接深度。且第三连接与源极、漏极同时形成，减少一次构图工艺。
本发明实施例提供了一种制作阵列基板的方法，如图8所示，方法包括：步骤101：在衬底基板上形成第一信号传输层。第一信号传输层包括：公共电极线。
示例地，步骤101包括：在衬底基板上形成金属薄膜，对金属薄膜进行曝光、刻蚀形成第一信号传输层，其中，第一信号传输层包括公共电极线。具体地，曝光、刻蚀可以是通过掩膜板构图形成。
方法还包括步骤102：在衬底基板上形成第一绝缘层，第一绝缘层覆盖第一信号传输层且在对应公共电极线的位置处具有第一过孔。
示例地，步骤102包括：在衬底基板上形成覆盖第一信号传输层的第一绝缘薄膜，对第一绝缘薄膜进行曝光、刻蚀，在第一绝缘薄膜的对应公共电极线的位置处形成过孔，由此，在第一绝缘薄膜的过孔处公共电极线的上表面被露出。
方法还包括步骤103：在衬底基板上形成第一电极层，第一电极层位于第一绝缘层上，第一电极层包括连接电极，连接电极位于第一过孔位置处。
优选地，步骤103包括：在衬底基板上形成覆盖第一电极层的第一导电薄膜、第二导电薄膜和光刻胶；其中，第一导电薄膜和第二导电薄膜覆盖第一过孔。
在本发明的实施例中，利用半灰阶掩膜板对光刻胶进行曝光和显影；半灰阶掩膜板包括透光区域、半透光区域和不透光区域，其中，不透光区域对应第一过孔，半透光区域对应像素电极；显影后对应透光区域的光刻胶完全去除露出第二导电薄膜，对应半透光区域的光刻胶部分去除；刻蚀对应透光区域的第二导电薄膜以及第一导电薄膜；对光刻胶进行灰化处理，对应半透光区域的光刻胶完全去除露出第二导电薄膜，对应不透光区域的光刻胶部分保留；刻蚀对应半透光区域的第二导电薄膜；将光刻胶剥离。
在本发明的一个实施例中，形成第二导电薄膜的材料为金属，即形成第二电极子层的材料为金属。相对于金属氧化物，金属的导电性更好。为了提高连接电极的导电性，优选的形成第二电极子层的材料 为金属。例如第二电极子层的材料可以为金属钼、金属铝等。
需要说明的是，第二电极子层一般为金属，则第二电极子层一般采用干法刻蚀，第一电极子层采用湿法刻蚀。若第二电极子层的材料为金属钼，则第二电极子层和第一电极子层均可以为采用湿法刻蚀，简化工艺步骤。
优选的，在衬底基板上形成覆盖第一电极层的第一导电薄膜、第二导电薄膜和光刻胶具体包括：
在第一绝缘层上形成第一导电薄膜；
在第一导电薄膜上形成第二导电薄膜，包括：依次形成钼金属薄膜、铝金属薄膜以及钼金属薄膜；
在第二导电薄膜上形成光刻胶。
即第二电极子层包括两层钼金属层以及位于两层钼金属层之间的铝金属层。以第二电极子层的材料为铝为例，铝金属性比较活泼，在第二电极子层后形成其他薄膜或层结构时，例如形成第二电极层时，在高温环境下铝金属容易再次生长即形成小的凸起，会导致与第二电极层接触从而造成短路。因此，本发明实施例优选的，在铝金属层的两侧分别形成钼金属层，钼金属层相对于铝金属层稳定性更好，从而可以避免高温下第二电极子层与其他电极层接触。
需要说明的是，第二电极材料包括钼铝钼三层材料层时，则第二电极子层采用干法刻蚀，第一电极材料采用湿法刻蚀。
优选的，形成第一导电薄膜的材料为铟氧化锡。像素电极一般为透明电极，则形成第一电极子层的材料为铟氧化锡。
方法还包括步骤104：在衬底基板上形成第二绝缘层，第二绝缘层覆盖第一电极层，且在对应连接电极的位置处具有第二过孔。
示例的，步骤104包括：在第一电极层上形成覆盖第一电极层的第二绝缘薄膜；对第二绝缘薄膜进行曝光、刻蚀，去除对应第一绝缘层过孔处的第二绝缘薄膜，连接电极的上表面露出。
优选的，第二绝缘层在对应连接电极位置处具有第二过孔具体包括：连接电极层在对应第一过孔的位置处具有第二过孔。即第二过孔 位于对应第一过孔的位置处，如图3所示，公共电极19与公共电极线122的连接深度为第一过孔和第二过孔的深度之和。
或者，连接电极从第一过孔延伸出并在第一绝缘层的上表面的至少部分上延伸，第二绝缘层在对应连接电极位置处具有第二过孔具体包括：第二绝缘层在对应连接电极从第一过孔延伸出的位置处具有第二过孔。
具体可以参照4所示，连接电极19从第一过孔延伸出并在第一绝缘层31的上表面的至少部分上延伸；第二绝缘层31在对应连接电极41从第一过孔延伸的位置处具有第二过孔。即第一过孔还可以与第二过孔错开，公共电极通过连接电极与公共电极线连接，从而避免第一过孔和第二过孔位置对应形成的过孔过深，导致公共电极与公共电极线容易断开的问题。
方法还可以包括步骤105：在衬底基板上形成第二电极层，第二电极层包括公共电极，公共电极覆盖第二过孔。其中，连接电极分别与公共电极线、公共电极接触。
可选的，第一信号传输层还包括栅线和栅极；如图9所示，在衬底基板上形成覆盖第一信号传输层的第一绝缘层的步骤包括：
步骤1021：在衬底基板上形成栅绝缘层，栅绝缘层覆盖第一信号传输层，且在对应公共电极线的位置处具有第一子过孔。
示例的，步骤201包括：在衬底基板上形成绝缘薄膜，对绝缘膜进行曝光、刻蚀形成栅绝缘层，在对应公共电极线的位置处具有第一子过孔。
在衬底基板上形成覆盖第一信号传输层的第一绝缘层的步骤还可以包括步骤1022：在衬底基板上形成有源层。具体包括：在衬底基板上形成半导体薄膜，对半导体薄膜进行曝光、刻蚀形成有源层。
在衬底基板上形成覆盖第一信号传输层的第一绝缘层的步骤还可以包括步骤1023：在衬底基板上形成第二信号传输层，第二信号传输层包括数据线、源极和漏极。
具体包括：在有源层上形成金属薄膜以及光刻胶；利用掩膜板对光刻胶进行曝光和显影，掩膜板包括透光区域和不透光区域，不透光 区域对应数据线、源极和漏极，显影后对应透光区域的光刻胶完全去除露出金属薄膜；刻蚀对应透光区的金属薄膜；将光刻胶剥离。
在衬底基板上形成覆盖第一信号传输层的第一绝缘层的步骤还可以包括步骤1024：在衬底基板上形成钝化层，钝化层在对应公共电极线的位置处具有第二子过孔，且在对应漏极的位置处具有第三过孔，像素电极在第三过孔处与漏极连接。
具体包括：在述第二信号传输层上形成绝缘薄膜，对绝缘薄膜进行曝光、刻蚀，在对应漏极和公共电极线的位置处分别形成过孔，漏极的上表面以及公共电极线的上表面露出。
第一绝缘层包括栅绝缘层以及钝化层，第二电极子层还包括辅助电极，辅助电极至少在对应第三过孔的位置处与像素电极连接。
形成的阵列基板如图6所示，阵列基板还包括薄膜晶体管，薄膜晶体管包括栅极、源极和漏极，其中，钝化层在对应漏极的位置处具有第三过孔，像素电极在第三过孔与漏极连接，且由于第二电极子层位于第一电极子层的上面，则第二电极子层在对应第三过孔的位置处包括与像素电极连接的辅助电极。以第二电极子层为两层钼金属层以及位于两层钼金属层之间的铝金属层为例，钼金属层的稳定性较好，在像素电极与漏极连接的位置处，第二电极子层位于像素电极的上面，可以进一步避免该位置处的像素电极与空气接触，进一步保护像素电极与漏极的正常连接。
如图6所示的阵列基板，第一绝缘层包括栅绝缘层13和钝化层15，第一过孔包括栅绝缘层13上的第一子过孔以及钝化层15上的第二子过孔。
优选的，第二信号传输层还包括位于第一过孔位置处的第三连接电极。即如图7所示，在公共电极19与公共电极线122之间，还包括第三连接电极413，进一步减小公共电极19与公共电极线122的连接深度。且第三连接与源极、漏极同时形成，减少一次构图工艺。具体的，掩膜板的不透光区域还对应公共电极线，即通过一次构图工艺形成源极、漏极以及第三连接电极。
优选的，如图10所示，在上述步骤1023之后，在上述步骤1024之前，所述方法还包括：
步骤1025：对源极和漏极之间的区域进行等离子体表面处理。
具体可以是利用(SF6+O2)或者H2等气体的等离子体处理，目的是扫导电沟道内的杂质离子，并对导电沟道膜层进行缺陷改善。当然，也可以利用其他气体对源极和漏极之间的区域进行等离子体表面处理，本发明实施例仅以上述为例进行说明。
本发明实施例提供的制作阵列基板的方法，在形成钝化层之前，对沟道区域进行等离子体处理，修正改善在沟道刻蚀过程中对导电沟道的轰击损坏，并且可以对沟道进行气体处理，清扫导电沟道内的杂质离子，并对导电沟道膜层进行缺陷改善，进而可以提高薄膜晶体管的性能。
下面，提供一具体实施例，以说明如图7所示的制作阵列基板的方法，如图11所示，该方法包括：
步骤201：在衬底基板上形成第一信号传输层。第一信号传输层包括栅线、栅极以及公共电极线。
步骤202：在衬底基板上形成栅绝缘层，栅绝缘层覆盖第一信号传输层且在对应公共电极线的位置处具有第一子过孔。
步骤203：在衬底基板上形成有源层。
步骤204：在衬底基板上形成第二信号传输层，第二信号传输层包括数据线、源极、漏极以及第三连接电极。
步骤205：对源极和漏极之间的区域进行等离子体表面处理。
步骤206：在衬底基板上形成钝化层，钝化层在对应公共电极线的位置处具有第二子过孔，且在对应漏极的位置处具有第三过孔。
步骤207：通过一次构图工艺在衬底基板上形成第一电极层。其中，第一电极层包括第一电极子层和第二电极子层。第一电极子层包括像素电极以及第一连接电极，第二电极子层包括第二连接电极。具体可以参照上述步骤103。
步骤208：在衬底基板上形成平坦层。平坦层覆盖第一电极层，且在对应连接电极的位置处具有第二过孔。
步骤209：在衬底基板上形成第二电极层，第二电极层包括公共 电极，公共电极覆盖第二过孔，其中，连接电极分别与公共电极线、公共电极接触。
当然，形成如图7所示的阵列基板的制作方法也不局限于上述具体步骤。例如第一电极子层和第二电极子层还可以是分别通过两次构图工艺分别形成。本发明实施例仅以上述为例进行说明。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板；
    第一信号传输层，所述第一信号传输层包括：公共电极线；
    第一绝缘层，所述第一绝缘层覆盖所述第一信号传输层，且在对应所述公共电极线的位置处具有第一过孔；
    第一电极层，所述第一电极层位于所述第一绝缘层上，包括：连接电极，所述连接电极位于所述第一过孔位置处；
    第二绝缘层，所述第二绝缘层覆盖所述第一电极层，且在对应所述连接电极的位置处具有第二过孔；
    第二电极层，所述第二电极层包括公共电极，所述公共电极覆盖所述第二过孔；
    其中，所述连接电极分别与所述公共电极线、公共电极接触。
  2. 根据权利要求1所述的阵列基板，其中所述第二过孔位于对应所述第一过孔的位置处；或者，
    所述连接电极从所述第一过孔延伸出并在所述第一绝缘层的上表面的至少部分上延伸；在所述第二绝缘层的对应所述连接电极从所述第一过孔延伸出并在第一绝缘层的上表面的至少部分上延伸的位置处具有第二过孔。
  3. 根据权利要求1所述的阵列基板，其中所述第一电极层包括：
    第一电极子层，所述第一电极子层包括像素电极以及位于所述第一过孔位置处的第一连接电极；
    第二电极子层，所述第二电极子层包括位于所述第一过孔位置处的第二连接电极，且所述第二电极子层位于所述第一电极子层上。
  4. 根据权利要求3所述的阵列基板，其中形成所述第一电极子层的材料为铟氧化锡，形成所述第二电极子层的材料为金属。
  5. 根据权利要求4所述的阵列基板，其中所述第二子层包括两层钼金属层以及位于所述两层钼金属层之间的铝金属层。
  6. 根据权利要求1所述的阵列基板，其中所述第一信号传输层还包括：栅线以及栅极；所述阵列基板还包括：
    栅绝缘层，所述栅绝缘层覆盖所述第一信号传输层，其中，所述栅绝缘层在对应所述公共电极线的位置处具有第一子过孔；
    有源层，所述有源层位于所述栅绝缘层上；
    第二信号传输层，所述第二信号传输层包括数据线、源极和漏极；
    钝化层，所述钝化层在对应所述第一子过孔的位置处具有第二子过孔，且在对应所述漏极的位置处具有第三过孔，所述像素电极在所述第三过孔处与所述漏极连接；
    所述第一电极层位于所述钝化层上，所述第一绝缘层包括栅绝缘层以及钝化层，所述第二电极子层还包括辅助电极，所述辅助电极至少在对应所述第三过孔的位置处与所述像素电极连接。
  7. 根据权利要求6所述的阵列基板，其中所述阵列基板包括透光区域和不透光区域，所述辅助电极在所述不透光区域与所述像素电极连接。
  8. 根据权利要求6所述的阵列基板，其中所述第二信号传输层还包括位于所述第一过孔位置处的第三连接电极。
  9. 一种制作阵列基板的方法，包括下列步骤：
    在衬底基板上形成第一信号传输层，所述第一信号传输层包括公共电极线；
    在所述衬底基板上形成第一绝缘层，所述第一绝缘层覆盖所述第一信号传输层且在对应所述公共电极线的位置处具有第一过孔；
    在所述衬底基板上形成第一电极层，所述第一电极层位于所述第一绝缘层上，所述第一电极层包括连接电极，所述连接电极位于所述第一过孔位置处；
    在所述衬底基板上形成第二绝缘层，所述第二绝缘层覆盖所述第一电极层且在对应所述连接电极的位置处具有第二过孔；
    在所述衬底基板上形成第二电极层，所述第二电极层包括公共电极，所述公共电极覆盖所述第二过孔；
    其中，所述连接电极分别与所述公共电极线、公共电极接触。
  10. 根据权利要求9所述的方法，其中所述第二绝缘层在对应所述连接电极位置处具有第二过孔的步骤进一步包括：
    所述连接电极层在对应所述第一过孔的位置处具有第二过孔；或者，
    所述连接电极从所述第一过孔延伸出并在所述第一绝缘层的上表面的至少部分上延伸，在所述第二绝缘层的对应所述连接电极从所述第一过孔延伸出并在第一绝缘层的上表面的至少部分上延伸的位置处具有第二过孔。
  11. 根据权利要求9所述的方法，其中所述在所述衬底基板上形成第一电极层的步骤进一步包括：
    在所述衬底基板上形成覆盖所述第一电极层的第一导电薄膜、第二导电薄膜和光刻胶；其中，所述第一导电薄膜和所述第二导电薄膜覆盖所述第一过孔；
    利用半灰阶掩膜板对所述光刻胶进行曝光和显影；所述半灰阶掩膜板包括透光区域、半透光区域和不透光区域，其中，所述不透光区域对应所述第一过孔，所述半透光区域对应像素电极；显影后对应透光区域的光刻胶完全去除露出所述第二导电薄膜，对应半透光区域的光刻胶部分去除；刻蚀对应透光区域的第二导电薄膜以及第一导电薄膜；对所述光刻胶进行灰化处理，对应半透光区域的光刻胶完全去除露出所述第二导电薄膜，对应不透光区域的光刻胶部分保留；刻蚀对应半透光区域的第二导电薄膜；将所述光刻胶剥离。
  12. 根据权利要求11所述的方法，其中形成所述第一导电薄膜的材料为铟氧化锡，形成所述第二导电薄膜的材料为金属。
  13. 根据权利要求11所述的方法，其中所述在所述衬底基板上形成覆盖所述第一电极层的第一导电薄膜、第二导电薄膜和光刻胶的步骤进一步包括：
    在所述第一绝缘层上形成第一导电薄膜；
    在所述第一导电薄膜上形成第二导电薄膜，包括：依次形成钼金属薄膜、铝金属薄膜以及钼金属薄膜；
    在所述第二导电薄膜上形成光刻胶。
  14. 根据权利要求9所述的方法，其中所述第一信号传输层还包括栅线和栅极；所述在所述衬底基板上形成覆盖所述第一信号传输层的第一绝缘层的步骤进一步包括：
    在所述衬底基板上形成栅绝缘层，所述栅绝缘层覆盖所述第一信号传输层，且在对应所述公共电极线的位置处具有第一子过孔；
    在所述衬底基板上形成有源层；
    在所述衬底基板上形成第二信号传输层，所述第二信号传输层包括数据线、源极和漏极；
    在所述衬底基板上形成钝化层，所述钝化层在对应所述公共电极线的位置处具有第二子过孔且在对应所述漏极的位置处具有第三过孔，所述像素电极在所述第三过孔处与所述漏极连接；
    所述第一绝缘层包括栅绝缘层以及钝化层，所述第二电极子层还包括辅助电极，所述辅助电极至少在对应所述第三过孔的位置处与所述像素电极连接。
  15. 根据权利要求12或13所述的方法，其中在所述栅绝缘层上形成第二信号传输层之后，且在所述第二信号传输层上形成钝化层之前，所述方法还包括：
    对所述源极和漏极之间的区域进行等离子体表面处理。
  16. 一种显示面板，包括权利要求1-8任一项所述的阵列基板。
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