WO2013155843A1 - 阵列基板及其制造方法和液晶显示面板 - Google Patents

阵列基板及其制造方法和液晶显示面板 Download PDF

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Publication number
WO2013155843A1
WO2013155843A1 PCT/CN2012/085688 CN2012085688W WO2013155843A1 WO 2013155843 A1 WO2013155843 A1 WO 2013155843A1 CN 2012085688 W CN2012085688 W CN 2012085688W WO 2013155843 A1 WO2013155843 A1 WO 2013155843A1
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Prior art keywords
gate
array substrate
data line
insulating layer
gate insulating
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PCT/CN2012/085688
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English (en)
French (fr)
Inventor
铃木照晃
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京东方科技集团股份有限公司
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Publication of WO2013155843A1 publication Critical patent/WO2013155843A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and a liquid crystal display panel. Background technique
  • Advanced Super Dimension Switch (ADS) technology is an important wide viewing angle display technology, which generates an electric field generated by the edge of the slit electrode in the same plane and between the slit electrode layer and the plate electrode layer.
  • the generated electric field forms a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the array substrate is an important component of the above ADS type liquid crystal display panel.
  • 6 is a schematic structural view of an array substrate of an ADS type liquid crystal display panel in the conventional art.
  • the array substrate includes a base substrate 10 and gate lines and data lines 12 above the base substrate 10.
  • the gate lines and the data lines 12 cross each other to define pixel cells.
  • a thin film transistor, a pixel electrode 13 (corresponding to a plate electrode), and a common electrode 14 (corresponding to a slit electrode) are formed in the pixel unit.
  • the pixel electrode 13 and the common electrode 14 form a multi-dimensional electric field.
  • the thin film transistor may include an active layer 16, a gate 17, a source 18, and a drain 19.
  • the gate electrode 17 is disposed in the same layer as the gate line.
  • the source 18 and the drain 19 are disposed in the same layer as the data line 12.
  • gate lines and gate electrodes 17 are formed on the base substrate 10, a gate insulating layer 20 is formed on the base substrate 10 to cover the gate lines and the gate electrodes 14, and an active layer pattern 16 is formed on the gate insulating layer 20.
  • the data line 12 is formed on the gate insulating layer 20, one end of the source 18 is formed on the active layer pattern 16, and the other end of the source 18 is formed on the gate insulating layer 20 and the data line.
  • the drain 19 is formed on the source layer pattern 16, the other end of the drain 19 is formed on the gate insulating layer 20, the pixel electrode 13 is formed on the gate insulating layer 20, and one end of the pixel electrode 13 is formed on the drain 19, a passivation layer 21 is formed on the pixel electrode 13 and covers the entire base substrate 10, a resin layer 22 is formed on the passivation layer 21 and covers the entire base substrate 10, and the common electrode 14 is formed on the resin layer.
  • a resin layer 22 is disposed on the array substrate, and the resin layer 22 is located between the data line 12 and the common electrode 14. The parasitic capacitance between the data line 12 and the common electrode 14 can be reduced, thereby improving the transmittance of the pixel unit. . However, since the resin layer 22 increases the distance between the pixel electrode 13 and the common electrode 14, the electric field efficiency between the pixel electrode 13 and the common electrode 14 is lowered. Summary of the invention
  • an array substrate includes a substrate substrate and gate lines and data lines formed on the base substrate.
  • the gate lines and the data lines cross each other to define a pixel unit.
  • a thin film transistor, a pixel electrode, and a common electrode are formed in the pixel unit.
  • the data line is squared to have a resin pattern covering the data lines.
  • a liquid crystal display panel includes a counter substrate and an array substrate provided to the cartridge, and a liquid crystal layer filled between the opposite substrate and the array substrate.
  • the array substrate is the same as the array substrate of the above embodiment.
  • a method of fabricating an array substrate includes: forming a gate line, a data line, a thin film transistor, a pixel electrode, a resin pattern, and a common electrode on a base substrate.
  • the gate lines and the data lines cross each other to define a pixel unit, and the thin film transistor, the pixel electrode, and the common electrode are located in the pixel unit, and the resin pattern is located above the data line and covers the data line.
  • the resin pattern is formed only above the data line, and no resin pattern is formed between the pixel electrode and the common electrode, thereby reducing the distance between the pixel electrode and the common electrode as compared with the conventional technique, thereby improving The electric field efficiency between the pixel electrode and the common electrode.
  • FIG. 1 is a schematic plan view showing the structure of an array substrate according to Embodiment 1 of the present invention.
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • Figure 3 is a cross-sectional view taken along line B-B of Figure 2;
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to Embodiment 3 of the present invention
  • FIG. 5a is a schematic diagram of forming a gate in Embodiment 3 of the present invention
  • FIG. 5a is a schematic diagram of forming a gate in Embodiment 3 of the present invention
  • FIG. 5b is a schematic diagram of forming a gate insulating layer in Embodiment 3 of the present invention.
  • 5c is a schematic diagram of forming an active layer in Embodiment 3 of the present invention.
  • 5d is a schematic diagram of forming a source and a drain in Embodiment 3 of the present invention.
  • 5e is a schematic diagram of forming a pixel electrode according to Embodiment 3 of the present invention.
  • 5f is a schematic view showing forming a passivation layer in Embodiment 3 of the present invention.
  • Figure 5g is a schematic view showing the formation of a resin pattern in the third embodiment of the present invention.
  • FIG. 6 is a schematic structural view of an array substrate of an ADS type liquid crystal panel in the conventional art. detailed description
  • FIG. 1 is a plan view showing a structure of an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1
  • FIG. 3 is a cross-sectional view taken along line B-B of FIG.
  • the array substrate includes a base substrate 10 and gate lines 11 and data lines 12 formed on the base substrate 10, and the gate lines 11 and the data lines 12 cross each other to define pixel units.
  • a thin film transistor, a pixel electrode 13 and a common electrode 14 forming a multi-dimensional electric field with the pixel electrode 13 are formed in the pixel unit, and a resin pattern 15 covering the data line 12 is formed over the data line 12.
  • the thin film transistor may include: an active layer 16, a gate 17, a source 18, and a drain 19.
  • the gate electrode 17 is disposed in the same layer as the gate line 11.
  • the source 18 and the drain 19 are disposed in the same layer as the data line 12.
  • the above components are disposed on the base substrate 10 in the following manner to form an array substrate according to an embodiment of the present invention.
  • a gate line 11 and a gate electrode 17 are formed on the base substrate 10, and a gate insulating layer 20 is formed on the base substrate 10 to cover the gate line 11 and the gate electrode 17.
  • the active layer 16 is formed on the gate insulating layer 20 and is located on the gate.
  • a data line 12 is formed on the gate insulating layer 20, one end of the source 18 is formed on the active layer pattern 16, and the other end of the source 18 is formed on the gate insulating layer 20 and connected to the data line 12.
  • One end of the drain 19 is formed on the source layer pattern 16, and the other end of the drain 19 is formed on the gate insulating layer 20.
  • the pixel electrode 13 is formed on the gate insulating layer 20, and one end of the pixel electrode 13 is formed on the drain electrode 19 to connect the drain electrode 19 to the pixel electrode 13.
  • the passivation layer 21 is formed on the pixel electrode 13 and covers the substrate substrate 10.
  • the resin pattern 15 is formed on the passivation layer 21, a part of the common electrode 14 is formed on the passivation layer 21, and another portion of the common electrode 14 is formed on the resin pattern 15.
  • the pixel electrode 13 is a plate electrode
  • the common electrode 14 is a slit electrode
  • the resin pattern 15 is formed only above the data line 12, and the width of the resin pattern 15 may be greater than or equal to the width of the data line 12 to achieve the purpose of covering the data line 12.
  • the width of the resin pattern 15 is larger than the width of the data line 12 to ensure that the resin pattern 15 can completely cover the data line 12.
  • the cross section of the resin pattern 15 may have a semicircular shape, a square shape or a triangular shape.
  • the shape of the cross section of the resin pattern 15 is preferably semicircular. In practical applications, the cross section of the resin pattern 15 can also be used in other shapes, which are not listed here.
  • the material of the resin pattern 15 comprises: an acrylic resin or a novolak resin.
  • the specific structure of the array substrate provided in Fig. 1 is only one embodiment of the present invention. In actual applications, the position and hierarchical relationship of each structure can be changed as needed.
  • the resin pattern 15 may be formed directly on the data line 12, and then the passivation layer 21 and the common electrode 14 may be sequentially formed.
  • the array substrate includes a base substrate and gate lines and data lines formed on the base substrate, and the pixel unit defined by the gate lines and the data lines is formed with a thin film transistor, a pixel electrode, and a multi-dimensional electric field formed with the pixel electrode
  • the common electrode has a resin pattern covering the data line formed above the data line.
  • the resin pattern is formed only above the data line, and no resin pattern is formed between the pixel electrode and the common electrode, thereby reducing the distance between the pixel electrode and the common electrode as compared with the conventional technique, thereby improving the pixel electrode. Electric field efficiency between the electrode and the common electrode.
  • a resin pattern is formed between the data line and the common electrode, which reduces the parasitic capacitance between the data line and the common electrode, thereby improving the light transmittance of the pixel unit.
  • the common electrode overlying the data line shields the unfavorable electric field from the data line.
  • Embodiment 2 of the present invention provides a liquid crystal display panel.
  • the liquid crystal display panel includes a facing substrate, an array substrate, and a liquid crystal layer filled between the opposite substrate and the array substrate.
  • the array substrate provided in the above embodiment 1 can be used for the array substrate, and details are not described herein again.
  • Embodiment 3 of the present invention provides a method of manufacturing an array substrate.
  • the method can include: Forming a gate line, a data line, a thin film transistor, a pixel electrode, a resin pattern, and a common electrode forming a multi-dimensional electric field with the pixel electrode on the base substrate, the gate line and the data line defining the pixel unit, and the thin film transistor, the pixel electrode, and the common electrode are located in the pixel unit Inside, the resin pattern is above the data line and covers the data line.
  • FIG. 4 is a flow chart of a method for fabricating an array substrate according to a third embodiment of the present invention
  • FIGS. 5a-5g are schematic structural views of an array substrate during a manufacturing process.
  • a method of manufacturing the array substrate provided in the third embodiment will be described in detail with reference to FIG. 4 and FIGS. 5a to 5g.
  • the method includes:
  • Step 101 Form a gate line and a gate on the base substrate, and connect the gate and the gate line.
  • Fig. 5a is a schematic view showing the formation of a gate electrode in the third embodiment.
  • a gate line 11 and a gate electrode 17 are formed on the base substrate 10 by a patterning process, and the gate electrode 17 is connected to the gate line 11.
  • the gate line 11 can be seen in FIG.
  • Step 102 Form a gate insulating layer on the substrate of the step 101, and the gate insulating layer covers the substrate.
  • Fig. 5b is a schematic view showing the formation of a gate insulating layer in the third embodiment. As shown in Figure 5b, after completing the steps
  • a gate insulating layer 20 is coated on the base substrate 10 of 101, and the gate insulating layer 20 covers the entire base substrate 10.
  • Step 103 Form an active layer pattern on the gate insulating layer, and the active layer pattern is located above the gate.
  • Fig. 5c is a schematic view showing the formation of an active layer pattern in the third embodiment. As shown in Fig. 5c, an active layer 16 is formed on the base substrate 10 by a patterning process, and the active layer 16 is located above the gate electrode 17.
  • Step 104 forming a data line, a source and a drain on the base substrate completing step 103, one end of the source is formed on the active layer pattern, and the other end of the source is formed on the gate insulating layer and connected to the data line
  • One end of the drain is formed on the active layer pattern, and the other end of the drain is formed on the gate insulating layer.
  • Fig. 5d is a schematic view showing the formation of a source drain pattern in the third embodiment.
  • a data line 12 a source 18 and a drain 19 are formed on the base substrate 10 completing the step 103 by a patterning process, and one end of the source 18 is formed on the active layer pattern 16, the source 18 The other end is formed on the gate insulating layer 20 and connected to the data line 12, one end of the drain 19 is formed on the active layer pattern 16, and the other end of the drain 19 is formed on the gate insulating layer 20.
  • Step 105 Form a pixel electrode on the substrate of the step 104.
  • the pixel electrode is formed on the gate insulating layer and one end of the pixel electrode is formed on the drain.
  • FIG. 5e is a schematic diagram of forming a pixel electrode in the third embodiment. As shown in Figure 5e, through the patterning process A pixel electrode 13 is formed on the base substrate 10 on which the step 104 is completed. The pixel electrode 13 is formed on the gate insulating layer 20 and one end of the pixel electrode 13 is formed on the drain electrode 19.
  • Step 106 Form a passivation layer on the substrate of the step 105, and the passivation layer covers the substrate.
  • Figure 5f is a schematic view showing the formation of a passivation layer in the third embodiment. As shown in Fig. 5f, a passivation layer 21 is coated on the base substrate 10 on which step 105 is completed, and the passivation layer 21 covers the entire base substrate 10.
  • Step 107 forming a resin pattern on the passivation layer.
  • Fig. 5g is a schematic view showing the formation of a resin pattern in the third embodiment.
  • a resin pattern 15 is formed on the passivation layer 21 by a patterning process, and the resin pattern 15 is located above the data line 12.
  • the step 107 may include: coating a resin layer on the passivation layer and coating a photoresist on the resin layer; exposing a portion of the photoresist by masking the mask and exposing the photoresist; The developing process removes the exposed photoresist; removing the resin layer not covered by the photoresist by an etching process to form a resin pattern; and peeling off the unexposed photoresist on the resin pattern.
  • the resin pattern 15 is formed over the data line 12 and covers the data line 12, and preferably, the width of the resin pattern 15 is larger than the width of the data line 12.
  • Step 108 forming a common electrode on the base substrate on which the step 107 is completed.
  • a common electrode 14 is formed on the base substrate 10 on which the step 107 is completed by a patterning process.
  • a part of the common electrode 14 is formed on the passivation layer 21, and a part is formed on the resin pattern 15.
  • the method for fabricating the array substrate provided in this embodiment can be used to manufacture the array substrate described in the first embodiment.
  • the resin pattern is formed only above the data line, and the resin pattern is not formed between the pixel electrode and the common electrode, thereby reducing the pixel electrode and the common electrode compared with the conventional technology. The distance, thereby increasing the electric field efficiency between the pixel electrode and the common electrode.
  • a resin pattern is formed between the data line and the common electrode, which reduces the parasitic capacitance between the data line and the common electrode, thereby improving the light transmittance of the pixel unit.
  • the common electrode overlying the data line shields the unfavorable electric field from the data line.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种阵列基板，其包括衬底基板（10）和形成于所述衬底基板（10）上的栅线（11）和数据线（12）。栅线（11）和数据线（12）彼此交叉以限定像素单元。像素单元内形成有薄膜晶体管、像素电极（13）和公共电极（14）。数据线（12）上方形成有覆盖数据线（12）的树脂图形（15）。还提供了一种所述阵列基板的制造方法以及液晶显示面板。

Description

阵列基板及其制造方法和液晶显示面板 技术领域
本发明的实施例涉及一种阵列基板， 该阵列基板的制造方法以及液晶显 示面板。 背景技术
高级超维场转换 ( Advanced Super Dimension Switch, 简称 ADS )技术 是一种重要的宽视角显示技术， 其通过同一平面内的狭缝电极边缘所产生的 电场以及狭缝电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内 狭缝电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液 晶工作效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD产 品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低 色差、 无挤压水波紋（push Mura )等优点。
阵列基板是上述 ADS型液晶显示面板的重要部件。 图 6为传统技术中 ADS型液晶显示面板的阵列基板的结构示意图。 如图 6所示， 该阵列基板包 括衬底基板 10和位于衬底基板 10上方的栅线和数据线 12。栅线和数据线 12 彼此交叉以限定像素单元。 像素单元内形成有薄膜晶体管、 像素电极 13 (相 当于板状电极）及公共电极 14 (相当于狭缝电极） 。 像素电极 13和公共电 极 14形成多维电场。 薄膜晶体管可包括有源层 16、栅极 17、 源极 18和漏极 19。 栅极 17与栅线同层设置。 源极 18、 漏极 19与数据线 12同层设置。
更具体地，栅线和栅极 17形成于衬底基板 10上，栅绝缘层 20形成在衬 底基板 10上以覆盖栅线和栅极 14, 有源层图形 16形成于栅绝缘层 20上且 位于栅极 17的上方， 数据线 12形成于栅绝缘层 20上， 源极 18的一端形成 于有源层图形 16上， 源极 18的另一端形成于栅绝缘层 20上且与数据线 12 连接，漏极 19的一端形成于源层图形 16上，漏极 19的另一端形成于栅绝缘 层 20上， 像素电极 13形成于栅绝缘层 20上且像素电极 13的一端形成于漏 极 19上， 钝化层 21形成在像素电极 13上并覆盖整个衬底基板 10, 树脂层 22形成在钝化层 21上并覆盖整个衬底基板 10, 公共电极 14形成于树脂层 上述阵列基板上设置了树脂层 22,树脂层 22位于数据线 12和公共电极 14之间， 可减小数据线 12和公共电极 14之间的寄生电容， 从而达到提高像 素单元透光率的目的。 但是， 由于树脂层 22增大了像素电极 13和公共电极 14之间的距离， 从而降低了像素电极 13和公共电极 14之间的电场效率。 发明内容
根据本发明的一个实施例， 提供一种阵列基板。 该阵列基板包括衬底基 板和形成于衬底基板上的栅线和数据线。 栅线和数据线彼此交叉以限定像素 单元。 像素单元内形成有薄膜晶体管、 像素电极和公共电极。 数据线上方形 成有覆盖数据线的树脂图形。
根据本发明的另一个实施例， 提供一种液晶显示面板。 该液晶显示面板 包括对盒设置的对向基板和阵列基板以及填充在对向基板和阵列基板之间的 液晶层。 该阵列基板釆用上述实施例的阵列基板。
根据本发明的再一个实施例， 提供一种阵列基板的制造方法。 该方法包 括： 在衬底基板上形成栅线、 数据线、 薄膜晶体管、 像素电极、 树脂图形和 公共电极。 栅线和数据线彼此交叉限定出像素单元， 薄膜晶体管、 像素电极 和公共电极位于像素单元内， 树脂图形位于数据线上方并覆盖数据线。
根据本发明的实施例， 树脂图形仅形成于数据线上方， 在像素电极和公 共电极之间未形成树脂图形， 因此与传统技术相比减小了像素电极和公共电 极之间的距离， 从而提高了像素电极和公共电极之间的电场效率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例一提供的阵列基板的结构的平面示意图；
图 2为图 1中 A-A向剖视图；
图 3为图 2中 B-B向剖视图；
图 4为本发明实施例三提供的阵列基板的制造方法的流程图； 图 5a为本发明实施例三中形成栅极的示意图；
图 5b为本发明实施例三中形成栅绝缘层的示意图；
图 5c为本发明实施例三中形成有源层的示意图；
图 5d为本发明实施例三中形成源漏极的示意图；
图 5e为本发明实施例三形成像素电极的示意图；
图 5f为本发明实施例三中形成钝化层的示意图；
图 5g为本发明实施例三中形成树脂图形的示意图； 以及
图 6为传统技术中 ADS型液晶面板的阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
图 1为本发明实施例一提供的阵列基板的结构的平面示意图， 图 2为图 1中 A-A向剖视图， 图 3为图 2中 B-B向剖视图。 如图 1、 图 2和图 3所示， 该阵列基板包括衬底基板 10和形成于衬底基板 10上的栅线 11和数据线 12, 栅线 11和数据线 12彼此交叉以限定像素单元， 像素单元内形成有薄膜晶体 管、 像素电极 13和与像素电极 13形成多维电场的公共电极 14, 数据线 12 上方形成有覆盖数据线 12的树脂图形 15。
薄膜晶体管可包括： 有源层 16、 栅极 17、 源极 18和漏极 19。 栅极 17 与栅线 11同层设置。 源极 18、 漏极 19与数据线 12同层设置。
例如，上述各部件以下述方式设置在衬底基板 10上以形成根据本发明实 施例的阵列基板。
栅线 11和栅极 17形成于衬底基板 10上， 栅绝缘层 20形成在衬底基板 10上以覆盖栅线 11和栅极 17, 有源层 16形成于栅绝缘层 20上且位于栅极 17的上方， 数据线 12形成于栅绝缘层 20上， 源极 18的一端形成于有源层 图形 16上， 源极 18的另一端形成于栅绝缘层 20上且与数据线 12连接， 漏 极 19的一端形成于源层图形 16上，漏极 19的另一端形成于栅绝缘层 20上， 像素电极 13形成于栅绝缘层 20上， 像素电极 13的一端形成于漏极 19上以 实现漏极 19与像素电极 13连接， 钝化层 21形成在像素电极 13上并覆盖衬 底基板 10, 树脂图形 15形成于钝化层 21上， 公共电极 14的一部分形成于 钝化层 21上， 公共电极 14的另一部分形成于树脂图形 15上。
本实施例中， 优选地， 像素电极 13为板状电极， 公共电极 14为狭缝电 极。
本实施例中， 树脂图形 15仅形成于数据线 12的上方， 该树脂图形 15 的宽度可大于或者等于数据线 12的宽度， 以达到覆盖数据线 12的目的。 优 选地，树脂图形 15的宽度大于数据线 12的宽度， 以保证树脂图形 15可完全 覆盖数据线 12。 树脂图形 15的横截面的形状可以为半圓形、 方形或者三角 形。优选地，树脂图形 15的横截面的形状优选为半圓形。在实际应用中树脂 图形 15的横截面还可以釆用其它形状， 此处不再——列举。优选地，树脂图 形 15的材料包括： 丙烯酸树脂 （acrylic resin )或者线性酚醛树脂 （novolak resin ) 。
图 1中提供的阵列基板的具体结构仅为本发明的一种实施例。 在实际应 用中， 根据需要可变更各个结构的位置和层次关系。 例如， 可以将树脂图形 15直接形成在数据线 12上， 然后再依次形成钝化层 21和公共电极 14。
在本实施例中， 阵列基板包括衬底基板和形成于衬底基板上的栅线和数 据线， 栅线和数据线限定的像素单元内形成有薄膜晶体管、 像素电极和与像 素电极形成多维电场的公共电极 ,数据线上方形成有覆盖数据线的树脂图形。 本实施例中树脂图形仅形成于数据线上方， 在像素电极和公共电极之间未形 成树脂图形， 因此与传统技术相比减小了像素电极和公共电极之间的距离， 从而提高了像素电极和公共电极之间的电场效率。 本实施例中， 数据线和公 共电极之间形成有树脂图形， 减小了数据线和公共电极之间的寄生电容， 从 而提高了像素单元的透光率。 本实施例中， 覆盖于数据线上方的公共电极可 屏蔽来自于数据线的不利电场。
本发明实施例二提供了一种液晶显示面板。 该液晶显示面板包括对向基 板、 阵列基板以及填充在对向基板和阵列基板之间的液晶层。 其中， 阵列基 板可釆用上述实施例一提供的阵列基板， 此处不再赘述。
本发明实施例三提供了一种阵列基板的制造方法。 该方法可包括： 在衬 底基板上形成栅线、 数据线、 薄膜晶体管、 像素电极、 树脂图形和与像素电 极形成多维电场的公共电极， 栅线和数据线限定出像素单元， 薄膜晶体管、 像素电极和公共电极位于像素单元内， 树脂图形位于数据线上方并覆盖数据 线。
图 4为本发明实施例三提供的阵列基板的制造方法的流程图， 图 5a-5g 为制造工艺过程中阵列基板的结构示意图。 下面， 将结合图 4以及图 5a-5g 对本实施例三提供的阵列基板的制造方法进行详细描述。 如图 4所示， 该方 法包括：
步骤 101、 在衬底基板上形成栅线和栅极， 栅极和栅线连接。
图 5a为实施例三中形成栅极的示意图。 如图 5a所示， 通过构图工艺在 衬底基板 10上同步形成栅线 11和栅极 17 , 栅极 17与栅线 11连接。 其中， 栅线 11可参见图 1中所示。
步骤 102、 在完成步骤 101的衬底基板上形成栅绝缘层， 栅绝缘层覆盖 衬底基板。
图 5b为实施例三中形成栅绝缘层的示意图。 如图 5b所示， 在完成步骤
101的衬底基板 10上涂布栅绝缘层 20,该栅绝缘层 20覆盖整个衬底基板 10。
步骤 103、 在栅绝缘层上形成有源层图形， 有源层图形位于栅极的上方。 图 5c为实施例三中形成有源层图形的示意图。 如图 5c所示， 通过构图 工艺在衬底基板 10上形成有源层 16, 该有源层 16位于栅极 17的上方。
步骤 104、 在完成步骤 103的衬底基板上形成数据线、 源极和漏极， 源 极的一端形成于有源层图形上， 源极的另一端形成于栅绝缘层上且与数据线 连接， 漏极的一端形成于有源层图形上， 漏极的另一端形成于栅绝缘层上。
图 5d为实施例三中形成源漏极图形的示意图。 如图 5d所示， 通过构图 工艺在完成步骤 103的衬底基板 10上形成数据线 12、源极 18和漏极 19,源 极 18的一端形成于有源层图形 16上， 源极 18的另一端形成于栅绝缘层 20 上且与数据线 12连接， 漏极 19的一端形成于有源层图形 16上， 漏极 19的 另一端形成于栅绝缘层 20上。
步骤 105、 在完成步骤 104的衬底基板上形成像素电极， 像素电极形成 于栅绝缘层上且像素电极的一端形成于漏极上。
图 5e为实施例三形成像素电极的示意图。 如图 5e所示， 通过构图工艺 在完成步骤 104的衬底基板 10上形成像素电极 13 ,像素电极 13形成于栅绝 缘层 20上且像素电极 13的一端形成于漏极 19上。
步骤 106、 在完成步骤 105的衬底基板上形成钝化层， 钝化层覆盖衬底 基板。
图 5f为实施例三中形成钝化层的示意图。如图 5f所示，在完成步骤 105 的衬底基板 10上涂布钝化层 21 , 该钝化层 21覆盖整个衬底基板 10上。
步骤 107、 在钝化层上形成树脂图形。
图 5g为实施例三中形成树脂图形的示意图。 如图 5g所示， 通过构图工 艺在钝化层 21上形成树脂图形 15 , 树脂图形 15位于数据线 12的上方。 例 如， 步骤 107可包括： 在钝化层上涂布树脂层以及在树脂层上涂布光刻胶； 通过对光刻胶进行掩膜板掩膜和曝光工艺， 将部分光刻胶曝光； 通过显影工 艺将已曝光的光刻胶去除； 通过刻蚀工艺将未被光刻胶覆盖的树脂层去除， 形成树脂图形； 剥离树脂图形上的未曝光的光刻胶。
树脂图形 15形成于数据线 12的上方并覆盖数据线 12, 优选地， 树脂图 形 15的宽度大于数据线 12的宽度。
步骤 108、 在完成步骤 107的衬底基板上形成公共电极。
如图 2所示，通过构图工艺在完成步骤 107的衬底基板 10上形成公共电 极 14。公共电极 14的一部分形成于钝化层 21上，一部分形成于树脂图形 15 上。
本实施例提供的阵列基板的制造方法可用于制造上述实施例一中所述的 阵列基板。
本实施例提供的阵列基板的制造方法中，仅在数据线上方形成树脂图形， 在像素电极和公共电极之间未形成树脂图形， 因此与传统技术相比减小了像 素电极和公共电极之间的距离， 从而提高了像素电极和公共电极之间的电场 效率。 本实施例中， 数据线和公共电极之间形成有树脂图形， 减小了数据线 和公共电极之间的寄生电容， 从而提高了像素单元的透光率。 本实施例中， 覆盖于数据线上方的公共电极可屏蔽来自于数据线的不利电场。
需要说明的是， 上面的描述主要针对单个像素单元进行， 其他像素单元 可以相同地形成。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板，该阵列基板包括衬底基板和形成于所述衬底基板上的 栅线和数据线， 所述栅线和所述数据线彼此交叉以限定像素单元， 像素单元 内形成有薄膜晶体管、 像素电极和公共电极，
其中， 所述数据线上方形成有覆盖所述数据线的树脂图形。
2、 根据权利要求 1所述的阵列基板， 其中所述薄膜晶体管包括有源层、 栅极、 源极和漏极；
所述栅线和所述栅极形成于所述衬底基板上， 栅绝缘层形成在所述衬底 基板上以覆盖所述栅线和所述栅极， 所述有源层形成于所述栅绝缘层上且位 于所述栅极的上方， 所述数据线形成于所述栅绝缘层上；
所述源极的一端形成于所述有源层图形上， 所述源极的另一端形成于所 述栅绝缘层上且与所述数据线连接；
所述漏极的一端形成于所述有源层图形上， 所述漏极的另一端形成于所 述栅绝缘层上。
3、根据权利要求 2所述的阵列基板，其中所述像素电极形成于所述栅绝 缘层上且所述像素电极的一端形成于所述漏极上， 所述像素电极上形成有钝 化层以覆盖所述衬底基板， 所述树脂图形形成于所述钝化层上。
4、根据权利要求 3所述的阵列基板，其中所述公共电极的一部分形成于 所述钝化层上， 另一部分形成于所述树脂图形上。
5、根据权利要求 1所述的阵列基板，其中所述树脂图形的宽度大于所述 数据线的宽度。
6、根据权利要求 1所述的阵列基板，其中所述树脂图形的横截面的形状 为半圓形。
7、根据权利要求 1所述的阵列基板，其中所述树脂图形由丙烯酸树脂或 者线性酚醛树脂形成。
8、根据权利要求 1所述的阵列基板，其中所述树脂图形仅形成在所述数 据线上方。
9、根据权利要求 1所述的阵列基板， 其中所述像素电极为板状电极，且 所述公共电极为狭缝电极。
10、 一种液晶显示面板， 其中包括对盒设置的对向基板和阵列基板以及 填充在所述对向基板和所述阵列基板之间的液晶层；
所述阵列基板釆用上述权利要求 1所述的阵列基板。
11、 一种阵列基板的制造方法， 其中包括：
在衬底基板上形成栅线、 数据线、 薄膜晶体管、 像素电极、 树脂图形和 公共电极， 所述栅线和所述数据线彼此交叉限定出像素单元， 所述薄膜晶体 管、 所述像素电极和所述公共电极位于所述像素单元内， 所述树脂图形位于 所述数据线上方并覆盖所述数据线。
12、 根据权利要求 11所述的阵列基板的制造方法， 其中所述方法包括： 在所述衬底基板上形成所述栅线和所述栅极，所述栅极和所述栅线连接； 在所述衬底基板上形成栅绝缘层， 所述栅绝缘层覆盖所述栅线和所述栅 极；
在所述栅绝缘层上形成所述有源层， 所述有源层位于所述栅极的上方； 形成所述数据线、 所述源极和所述漏极， 所述数据线形成于所述栅绝缘 层上， 所述源极的一端形成于有源层图形上， 所述源极的另一端形成于所述 栅绝缘层上且与所述数据线连接，所述漏极的一端形成于所述有源层图形上， 所述漏极的另一端形成于所述栅绝缘层上；
在所述栅绝缘层上形成所述像素电极， 且所述像素电极的一端形成于所 述漏极上；
在所述像素电极上形成钝化层， 所述钝化层覆盖所述衬底基板； 在所述钝化层上形成所述树脂图形；
在所述衬底基板上形成所述公共电极。
13、根据权利要求 12所述的阵列基板的制造方法，其中所述公共电极的 一部分形成于所述钝化层上， 另一部分形成于所述树脂图形上。
14、根据权利要求 11所述的阵列基板的制造方法，其中所述树脂图形形 成为仅位于所述数据线上方。
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CN101493593A (zh) * 2008-01-21 2009-07-29 精工爱普生株式会社 电光学装置、电光学装置的制造方法及电子设备
JP2010145449A (ja) * 2008-12-16 2010-07-01 Epson Imaging Devices Corp 液晶表示装置及びその製造方法
CN202183002U (zh) * 2011-06-29 2012-04-04 北京京东方光电科技有限公司 阵列基板及液晶显示器件
CN102681277A (zh) * 2012-04-16 2012-09-19 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示面板

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