WO2013166831A1 - 薄膜晶体管阵列基板及制作方法和显示装置 - Google Patents

薄膜晶体管阵列基板及制作方法和显示装置 Download PDF

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Publication number
WO2013166831A1
WO2013166831A1 PCT/CN2012/086307 CN2012086307W WO2013166831A1 WO 2013166831 A1 WO2013166831 A1 WO 2013166831A1 CN 2012086307 W CN2012086307 W CN 2012086307W WO 2013166831 A1 WO2013166831 A1 WO 2013166831A1
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Prior art keywords
passivation layer
via hole
substrate
electrode
pixel
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PCT/CN2012/086307
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English (en)
French (fr)
Inventor
李田生
张文余
谢振宇
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北京京东方光电科技有限公司
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Priority to US13/993,666 priority Critical patent/US9530807B2/en
Publication of WO2013166831A1 publication Critical patent/WO2013166831A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode

Definitions

  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • ADSDS Advanced Super-Dimensional Field Switching
  • IPS In-plane Switching
  • the ADS technology forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be The rotation is generated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the existing HADS type TFT-LCD array substrate structure mainly includes: a substrate 1 , a gate scan line 13 , a thin film transistor (TFT) switch, and a data line 14 .
  • the pixel electrode 7 (corresponding to a plate electrode), the flat wiring PAD region 10, the via hole 11 and the common electrode 9 (corresponding to a slit electrode).
  • the TFT-LCD array substrate is completed by a plurality of patterning processes, and each of the patterning processes includes a process of masking, exposing, developing, etching, and stripping, and the specific manufacturing method includes: forming on the substrate 1. a pattern of the gate electrode 2 and the gate scan line 13; a gate insulating layer 3 is formed on the gate electrode 2 and the gate scan line 13, and a pattern of the active layer 4 is formed on the gate insulating layer 3; The electrode 7, the source 5, the drain 6 and the data line 14, and the drain 6 is in direct contact with the pixel electrode 7; a passivation layer 8 is deposited on the above pattern, and formed on the flat wiring PAD region 10 by a patterning process a pattern of holes 11; depositing a common electrode metal, and constructing The patterning process forms a pattern of a common electrode 9 of a comb-like slim structure.
  • wet etching is generally employed.
  • the etching solution may not completely etch away the metal portion of the ITO electrode that is not covered with the photoresist, and eventually the electrode remains. Uniform comb electrode patterns cannot be formed, resulting in uneven display, which seriously affects the yield and cost of the array substrate. Summary of the invention
  • An embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, including: forming a first blunt on a substrate on which a gate scan line, a thin film transistor switch, a data line, a first display electrode, and a flat panel PAD region are formed And forming a flat wiring PAD region via hole in the first passivation layer above the flat wiring PAD region by a first patterning process; forming a second blunt on the substrate on which the via wiring PAD region via is formed And forming a pixel via hole in the first passivation layer and the second passivation layer above the pixel electrode by a second patterning process, such that a top size of the pixel region via hole is smaller than a bottom portion thereof; And covering the transparent conductive layer on the substrate on which the via hole of the pixel region is formed to form a second display electrode.
  • a thin film transistor array substrate including: a substrate; a gate scan line formed on the substrate, a thin film transistor switch, a data line, a pixel electrode, a common electrode, a flat wiring PAD area, and a PAD a via hole, wherein the passivation layer between the pixel electrode and the common electrode has a pixel via hole, wherein the passivation layer includes a first passivation layer and a second passivation layer, and the pixel The top size of the via is smaller than the bottom size.
  • Still another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
  • FIG. 1( a ) is a schematic structural view of an array substrate in the prior art
  • Figure 1 (b) is a cross-sectional view of the direction of Figure 1 (a);
  • 2 is a schematic diagram of a via hole formed by dry etching a first passivation layer according to an embodiment of the present invention;
  • FIG. 3 is a schematic diagram of a via hole formed by dry etching a second passivation layer and a first passivation layer according to an embodiment of the present invention; schematic diagram;
  • FIG. 4(a) is a schematic view showing a substrate including a gate scan line pattern in a specific embodiment of the present invention
  • FIG. 4(b) is a cross-sectional view of the direction of FIG. 4(a);
  • Figure 5 (a) is a schematic view showing a substrate including an active layer pattern in a specific embodiment of the present invention
  • Figure 5 (b) is a cross-sectional view in the direction of Figure 5 (a);
  • FIG. 6(a) is a schematic view showing a substrate including a pixel electrode pattern in a specific embodiment of the present invention
  • FIG. 6(b) is a cross-sectional view in the direction of FIG. 6(a);
  • Figure 7 (a) is a schematic view showing a substrate including a data line pattern in a specific embodiment of the present invention
  • Figure 7 (b) is a cross-sectional view in the direction of Figure 7 (a);
  • Figure 8 (a) is a schematic view showing the formation of a substrate including a via pattern of a PAD region in a specific embodiment of the present invention
  • Figure 8 (b) is a cross-sectional view in the direction of Figure 8 (a);
  • FIG. 9(a) is a schematic view showing a substrate including a via pattern of a pixel region in a specific embodiment of the present invention
  • FIG. 9(b) is a cross-sectional view in the direction of FIG. 9(a);
  • Figure 10 (a) is a schematic view showing a substrate including a common electrode pattern in a specific embodiment of the present invention
  • Figure 10 (b) is a cross-sectional view taken along the line of Figure 10 (a).
  • the first substrate is formed after the substrate including the gate scan line, the thin film transistor (TFT) switch, the data line, the pixel electrode, and the flat wiring PAD area is completed.
  • TFT thin film transistor
  • a process for fabricating a TFT array substrate includes:
  • Step 201 fabricating a substrate including a gate scan line, a thin film transistor TFT switch, a data line, a pixel electrode, and a flat wiring PAD area.
  • the substrate including the pattern of the gate scan line, the thin film transistor switch, the data line, the pixel electrode, and the flat wiring PAD region may be fabricated using a plurality of patterning processes.
  • Solution 1 Sl, forming a gate of the TFT switch on the base substrate, a gate scan line, and a pattern of the PAD area of the flat wiring.
  • a gate metal layer may be deposited, coated, or sputtered on the substrate, and then patterned, ie, coated with a photoresist, exposed and developed with a mask, and then etched, and finally stripped.
  • the glue is formed into a gate, a gate scan line, and a pattern of the flat wiring PAD area.
  • a pixel electrode metal layer is deposited, coated, or sputtered on the active layer substrate, and a pattern of the pixel electrode is formed by a patterning process.
  • a data line metal layer is deposited or sputtered on a substrate including a pixel electrode, and a source, a drain, and a TFT channel forming a TFT switch, and a pattern of a data line are formed by a patterning process.
  • Solution 2 forming a gate of the TFT switch, a gate scan line, and a pattern of the flat wiring PAD region on the base substrate; forming a source of the active layer and the TFT switch on the substrate including the gate scan line pattern a pattern of a drain electrode, a drain and a TFT channel, and a data line; a pattern of a pixel electrode formed on a substrate including the data line pattern.
  • the specific process in the scheme can also be completed by a patterning process. The details are no longer exhausted.
  • the fabrication of the body tube TFT switch, the data line, the pixel electrode, and the substrate of the flat wiring PAD area pattern are examples of the body tube TFT switch, the data line, the pixel electrode, and the substrate of the flat wiring PAD area pattern.
  • Step 202 Form a first passivation layer on the substrate, and form a via of the flat wiring PAD region by the first patterning process.
  • the first patterning process specifically includes: coating a photoresist on the first passivation layer, performing exposure by using the first mask, performing development processing, and etching the first blunt uncovered photoresist by dry etching
  • the layer is formed to form a via of the PAD region of the flat panel wiring.
  • the PAD region via hole is an inverted trapezoidal via having an opening larger than the bottom edge.
  • Dry etching is a technique of performing plasma etching using plasma. This type of etching is a combination of physical etching and chemical etching. The physical etching is biased in the vertical direction, and the chemical etching is biased in the lateral etching. As shown in FIG. 2, the first passivation layer is coated.
  • the photoresist is exposed by the first mask and subjected to development processing, and the first passivation layer of the uncovered photoresist is etched by dry etching, because the first passivation layer and the plasma of the point A are
  • the contact time of the body is longer than the contact time of the first passivation layer at point B with the plasma, so that the passivation layer will be retracted laterally due to the chemical etching, and finally an inverted trapezoidal PAD as shown in FIG. 2 is formed.
  • Zone via, the PAD zone via opening is larger than the bottom edge. That is, the cross section of the PAD region via hole taken in a direction perpendicular to the surface of the substrate is an inverted trapezoidal shape in which the upper bottom is larger than the lower bottom.
  • Step 203 forming a second passivation layer on the substrate forming the via of the flat wiring PAD region, and forming a via hole of the pixel region by a second patterning process.
  • the second passivation layer is denser than the film layer of the first passivation layer, and the chemical vapor deposition method is taken as an example.
  • the process temperature for forming the second passivation layer is lower than the process temperature for forming the first passivation layer, that is, The formation process temperature of the second passivation layer is lower than the formation process temperature of the first passivation layer. Therefore, the second passivation layer is relatively dense, that is, the material density of the second passivation layer is greater than the material density of the first passivation layer. Thereby, the etching rate of the second passivation layer is smaller than the etching rate of the first passivation layer.
  • other process parameters, such as pressure, or a cost ratio of the passivation layer may be changed to make the etching rate of the second passivation layer smaller than the etching rate of the first passivation layer.
  • the specific process includes: coating a photoresist on the second passivation layer, performing exposure by using a second mask, and performing development processing; etching the second blunt without covering the photoresist by dry etching
  • the layer and the underlying first passivation layer form a via hole in the pixel region.
  • the depth of the via hole of the pixel region is less than or equal to the thickness of the sum of the first passivation layer and the second passivation layer.
  • the opening of the pixel area via is smaller than the bottom side.
  • the passivation layer includes a first passivation layer and a second passivation layer having a plurality of positive trapezoidal pixel vias on the passivation layer. That is to say, the top size of the pixel area via is smaller than the bottom size.
  • the pixel region via holes are in a strip shape extending at least in one direction as viewed in a plan view.
  • the pixel region via holes herein are slit structures for forming a common electrode formed above. Therefore, the pixel region via is disposed corresponding to the slit structure of the upper common electrode.
  • the strip shape of the pixel region via holes may extend in one direction, two directions or more to form a slit structure extending in the corresponding direction.
  • the cross-sectional shape of the pixel region via hole perpendicular to the extending direction of the strip shape is a positive trapezoidal shape whose upper base is smaller than the lower bottom.
  • the second passivation layer in the via hole of the PAD region also needs to be etched, because only the second passivation layer and the gate insulating layer are in the via hole of the PAD region, due to the second passivation
  • the layer is relatively thin relative to the first passivation layer, the thickness of the first passivation layer is generally 200-900 nm, and the thickness of the second passivation layer is generally 5-100 nm, so that a via hole of a positive trapezoid is not formed, PAD
  • the via hole of the inverted trapezoid is not problematic for the subsequent formation of the common electrode ITO film.
  • Step 204 Cover the transparent conductive layer on the substrate forming the via hole of the pixel region to form a common electrode.
  • the via hole in the pixel region on the passivation layer is a positive trapezoid, and the opening is smaller than the bottom edge.
  • the common electrode can be directly formed, without The composition process was carried out.
  • a transparent conductive layer may be deposited, coated, or sputtered on the passivation layer to form a common electrode.
  • the transparent conductive layer is broken at the via hole of the pixel region to form a common electrode having a slit structure.
  • the slit structure is disposed corresponding to the pixel via hole.
  • the array substrate can be formed, and the array substrate includes:
  • a gate scan line a thin film transistor TFT switch, a data line, a pixel electrode, a common electrode, a flat panel wiring PAD region, and a PAD region via hole, wherein
  • a passivation layer between the pixel electrode and the common electrode has a pixel via hole
  • the passivation layer comprises: a first passivation layer and a second passivation layer, wherein the pixel region via hole is a positive trapezoid having an opening smaller than a bottom edge hole.
  • the gate metal layer may be a single layer film of AlNd, Al, Cu, Mo, MoW or Cr, or a composite of one or any combination of AlNd, Al, Cu, Mo, MoW or Cr. a film; the gate insulating layer may specifically be a single layer film of SiNx, SiOx or SiOxNy or A composite film composed of one or any combination of SiNx, SiOx or SiOxNy.
  • the data line metal layer may specifically be a single layer film of Mo, MoW or Cr or a composite film composed of one or any combination of Mo, MoW or Cr; the passivation layer is composed of one or any combination of SiNx, SiOx or SiOxNy.
  • the pixel electrode and the common electrode metal layer may be a composite film composed of one or a combination of ⁇ 0, ⁇ .
  • a patterning process is added, a pixel via hole is formed on the passivation layer, and then a common electrode metal layer is formed, and a patterning process is not required to directly form the common electrode. Therefore, compared with the prior art, there is no increase in the number of patterning processes, that is, the process cost is not increased.
  • the passivation layer is formed with the via hole of the pixel region, and the etch rate of the second passivation layer is smaller than the etch rate of the first passivation layer, the pixel region via hole of the positive trapezoid is formed, thereby not generating a common
  • the residue of the electrode facilitates process control and ultimately improves product quality.
  • the depth of the via hole of the pixel region is less than or equal to the thickness of the sum of the first passivation layer and the second passivation layer. That is, the depth of the via hole of the pixel region is less than or equal to the thickness of the passivation layer.
  • a part of the deposited pixel electrode metal layer directly covers the pixel electrode.
  • it is also advantageous to reduce the sheet resistance of the pixel electrode which is advantageous for improving the screen product.
  • the drain of the TFT switch is located above the first pixel electrode, and the depth of the via hole of the pixel region is equal to the thickness of the passivation layer.
  • the fabrication process of the array substrate includes:
  • Step 501 depositing a gate metal layer on the substrate 1, and forming a gate 2 of the TFT switch, a gate scan line 13, and a pattern of the flat wiring PAD region 10 by a patterning process.
  • Step 502 depositing a gate insulating layer 3, an active layer on the substrate 1 including the gate scanning line 13, and forming the active layer 4 by a patterning process.
  • Step 503 depositing a pixel electrode metal layer on the substrate 1 including the active layer 4, and forming a pixel electrode 7 by a patterning process.
  • Step 504 depositing a data line metal layer on the substrate 1 including the pixel electrode 7, and forming a source 5, a drain 6 and a TFT channel 12 of the TFT switch, and a data line 14 by a patterning process.
  • the resulting pattern is shown in Figure 7 (a), and the - direction cross section is shown in Figure 7 (b).
  • Step 505 depositing a first passivation layer 8 on the substrate 1 including the data line 14 to form a flat wiring PAD region via hole 11 by a patterning process.
  • the resulting pattern is shown in Figure 8 (a), and the cross section is shown in Figure 8 (b).
  • dry etching is used, and the formed via hole 11 of the PAD region is an inverted trapezoidal structure, and the opening is larger than the bottom edge.
  • Step 506 depositing a second passivation layer 16 on the substrate 1 including the PAD region via 11 to form a pixel region via 15 by a patterning process.
  • the temperature at which the second passivation layer 16 is deposited is lower than the temperature at which the first passivation layer 8 is deposited, such that the etching rate of the second passivation layer is less than the first passivation during the patterning process for dry etching.
  • the etch rate of the layer is shown in Figure 9 (a), and the cross section is shown in Figure 9 (b).
  • the pixel region via 15 has a positive trapezoidal structure with an opening smaller than the bottom edge.
  • the depth of the via 15 is equal to the thickness of the passivation layer, that is, the sum of the thicknesses of the first passivation layer 8 and the second passivation layer 16 is equal to the thickness of the via hole 15 of the pixel region;
  • the second passivation layer 16 also needs to be etched. Since the second passivation layer 16 and the gate insulating layer 3 are only in the via hole of the PAD region, since the second passivation 16 is thin relative to the first passivation layer 8, it will not A via hole having a trapezoidal shape is formed, and a via hole of an inverted trapezoid in the PAD region does not cause a problem of disconnection when a common electrode ITO film is formed.
  • Step 507 A transparent conductive layer is formed on the substrate 1 forming the pixel via 15 to form the common electrode 9.
  • the formed array substrate is different from the existing array substrate.
  • the passivation layer of the array substrate has pixel vias 15 on the passivation layer.
  • the electrode 9 covers the entire substrate, but since the passivation layer is segmented, the residual of the common electrode 9 is not caused, and the yield of the array substrate is improved.
  • the sum of the thicknesses of the first passivation layer 8 and the second passivation layer 16 is equal to the thickness of the via hole 15 of the pixel region, since the pixel electrode at the via hole is covered when the common electrode is formed.
  • the layer is transparent and conductive, and therefore, it is advantageous to reduce the sheet resistance of the pixel electrode 7, which is advantageous for improving picture quality.
  • the array substrate in the embodiment of the present invention can be applied to a thin film transistor display device.
  • the display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a first passivation layer is formed on a substrate on which a pattern of a gate scan line, a thin film transistor TFT switch, a data line, a pixel electrode, and a flat wiring PAD region has been formed, and a flat plate is formed by a first patterning process.
  • the via hole forms a transparent conductive layer on the substrate forming the via hole of the pixel region to form a common electrode, thereby completing the array substrate. Since the passivation layer is formed with a gap, and the thickness of the passivation layer is generally about ten times that of the pixel electrode, after the via hole of the positive trapezoid is formed, the high gap of the passivation layer ensures that the common electrode does not remain. , which is conducive to process control and ultimately improves product quality.
  • the depth of the via hole of the pixel region is equal to the thickness of the passivation layer, a part of the deposited metal layer of the pixel electrode directly covers the pixel electrode, which is also beneficial for reducing the sheet resistance of the pixel electrode, thereby improving the picture. quality.
  • the display electrode under the passivation layer may also be a common electrode, and the electrode above the passivation layer. It can also be a pixel electrode. At this time, it is only necessary to change the connection relationship between the upper electrode and the lower electrode and the thin film transistor and the flat wiring PAD area, and details are not described herein again.

Abstract

提供一种薄膜晶体管阵列基板及其制作方法和显示装置。其制作方法包括：在基板（1）上形成第一钝化层（8），并通过第一构图工艺在平板接线PAD区（10）上方的第一钝化层（8）中形成平板接线PAD区过孔（11）；在形成有平板接线PAD区过孔（11）的基板（1）上形成第二钝化层（16），通过第二构图工艺在像素电极（7）上方的第一钝化层（8）和第二钝化层（16）中形成像素区过孔（15），以使得像素区过孔（15）的顶部尺寸小于底部尺寸；以及在形成有像素区过孔（15）的基板（1）上覆盖透明导电层，以形成第二显示电极。

Description

薄膜晶体管阵列基板及制作方法和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板及制作方法和显示装置。 背景技术
近年来， 随着科学技术的进步， 数字化电视开始走进日常生活中。 薄膜 晶体管液晶显示器 ( Thin Firm Transistor Liquid Crystal Display , TFT-LCD ) 以其体积小， 功耗低， 无辐射， 分辨率高等优点成为了目前的主导产品。
目前， 广视角高透过率的平面显示技术包括： 高级超维场转换技术 ( ADSDS, ADvanced Super Dimension Switch , 简称 ADS )与平面开关技术 ( In-plane Switching, IPS ) 。 ADS技术通过同一平面内狭缝电极边缘所产生 的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场， 使液晶盒 内狭缝电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了 液晶工作效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD 产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋（push Mura )等优点。
作为 ADS技术的改进技术， HADS (高透过率 -高级超维场转换）技术 具有更高的光透过率， 对比度与视角， 因此， HADS技术具有非常广阔的前 景。 如图 1 ( a )和图 1 ( b )所示， 现有的 HADS型的 TFT-LCD阵列基板结 构主要包括： 基板 1 , 栅极扫描线 13 , 薄膜晶体管（TFT )开关， 数据线 14, 像素电极 7(相当于板状电极)， 平板接线 PAD区 10, 过孔 11和公共电极 9 (相当于狭缝电极） 。 该 TFT-LCD阵列基板是通过多次构图工艺来完成， 每一次构图工艺中有分别包括： 掩模、 曝光、 显影、 刻蚀和剥离等工艺， 其 具体的制造方法包括：在基板 1上形成栅极 2和栅极扫描线 13的图案；在栅 极 2和栅极扫描线 13上形成栅极绝缘层 3 ,并在栅极绝缘层 3上形成有源层 4的图案； 再依次形成像素电极 7、 源极 5、 漏极 6和数据线 14, 且漏极 6 与像素电极 7直接接触； 在上述图案上沉积层钝化层 8, 并通过构图工艺形 成平板接线 PAD区 10上的过孔 11的图案； 沉积公共电极金属， 并通过构 图工艺形成梳状狭长（slim )结构的公共电极 9的图案。
在通过构图工艺形成梳状狭长结构 （即狭缝结构） 的公共电极 9的图案 的过程中， 一般釆用湿法刻蚀。 这样， 由于沉积的 ITO电极金属较厚或衬底 不良等因素的影响， 可能会导致刻蚀液不能完全刻蚀掉未覆盖光刻胶的 ITO 电极金属部分， 最终导致电极残留。 无法形成均匀的梳状电极图案， 从而使 画面显示不均匀， 严重影响了阵列基板的良品率和成本。 发明内容
本发明的一个实施例提供一种薄膜晶体管阵列基板的制作方法， 包括： 在形成有栅极扫描线、 薄膜晶体管开关、 数据线、 第一显示电极以及平板接 线 PAD 区的基板上形成第一钝化层， 并通过第一构图工艺在所述平板接线 PAD区上方的第一钝化层中形成平板接线 PAD区过孔； 在形成有所述平板 接线 PAD 区过孔的基板上形成第二钝化层， 并通过第二构图工艺在所述像 素电极上方的第一钝化层和第二钝化层中形成像素区过孔， 以使得所述像素 区过孔的顶部尺寸小于其底部尺寸； 以及在形成有所述像素区过孔的基板上 覆盖透明导电层， 以形成第二显示电极。
本发明的另一个实施例提供一种薄膜晶体管阵列基板， 包括： 基板； 形 成于所述基板上的栅极扫描线、 薄膜晶体管开关、 数据线、 像素电极、 公共 电极、 平板接线 PAD区以及 PAD区过孔， 其中所述像素电极与所述公共电 极之间的钝化层中有像素区过孔， 其中所述钝化层包括第一钝化层和第二钝 化层， 且所述像素区过孔的顶部尺寸小于其底部尺寸。
本发明的再一个实施例提供一种显示装置， 包括根据本发明任一实施例 的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1 ( a )为现有技术中阵列基板的结构示意图；
图 1 ( b )为图 1 ( a ) 的 向的截面图； 图 2为本发明实施例中干法刻蚀第一钝化层形成的过孔示意图； 图 3为本发明实施例中干法刻蚀第二钝化层以及第一钝化层形成的过孔 示意图；
图 4 ( a )为本发明具体实施例中形成包括栅极扫描线图形的基板示意图； 图 4 (b)为图 4 (a) 的 向的截面图；
图 5 (a)为本发明具体实施例中形成包括有源层图形的基板示意图； 图 5 (b)为图 5 (a) 的 - 方向的截面图；
图 6 (a)为本发明具体实施例中形成包括像素电极图形的基板示意图； 图 6 (b)为图 6 (a) 的 - 方向的截面图；
图 7 (a)为本发明具体实施例中形成包括数据线图形的基板示意图； 图 7 (b)为图 7 (a) 的 - 方向的截面图；
图 8 (a)为本发明具体实施例中形成包括 PAD区过孔图形的基板示意 图；
图 8 (b)为图 8 (a) 的 - 方向的截面图；
图 9(a)为本发明具体实施例中形成包括像素区过孔图形的基板示意图； 图 9 (b)为图 9 (a) 的 - 方向的截面图；
图 10 (a)为本发明具体实施例中形成包括公共电极图形的基板示意图； 图 10 (b)为图 10 (a) 的 向的截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例中， 制作 TFT-LCD阵列基板时， 在完成了包括栅极扫描 线， 薄膜晶体管（TFT)开关， 数据线， 像素电极， 以及平板接线 PAD区的 图形的基板后， 形成第一钝化层， 并通过第一构图工艺在 PAD 区上形成的 PAD区过孔， 然后继续形成第二钝化层， 并通过第二构图工艺形成开口小于 底边的正梯形的像素区过孔， 最后， 直接覆盖透明导电层， 利用正梯形的像 素区过孔的断差自然形成梳状狭长结构的公共电极， 这样， 像素电极与公共 电极之间的钝化层上有像素区过孔， 由于这些像素区过孔是正梯形的， 其开 口小于底边， 因此， 不会导致像素电极残留， 提高了阵列基板的良品率。
参见图 2, 本发明实施例中， TFT阵列基板的制作过程包括：
步骤 201: 制作包括栅极扫描线， 薄膜晶体管 TFT开关， 数据线， 像素 电极， 以及平板接线 PAD区的图形的基板。
这里， 可以利用多次构图工艺制作所述包含有栅极扫描线， 薄膜晶体管 开关， 数据线， 像素电极， 以及平板接线 PAD区的图形的基板。
方案一： Sl、 在衬底基板上形成 TFT开关的栅极， 栅极扫描线， 以及平 板接线 PAD区的图形。
这里， 可在衬底基板上沉积、 涂覆、 或溅射形成一层栅极金属层， 然后 通过构图工艺， 即涂覆光刻胶、 用掩模板进行曝光显影后进行刻蚀， 最后剥 离光刻胶形成栅极， 栅极扫描线， 以及平板接线 PAD区的图形。
S2、 在包括栅极扫描线图形的基板上形成有源层的图形。
在包括栅极扫描线的基板上沉积、 涂覆、 或氧化形成栅极绝缘层以及有 源层， 通过构图工艺， 即涂覆光刻胶、 用掩模板进行曝光显影后进行刻蚀， 最后剥离光刻胶形成有源层的图形。
53、 在包括有源层图形的基板上形成像素电极的图形。
在包括有源层基板上沉积、 涂覆、 或溅射形成像素电极金属层， 通过构 图工艺形成像素电极的图形。
54、 在包括像素电极图形的基板上形成 TFT开关的源极、 漏极和 TFT 沟道， 以及数据线的图形。
即在包括像素电极的基板上沉积或溅射形成数据线金属层， 通过构图工 艺形成形成 TFT开关的源极、 漏极和 TFT沟道， 以及数据线的图形。
方案二： 在衬底基板上形成 TFT开关的栅极， 栅极扫描线， 以及平板接 线 PAD 区的图形； 在包括在形成有栅极扫描线图形的基板上形成有源层、 TFT开关的源极、 漏极和 TFT沟道， 以及数据线的图形； 在包括数据线图形 的基板上形成像素电极的图形。 该方案中的具体工艺也可通过构图工艺来完 成。 具体就不再累述了。 体管 TFT开关， 数据线， 像素电极， 以及平板接线 PAD区图形的基板的制 作。
步骤 202: 在基板上形成第一钝化层， 并通过第一构图工艺形成平板接 线 PAD区过孔。
第一构图工艺具体包括： 在第一钝化层上涂覆光刻胶， 利用第一掩模板 进行曝光， 并进行显影处理， 利用干法刻蚀， 刻蚀未覆盖光刻胶的第一钝化 层， 形成平板接线 PAD区过孔。
本发明实施例中，较佳地， PAD区过孔为开口大于底边的倒梯形的过孔。 干法刻蚀是用等离子体进行薄膜刻蚀的技术。 此种形式的刻蚀是物理刻 蚀和化学刻蚀相结合的方式， 物理刻蚀偏重垂直方向， 而化学刻蚀偏重横向 刻蚀，如图 2所示， 在第一钝化层上涂覆光刻胶， 利用第一掩模板进行曝光， 并进行显影处理后， 利用干法刻蚀， 刻蚀未覆盖光刻胶的第一钝化层时， 由 于 A点的第一钝化层与等离子体的接触时间比 B点的第一钝化层与等离子体 接触的时间长， 这样由于化学刻蚀的作用钝化层会向横向缩进， 最终会形成 如图 2所示的倒梯形的 PAD区过孔， 该 PAD区过孔开口大于底边。 也就是 说， PAD区过孔沿垂直于基板表面的方向剖取的截面为上底大于下底的倒梯 形形状。
步骤 203: 在形成平板接线 PAD区过孔的基板上形成第二钝化层， 并通 过第二构图工艺形成像素区过孔。
这里， 第二钝化层比第一钝化层的膜层致密， 以化学气相沉积方法为例 进行说明， 形成第二钝化层的工艺温度低于形成第一钝化层的工艺温度， 即 第二钝化层的形成工艺温度低于第一钝化层的形成工艺温度， 因此， 第二钝 化层比较致密， 即第二钝化层的材质密度大于第一钝化层的材质密度，从而， 第二钝化层的刻蚀速率小于第一钝化层的刻蚀速率。 当然， 也可以改变别的 工艺参数， 例如， 压力， 或者， 钝化层的成本比例， 可使得第二钝化层的刻 蚀速率小于第一钝化层的刻蚀速率。
这样， 具体的过程包括： 在第二钝化层上涂覆光刻胶， 利用第二掩模板 进行曝光， 并进行显影处理； 利用干法刻蚀， 刻蚀未覆盖光刻胶的第二钝化 层和下方的第一钝化层， 形成像素区过孔。 一般， 像素区过孔的深度小于或 等于第一钝化层与第二钝化层之和的厚度。 如图 3所示， 进行干法刻蚀时， C点的刻蚀速率最小， 刻蚀速率大小为 C<A=B, 由于 C点刻蚀速率慢而 A 点和 B点刻蚀速率相对较快而最终出现正梯形的像素区过孔， 该像素区过孔 的开口小于底边。
该钝化层包括第一钝化层和第二钝化层， 在钝化层上有多个正梯形的像 素区过孔。也就是说，像素区过孔的顶部尺寸小于其底部尺寸。 结合图 9 ( a ) 和图 9 ( b )可以看到， 在平面图中看， 像素区过孔呈至少沿一个方向延伸的 条形。 从下文可以知道， 这里的像素区过孔是为了形成在上方形成的公共电 极的狭缝结构。 因此， 像素区过孔与上方的公共电极的狭缝结构对应设置。 因此， 像素区过孔的条形可以沿一个方向、 两个方向或更多个方向延伸， 以 形成沿对应方向延伸的狭缝结构。 从图 9 ( b )可以看到， 像素区过孔的垂直 于条形的延伸方向的截面形状为上底小于下底的正梯形形状。
在刻蚀形成像素区过孔时， 对 PAD 区过孔中的第二钝化层也需进行刻 蚀， 由于 PAD 区过孔中只有第二钝化层和栅绝缘层， 由于第二钝化层相对 于第一钝化层较薄， 第一钝化层的厚度一般在 200-900纳米， 第二钝化层的 厚度一般在 5-100纳米， 因此不会形成正梯形的过孔， PAD区倒梯形的过孔 对于后续形成公共电极 ITO薄膜时， 不会出现断线的问题。
步骤 204: 在形成像素区过孔的基板上覆盖透明导电层， 形成公共电极。 钝化层上的像素区过孔是正梯形的， 其开口小于底边， 这样， 由像素区 过孔形成的有段差的钝化层上覆盖透明导电层后， 就可直接形成公共电极， 不需进行构图工艺了。 具体可在钝化层上沉积、 涂覆、 或溅射透明导电层， 形成公共电极。 如图 10 ( b )所示， 透明导电层在像素区过孔处断开， 以形 成具有狭缝结构的公共电极。 并且， 狭缝结构与像素区过孔对应设置。
通过上述过程， 即可形成阵列基板， 该阵列基板包括：
栅极扫描线， 薄膜晶体管 TFT开关， 数据线， 像素电极， 公共电极， 平 板接线 PAD区 , 以及 PAD区过孔， 其中 ,
像素电极与公共电极之间的钝化层上有像素区过孔，其中，钝化层包括： 第一钝化层和第二钝化层， 像素区过孔为开口小于底边的正梯形过孔。
本发明实施例中， 栅金属层具体可以为 AlNd、 Al、 Cu、 Mo、 MoW 或 Cr的单层膜， 或者为 AlNd、 Al、 Cu、 Mo、 MoW或 Cr之一或任意组 合所构成的复合膜； 栅绝缘层具体可以为 SiNx、 SiOx或 SiOxNy的单层膜或 者 SiNx、 SiOx或 SiOxNy之一或任意组合所构成的复合膜。 数据线金属层 具体可以为 Mo、 MoW或 Cr的单层膜或 Mo、 MoW或 Cr之一或任意组合所 构成的复合膜； 钝化层为 SiNx、 SiOx或 SiOxNy之一或任意组合所构成的 复合膜。 像素电极和公共电极金属层可以为 ΙΤ0、 ΙΖΟ之一或组合所构成的 复合膜。
根据上述制作过程可知， 在形成了 PAD 区过孔后， 增加了一次构图工 艺， 在钝化层上形成像素区过孔， 然后， 形成公共电极金属层， 不需要构图 工艺， 直接形成公共电极。 因此， 与现有技术相比， 没有增加构图工艺的次 数， 即不会增加工艺成本。 但是由于形成有像素区过孔的钝化层， 并由于第 二钝化层的刻蚀速率小于第一钝化层的刻蚀速率形成的正梯形的像素区过 孔， 从而， 不会产生公共电极的残留， 利于工艺管控， 最终提高了产品质量。
由于像素区过孔的深度小于或等于第一钝化层与第二钝化层之和的厚 度。 即像素区过孔的深度小于或等于钝化层的厚度， 较佳地， 当像素区过孔 的深度等于钝化层的厚度时， 沉积的像素电极金属层， 有一部分会直接覆盖 在像素电极上， 这样还有利于减小像素电极的方块电阻， 有利于改善画面品 下面结合说明书附图对本发明实施例作进一步详细描述。
本实施例中， TFT开关的漏极位于第一像素电极的上方， 并且， 像素区 过孔的深度等于钝化层的厚度。 阵列基板的制作过程包括：
步骤 501 : 在基板 1上沉积积栅金属层， 通过构图工艺， 形成 TFT开关 的栅极 2, 栅极扫描线 13 , 以及平板接线 PAD区 10的图形。
形成的图形如图 4 ( a )所示， - 方向的截面如图 4 ( b )所示。
步骤 502: 在包括栅极扫描线 13的基板 1上沉积栅绝缘层 3、 有源层， 通过构图工艺形成有源层 4。
形成的图形如图 5 ( a )所示， - 方向的截面如图 5 ( b )所示。
步骤 503: 在包括有源层 4的基板 1上沉积像素电极金属层， 通过构图 工艺， 形成像素电极 7。
形成的图形如图 6 ( a )所示， - 方向的截面如图 6 ( b )所示。
步骤 504: 在包括像素电极 7的基板 1上沉积数据线金属层， 通过构图 工艺， 形成 TFT开关的源极 5、 漏极 6和 TFT沟道 12 , 以及数据线 14。 形成的图形如图 7 (a)所示， - 方向的截面如图 7 (b)所示。
步骤 505: 在包括数据线 14的基板 1上沉积第一钝化层 8, 通过构图工 艺形成平板接线 PAD区过孔 11。
形成的图形如图 8 (a)所示， 向的截面如图 8 (b)所示。 本次 构图工艺中釆用干法刻蚀， 形成的 PAD区过孔 11为倒梯形的结构， 其开口 大于底边。
步骤 506: 在包括 PAD区过孔 11基板 1上沉积第二钝化层 16, 通过构 图工艺形成像素区过孔 15。
沉积第二钝化层 16时的温度要低于沉积第一钝化层 8时的温度， 这样， 在构图工艺进行干法刻蚀时， 第二钝化层的刻蚀速率小于第一钝化层的刻蚀 速率。 从而形成的图形如图 9 (a)所示， 向的截面如图 9 (b)所示。 像素区过孔 15为正梯形的结构， 其开口小于底边。 并且， 该过孔 15的深度 等于钝化层的厚度，即第一钝化层 8和第二钝化层 16的厚度之和等于像素区 过孔 15的厚度； 同时对 PAD区过孔中的第二钝化层 16也需进行刻蚀， 由 于 PAD区过孔中只有第二钝化层 16和栅绝缘层 3, 由于第二钝化 16相对于 第一钝化层 8较薄， 不会形成正梯形的过孔， PAD区倒梯形的过孔对于后续 形成公共电极 ITO薄膜时， 不会出现断线的问题。
步骤 507: 在形成像素区过孔 15的基板 1上形成透明导电层， 形成公共 电极 9。
由于正梯形结构的像素区过孔 15, 使得钝化层分段了， 这样沉积像素电 极金属层， 就可直接形成公共电极 9。 形成的图形如图 10 (a)所示， A-Ai 方向的截面如图 10 (b)所示。
由图 10 (a)和图 10 (b)所示， 形成的阵列基板与现有的阵列基板有不 同之处， 本实施例中的阵列基板的钝化层上有像素区过孔 15, 公共电极 9覆 盖了整个基板，但是由于钝化层分段了， 因此， 不会造成公共电极 9的残留， 提高了阵列基板的良品率。
并且，本实施例中，第一钝化层 8和第二钝化层 16的厚度之和等于像素 区过孔 15的厚度， 由于在形成公共电极时，过孔处像素电极上均会覆盖一层 透明导电层， 因此， 有利于减小像素电极 7的方块电阻， 有利于改善画面品 质。 本发明实施例中的阵列基板可应用于薄膜晶体管显示装置中。 所述显示 装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数 码相框、 手机、 平板电脑等具有任何显示功能的产品或部件。
本发明实施例中， 在已形成了栅极扫描线， 薄膜晶体管 TFT开关， 数据 线， 像素电极， 以及平板接线 PAD 区的图形的基板上形成第一钝化层， 通 过第一构图工艺形成平板接线 PAD区过孔， 在形成平板接线区 PAD区过孔 的基板上形成第二钝化层， 通过第二构图工艺形成像素区过孔， 其中， 像素 区过孔为开口小于底边的正梯形过孔， 在形成像素区过孔的基板上形成透明 导电层， 形成公共电极， 从而制作完成了阵列基板。 由于形成有断差的钝化 层， 并且， 一般钝化层的厚度是像素电极的十倍左右， 形成的正梯形的像素 区过孔后， 钝化层的高断差保证公共电极的不残留， 利于工艺管控， 最终提 高了产品质量。
并且， 当像素区过孔的深度等于钝化层的厚度时， 沉积的像素电极金属 层， 有一部分会直接覆盖在像素电极上， 这样还有利于减小像素电极的方块 电阻， 有利于改善画面品质。
以上以钝化层下方的显示电极为像素电极、 钝化层上方的显示电极为公 共电极为例进行了描述， 然而， 钝化层下方的显示电极也可以为公共电极， 钝化层上方的电极也可以为像素电极。 此时， 仅仅需要改变上方电极和下方 电极与薄膜晶体管和平板接线 PAD区的连接关系即可， 这里不再赘述。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管阵列基板的制作方法， 包括：
在形成有栅极扫描线、 薄膜晶体管开关、 数据线、 第一显示电极以及平 板接线 PAD 区的基板上形成第一钝化层， 并通过第一构图工艺在所述平板 接线 PAD区上方的第一钝化层中形成平板接线 PAD区过孔；
在形成有所述平板接线 PAD 区过孔的基板上形成第二钝化层， 并通过 第二构图工艺在所述像素电极上方的第一钝化层和第二钝化层中形成像素区 过孔， 以使得所述像素区过孔的顶部尺寸小于其底部尺寸； 以及
在形成有所述像素区过孔的基板上覆盖透明导电层， 以形成第二显示电 极。
2、如权利要求 1所述的方法， 其中在平面图中看， 所述像素区过孔呈至 少沿一个方向延伸的条形； 且
其中所述像素区过孔的垂直于所述条形的延伸方向的截面形状为上底小 于下底的正梯形形状。
3、如权利要求 2所述的方法，其中在形成有所述像素区过孔的基板上覆 盖透明导电层的步骤中， 透明导电层在所述像素区过孔处断开， 以形成具有 狭缝结构的第二显示电极。
4、如权利要求 1-3中任一项所述的方法， 其中所述第一显示电极为像素 电极， 所述第二显示电极为公共电极。
5、 如权利要求 1-4中任一项所述的方法， 其中所述 PAD区过孔垂直于 所述基板表面的方向剖取的截面为上底大于下底的倒梯形过孔。
6、如权利要求 1-5中任一项所述的方法， 其中所述通过第一构图工艺形 成平板接线 PAD区过孔包括：
在所述第一钝化层上涂覆光刻胶， 利用第一掩模板进行曝光， 并进行显 影处理； 以及
利用干法刻蚀， 刻蚀未覆盖光刻胶的第一钝化层， 形成平板接线 PAD 区过孔。
7、如权利要求 6所述的方法， 其中在所述第二构图工艺中，在所述平板 接线 PAD区过孔上方的第二钝化层中也形成过孔。
8、如权利要求 1-7中任一项所述的方法， 其中所述通过第二构图工艺形 成像素区过孔包括：
在所述第二钝化层上涂覆光刻胶， 利用第二掩模板进行曝光， 并进行显 影处理； 以及
利用干法刻蚀， 刻蚀未覆盖光刻胶的第二钝化层和下方的第一钝化层， 形成所述像素区过孔。
9、如权利要求 1-8中任一项所述的方法， 其中所述像素区过孔的深度小 于或等于第一钝化层与第二钝化层之和的厚度。
10、如权利要求 1-9中任一项所述的方法， 其中在所述第二构图工艺中， 所述第二钝化层的刻蚀速率 d、于所述第一钝化层的刻蚀速率。
11、如权利要求 10所述的方法，其中所述第二钝化层的形成工艺温度低 于所述第一钝化层的形成工艺温度。
12、 如权利要求 1-11中任一项所述的方法， 其中， 所述栅极扫描线、 薄 膜晶体管开关、 数据线、 第一显示电极以及平板接线 PAD 区的形成过程包 括：
在基板上形成薄膜晶体管开关的栅极、以及栅极扫描线和平板接线 PAD 区；
在形成有所述栅极的基板上形成半导体有源层、 数据线以及薄膜晶体管 开关的源极和漏极； 以及
在形成有所述源极和漏极的基板上形成第一显示电极。
13、 如权利要求 1-11中任一项所述的方法， 其中， 所述栅极扫描线、 薄 膜晶体管开关、 数据线、 第一显示电极以及平板接线 PAD 区的形成过程包 括：
在基板上形成薄膜晶体管开关的栅极、以及栅极扫描线和平板接线 PAD 区；
在形成有所述栅极的基板上形成半导体有源层；
在形成有所述半导体有源层的基板上形成第一显示电极； 以及
在形成有所述像素电极图形的基板上形成数据线以及薄膜晶体管开关的 源极和漏极。
14、 一种薄膜晶体管阵列基板， 包括： 基板；
形成于所述基板上的栅极扫描线、薄膜晶体管开关、数据线、像素电极、 公共电极、 平板接线 PAD区以及 PAD区过孔，
其中所述像素电极与所述公共电极之间的钝化层中有像素区过孔， 其中所述钝化层包括第一钝化层和第二钝化层， 且所述像素区过孔的顶 部尺寸小于其底部尺寸。
15、如权利要求 14所述的阵列基板， 其中在平面图中看， 所述像素区过 孔呈至少沿一个方向延伸的条形； 且
其中所述像素区过孔的垂直于所述条形的延伸方向的截面形状为上底小 于下底的正梯形形状。
16、如权利要求 15所述的阵列基板，其中所述像素电极和所述公共电极 中在所述钝化层上方的一者为具有狭缝结构的电极， 且所述狭缝结构与所述 像素区过孔对应设置。
17、如权利要求 14-16中任一项所述的阵列基板， 其中所述 PAD区过孔 沿垂直于所述基板表面的方向剖取的截面为上底大于下底的倒梯形形状。
18、 如权利要求 14-17中任一项所述的阵列基板， 其中所述像素区过孔 的深度小于或等于第一钝化层与第二钝化层之和的厚度。
19、 如权利要求 14-18中任一项所述的阵列基板， 其中所述第二钝化层 的材质密度大于所述第一钝化层的材质密度。
20、 一种显示装置， 包括： 如权利要求 14-19中任一权利要求所述的阵 列基板。
PCT/CN2012/086307 2012-05-11 2012-12-10 薄膜晶体管阵列基板及制作方法和显示装置 WO2013166831A1 (zh)

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