JP6818554B2 - アレイ基板の製造方法、アレイ基板および表示装置 - Google Patents
アレイ基板の製造方法、アレイ基板および表示装置 Download PDFInfo
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- JP6818554B2 JP6818554B2 JP2016566218A JP2016566218A JP6818554B2 JP 6818554 B2 JP6818554 B2 JP 6818554B2 JP 2016566218 A JP2016566218 A JP 2016566218A JP 2016566218 A JP2016566218 A JP 2016566218A JP 6818554 B2 JP6818554 B2 JP 6818554B2
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Description
ベースに、画素電極を含むパターンが形成されるステップS1と、
ステップS1の後、前記ベースに、薄膜トランジスタのゲートを含むパターンが形成されるステップS2と、
ステップS2の後、前記ベースにゲート絶縁層が形成されるステップS3と、
ステップS3の後、前記ベースにパターニング処理により、薄膜トランジスタの活性層と、前記活性層に形成されたソース、ドレインとを含むパターンが形成されるステップS4と、
ステップS4の後、前記ベースにパッシベーション層が形成されるステップS5と、
ステップS5の後、前記ベースにパターニング処理により、前記ゲート絶縁層と前記パッシベーション層とを貫通した主ビアおよび、前記ドレインの一部領域下方に位置する主ビア延出部を含むパターンが形成され、そのうち前記主ビアと前記主ビア延出部は貫通するステップS6と、
ステップS6の後、前記ドレインの、前記主ビア延出部から突出した部分が除去され、最終のビアを含むパターンが形成されるステップS7と、
ステップS7の後、前記ベースには、前記最終のビアを介して前記ドレインを前記画素電極に電気的に接続する接続電極と、共通電極とを含むパターンが形成されるステップS8と、を備える。
前記パッシベーション層が形成されたベースに第1のフォトレジスト層が形成されるステップと、
ハーフトーンマスク板またはグレイトーンマスク板を用いて前記第1のフォトレジスト層を露光することで、前記第1のフォトレジスト層に、第1のフォトレジストが完全に除去された領域と、第1のフォトレジストが完全に残された領域と、第1のフォトレジストが一部残された領域とが形成され、そのうち、前記第1のフォトレジストが完全に除去された領域は前記ビア領域の中間領域に対応し、前記第1のフォトレジストが一部残された領域は前記薄膜トランジスタ領域のドレイン領域における、前記ビア領域に近い部分と、前記ビア領域における、前記薄膜トランジスタ領域に近い周辺領域とに対応し、前記第1のフォトレジストが完全に残された領域は上記領域以外の領域に対応し、現像処理後、前記第1のフォトレジストが完全に残された領域のフォトレジスト厚さは変化せず、前記第1のフォトレジストが完全に除去された領域のフォトレジストは完全に除去され、前記第1のフォトレジストが一部残された領域のフォトレジスト厚さは小さくなるステップと、
エッチング処理により前記パッシベーション層と前記ゲート絶縁層の、前記第1のフォトレジストが完全に除去された領域下の部分を除去するステップと、
アッシング処理により、前記第1のフォトレジストが一部残された領域のフォトレジストを除去することで、前記パッシベーション層の、前記第1のフォトレジストが一部残された領域下に位置する部分と、前記ビア領域の、前記薄膜トランジスタ領域に近い周辺領域とを露出させるステップと、
エッチング処理により、前記パッシベーション層と前記活性層と前記ゲート絶縁層の、前記第1のフォトレジストが一部残された領域下の部分を除去することで、前記主ビアと前記主ビア延出部とを含むパターンが形成されるステップと、
残りのフォトレジストを除去するステップと、を、備える。
前記主ビアと前記主ビア延出部とを含むパターンが形成されたベースに、一回のパターニング処理により前記ドレインの、前記主ビア延出部から突出した部分が除去され、前記最終のビアを含むパターンが形成されるステップを備える。
透明導電薄膜が形成され、一回のパターニング処理により前記接続電極と前記共通電極とを含むパターンが形成されるステップを備える。
前記主ビアと前記主ビア延出部とを含むパターンが形成されたベースに、第2のフォトレジスト層が形成されるステップと、
ハーフトーンマスク板またはグレイトーンマスク板を用いて前記第2のフォトレジスト層を露光することで、前記第2のフォトレジスト層に、第2のフォトレジストが完全に除去された領域と、第2のフォトレジストが完全に残された領域と、第2のフォトレジストが一部残された領域とが形成され、そのうち、前記第2のフォトレジストが完全に除去された領域は前記薄膜トランジスタ領域のソース領域、前記ビア領域、前記共通電極領域の第2の領域に対応し、前記第2のフォトレジストが一部残された領域は前記薄膜トランジスタ領域のドレイン領域に対応し、前記第2のフォトレジストが完全に残された領域は上記領域以外の、前記第1の領域を含む領域に対応し、現像処理後、前記第2のフォトレジストが完全に残された領域のフォトレジスト厚さは変化せず、前記第2のフォトレジストが完全に除去された領域のフォトレジストは完全に除去され、前記第2のフォトレジストが一部残された領域のフォトレジスト厚さは小さくなるステップと、
エッチング処理により前記ドレインの、前記主ビア延出部から突出した部分が除去され、前記最終のビアを含むパターンが形成されるステップと、
アッシング処理により、第2のフォトレジストが一部残された領域のフォトレジストが除去されるステップと、
アッシング処理により、第2のフォトレジストが一部残された領域のフォトレジストが除去された後のベースに、透明導電薄膜が形成されるステップと、
段差剥離処理により残りのフォトレジストが除去されて、前記共通電極と前記接続電極のパターンが形成されるステップと、を備える。
活性層薄膜とソース・ドレイン金属薄膜が順に蒸着されるステップと、
グレイトーンマスク板またはハーフトーンマスク板を用いて、一回のパターニング処理により前記薄膜トランジスタの活性層および、前記活性層上の前記ソースと前記ドレインを含むパターンが形成されるステップと、を備える。
活性層薄膜が蒸着され、一回のパターニング処理により前記薄膜トランジスタの活性層を含むパターンが形成されるステップと、
ソース・ドレイン金属薄膜が蒸着され、別の一回のパターニング処理により前記薄膜トランジスタのソースとドレインとを含むパターンが形成されるステップと、を備える。
2 ゲート
3 ゲート絶縁層
4 活性層
6 パッシベーション層
10 ベース
51 ソース
52 ドレイン
71 主ビア
72 主ビア延出部
81 共通電極
82 接続電極
91 第1のフォトレジストが完全に残された領域
92 第1のフォトレジストが一部残された領域
94 第2のフォトレジストが完全に残された領域
95 第2のフォトレジストが一部残された領域
Claims (9)
- ベースに、画素電極を含むパターンが形成されるステップS1と、
ステップS1の後、前記ベースに、薄膜トランジスタのゲートを含むパターンが形成されるステップS2と、
ステップS2の後、前記ベースにゲート絶縁層が形成されるステップS3と、
ステップS3の後、前記ベースにパターニング処理により、薄膜トランジスタの活性層と、前記活性層に形成されたソース、ドレインとを含むパターンが形成されるステップS4と、
ステップS4の後、前記ベースにパッシベーション層が形成されるステップS5と、
ステップS5の後、前記ベースにパターニング処理により、前記ゲート絶縁層と前記パッシベーション層とを貫通した主ビアおよび、前記ドレインの一部領域下方に位置する主ビア延出部を含むパターンが形成され、そのうち前記主ビアと前記主ビア延出部は貫通するステップS6と、
ステップS6の後、前記ドレインの、前記主ビア延出部から突出した部分が除去され、最終のビアを含むパターンが形成されるステップS7と、
ステップS7の後、前記ベースには、前記最終のビアを介して前記ドレインを前記画素電極に電気的に接続する接続電極と、共通電極とを含むパターンが形成されるステップS8と、
を備え、
ステップS7には、前記主ビアと前記主ビア延出部とを含むパターンが形成されたベースに、一回のパターニング処理により前記ドレインの、前記主ビア延出部から突出した部分が除去され、前記最終のビアを含むパターンが形成されるステップを備える、アレイ基板の製造方法。 - 前記アレイ基板は、薄膜トランジスタ領域、共通電極領域、前記薄膜トランジスタ領域と前記共通電極領域との間に位置するビア領域を備え、
前記ステップS6には、
前記パッシベーション層が形成されたベースに第1のフォトレジスト層が形成されるステップと、
ハーフトーンマスク板またはグレイトーンマスク板を用いて前記第1のフォトレジスト層を露光することで、前記第1のフォトレジスト層に、第1のフォトレジストが完全に除去された領域と、第1のフォトレジストが完全に残された領域と、第1のフォトレジストが一部残された領域とが形成され、そのうち、前記第1のフォトレジストが完全に除去された領域は前記ビア領域の中間領域に対応し、前記第1のフォトレジストが一部残された領域は前記薄膜トランジスタ領域のドレイン領域における、前記ビア領域に近い部分と、前記ビア領域における、前記薄膜トランジスタ領域に近い周辺領域とに対応し、前記第1のフォトレジストが完全に残された領域は上記領域以外の領域に対応し、現像処理後、前記第1のフォトレジストが完全に残された領域のフォトレジスト厚さは変化せず、前記第1のフォトレジストが完全に除去された領域のフォトレジストは完全に除去され、前記第1のフォトレジストが一部残された領域のフォトレジスト厚さは小さくなるステップと、
エッチング処理により、前記パッシベーション層と前記ゲート絶縁層の、前記第1のフォトレジストが完全に除去された領域下の部分を除去するステップと、
アッシング処理により、前記第1のフォトレジストが一部残された領域のフォトレジストを除去することで、前記パッシベーション層の、前記第1のフォトレジストが一部残された領域下に位置する部分と、前記ビア領域の、前記薄膜トランジスタ領域に近い周辺領域とを露出させるステップと、
エッチング処理により、前記パッシベーション層と前記活性層と前記ゲート絶縁層の、前記第1のフォトレジストが一部残された領域下の部分を除去することで、前記主ビアと前記主ビア延出部とを含むパターンが形成されるステップと、
残りのフォトレジストを除去するステップと、
を備える、請求項1に記載のアレイ基板の製造方法。 - 前記第1のフォトレジスト層の厚さは2.2〜2.5μmである、請求項2に記載のアレイ基板の製造方法。
- エッチング処理により、前記パッシベーション層と前記ゲート絶縁層の、前記第1のフォトレジストが完全に除去された領域下の部分を除去する前記ステップと、エッチング処理により、前記パッシベーション層と前記活性層と前記ゲート絶縁層の、前記第1のフォトレジストが一部残された領域下の部分を除去する前記ステップとで採用されるエッチング処理は、ドライエッチングである、請求項2に記載のアレイ基板の製造方法。
- ステップS8には、透明導電薄膜が形成され、一回のパターニング処理により前記接続電極と前記共通電極とを含むパターンが形成されるステップを備える、請求項1または2に記載のアレイ基板の製造方法。
- 前記共通電極領域は、交互に配列された第1の領域と第2の領域とを含み、ステップS8には、
前記ベースに、第2のフォトレジスト層が形成されるステップと、
ハーフトーンマスク板またはグレイトーンマスク板を用いて前記第2のフォトレジスト層を露光することで、前記第2のフォトレジスト層に、第2のフォトレジストが完全に除去された領域と、第2のフォトレジストが完全に残された領域と、第2のフォトレジストが一部残された領域とが形成され、そのうち、前記第2のフォトレジストが完全に除去された領域は前記薄膜トランジスタ領域のソース領域、前記ビア領域、前記共通電極領域の第2の領域に対応し、前記第2のフォトレジストが一部残された領域は前記薄膜トランジスタ領域のドレイン領域に対応し、前記第2のフォトレジストが完全に残された領域は上記領域以外の、前記第1の領域を含む領域に対応し、現像処理後、前記第2のフォトレジストが完全に残された領域のフォトレジスト厚さは変化せず、前記第2のフォトレジストが完全に除去された領域のフォトレジストは完全に除去され、前記第2のフォトレジストが一部残された領域のフォトレジスト厚さは小さくなるステップと、
アッシング処理により、第2のフォトレジストが一部残された領域のフォトレジストが除去されるステップと、
アッシング処理により、第2のフォトレジストが一部残された領域のフォトレジストが除去された後のベースに、透明導電薄膜が形成されるステップと、
段差剥離処理により残りのフォトレジストが除去されて、前記共通電極と前記接続電極のパターンが形成されるステップと、を備える、請求項1または2に記載のアレイ基板の製造方法。 - 前記第2のフォトレジスト層の厚さは2.5〜3.0μmである、請求項6に記載のアレイ基板の製造方法。
- ステップS4には、
活性層薄膜とソース・ドレイン金属薄膜が順に蒸着されるステップと、
グレイトーンマスク板またはハーフトーンマスク板を用いて、一回のパターニング処理により前記薄膜トランジスタの活性層および、前記活性層上の前記ソースと前記ドレインを含むパターンが形成されるステップと、を備える、請求項1〜7のいずれか1項に記載のアレイ基板の製造方法。 - ステップS4には、
活性層薄膜が蒸着され、一回のパターニング処理により前記薄膜トランジスタの活性層を含むパターンが形成されるステップと、
ソース・ドレイン金属薄膜が蒸着され、別の一回のパターニング処理により前記薄膜トランジスタのソースとドレインとを含むパターンが形成されるステップと、を備える、請求項1〜7のいずれか1項に記載のアレイ基板の製造方法。
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