WO2013174105A1 - 阵列基板、其制造方法、显示面板及显示装置 - Google Patents

阵列基板、其制造方法、显示面板及显示装置 Download PDF

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Publication number
WO2013174105A1
WO2013174105A1 PCT/CN2012/084166 CN2012084166W WO2013174105A1 WO 2013174105 A1 WO2013174105 A1 WO 2013174105A1 CN 2012084166 W CN2012084166 W CN 2012084166W WO 2013174105 A1 WO2013174105 A1 WO 2013174105A1
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Prior art keywords
contact hole
substrate
layer
drain electrode
electrode
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PCT/CN2012/084166
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English (en)
French (fr)
Inventor
杨玉清
朴承翊
李炳天
蒋冬华
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2013174105A1 publication Critical patent/WO2013174105A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, a display panel, and a display device. Background technique
  • a disadvantage of fabricating a thin film transistor display using an amorphous silicon (a-Si) thin film transistor (TFT) is that its electron mobility is very low ( ⁇ 1 cm 2 /VS), while a-Si is opaque in the visible range and has high photosensitivity, so The scope of application is limited.
  • a-Si amorphous silicon
  • TFT thin film transistor
  • Metal oxide semiconductor thin film transistor Metal Oxide Semiconductor TFT
  • the MOS-TFT metal oxide semiconductor thin film has a low deposition temperature, high electron mobility, easy etching, high transmittance in the visible light range, and relatively low correlation between electron mobility and particle size of the film, that is, It has the advantages of high Vth uniformity.
  • Figs. 1 and 1b are schematic views showing the structure of a conventional metal oxide thin film transistor array substrate, wherein Fig. 1b is a plan view of the array substrate, and Fig. la is a cross-sectional view taken along line A-A of Fig. 1b. Referring to FIGS.
  • the array substrate includes: a substrate 101; a gate electrode 102 and a gate line formed on the substrate 101; a gate insulating layer 103 formed on the gate electrode 102 and the gate line; and a gate insulating layer 103 formed thereon a metal oxide active layer 104; an etch stop layer (ESL) 105 formed on the active layer 104, a source electrode 106, a drain electrode 107, and a data line; a source electrode 106, a drain electrode 107, and A passivation layer 108 on the data line is formed with a contact hole 109 formed on the passivation layer 108; a pixel electrode 110 formed on the passivation layer 108, and the pixel electrode 110 is connected to the drain electrode 107 through the contact hole 109.
  • ESL etch stop layer
  • the manufacturing process of the MOS-TFT array substrate is as follows: a gate metal layer is deposited on the substrate 101, exposed by a mask, and then a gate electrode 102 is formed by a development and etching process; a gate insulating layer 103 and a metal are sequentially deposited thereon.
  • the oxide semiconductor layer is exposed by a mask, and then the active layer 104 is formed by a development and etching process; a barrier layer material is deposited thereon, and the mask is used for exposure, and then Developing and etching processes to form the etch barrier layer 105; depositing a source/drain metal layer thereon, exposing with a mask, and then developing and etching the source electrode 106 and the drain electrode 107; depositing thereon
  • the layer 108 is exposed by a mask, and then a contact hole 109 is formed by a development and etching process; a transparent electrode layer is deposited thereon, exposed by a mask, and the pixel electrode 110 is formed by a development and etching process.
  • the manufacturing process of the above array substrate includes six patterning processes, and each masking process uses a different masking plate, resulting in a high manufacturing cost of the array substrate.
  • a technical problem to be solved by embodiments of the present invention is to provide an array substrate, a method of manufacturing the same, a display panel, and a display device to reduce the manufacturing cost of the array substrate.
  • the embodiments of the present invention provide the following technical solutions.
  • An aspect of an embodiment of the present invention provides an array substrate, comprising: an etch barrier layer having a source electrode contact hole and a drain electrode contact hole formed on a substrate on which an active layer is formed; Etching the source electrode, the drain electrode and the data line on the substrate of the barrier layer, the source electrode is connected to the active layer through the source electrode contact hole, and the drain electrode is connected to the active layer through the drain electrode contact hole; forming the active electrode, a passivation layer having a pixel electrode contact hole on the substrate of the drain electrode and the data line, the orthographic projection of the pixel electrode contact hole on the substrate coincides with the orthographic projection of the drain electrode contact hole on the substrate; formed in the formed a pixel electrode on the substrate of the passivation layer, the pixel electrode being connected to the drain electrode through the pixel electrode contact hole.
  • the above array substrate may further include: a gate electrode and a gate line formed on the substrate; a gate insulating layer formed on the substrate on which the gate electrode and the gate line are formed; and an active layer formed on the gate insulating layer.
  • the active layer is a metal oxide active layer.
  • the orthographic projection of the pixel electrode contact hole on the substrate is located in a region where the gate electrode is located.
  • the etch barrier layer entirely covers the substrate.
  • An aspect of an embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming an etch barrier layer on a substrate on which an active layer is formed, performing photolithography using a first mask, and etching a source electrode contact hole and a drain electrode contact hole; a source electrode, a drain electrode and a data line are formed on the substrate on which the etch barrier layer is formed, the source electrode is connected to the active layer through the source electrode contact hole, and the drain electrode passes through the drain electrode contact hole Connected to the active layer; formed on the substrate on which the active electrode, the drain electrode, and the data line are formed Forming a passivation layer, performing photolithography using the first mask, etching a pixel electrode contact hole; forming a pixel electrode on the substrate on which the passivation layer is formed, the pixel electrode passing through the pixel electrode contact hole and leakage Extremely connected.
  • the method before forming the etch barrier layer, further comprises: forming a gate electrode and a gate line on the substrate; forming a gate insulating layer on the substrate on which the gate electrode and the gate line are formed; on the gate insulating layer An active layer is formed.
  • the active layer is a metal oxide active layer.
  • An aspect of an embodiment of the present invention provides a display panel including the above array substrate.
  • An aspect of an embodiment of the present invention provides a display device including the above array substrate.
  • the same mask can be used, thereby reducing the number of masks and reducing the manufacturing cost of the array substrate;
  • the pixel electrode contact hole is formed in the upper region of the gate electrode, and is formed in the pixel region relative to the prior art, thereby increasing the aperture ratio of the array substrate;
  • the etch barrier layer completely covers the substrate, and the prior art alignment deviation problem does not occur, and the width-to-length ratio (W/L) of the thin film transistor can be finely adjusted by the exposure device according to the actual process conditions, and the device characteristics can be micro-controlled. , flexible process conditions.
  • FIGS. 1a and 1b are schematic structural diagrams of a metal oxide thin film transistor array substrate of the prior art
  • FIG. 2 is a schematic structural view of an array substrate after forming a gate electrode according to an embodiment of the present invention
  • FIG. 3 is a gate insulating structure according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an array substrate after forming an active layer according to an embodiment of the present invention
  • FIGS. 5a and 5b are array substrates after forming an etch barrier layer according to an embodiment of the present invention
  • 6a and 6b are schematic structural views of an array substrate after forming a source/drain electrode according to an embodiment of the present invention
  • FIGS. 7a and 7b are schematic structural views of an array substrate after forming a passivation layer according to an embodiment of the present invention
  • FIGS. 8a and 8b are diagrams Schematic diagram of the array substrate of the embodiment of the invention.
  • FIG. 9 is a flow chart of a method of fabricating an array substrate according to an embodiment of the invention. detailed description
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and A pixel electrode that controls the arrangement of liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • a gate metal layer may be formed on the glass substrate 101 or other types of transparent substrates by sputtering, thermal evaporation or other film forming methods, and the gate metal layer may be made of chromium (Cr) or molybdenum (Mo).
  • the layer may be one or more layers; then, a photoresist is formed on the gate metal layer; secondly, the photoresist is exposed and developed by using a patterned mask to form a photoresist mask; The gate metal layer is etched using a photoresist mask to form a pattern of the gate electrode 201 and the gate line; finally, the remaining photoresist is stripped.
  • step 92 a gate insulating layer is formed on the substrate on which the step 91 is completed, and an active layer is formed on the gate insulating layer;
  • a gate insulating layer 301 may be deposited on the substrate 101 by plasma enhanced chemical vapor deposition (PECVD) or the like.
  • the gate insulating layer 301 may be made of a material such as an oxide (for example, SiOx) or a nitride (for example, SiNx), or a combination of the two.
  • a semiconductor layer may be formed on the substrate 101 by sputtering or the like. It may be a metal oxide semiconductor layer, and the material thereof may be a ZnO-based material or an IGZO-based material having a thickness of 200 to 2000 A; then, a photoresist is formed on the semiconductor layer; secondly, a patterned mask pair is used.
  • the photoresist is exposed and developed to form a photoresist mask; again, the semiconductor layer is etched using a photoresist mask to form a pattern of the active layer 401; finally, the remaining photoresist is stripped.
  • the active layer 401 may be a block pattern.
  • Step 93 forming an etch barrier layer on the substrate of the step 92, and performing photolithography using the first mask, etching the source electrode contact hole and the drain electrode contact hole;
  • an etch stop layer 501 may be formed on the substrate 101 by a method such as PECVD.
  • the etch stop layer 501 may be used.
  • a material such as SiNx or SiOx may also be a combination of two, having a thickness of between 200 and 2000 A; then, a photoresist is formed on the etch stop layer 501; secondly, a mask having a pattern is used (referred to as a a mask) exposing and developing the photoresist to form a photoresist mask; again, etching the etch barrier layer 501 by using a photoresist mask to form a first contact hole (source electrode contact hole) 502 and a second contact hole (drain electrode contact hole) 503; Finally, the remaining photoresist is peeled off.
  • the lengths of the source electrode contact hole 502 and the drain electrode contact hole 503 are W of the active switch, and between the source electrode contact hole 502 and the drain electrode contact hole 503.
  • the distance (in FIG. 5b, the distance between the upper side of the source electrode contact hole 502 and the lower side of the drain electrode contact hole 503) is L of the active switch. Since the etch barrier layer 501 completely covers the substrate, the prior art alignment deviation problem does not occur, and the width to length ratio (W/L) of the thin film transistor can be finely adjusted by the exposure device according to the actual process conditions, and the device characteristics can be micro-controlled. , flexible process conditions. In this embodiment, W is between 2 and 30 um, and L is between 2 and 30 um.
  • Step 94 forming a source electrode, a drain electrode and a data line on the substrate on which step 93 is completed; as shown in FIG. 6a and FIG. 6b (FIG. 6a is a cross-sectional view, FIG. 6b is a plan view), first, sputtering, thermal evaporation may be employed. Or another film forming method, forming a source/drain metal layer on the substrate 101, and the source/drain gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W).
  • Cr chromium
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • W tungsten
  • the source/drain metal layer may be one or more layers; then, in the source/drain metal layer Forming a photoresist thereon; secondly, exposing and developing the photoresist by using a patterned mask to form a photoresist mask; again, etching the source/drain metal layer by using a photoresist mask to form a source A pattern of electrode 601, drain electrode 602, and data lines; finally, the remaining photoresist is stripped.
  • the source electrode 601 is connected to the active layer 401 through the source electrode contact hole 502, and the drain electrode 602 is connected to the active layer 401 through the drain electrode contact hole 503.
  • Step 95 forming a passivation layer on the substrate on which step 94 is completed, and performing photolithography using the first mask plate to etch the pixel electrode contact hole;
  • a passivation layer 701 may be formed on the substrate 101 by a method such as PECVD, and the passivation layer 701 may be SiNx or SiOx.
  • a material, or a combination of the two then, forming a photoresist on the passivation layer 701; secondly, exposing the photoresist with a patterned mask (ie, the first mask described above) Developing, forming a photoresist mask; again, etching the etch barrier layer 701 with a photoresist mask to form a third contact hole 702 and a fourth contact hole (pixel electrode contact hole) 703; finally, peeling off the remaining Photoresist.
  • a patterned mask ie, the first mask described above
  • Step 96 forming a pixel electrode on the substrate on which the step 95 is completed, and the pixel electrode is connected to the drain electrode through the pixel electrode contact hole.
  • a transparent conductive layer may be formed on the substrate 101 by magnetron sputtering, thermal evaporation or other film forming method, which is transparent.
  • the conductive layer may be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO) or aluminum oxide; then, a photoresist is formed on the transparent conductive layer; secondly, a patterned mask is used for the photoresist.
  • Exposure and development are performed to form a photoresist mask; again, the transparent conductive layer is etched by a photoresist mask to form a pattern of the pixel electrode 801, and the pixel electrode 801 passes through the pixel electrode contact hole 703 and the drain electrode 602. Connection; Finally, strip the remaining photoresist.
  • the transparent conductive portion 802 is also formed in the third contact hole 702. However, since the pixel electrode 801 and the transparent conductive portion 802 are not connected, and the portion is above the gate electrode 201, it is transparent. The presence of the conductive portion 802 does not affect display performance and display quality.
  • the contact hole is formed on the etch barrier layer and the contact hole is formed on the passivation layer, and the same mask is used, thereby reducing the number of masks and saving cost.
  • the etch stop layer completely covers the substrate without causing the problem of prior art alignment deviation and having no effect on the transmittance. Since the active switches W and L are directly exposed through the etch barrier mask, the W/L can be fine-tuned by the exposure device according to the actual process conditions, the device characteristics can be micro-controlled, and the process conditions are flexible.
  • the pixel electrode contact hole is located above the drain electrode above the gate electrode, and does not cause a decrease in the aperture ratio caused by the prior art pixel electrode contact hole located in the pixel portion, thereby improving the aperture ratio of the product.
  • An embodiment of the present invention further provides an array substrate, in which an etch barrier layer is formed with a first contact hole and a second contact hole, and a third contact hole and a fourth contact hole are formed on the ruthenium layer. Since the contact holes are formed by the same mask, the first contact holes have the same shape as the third contact holes, and the positions correspond to each other (ie, the orthographic projection of the first contact holes on the substrate and the The positive contact of the third contact hole on the substrate coincides; the second contact hole has the same shape as the fourth contact hole, and the position corresponds to (ie, the orthographic projection of the second contact hole on the substrate and the fourth contact The orthographic projection of the hole on the substrate coincides)
  • an array substrate according to an embodiment of the present invention may include:
  • a gate electrode 201 and a gate line formed on the substrate 101 a gate electrode 201 and a gate line formed on the substrate 101; a gate insulating layer 301 formed on the substrate 101 on which the gate electrode 201 and the gate line are formed;
  • the source electrode 601, the drain electrode 602, and the data line are formed on the substrate 101 on which the etch stop layer 501 is formed, the source electrode 601 is connected to the active layer 401 through the source electrode contact hole 502, and the drain electrode 602 is passed through the drain electrode contact hole 503. Connected to the active layer 401;
  • the orthographic projections of the holes 503 on the substrate 101 are coincident;
  • the pixel electrode 801 is formed on the substrate 101 on which the passivation layer 701 is formed, and the pixel electrode 801 is connected to the drain electrode 602 through the pixel electrode contact hole 703.
  • the active layer 401 is a metal oxide active layer, and the material thereof may be a ZnO-based material or an IGZO-based material, and the thickness thereof is between 200 and 2000 ⁇ .
  • an orthographic projection of the pixel electrode contact hole 703 on the substrate 101 is located in a region where the gate electrode 201 is located.
  • a third contact hole 702 completely corresponding to the first contact hole 502 is formed in the passivation layer 701, and a transparent conductive portion 802 is also formed in the third contact hole 702.
  • the pixel electrode 801 and the transparent conductive portion 802 are not connected, and the portion is above the gate electrode 201, the presence of the transparent conductive portion 802 does not affect display performance and display quality.
  • the embodiment of the invention further provides a display panel, wherein the display panel comprises any one of the array substrates described above.
  • the embodiment of the invention further provides a display device, which comprises any of the array substrates described above.
  • the display device may be: a product or a component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

提供一种阵列基板，其制造方法、显示面板及显示装置，该阵列基板包括：形成在形成有有源层的基板（101）上的具有源电极接触孔（502）和漏电极接触孔（503）的蚀刻阻挡层（501）；形成在形成有刻蚀阻挡层（501）的基板上的源电极、漏电极和数据线，源电极通过源电极接触孔（502）与有源层连接，漏电极通过漏电极接触孔（503）与有源层连接；形成在形成有源电极、漏电极和数据线的基板上的具有像素电极接触孔的钝化层（701），所述像素电极接触孔在基板（101）上的正投影与所述漏电极接触孔（503）在基板上的正投影重合；形成在形成有钝化层（701）的基板上的像素电极，所述像素电极（801）通过像素电极接触孔与漏电极连接。能够降低阵列基板的制造成本。

Description

阵列基板、 其制造方法、 显示面板及显示装置 技术领域
本发明的实施例涉及一种阵列基板、其制造方法、显示面板及显示装置。 背景技术
利用非晶硅（a-Si )薄膜晶体管（TFT )制作薄膜晶体管显示器的缺点是 其电子迁移率非常低（<lcm2/V.S ), 同时 a-Si在可见光范围不透明， 光敏性 强， 因此其应用范围受到了限制。 随着新技术的出现， 如有机发光二极管 ( OLED )显示技术、 透明液晶显示技术、 栅极集成在阵列基板技术（Gate Driver on Array, GOA )等逐渐进入人们的视野， 需要薄膜半导体材料具有 更高的电子迁移率、 更佳的非晶态均一性、 以及减少的阀值电压（Vth )漂移 等。
金属氧化物半导体薄膜晶体管 （ Metal Oxide Semiconductor TFT,
MOS-TFT )的金属氧化物半导体薄膜具有沉积温度低、 电子迁移率高、 易于 刻蚀、 在可见光范围内透过率高、 且电子迁移率与膜的颗粒尺寸的相对低的 相关性， 即具有 Vth均一性高等优点。
图 la和图 lb为现有的金属氧化物薄膜晶体管阵列基板的结构示意图， 其中， 图 lb是阵列基板的平面图， 图 la是图 lb的沿 A-A线的截面图。 参 照图 la和图 lb， 所述阵列基板包括： 基板 101; 形成在基板 101上的栅电极 102和栅线； 形成在栅电极 102和栅线上的栅绝缘层 103; 形成在栅绝缘层 103上的金属氧化物有源层 104;形成在有源层 104上的刻蚀阻挡层( Etch Stop Layer, ESL ) 105、 源电极 106、 漏电极 107和数据线； 源电极 106、 漏电极 107和数据线上的钝化层 108, 钝化层 108上形成有接触孔 109; 形成在钝化 层 108上的像素电极 110,像素电极 110通过接触孔 109与漏电极 107连接。
上述 MOS-TFT阵列基板的制造工艺如下：在基板 101上沉积栅金属层， 用掩膜板进行曝光， 再经显影、 刻蚀工艺制作栅电极 102; 在其上依次沉积 栅绝缘层 103和金属氧化物半导体层， 利用掩膜板进行曝光， 再经显影、 刻 蚀工艺制作有源层 104; 在其上沉积阻挡层材料， 用掩膜板进行曝光， 再经 显影、 刻蚀工艺制作刻蚀阻挡层 105; 在其上沉积源漏金属层， 用掩膜板进 行曝光， 再经显影、 刻蚀工艺制作源电极 106、 漏电极 107; 在其上沉积飩化 层 108, 用掩膜板进行曝光， 再经显影、 刻蚀工艺制作接触孔 109; 在其上沉 积透明电极层， 用掩膜板进行曝光， 再经显影、 刻蚀工艺制作像素电极 110。
可以看出， 上述阵列基板的制造过程包括了六次构图工艺， 每次构图工 艺都用到一块不同的掩膜板， 导致该阵列基板的制造成本较高。 发明内容
本发明的实施例所要解决的技术问题是提供一种阵列基板、其制造方法、 显示面板及显示装置， 以降低阵列基板的制造成本。
为解决上述技术问题， 本发明的实施例提供技术方案如下。
本发明的实施例的一个方面提供一种阵列基板， 该阵列基板包括： 形成 在形成有有源层的基板上的具有源电极接触孔和漏电极接触孔的刻蚀阻挡 层； 形成在形成有刻蚀阻挡层的基板上的源电极、 漏电极和数据线， 源电极 通过源电极接触孔与有源层连接， 漏电极通过漏电极接触孔与有源层连接； 形成在形成有源电极、 漏电极和数据线的基板上的具有像素电极接触孔的钝 化层， 所述像素电极接触孔在基板上的正投影与所述漏电极接触孔在基板上 的正投影重合； 形成在形成有钝化层的基板上的像素电极， 所述像素电极通 过像素电极接触孔与漏电极连接。
例如， 上述的阵列基板还可以包括： 形成在基板上的栅电极和栅线； 形 成在形成有栅电极和栅线的基板上的栅绝缘层；形成在栅绝缘层上的有源层。
例如， 在上述的阵列基板中， 所述有源层为金属氧化物有源层。
例如， 在上述的阵列基板中， 所述像素电极接触孔在基板上的正投影位 于栅电极所处的区域内。
例如， 在上述的阵列基板中， 所述刻蚀阻挡层全部覆盖所述基板。
本发明的实施例的一个方面提供一种阵列基板的制造方法，该方法包括： 在形成有有源层的基板上形成刻蚀阻挡层， 采用第一掩膜板进行光刻后， 刻 蚀出源电极接触孔和漏电极接触孔； 在形成有刻蚀阻挡层的基板上形成源电 极、 漏电极和数据线， 源电极通过源电极接触孔与有源层连接， 漏电极通过 漏电极接触孔与有源层连接； 在形成有源电极、 漏电极和数据线的基板上形 成钝化层， 采用所述第一掩膜板进行光刻后， 刻蚀出像素电极接触孔； 在形 成有钝化层的基板上形成像素电极， 所述像素电极通过像素电极接触孔与漏 电极连接。
例如， 上迷的制造方法中， 在形成刻蚀阻挡层之前还包括： 在基板上形 成栅电极和栅线； 在形成有栅电极和栅线的基板上形成栅绝缘层； 在栅绝缘 层上形成有源层。
例如， 上述的制造方法中， 所述有源层为金属氧化物有源层。
本发明的实施例的一个方面提供一种显示面板， 该显示面板包括上述的 阵列基板。
本发明的实施例的一个方面提供一种显示装置， 该显示装置包括上述的 阵列基板。
与现有技术相比， 本发明实施例的有益效果是：
1、在形成刻蚀阻挡层的图形以及钝化层的图形时，可以使用同一块掩膜 板， 从而减少了掩膜板的数量， 能够降低阵列基板的制造成本；
2、像素电极接触孔形成在栅电极上方区域，相对于现有技术形成在像素 区而言， 提高了阵列基板的开口率；
3、刻蚀阻挡层全部覆盖基板， 不会产生现有技术的对位偏差问题，且薄 膜晶体管的宽长比（W/L )可以根据实际工艺情况通过曝光设备进行微调， 器件特性可微控， 工艺条件灵活。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 la和 lb为现有技术的金属氧化物薄膜晶体管阵列基板的结构示意图； 图 2为本发明实施例中形成栅电极后的阵列基板的结构示意图； 图 3为本发明实施例中形成栅绝缘层后的阵列基板的结构示意图； 图 4a和 4b为本发明实施例中形成有源层后的阵列基板的结构示意图； 图 5a和 5b为本发明实施例中形成刻蚀阻挡层后的阵列基板的结构示意 图； 图 6a和 6b为本发明实施例中形成源漏电极后的阵列基板的结构示意图； 图 7a和 7b为本发明实施例中形成钝化层后的阵列基板的结构示意图； 图 8a和 8b为本发明实施例的阵列基板的结构示意图；
图 9为根据本发明实施例的阵列基板的制造方法流程图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制，而是表示存在至少一个。 "包括"或者"包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出 现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其 他元件或者物件。 "连接"或者 "相连"等类似的词语并非限定于物理的或者 机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置 改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个像素的薄 膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线电连 接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述主要 针对单个或多个像素单元进行， 但是其他像素单元可以相同地形成。
参照图 9, 详细描述根据本发明实施例的阵列基板的制造方法。
在步骤 91 , 在基板上形成栅电极和栅线； 如图 2所示， 首先， 可以采用溅射、 热蒸发或其它成膜方法， 在玻璃基 板 101或其他类型的透明基板上面形成栅金属层，栅金属层可以采用铬 ( Cr )、 钼 （Mo )、 铝（Al )、 铜（Cu )、 钨（W )、 钕（Nd )、 铟锌氧化物（IZO )、 铟 锡氧化物（ITO )及其合金中的任何一种， 并且， 栅金属层可以为一层或多 层； 然后， 在栅金属层上形成光刻胶； 其次， 通过使用具有图形的掩膜板对 光刻胶进行曝光和显影， 形成光刻胶掩膜； 再次， 通过使用光刻胶掩膜对栅 金属层进行刻蚀， 形成栅电极 201和栅线的图形； 最后， 剥离剩余的光刻胶。
在步骤 92, 在完成步骤 91的基板上形成栅绝缘层， 并在栅绝缘层上形 成有源层；
如图 3所示， 可以采用等离子体增强化学气相沉积（PECVD )等方法， 在所述基板 101上沉积栅绝缘层 301。 其中， 栅绝缘层 301可以选用氧化物 (例如 SiOx )或者氮化物（例如 SiNx )等材料， 也可以为两种的组合。
形成有源层的方法为： 如图 4a和图 4b所示（图 4a为截面图， 图 4b为 平面图）， 首先， 可以采用溅射等方法， 在所述基板 101上形成半导体层， 半 导体层可以为金属氧化物半导体层，其材料可以为 ZnO基材料或者 IGZO基 材料， 其厚度在 200〜2000A之间； 然后， 在半导体层上形成光刻胶； 其次， 采用具有图形的掩膜板对光刻胶进行曝光和显影， 形成光刻胶掩膜； 再次， 采用光刻胶掩膜对半导体层进行刻蚀， 形成有源层 401的图形； 最后， 剥离 剩余的光刻胶。 其中， 有源层 401可以为块状图形。
步骤 93 , 在完成步骤 92的基板上形成刻蚀阻挡层， 采用第一掩膜板进 行光刻后， 刻蚀出源电极接触孔和漏电极接触孔；
如图 5a和图 5b所示（图 5a为截面图， 图 5b为平面图）， 首先， 可以釆 用 PECVD等方法， 在所述基板 101上形成刻蚀阻挡层 501， 刻蚀阻挡层 501 可以采用 SiNx或 SiOx等材料， 也可以为两种的組合， 其厚度在 200 2000A 之间； 然后， 在刻蚀阻挡层 501上形成光刻胶； 其次， 采用具有图形的掩膜 板（称之为第一掩模板）对光刻胶进行曝光和显影， 形成光刻胶掩膜； 再次， 通过釆用光刻胶掩膜对刻蚀阻挡层 501进行刻蚀， 形成第一接触孔（源电极 接触孔） 502和第二接触孔（漏电极接触孔） 503 ; 最后， 剥离剩余的光刻胶。
如图 5b所示，源电极接触孔 502和漏电极接触孔 503的长度（指沿栅线 方向的长度 )为有源开关的 W， 源电极接触孔 502和漏电极接触孔 503之间 的距离（在图 5b中，指源电极接触孔 502的上边和漏电极接触孔 503的下边 之间的距离）为有源开关的 L。 由于刻蚀阻挡层 501全部覆盖基板， 不会产 生现有技术的对位偏差问题， 且薄膜晶体管的宽长比（W/L )可以根据实际 工艺情况通过曝光设备进行微调， 器件特性可微控， 工艺条件灵活。 在本实 施例中， W在 2〜30um之间， L在 2〜30um之间。
步骤 94， 在完成步骤 93的基板上形成源电极、 漏电极和数据线； 如图 6a和图 6b所示（图 6a为截面图， 图 6b为平面图）， 首先， 可以采 用溅射、 热蒸发或其它成膜方法， 在所述基板 101上面形成源漏金属层， 源 漏栅金属层可以釆用铬（Cr )、 钼 （Mo )、 铝（Al )、 铜（Cu )、 钨（W )、 钕 ( Nd )、 铟锌氧化物（IZO )、 铟锡氧化物 （ITO )及其合金的其中之一， 并 且， 源漏金属层可以为一层或多层； 然后， 在源漏金属层上形成光刻胶； 其 次， 采用具有图形的掩膜板对光刻胶进行曝光和显影， 形成光刻胶掩膜； 再 次， 采用光刻胶掩膜对源漏金属层进行刻蚀， 形成源电极 601、 漏电极 602 和数据线的图形； 最后， 剥离剩余的光刻胶。 其中， 源电极 601通过源电极 接触孔 502与有源层 401连接， 漏电极 602通过漏电极接触孔 503与有源层 401连接。
步骤 95 , 在完成步骤 94的基板上形成钝化层， 通过采用所述第一掩膜 板进行光刻后， 刻蚀出像素电极接触孔；
如图 7a和图 7b所示（图 7a为截面图， 图 7b为平面图）， 首先， 可以采 用 PECVD等方法， 在所述基板 101上形成钝化层 701， 钝化层 701可以采 用 SiNx或 SiOx等材料， 也可以为两种的组合； 然后， 在钝化层 701上形成 光刻胶； 其次， 釆用具有图形的掩膜板（即前述的第一掩模板）对光刻胶进 行曝光和显影， 形成光刻胶掩膜； 再次， 采用光刻胶掩膜对刻蚀阻挡层 701 进行刻蚀，形成第三接触孔 702和第四接触孔（像素电极接触孔） 703; 最后， 剥离剩余的光刻胶。
在本步骤中， 采用了和形成刻蚀阻挡层的图形时相同的掩膜板， 并刻蚀 出用于像素电极与漏电极 602连接的第四接触孔 703。 需要说明的是， 本步 骤同时也刻蚀出了和第一接触孔 502完全对应的第三接触孔 702， 第三接触 孔 702的产生不会影响本工序复杂性以及后续的工艺复杂性， 对薄膜晶体管 的产品特性也不产生影响。 步骤 96, 在完成步骤 95的基板上形成像素电极， 所述像素电极通过像 素电极接触孔与漏电极连接。
如图 8a和图 8b所示（图 8a为截面图， 图 8b为平面图）， 首先， 可以采 用磁控溅射、 热蒸发或其它成膜方法， 在所述基板 101上形成透明导电层， 透明导电层可以釆用氧化铟锡（ ITO )、 氧化铟锌（ IZO )或氧化铝锌等材料； 然后， 在透明导电层上形成光刻胶； 其次， 采用具有图形的掩膜板对光刻胶 进行曝光和显影， 形成光刻胶掩膜； 再次， 采用光刻胶掩膜对透明导电层进 行刻蚀， 形成像素电极 801的图形， 所述像素电极 801通过像素电极接触孔 703与漏电极 602连接； 最后， 剥离剩余的光刻胶。
需要说明的是， 在本步骤中， 还会在第三接触孔 702中形成透明导电部 分 802， 但是， 由于像素电极 801和透明导电部分 802不相连， 且该部分在 栅电极 201上方， 因此透明导电部分 802的存在不会对显示性能和显示品质 产生影响。
根据本发明上述实施例的制造方法， 在刻蚀阻挡层上形成接触孔和在钝 化层上形成接触孔， 采用的是同一块掩膜板， 因此减少了掩膜板数量， 节约 了成本。 刻蚀阻挡层全部覆盖基板， 不会产生现有技术对位偏差的问题， 且 对透过率没有影响。 由于有源开关的 W和 L通过刻蚀阻挡层掩膜板直接曝 光， 因此 W/L可以根据实际工艺情况通过曝光设备进行微调， 器件特性可微 控， 工艺条件灵活。 像素电极接触孔位于栅电极上方漏电极上方， 不会产生 现有技术像素电极接触孔位于像素部分而引起的开口率的降低， 提高了产品 的开口率。
本发明实施例还提供一种阵列基板， 在该阵列基板中， 刻蚀阻挡层上形 成有第一接触孔和第二接触孔， 飩化层上形成有第三接触孔和第四接触孔， 由于形成这些接触孔采用的是同一块掩膜板， 因此， 第一接触孔与第三接触 孔的形状相同， 且位置对应 （即， 所述第一接触孔在基板上的正投影与所述 第三接触孔在基板上的正投影重合 ); 第二接触孔与第四接触孔的形状相同， 且位置对应 （即， 所述第二接触孔在基板上的正投影与所述第四接触孔在基 板上的正投影重合）
参照图 8a和图 8b, 根据本发明实施例的阵列基板可以包括：
形成在基板 101上的栅电极 201和栅线； 形成在形成有栅电极 201和栅线的基板 101上的栅绝缘层 301 ;
形成在栅绝缘层 301上的有源层 401 ;
形成在形成有有源层 401的基板 101上的具有源电极接触孔 502和漏电 极接触孔 503的刻蚀阻挡层 501 ;
形成在形成有刻蚀阻挡层 501的基板 101上的源电极 601、 漏电极 602 和数据线，源电极 601通过源电极接触孔 502与有源层 401连接，漏电极 602 通过漏电极接触孔 503与有源层 401连接；
形成在形成有源电极 601、 漏电极 602和数据线的基板上的具有像素电 极接触孔 703的钝化层 701 , 所述像素电极接触孔 703在基板 101上的正投 影与所述漏电极接触孔 503在基板 101上的正投影重合；
形成在形成有钝化层 701的基板 101上的像素电极 801， 所述像素电极 801通过像素电极接触孔 703与漏电极 602连接。
例如， 所述有源层 401为金属氧化物有源层， 其材料可以为 ZnO基材料 或 IGZO基材料， 其厚度在 200~2000A之间。
例如， 所述像素电极接触孔 703在基板 101上的正投影位于栅电极 201 所处的区域内。
需要说明的是， 在上述阵列基板中， 钝化层 701中还形成有和第一接触 孔 502完全对应的第三接触孔 702, 而且， 在第三接触孔 702中还形成透明 导电部分 802。 但是， 由于像素电极 801和透明导电部分 802不相连， 且该 部分在栅电极 201上方， 因此透明导电部分 802的存在不会对显示性能和显 示品质产生影响。
本发明实施例还提供一种显示面板， 所述显示面板包括上述的任一种阵 列基板。
本发明实施例还提供一种显示装置， 所述显示装置包括上述的任一种阵 列基板。 所述显示装置可以为： 液晶面板、 电子纸、 手机、 平板电脑、 电视 机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或 部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1.一种阵列基板， 包括：
形成在形成有有源层的基板上的具有源电极接触孔和漏电极接触孔的刻 蚀阻挡层；
形成在形成有刻蚀阻挡层的基板上的源电极、 漏电极和数据线， 源电极 通过源电极接触孔与有源层连接， 漏电极通过漏电极接触孔与有源层连接； 形成在形成有源电极、 漏电极和数据线的基板上的具有像素电极接触孔 的钝化层， 所迷像素电极接触孔在基板上的正投影与所述漏电极接触孔在基 板上的正投影重合；
形成在形成有钝化层的基板上的像素电极， 所述像素电极通过像素电极 接触孔与漏电极连接。
2. 如权利要求 1所述的阵列基板， 还包括：
形成在基板上的栅电极和栅线；
形成在形成有栅电极和栅线的基板上的栅绝缘层；
形成在栅绝缘层上的有源层。
3. 如权利要求 1或 2所述的阵列基板， 其中：
所述有源层为金属氧化物有源层。
4. 如权利要求 1至 3的任一项所述的阵列基板， 其中：
所述像素电极接触孔在基板上的正投影位于栅电极所处的区域内。
5. 如权利要求 1至 4的任一项所述的阵列基板， 其中：
所述刻蚀阻挡层全部覆盖所述基板。
6. 一种阵列基板的制造方法， 包括：
在形成有有源层的基板上形成刻蚀阻挡层，采用第一掩膜板进行光刻后， 刻蚀出源电极接触孔和漏电极接触孔；
在形成有刻蚀阻挡层的基板上形成源电极、 漏电极和数据线， 源电极通 过源电极接触孔与有源层连接， 漏电极通过漏电极接触孔与有源层连接； 在形成有源电极、 漏电极和数据线的基板上形成钝化层， 釆用所述第一 掩膜板进行光刻后， 刻蚀出像素电极接触孔；
在形成有钝化层的基板上形成像素电极， 所述像素电极通过像素电极接 触孔与漏电极连接。
7. 如权利要求 6所述的制造方法，其中，在形成刻蚀阻挡层之前还包括: 在基板上形成栅电极和栅线；
在形成有栅电极和栅线的基板上形成栅绝缘层；
在栅绝缘层上形成有源层。
8. 如权利要求 6或 7所述的制造方法， 其中：
所述有源层为金属氧化物有源层。
9.一种显示面板， 包括权利要求 1至 5中任一项所述的阵列基板。
10.—种显示装置， 包括权利要求 1至 5中任一项所述的阵列基板。
PCT/CN2012/084166 2012-05-25 2012-11-06 阵列基板、其制造方法、显示面板及显示装置 WO2013174105A1 (zh)

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