WO2015180357A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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WO2015180357A1
WO2015180357A1 PCT/CN2014/088079 CN2014088079W WO2015180357A1 WO 2015180357 A1 WO2015180357 A1 WO 2015180357A1 CN 2014088079 W CN2014088079 W CN 2014088079W WO 2015180357 A1 WO2015180357 A1 WO 2015180357A1
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Prior art keywords
electrode
photoresist
region
array substrate
layer
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PCT/CN2014/088079
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English (en)
French (fr)
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孙双
崔承镇
牛菁
张方振
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京东方科技集团股份有限公司
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Priority to US14/443,474 priority Critical patent/US9627421B2/en
Priority to EP14861123.9A priority patent/EP3151279B1/en
Publication of WO2015180357A1 publication Critical patent/WO2015180357A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the TFT-LCD can be classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field driving the liquid crystal.
  • the vertical electric field type includes a twisted nematic type
  • the horizontal electric field type includes an Advanced Super Dimension Switch (ADS) type and an In-Plane Switching (IPS) type.
  • ADS Advanced Super Dimension Switch
  • IPS In-Plane Switching
  • the horizontal electric field type TFT-LCD especially the ADS type TFT-LCD, has a wide viewing angle and a high aperture ratio and is widely used.
  • high transmittance-Advanced Super Dimension Switch (HADS) mode TFT-LCDs have received increasing attention.
  • At least one embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device for solving the cumbersome manufacturing process of the TFT-LCD array substrate of the prior art, and the cost of the conductive material of the source/drain layer is easily corroded during fabrication.
  • Technical problem is a problem that
  • At least one embodiment of the present invention provides an array substrate including: a pixel electrode including a display region portion and a non-display region portion; a first electrode formed on the non-display region of the pixel electrode; a pixel electrode and a passivation layer on the first electrode, the passivation layer including a via hole over the first electrode; an active layer and a second electrode formed on the passivation layer, The active layer connects the first electrode through a via of the passivation layer.
  • At least one embodiment of the present invention provides a display device comprising the array substrate of any of the above.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate, comprising: forming a pattern including a pixel electrode and a first electrode, wherein the pixel electrode includes a display area portion and a non-display area portion a first electrode is located on a non-display area of the pixel electrode;
  • the passivation layer Forming a pattern of a passivation layer on the pixel electrode and the first electrode, the passivation layer including a via hole over the first electrode;
  • a pattern including an active layer and a second electrode is formed on the passivation layer, the active layer connecting the first electrode through a via of the passivation layer.
  • FIG. 1 is a schematic structural view of a HADS mode TFT-LCD array substrate
  • FIG. 2 is a schematic view showing the basic structure of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of an array substrate according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing the basic flow of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural view showing formation after the first photolithography etching in Embodiment 1 of the present invention.
  • FIG. 7 is a schematic view showing a structure after a second photolithography etching in Embodiment 1 of the present invention.
  • Embodiment 8 is a schematic view showing a structure after a third photolithography etching in Embodiment 1 of the present invention.
  • Embodiment 9 is a schematic structural view of forming a fourth photolithography etching in Embodiment 1 of the present invention.
  • FIG. 10 is a schematic structural view of an array substrate according to another embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a HADS mode TFT-LCD array substrate.
  • the first patterning process forms a pattern of the gate electrode 2 and the gate line on the glass substrate 1; deposits the gate insulating layer 3; forms a pattern of the active layer 4 by a second patterning process; and forms a data line through the third patterning process And a pattern of the source 6, the drain 7, and the TFT channel; forming a pattern of the pixel electrode 8 by a fourth patterning process; forming a pattern of the passivation layer 9 by a fifth patterning process; forming a common electrode by the sixth patterning process 10 graphics.
  • an etch protection layer is generally formed after the active layer 4 is formed before the source 6 and the drain 7 are formed. 5, therefore, a patterning process will be added again, so the number of masks used is relatively large and the cost is relatively high.
  • the conductive material of the source-drain layer of the TFT-LCD generally uses a low-resistance material such as copper.
  • a low-resistance material such as copper.
  • the patterning process of the pixel electrode 8 is usually performed after the source 6 and the drain 7 are completed, but if the pixel electrode 8 is prepared using ITO, the etching solution for ITO (indium tin oxide) is used. There is contact and corrosion of copper, which deteriorates the electrical characteristics of the copper electrode.
  • the method includes a pixel electrode 8 including a display region portion a and a non-display region portion b.
  • the pixel electrode 8 is formed on the non-display region b of the pixel electrode 8.
  • the array substrate may further include: a common electrode 10, as shown in FIG. 3, on the passivation layer 9, which is formed by the plasma treatment of the display region of the active layer 4 corresponding to the pixel electrode 8 Slit-like.
  • the array substrate may further include: an etch protection layer 5 formed on the active layer 4 and the second electrode 7.
  • the array substrate may be a top gate structure or a bottom gate structure.
  • the array substrate may further include: a gate electrode 2 and a gate line formed on the glass substrate 1, formed on the gate electrode 2 and A gate insulating layer 3 is formed on the gate line, and a pixel electrode 8 is formed on the gate insulating layer 3.
  • the first electrode 6 and the second electrode 7 may be a source and a drain, respectively.
  • the material of the gate 2, the first electrode 6, and the second electrode 7 may be Copper or copper alloy to reduce the signal delay of the array substrate.
  • the position of the second electrode 7 may not overlap with the first electrode 6.
  • At least one embodiment of the present invention provides a display device comprising the array substrate of any of the above.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate. Referring to FIG. 4, the method includes:
  • Step 401 Form a pattern including a pixel electrode and a first electrode, the pixel electrode including a display region portion and a non-display region portion, the first electrode being located on a non-display region of the pixel electrode.
  • Step 402 forming a pattern of a passivation layer on the pixel electrode and the first electrode, the passivation layer including a via hole on the first electrode.
  • Step 403 forming a pattern including an active layer and a second electrode on the passivation layer, the active layer connecting the first electrode through a via of the passivation layer.
  • the manufacturing method may further include: performing plasma processing on a portion of the display region corresponding to the pixel electrode of the active layer to metallize it to form a common electrode.
  • the manufacturing method may further include: forming a pattern of the etch protection layer on the active layer and the second electrode.
  • the manufacturing method may further include: forming a pattern including a gate electrode and a gate line on the glass substrate, forming a pattern of the gate insulating layer on the gate and the gate line, and forming a pixel electrode on the gate insulating layer .
  • the photoresist development and the two etchings may be performed by one photoresist exposure to form a pattern including the pixel electrode and the first electrode, and the steps may be:
  • the photoresist is stripped to form a pattern including the pixel electrode and the first electrode.
  • a photoresist exposure development and two etchings may also be performed to form a pattern including an active layer, a second electrode, and a data line, the steps of which may be:
  • a second photoresist completely reserved region After coating the second photoresist on the second electrode layer film and exposing and developing using the gray mask, forming a second photoresist completely reserved region, the second photoresist semi-reserved region and the second photoresist are completely removed.
  • the first electrode and the second electrode may be a source and a drain, respectively.
  • the material of the gate electrode, the first electrode, and the second electrode may be copper or a copper alloy to reduce signal delay of the array substrate.
  • the position of the second electrode may not overlap with the first electrode.
  • Embodiment 1 of the present invention provides a method for fabricating a TFT-LCD array substrate to explain in detail a specific implementation process of the embodiment of the present invention. See FIG. 5:
  • Step 501 depositing a gate film on the glass substrate, forming a pattern including a gate electrode and a gate line by photolithography etching, and connecting electrodes of the common electrode.
  • the material of the deposited gate film is copper.
  • the gate film of the glass substrate 1 is exposed, developed, and then etched using a common mask to form a pattern of the gate electrode 2 and the gate line, and a connection electrode of the common electrode 10. See Figure 6.
  • Step 502 depositing a gate insulating layer film, a transparent conductive layer film, and a drain layer film, Photolithography etching forms a pattern including a gate insulating layer, a pixel electrode, and a drain.
  • a gate insulating layer film, a transparent conductive layer film, and a drain layer film are first deposited, respectively.
  • the material for the gate insulating film is SiNx
  • the material for the transparent conductive film is ITO
  • the material for the drain film is copper.
  • the first photoresist completely reserved region corresponds to the pre-formed drain region, corresponding to the non-display region of the pixel electrode, and the first photoresist semi-reserved region corresponds to a region of the display region portion pre-formed into the pixel electrode, the first photoresist
  • the completely removed area corresponds to an area other than the above area.
  • the photoresist is stripped to form a pattern including the gate insulating layer 3, the pixel electrode 8 and the drain electrode 6, see FIG.
  • Step 503 depositing a passivation layer film, forming a pattern of a passivation layer on the gate insulating layer, the pixel electrode and the drain by photolithography, wherein the passivation layer comprises a via hole on the drain.
  • a passivation layer film is first deposited, for example, the material used is SiNx. Photolithography is then performed using a conventional mask to form a pattern of passivation layer 9.
  • the passivation layer 9 includes a via hole 11 above the drain electrode 6, corresponding to the position where the active layer 4 and the drain electrode 6 are in contact, the position of the gate line interface, and the position at which the common electrode 10 is connected to the connection electrode, as shown in FIG. .
  • Step 504 depositing an active layer film and a source layer film, and forming a pattern including an active layer, a source, and a data line by photolithography etching.
  • an active layer film and a source layer film are first deposited on the passivation layer, the active layer film is made of IGZO, and the source layer film material is copper.
  • the second photoresist completely reserved region corresponds to the pre-formed source region and the data line region.
  • the position of the source region does not overlap with the drain.
  • the source location may also overlap with the drain.
  • the second photoresist semi-reserved area corresponds to a pre-formed active layer region, where the active layer region is further
  • the region including the pre-formed common electrode and the gate line interface corresponds to the display region of the pixel electrode, and the second photoresist completely removed region corresponds to a region other than the above region.
  • the photoresist is stripped to form a pattern including the source 7 and the active layer 4, wherein the source 7 is connected to the data line, and the active layer 4 is connected to the drain 6 through the via 11 as shown in FIG.
  • Step 505 depositing an etch protection layer film, forming a pattern of the etch protection layer by photolithography etching, and performing plasma treatment on the portion of the display region corresponding to the pixel electrode of the active layer to metallize to form a common electrode pattern And a conductive material connected to the gate line.
  • the material of the etch protection layer film is SiO2
  • photolithography is performed using a common mask to form a pattern of the etch protection layer 5.
  • the IGZO active layer material exposed on the surface of the pre-formed common electrode region is subjected to plasma treatment to be metallized to form a common electrode 10 pattern and a conductive material located in the gate line interface via hole connecting the gate line, and finally
  • the formed array substrate is as shown in FIG.
  • the first electrode and the second electrode as the source and the drain are formed over the ITO material as the pixel electrode, thereby making the conductive material etched when the ITO material is etched.
  • photoresist protection which avoids the contact between the conductive material and the etchant of the ITO material, greatly reduces the corrosion effect of the etching solution on the conductive material, and improves the quality of the array substrate.
  • the TFT-LCD array substrate can be fabricated only by five mask processes, which saves production time and reduces manufacturing cost.
  • the array substrate being of a top gate type, comprising a glass substrate 101 and a pixel electrode 108 formed on the glass substrate 101, the pixel electrode 8 also including a display Partial and non-display area parts.
  • Non-pixel electrode 108 A first electrode 106 is formed on the display region, a passivation layer 109 is formed on the pixel electrode 108 and the first electrode 106, and the passivation layer 109 includes a via 111 on the first electrode 106; on the passivation layer 109 Forming an active layer 104 and a second electrode 107, the active layer 104 is connected to the first electrode 106 through the via 111 of the passivation layer 109; a gate insulating layer 103 is formed over the active layer 104 and the second electrode 107; A gate electrode 102 is formed over the gate insulating layer 103.
  • a method of forming a pattern including a pixel electrode and a first electrode, a pattern of a passivation layer, a pattern including an active layer and a second electrode, and a step 401 described above in connection with FIG. 4 are formed in the method of fabricating the top gate type array substrate.
  • ⁇ 403 is the same, will not be detailed here.
  • the manufacturing method may further include: forming a gate insulating layer on the pattern including the active layer and the second electrode, and then forming a pattern including a gate and a gate line on the gate insulating layer, forming on the gate and the gate line A pattern of a gate insulating layer on which a pixel electrode is formed.

Abstract

一种阵列基板及其制作方法和显示装置。该显示装置包括：像素电极（8），像素电极（8）包括显示区域部分（a）和非显示区域部分（b）；形成在像素电极（8）的非显示区域（b）上的第一电极（6）；形成在像素电极（8）和第一电极（6）上的钝化层（9），钝化层（9）包括位于第一电极（6）之上的过孔（11）；形成在钝化层（9）上的有源层（4）和第二电极（7），有源层（4）通过钝化层（9）的过孔（11）连接第一电极（6）。该阵列基板及其制作方法降低了制作成本，减少了对电极材料的腐蚀，提高了阵列基板的质量。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明的实施例涉及阵列基板及其制作方法和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有体积小、功耗低、无辐射等特点而备受关注，在平板显示领域中占据了主导地位，被广泛的应用到各行各业中。
TFT-LCD根据驱动液晶的电场方向可分为垂直电场型与水平电场型。垂直电场型包括扭曲向列型，水平电场型包括高级超维场转换(ADvanced Super Dimension Switch，ADS)型和共平面切换(In-Plane Switching，IPS)型。水平电场型TFT-LCD，尤其是ADS型TFT-LCD，具有宽视角，开口率高等优点而被广泛的应用。特别地，高透过率-高级超维场转换(High transmittance-Advanced Super Dimension Switch，HADS)模式TFT-LCD越来越受到重视。
发明内容
本发明至少一实施例提供一种阵列基板及其制作方法和显示装置，以解决现有技术的TFT-LCD阵列基板制作工艺繁琐，成本较高且源漏层的导电材料在制作中易被腐蚀的技术问题。
本发明至少一实施例提供一种阵列基板，包括：像素电极，所述像素电极包括显示区域部分和非显示区域部分；形成在所述像素电极的非显示区域上的第一电极；形成在所述像素电极和所述第一电极上的钝化层，所述钝化层包括位于所述第一电极之上的过孔；形成在所述钝化层上的有源层和第二电极，所述有源层通过所述钝化层的过孔连接所述第一电极。
本发明至少一实施例还提供一种显示装置，包括如上任一项所述的阵列基板。
本发明至少一实施例还提供一种阵列基板制作方法，包括：形成包括像素电极和第一电极的图形，所述像素电极包括显示区域部分和非显示区域部 分，所述第一电极位于所述像素电极的非显示区域上；
在所述像素电极和第一电极上形成钝化层的图形，所述钝化层包括位于所述第一电极之上的过孔；
在所述钝化层上形成包括有源层和第二电极的图形，所述有源层通过所述钝化层的过孔连接所述第一电极。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是一种HADS模式TFT-LCD阵列基板结构示意图；
图2是本发明一实施例阵列基板的基本结构示意图；
图3是本发明另一实施例阵列基板的结构示意图；
图4是本发明实施例阵列基板制作方法的基本流程示意图；
图5是本发明实施例1阵列基板制作方法的流程示意图；
图6是本发明实施例1中第一次光刻刻蚀后形成结构示意图；
图7是本发明实施例1中第二次光刻刻蚀后形成结构示意图；
图8是本发明实施例1中第三次光刻刻蚀后形成结构示意图；
图9是本发明实施例1中第四次光刻刻蚀后形成结构示意图；
图10是本发明另一实施例阵列基板的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
在制造HADS模式TFT-LCD的阵列基板的制备过程中，构图次数比较多，例如，量产中一般采用六次构图工艺。图1是一种HADS模式TFT-LCD阵列基板结构示意图。对于如图1所示的阵列基板结构，在制备过程，通过 第一次构图工艺在玻璃基板1上形成栅极2和栅线的图形；沉积栅极绝缘层3；通过第二次构图工艺形成有源层4的图形；通过第三次构图工艺形成数据线以及源极6、漏极7和TFT沟道的图形；通过第四次构图工艺形成像素电极8的图形；通过第五次构图工艺形成钝化层9图形；通过第六次构图工艺形成公共电极10图形。如果有源层4使用金属氧化物，为了保护金属氧化物免受外界环境的影响，一般还要在形成有源层4之后，形成源极6和漏极7之前，形成一层刻蚀保护层5，因此又会增加一次构图工艺，因此掩模板使用数量比较多，成本比较高。
另外，为了减少信号延迟，TFT-LCD的源漏层的导电材料一般使用低电阻材料，如铜。在HADS技术中，通常是在制作完成源极6和漏极7之后，再进行像素电极8的构图工艺，但是如果像素电极8使用ITO制备，则用于ITO(氧化铟锡)的刻蚀液会对铜有接触和腐蚀，从而使铜电极的电学特性变差。
本发明至少一实施例提供一种阵列基板，参见图2，其包括：像素电极8，像素电极8包括显示区域部分a和非显示区域部分b；形成在像素电极8的非显示区域b上的第一电极6；形成在像素电极8和第一电极6上的钝化层9，钝化层9包括位于第一电极6之上的过孔11；形成在钝化层9上的有源层4和第二电极7，有源层4通过钝化层9的过孔11连接第一电极6。
本发明至少一实施例中，阵列基板还可以包括：公共电极10，见图3，位于钝化层9上，为有源层4对应像素电极8的显示区域部分经等离子体处理后形成，呈狭缝状。
本发明至少一实施例中，阵列基板还可以包括：形成在有源层4和第二电极7上的刻蚀保护层5。
本发明至少一实施例中，阵列基板可以为顶栅结构，也可以为底栅结构。例如，当本实施例中的阵列基板为底栅结构时，如图2、3所示，阵列基板还可以包括：形成在玻璃基板1上的栅极2和栅线，形成在栅极2和栅线上的栅绝缘层3，栅绝缘层3上形成有像素电极8。
本发明至少一实施例中，第一电极6和第二电极7可以分别为源极和漏极。
本发明至少一实施例中，栅极2、第一电极6、第二电极7的材料可以为 铜或铜合金，以减少阵列基板的信号延迟。
本发明至少一实施例中，第二电极7的位置可以不与第一电极6重叠。
本发明至少一实施例还提供一种显示装置，包括如上任一项所述的阵列基板。
本发明至少一实施例还提供一种阵列基板制作方法，参见图4，包括：
步骤401：形成包括像素电极和第一电极的图形，所述像素电极包括显示区域部分和非显示区域部分，所述第一电极位于所述像素电极的非显示区域上。
步骤402：在所述像素电极和第一电极上形成钝化层的图形，所述钝化层包括位于第一电极之上的过孔。
步骤403：在所述钝化层上形成包括有源层和第二电极的图形，所述有源层通过所述钝化层的过孔连接所述第一电极。
本发明至少一实施例中，该制作方法还可以包括：对有源层对应像素电极的显示区域部分进行等离子体处理，使其金属化，形成公共电极。
本发明至少一实施例中，该制作方法还可以包括：在有源层和第二电极上形成刻蚀保护层的图形。
本发明至少一实施例中，该制作方法还可以包括：在玻璃基板上形成包括栅极和栅线的图形，在栅极和栅线上形成栅绝缘层的图形，栅绝缘层上形成像素电极。
例如，在一个示例中，可以通过一次光刻胶曝光显影和两次刻蚀以形成包括像素电极和第一电极的图形，其步骤可以为：
依次形成透明导电层薄膜和第一电极层薄膜；
在第一电极层薄膜上涂第一光刻胶并使用灰度掩膜板曝光显影，形成第一光刻胶完全保留区域，第一光刻胶半保留区域和第一光刻胶完全去除区域，第一光刻胶完全保留区域对应预形成第一电极区域，第一光刻胶半保留区域对应预形成像素电极的显示区域部分的区域，第一光刻胶完全去除区域对应除上述区域之外的区域；
进行一次刻蚀，刻蚀掉第一光刻胶完全去除区域的第一电极层薄膜和透明导电层薄膜，对第一光刻胶进行灰化处理，使得第一光刻胶完全保留区域的光刻胶变薄，第一光刻胶半保留区域的光刻胶被完全去除，然后进行二次 刻蚀，刻蚀掉第一光刻胶半保留区域的第一电极层薄膜；
剥离光刻胶，形成包括像素电极和第一电极的图形。
例如，在另一个示例中，还可以通过一次光刻胶曝光显影和两次刻蚀以形成包括有源层、第二电极和数据线的图形，其步骤可以是：
在钝化层上依次形成有源层薄膜和第二电极层薄膜；
在第二电极层薄膜上涂第二光刻胶并使用灰度掩膜板曝光显影后，形成第二光刻胶完全保留区域，第二光刻胶半保留区域和第二光刻胶完全去除区域，第二光刻胶完全保留区域对应预形成第二电极区域和数据线区域，第二光刻胶半保留区域对应预形成有源层区域，上述有源层区域可以包括预形成公共电极的部分，第二光刻胶完全去除区域对应除上述区域之外的区域；
进行一次刻蚀，刻蚀掉第二光刻胶完全去除区域的第二电极层薄膜和有源层薄膜，对第二光刻胶进行灰化处理，使得第二光刻胶完全保留区域的光刻胶变薄，第二光刻胶半保留区域的光刻胶被完全去除，然后进行二次刻蚀，刻蚀掉第二光刻胶半保留区域的第二电极层薄膜；
剥离光刻胶，形成包括第二电极、数据线和有源层的图形，此时有源层还包括预形成公共电极的区域，这部分区域可以经后续的等离子处理后金属化，直接形成公共电极，以减少制作步骤。
本发明至少一实施例中，第一电极和第二电极可以分别为源极和漏极。
本发明至少一实施例中，栅极、第一电极、第二电极的材料可以为铜或铜合金，以减少阵列基板的信号延迟。
本发明至少一实施例中，第二电极的位置可以不与第一电极重叠。
实施例1：
本发明实施例1提供一种TFT-LCD阵列基板制作方法，以详细说明本发明实施例的具体实现过程，参见图5：
步骤501：在玻璃基板上沉积栅极薄膜，通过光刻刻蚀形成包括栅极和栅线的图形，以及公共电极的连接电极。
本步骤中，所沉积的栅极薄膜的材料为铜。在玻璃基板1的栅极薄膜上使用普通掩膜曝光、显影，然后刻蚀，形成栅极2和栅线的图形，以及公共电极10的连接电极。见图6。
步骤502：沉积栅极绝缘层薄膜、透明导电层薄膜和漏极层薄膜，通过 光刻刻蚀形成包括栅极绝缘层、像素电极和漏极的图形。
本步骤中，首先分别沉积栅极绝缘层薄膜、透明导电层薄膜和漏极层薄膜。例如，栅极绝缘层薄膜所用材料为SiNx，透明导电层薄膜所用材料为ITO，漏极层薄膜所用材料为铜。
在漏极层薄膜上涂第一光刻胶并使用灰度掩膜板曝光显影后，形成第一光刻胶完全保留区域，第一光刻胶半保留区域和第一光刻胶完全去除区域，其中第一光刻胶完全保留区域对应预形成漏极区域，对应像素电极的非显示区域，第一光刻胶半保留区域对应预形成像素电极的显示区域部分的区域，第一光刻胶完全去除区域对应除上述区域之外的区域。
进行一次刻蚀，刻蚀掉第一光刻胶完全去除区域的漏极层薄膜和透明导电层薄膜，对第一光刻胶进行灰化处理，使得第一光刻胶完全保留区域的光刻胶变薄，第一光刻胶半保留区域的光刻胶被完全去除，然后进行二次刻蚀，刻蚀掉第一光刻胶半保留区域的漏极层薄膜。
最后剥离光刻胶，形成包括栅绝缘层3，像素电极8和漏极6的图形，见图7。
步骤503：沉积钝化层薄膜，通过光刻刻蚀在栅极绝缘层、像素电极和漏极上形成钝化层的图形，其中钝化层包括位于漏极之上的过孔。
本步骤中，首先沉积钝化层薄膜，例如所用材料为SiNx。然后使用普通掩膜板进行光刻刻蚀，形成钝化层9的图形。
钝化层9包括过孔11，过孔11在漏极6之上，对应有源层4和漏极6接触的位置，栅线接口位置以及公共电极10与连接电极连接的位置，见图8。
步骤504：沉积有源层薄膜和源极层薄膜，通过光刻刻蚀形成包括有源层、源极和数据线的图形。
本步骤中，首先在钝化层上分别沉积有源层薄膜和源极层薄膜，有源层薄膜所用材料为IGZO，源极层薄膜材料为铜。
在源极层薄膜上涂第二光刻胶并使用灰度掩膜板曝光显影后，形成第二光刻胶完全保留区域，第二光刻胶半保留区域和第二光刻胶完全去除区域，第二光刻胶完全保留区域对应预形成源极区域和数据线区域。本实施例中源极区域的位置不与漏极重叠，在本发明的其他实施例中源极位置也可以与漏极重叠。第二光刻胶半保留区域对应预形成有源层区域，此处有源层区域还 包括预形成公共电极和栅线接口的区域，对应像素电极的显示区域，第二光刻胶完全去除区域对应除上述区域之外的区域。
进行一次刻蚀，刻蚀掉第二光刻胶完全去除区域的源极层薄膜和有源层薄膜，对第二光刻胶进行灰化处理，使得第二光刻胶完全保留区域的光刻胶变薄，第二光刻胶半保留区域的光刻胶被完全去除，然后进行二次刻蚀，刻蚀掉第二光刻胶半保留区域的源极层薄膜。
剥离光刻胶，形成包括源极7和有源层4的图形，其中源极7与数据线连接，有源层4通过过孔11与漏极6相连，见图9。
步骤505：沉积刻蚀保护层薄膜，通过光刻刻蚀形成刻蚀保护层的图形，并对有源层对应像素电极的显示区域的部分进行等离子体处理，使其金属化，形成公共电极图形和与栅线连接的导电材料。
本步骤中，例如，刻蚀保护层薄膜的材料为SiO2，在沉积刻蚀保护层薄膜后使用普通掩膜板进行光刻刻蚀，形成刻蚀保护层5的图形。然后，对暴露在表面的位于预形成公共电极区域的IGZO有源层材料进行等离子体处理，使其金属化，形成公共电极10图形和位于栅线接口过孔内连接栅线的导电材料，最终形成的阵列基板即如图3所示。
至此，则完成了本发明实施例HADS模式TFT-LCD阵列基板制作方法的全过程。
可见，本发明的上述实施例至少具有如下有益效果。
在本发明实施例的阵列基板及其制作方法和显示装置中，作为源极和漏极的第一电极和第二电极形成在作为像素电极的ITO材料上方，从而使得在刻蚀ITO材料时导电材料的绝大部分表面均覆盖有光刻胶保护，避免了导电材料与ITO材料刻蚀液接触，大大减少了刻蚀液对导电材料的腐蚀作用，提高了阵列基板的质量。
另外，在本发明提供的阵列基板及其制作方法和显示装置中，仅需通过5次掩模工艺即可制成TFT-LCD阵列基板，节省了制作时间，降低了制作成本。
图10示出了发明至少一实施例提供阵列基板的结构，该阵列基板是顶栅型的，其包括玻璃基板101以及形成在玻璃基板101之上的像素电极108，该像素电极8也包括显示区域部分和非显示区域部分。在像素电极108的非 显示区域上形成有第一电极106，在像素电极108和第一电极106上形成有钝化层109，钝化层109包括位于第一电极106之上的过孔111；在钝化层109上形成有有源层104和第二电极107，有源层104通过钝化层109的过孔111连接第一电极106；在有源层104和第二电极107之上形成有栅绝缘层103；在栅绝缘层103之上形成有栅电极102。
该顶栅型的阵列基板的制备方法之中形成包括像素电极和第一电极的图形、钝化层的图形、包括有源层和第二电极的图形的方法与上述结合图4描述的步骤401～403相同，这里不再详述。另外，该制作方法还可以包括：在包括有源层和第二电极的图形上形成栅绝缘层，然后在栅绝缘层上形成包括栅极和栅线的图形，在栅极和栅线上形成栅绝缘层的图形，栅绝缘层上形成像素电极。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
可以理解，执行本发明所披露的制造方法的操作步骤的顺序不限于这里阐述的，除非具体地另外提及。因此，执行本发明所披露的制造方法的操作步骤的顺序可以在本发明的范围内变化，且对于本发明相关领域的普通技术人员显而易见的结果也将被认为在本发明的范围内。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年5月29日递交的中国专利申请第201410234336.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括：
    像素电极，所述像素电极包括显示区域部分和非显示区域部分；形成在所述像素电极的非显示区域上的第一电极；
    形成在所述像素电极和所述第一电极上的钝化层，所述钝化层包括位于所述第一电极之上的过孔；
    形成在所述钝化层上的有源层和第二电极，所述有源层通过所述钝化层的过孔连接所述第一电极。
  2. 根据权利要求1所述的阵列基板，还包括：
    公共电极，所述公共电极位于所述钝化层上，为所述有源层对应所述像素电极的显示区域部分经等离子体处理后形成。
  3. 根据权利要求1或2所述的阵列基板，还包括：
    形成在所述有源层和第二电极上的刻蚀保护层。
  4. 根据权利要求1-3任一项所述的阵列基板，还包括：
    形成在玻璃基板上的栅极和栅线，
    形成在所述栅极和栅线上的栅绝缘层，所述栅绝缘层上形成有所述像素电极。
  5. 根据权利要求1-4任一项所述的阵列基板，其中：
    所述第一电极为源极，所述第二电极为漏极；或，所述第一电极为漏极，所述第二电极为源极。
  6. 根据权利要求4所述的阵列基板，其中：
    所述栅极、第一电极和/或第二电极的材料为铜或铜合金。
  7. 根据权利要求1-6任一项所述的阵列基板，其中：
    所述第二电极的位置不与所述第一电极重叠。
  8. 一种显示装置，包括如权利要求1-7中任一项所述的阵列基板。
  9. 一种阵列基板制作方法，包括：
    形成包括像素电极和第一电极的图形，所述像素电极包括显示区域部分和非显示区域部分，所述第一电极位于所述像素电极的非显示区域上；
    在所述像素电极和第一电极上形成钝化层的图形，所述钝化层包括位于 所述第一电极之上的过孔；
    在所述钝化层上形成包括有源层和第二电极的图形，所述有源层通过所述钝化层的过孔连接所述第一电极。
  10. 根据权利要求9所述的阵列基板制作方法，还包括：
    对所述有源层对应所述像素电极的显示区域部分进行等离子体处理，以形成公共电极。
  11. 根据权利要求9或10所述的阵列基板制作方法，还包括：
    在所述有源层和所述第二电极上形成刻蚀保护层的图形。
  12. 根据权利要求9-11任一项所述的阵列基板制作方法，还包括：
    在玻璃基板上形成包括栅极和栅线的图形，在所述栅极和所述栅线上形成栅绝缘层的图形，所述栅绝缘层上形成像素电极。
  13. 根据权利要求9所述的阵列基板制作方法，其中，
    依次形成透明导电层薄膜和第一电极层薄膜；
    在所述第一电极层薄膜上涂第一光刻胶并使用灰度掩膜板曝光显影，形成第一光刻胶完全保留区域，第一光刻胶半保留区域和第一光刻胶完全去除区域，所述第一光刻胶完全保留区域对应预形成第一电极区域，所述第一光刻胶半保留区域对应预形成像素电极的显示区域部分的区域，所述第一光刻胶完全去除区域对应除上述区域之外的区域；
    进行一次刻蚀，刻蚀掉所述第一光刻胶完全去除区域的第一电极层薄膜和透明导电层薄膜，对第一光刻胶进行灰化处理，使得第一光刻胶完全保留区域的光刻胶变薄，第一光刻胶半保留区域的光刻胶被完全去除，然后进行二次刻蚀，刻蚀掉第一光刻胶半保留区域的第一电极层薄膜；
    剥离光刻胶，形成包括像素电极和第一电极的图形。
  14. 根据权利要求9所述的阵列基板制作方法，其中，
    在所述钝化层上依次形成有源层薄膜和第二电极层薄膜；
    在所述第二电极层薄膜上涂第二光刻胶并使用灰度掩膜板曝光显影后，形成第二光刻胶完全保留区域，第二光刻胶半保留区域和第二光刻胶完全去除区域，所述第二光刻胶完全保留区域对应预形成第二电极区域和数据线区域，所述第二光刻胶半保留区域对应预形成有源层区域，所述第二光刻胶完全去除区域对应除上述区域之外的区域；
    进行一次刻蚀，刻蚀掉所述第二光刻胶完全去除区域的第二电极层薄膜和有源层薄膜，对第二光刻胶进行灰化处理，使得第二光刻胶完全保留区域的光刻胶变薄，第二光刻胶半保留区域的光刻胶被完全去除，然后进行二次刻蚀，刻蚀掉第二光刻胶半保留区域的第二电极层薄膜；
    剥离光刻胶，形成包括第二电极、数据线和有源层的图形。
  15. 根据权利要求12所述的阵列基板制作方法，其中：
    所述栅极、第一电极和/或第二电极的材料为铜或铜合金。
  16. 根据权利要求9所述的阵列基板制作方法，其中：
    所述第二电极的位置不与所述第一电极重叠。
  17. 根据权利要求9至16中任一项所述的阵列基板制作方法，其中：
    所述第一电极为源极，第二电极为漏极；或，所述第一电极为漏极，第二电极为源极。
PCT/CN2014/088079 2014-05-29 2014-10-01 阵列基板及其制作方法和显示装置 WO2015180357A1 (zh)

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