WO2013127202A1 - 阵列基板的制造方法及阵列基板、显示器 - Google Patents

阵列基板的制造方法及阵列基板、显示器 Download PDF

Info

Publication number
WO2013127202A1
WO2013127202A1 PCT/CN2012/084966 CN2012084966W WO2013127202A1 WO 2013127202 A1 WO2013127202 A1 WO 2013127202A1 CN 2012084966 W CN2012084966 W CN 2012084966W WO 2013127202 A1 WO2013127202 A1 WO 2013127202A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
layer
metal oxide
film transistor
active layer
Prior art date
Application number
PCT/CN2012/084966
Other languages
English (en)
French (fr)
Inventor
姚琪
戴天明
张锋
曹占锋
朱佩誉
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/991,371 priority Critical patent/US9099440B2/en
Priority to EP12844653.1A priority patent/EP2822030B1/en
Priority to KR1020137012238A priority patent/KR101530459B1/ko
Priority to JP2014557974A priority patent/JP6092260B2/ja
Publication of WO2013127202A1 publication Critical patent/WO2013127202A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display. Background technique
  • TFTs thin film transistors
  • the TFT includes: a gate, a gate insulating layer, an active layer, a source, and a drain.
  • the mobility of the above TFT actually means the average drift velocity of carriers (electrons and holes) in the active layer of the TFT under the action of a unit electric field.
  • the production of active layers using amorphous silicon has been unable to meet the mobility requirements, and people have turned their attention to metal oxide materials with higher mobility.
  • a source/drain patterning process is performed using an acid to etch a pattern, and a metal oxide material is generally used.
  • An embodiment of the present invention provides a method for fabricating an array substrate, comprising: fabricating an underlying metal thin film on a substrate, and forming at least a gate of the thin film transistor by a patterning process; and fabricating a gate insulating layer covering the gate; Fabricating a metal oxide semiconductor film and a top metal film, and patterning the metal oxide semiconductor film and the top metal film to form an active layer opposite to the gate and a source of the thin film transistor, respectively a drain layer; and a passivation layer covering the source and the drain, and a via hole connecting the pixel electrode is formed at a position of the drain electrode, wherein in the process of patterning the top metal film, a hydrogen peroxide base is used
  • the top metal film is etched by an etchant, and the pH of the etchant is between 6-8.
  • an array substrate including: a pixel unit in the form of an array disposed on a substrate, and including, in each pixel unit: a thin film transistor and a passivation layer covering the thin film transistor;
  • the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer of a metal oxide semiconductor material, and a source/drain; wherein the gate insulating layer and the active layer are further provided for preventing a first isolation layer contacting the gate insulating layer and the active layer; and the material of the first isolation layer is a non-metal oxide material containing no hydrogen.
  • Yet another embodiment of the present invention provides a display including an array substrate in accordance with an embodiment of the present invention.
  • Embodiment 1 is a schematic structural view of an array substrate provided in Embodiment 1;
  • Embodiment 2 is a schematic structural view of another array substrate provided in Embodiment 1;
  • FIG. 3 is a schematic structural view of still another array substrate provided in Embodiment 1;
  • Embodiment 4 is a schematic structural view of an array substrate provided in Embodiment 2;
  • 5A-5G are schematic diagrams showing the steps of fabricating the array substrate shown in FIG. 4;
  • FIG. 6 is a schematic structural diagram of another array substrate provided in Embodiment 2.
  • FIG. 7 is a schematic structural diagram of still another array substrate provided in the second embodiment. detailed description
  • the array substrate includes: pixel units in an array form disposed on the base substrate 100, and includes, in each pixel unit: a thin film transistor, a cover A passivation layer 14 covering the thin film transistor and a pixel electrode 15 disposed horizontally with the thin film transistor are disposed.
  • the thin film transistor includes: a gate electrode 11 a sequentially disposed, a gate insulating layer 12, an active layer 13 of a metal oxide semiconductor material, a source lib/drain 11c; and a drain 11c of the thin film transistor passes through the passivation layer 14 The via is connected to the pixel electrode 15.
  • embodiments of the present invention provide a method of fabricating the above array substrate structure to protect the active layer.
  • a method for fabricating an array substrate according to an embodiment of the present invention includes:
  • S101 forming a bottom metal film on the substrate 100, and forming at least a gate 11a of the thin film transistor by one patterning process;
  • the material of the underlying metal thin film may be any metal such as molybdenum, aluminum, copper, or chromium, or may be an alloy containing these metals.
  • the patterning process may include: a process of applying photoresist, exposure, development, etching, and the like.
  • the exposure process requires the use of a mask to control the exposure of the photoresist in different areas.
  • the number of masks is usually used as the number of patterning processes; that is, the patterning process is performed using a mask to complete the patterning.
  • the material of the gate insulating layer 12 may be a commonly used SiNx (silicon nitride) material.
  • the material of the metal oxide semiconductor may be any metal oxide which can serve as a semiconductor, and may be, for example, IGZO (a metal oxide containing indium, gallium, or rhenium) or IZO (a metal oxide containing indium or rhodium).
  • IGZO a metal oxide containing indium, gallium, or rhenium
  • IZO a metal oxide containing indium or rhodium
  • S104 forming a top metal film, and forming at least a source lib and a drain 11c of the thin film transistor by one patterning process;
  • the composition of the etching liquid used in the patterning process includes: hydrogen peroxide, a top metal ion complexing agent, a stabilizer for hydrogen peroxide, and a surfactant; and the pH of the etching solution is between 6-8;
  • the material of the top metal film may be any metal such as molybdenum, aluminum, copper, or chromium, or an alloy containing at least one of the metals.
  • high requirements for display resolution and switching delay characteristics are considered, because the low resistivity of copper makes the charging time short, and copper is used as the source/drain, and the pixel can be made smaller. , that is, the number of pixels per unit area is increased, so that it can be improved The resolution of the display. Therefore, copper or a copper alloy is preferable as the material of the top metal film in this embodiment.
  • the top metal complexing agent in the present embodiment refers to a compound which can form complex ions with the top metal ion. In the embodiment of the present invention, in the case where the top metal is selected from copper or a copper alloy, the top metal ion complexing agent is selected from a copper ion complexing agent.
  • the content of the hydrogen peroxide solution may be, for example, between 5% and 20%, and the content of the surfactant, for the component of the hydrogen peroxide-based etching solution.
  • the content of the top metal ion complexing agent may be between 1% and 10%, depending on the amount of the top metal to be etched, and the content of the top metal ion complexing agent is generally 1% - Between 25%.
  • a part (for example, 50%) of the top metal complexing agent may be added to the etching liquid, and according to the content of the top metal ion dissolved in the etching liquid.
  • the top metal ion complexing agent may be selected from any suitable complexing agent depending on the material of the top metal film.
  • the stabilizer of the hydrogen peroxide and the surfactant may also be selected from any suitable reagent, and will not be described herein.
  • S105 forming a passivation layer 14 covering the source and the drain, and forming a via hole connecting the pixel electrode 15 at a position of the drain electrode 11c by a patterning process.
  • the material of the passivation layer 14 may be a commonly used SiNx (silicon nitride) material.
  • the method of forming the array substrate shown in Fig. 1 may further include step S106.
  • S106 A transparent conductive film covering the via holes in the S105 is formed, and the pixel electrode 15 is formed by one patterning process.
  • the material of the transparent conductive film may be ITO (Indium Tin Oxide) which is usually used.
  • the method for manufacturing an array substrate provided by the embodiment of the invention etches the top metal film by using a hydrogen peroxide-based etching solution, and the pH of the hydrogen peroxide-based etching solution is between 6 and 8, so that the hydrogen peroxide-based etching solution passes through the oxidation and
  • the method of patterning the top metal film is performed in a complex manner, and the oxide in the etching liquid does not react to the underlying metal oxide semiconductor, and the semiconductor characteristics of the metal oxide are not changed.
  • the array substrate shown in FIG. 2 includes: a pixel unit in the form of an array disposed on the base substrate 100, and Each of the pixel units includes: a thin film transistor and a passivation layer 14 covering the thin film transistor.
  • the thin film transistor includes: a gate 1 la, a gate insulating layer 12, an active layer 13 of a metal oxide semiconductor material, and a source 1 ib/drain 1 lc.
  • a first isolation layer 21 for preventing contact between the gate insulating layer 12 and the active layer 13 is further disposed between the gate insulating layer 12 and the active layer 13.
  • the material of the first isolation layer 21 is a non-metal oxide material containing no hydrogen.
  • the non-metal oxide material containing no hydrogen in all embodiments of the present invention may be, for example, a material such as SiO 2 (silica).
  • the substrate substrate shown in FIG. 2 is required to be formed on the basis of the steps of the above-mentioned array substrate shown in FIG. 1, further between steps S102 and S103, further comprising: S102a;
  • SI 02a producing a non-metal oxide film containing no hydrogen, and forming a first portion for preventing contact between the gate insulating layer 12 and the active layer 13 at a position opposite to the gate electrode 11a by one patterning process The isolation layer 21.
  • a non-metal oxide material containing no hydrogen is deposited on the substrate on which the gate insulating layer 12 is formed to form a thin film; and a pattern larger than the periphery of the active layer 13 is formed at a position opposite to the gate electrode 11a to prevent the gate insulating layer Contact with the active layer 13.
  • the H element in the gate insulating layer 12 can be effectively prevented from entering the metal oxide semiconductor material, thereby protecting the active layer 13, preventing the deterioration of the characteristics of the thin film transistor, and improving the response time of the thin film transistor.
  • the passivation layer when the passivation layer is formed, it is mainly prepared by a chemical vapor deposition method using a gas such as silane, which causes the presence of the H element in the prepared passivation layer. Therefore, in order to prevent the H element in the passivation layer 14 from entering the active layer 13 of the metal oxide semiconductor material, referring to FIG. 3, based on the array substrate shown in FIG. 2, the method further includes: the thin film transistor and the A second isolation layer 22 for preventing contact between the active layer 13 of the thin film transistor and the passivation layer 14 is further disposed between the passivation layers 14 covering the thin film transistor; and a material of the second isolation layer 22 It is a non-metal oxide material that does not contain hydrogen.
  • the substrate substrate shown in FIG. 3 is required to be formed on the basis of the steps of manufacturing the array substrate shown in FIG. 2, and further between steps S104 and S105, further comprising: S104a;
  • SI 04a producing a film of a non-metal oxide containing no hydrogen, and forming a portion for preventing contact between the active layer 13 and the passivation layer 14 at a position opposite to the gate electrode 11a by a patterning process Two isolation layers 22.
  • a non-metal oxide material containing no hydrogen is deposited on the substrate on which the source and drain 11c are formed, Forming a thin film; and forming a pattern capable of covering a channel region of the active layer 13 (ie, an active layer 13 region not covered by the source and the drain) at a position opposite to the gate electrode 11a to prevent the active layer 13 and The passivation layer 14 is in contact.
  • the H element in the passivation layer 14 can be effectively prevented from entering the metal oxide semiconductor material, thereby protecting the active layer 13, preventing deterioration of characteristics of the thin film transistor, and improving response time of the thin film transistor.
  • the pattern of the second isolation layer 22 may be the same as the pattern of the channel region of the active layer 13, and may of course be slightly larger than the pattern of the channel region. If the pattern of the second isolation layer is large enough to cover not only the channel region but also the entire drain pattern, when the via is formed in S105, the passivation layer and the second isolation layer need to be turned on to make the drain and the pixel. The electrodes are in contact.
  • the array substrate includes: pixel units in an array form disposed on the base substrate 100, and includes, in each pixel unit: a thin film transistor and a passivation covering the thin film transistor Layer 14, pixel electrode 15.
  • the thin film transistor includes: a gate electrode 11a, a gate insulating layer 12, an active layer 13 of a metal oxide semiconductor material, a source 1 ib / a drain 11c; and a drain 11c of the thin film transistor passes through the passivation layer 14
  • the upper via is connected to the pixel electrode 15.
  • the active layer 13 and the source lb and the drain 11c are formed by the same layer patterning process. Description, which is not described in this embodiment.
  • S201 forming a bottom metal film on the base substrate 100, and forming at least a gate 11a of the thin film transistor by one patterning process;
  • a gate insulating layer 12 covering the gate electrode is formed, referring to the structure shown in FIG. 5A.
  • S203 sequentially forming a metal oxide semiconductor film and a top metal film, and forming at least an active layer 13 and a source lib, a drain 11c by a patterning process;
  • the step may include: coating a photoresist on two layers of the film which are sequentially produced, and the photoresist is divided into a semi-reserved area (marked by B in the figure), a completely reserved area (marked by A in the figure), and completely removed.
  • the composition of the hydrogen peroxide-based etching solution comprises: hydrogen peroxide, a top metal ion complexing agent, a stabilizer of hydrogen peroxide, and a surfactant; and the pH of the etching solution is between 6 and 8; the hydrogen peroxide
  • the content of the surfactant is, for example, between 5% and 20%, the content of the surfactant is, for example, between 1% and 10%, and the content of the top metal ion complexing agent is, for example, between 1% and 25%.
  • the top layer metal is, for example, copper or a copper alloy.
  • a passivation layer 14 covering the source and the drain is formed, and a via hole connecting the pixel electrode is formed at a position of the drain.
  • Forming the array substrate shown in FIG. 4 may further include step S205.
  • S205 A transparent conductive film covering the via holes in the S105 is formed, and the pixel electrode 15 is formed by one patterning process.
  • the material of the transparent conductive film may be ITO (Indium Tin Oxide) which is generally used.
  • the method for manufacturing an array substrate provided by the embodiment of the invention etches the top metal film by using a hydrogen peroxide-based etching solution, and the pH of the hydrogen peroxide-based etching solution is between 6 and 8, so that the hydrogen peroxide-based etching solution passes through the oxidation and
  • the method of patterning the top metal film is performed in a complex manner, and the oxide in the etching liquid does not react to the underlying metal oxide semiconductor, and the semiconductor characteristics of the metal oxide are not changed.
  • the array substrate shown in FIG. 6 includes: pixels in an array form provided on the base substrate 100 a unit, and comprising, in each pixel unit: a thin film transistor and a passivation layer 14 covering the thin film transistor; wherein, the thin film transistor comprises: a gate l la, a gate insulating layer 12, and a metal oxide semiconductor material which are sequentially disposed a source layer 13, a source 11b, and a drain 11c; a first isolation layer 21 for preventing contact between the gate insulating layer 12 and the active layer 13 is further disposed between the gate insulating layer 12 and the active layer 13. And the material of the first isolation layer 21 is a non-metal oxide material containing no hydrogen.
  • steps S202 and S203 includes: S202a;
  • the method further includes: the thin film transistor And a second isolation layer 22 for preventing contact between the active layer 13 of the thin film transistor and the passivation layer 14 between the passivation layer 14 covering the thin film transistor; and the second isolation layer
  • the material of 22 is a non-metal oxide material that does not contain hydrogen.
  • the substrate substrate shown in FIG. 7 is required to be formed on the basis of the steps of manufacturing the array substrate shown in FIG. 6, and further comprising: S203a between steps S203 and S204;
  • S203a forming a film of a non-metal oxide containing no hydrogen, and forming a second portion for preventing contact between the active layer 13 and the passivation layer 14 at a position opposite to the gate electrode 11a by one patterning process
  • the isolation layer 22 is
  • This step can be referred to step S104a.
  • the pattern of the second isolation layer 22 may be the same as the pattern of the channel region of the active layer 13, and may of course be slightly larger than the pattern of the channel region; if the pattern of the second isolation layer is large enough to cover not only The channel region also covers the pattern of the entire drain.
  • the passivation layer and the second isolation layer are required to be opened so that the drain and the pixel electrode are in contact.
  • the embodiment of the present invention effectively prevents the H element in the gate insulating layer 12 from entering the metal oxide semiconductor material through the first isolation layer 21, and effectively prevents the H element in the passivation layer 14 from entering through the second isolation layer 22.
  • the active layer 13 is further protected from corrosion.
  • the embodiment of the invention provides a display, which may include any one of the array substrates described in the first embodiment or the second embodiment.
  • the display can be a liquid crystal display.
  • the method for manufacturing an array substrate and the array substrate and the display provided by the embodiments of the present invention etch the top metal film by using a hydrogen peroxide-based etching solution, and the pH of the hydrogen peroxide-based etching liquid is between 6 and 8, so that the hydrogen peroxide is engraved.
  • the etching solution does not react with the metal oxide semiconductor, thereby protecting the active layer of the TFT from being corroded; and further, since the material of the gate insulating layer in the prior art contains hydrogen (H) Element, in order to prevent H from entering the active layer and causing deterioration of characteristics of the active layer, the active layer may be further protected by using the non-metal oxide material containing no hydrogen to form the first isolation layer to prevent the occurrence of the above defect.
  • a method of manufacturing an array substrate comprising:
  • the top metal film is etched using a hydrogen peroxide based etching solution, and the pH of the etching solution is between 6-8.
  • composition of the hydrogen peroxide-based etching liquid comprises: hydrogen peroxide, a top metal ion complexing agent, a stabilizer of hydrogen peroxide, and a surfactant.
  • a film of a non-metal oxide containing no hydrogen is formed, and a first isolation layer for preventing contact between the gate insulating layer and the active layer is formed at a position opposite to the gate by a patterning process.
  • a film of a non-metal oxide containing no hydrogen is formed, and a second isolation layer for preventing contact between the active layer and the passivation layer is formed at a position opposite to the gate by a patterning process.
  • the manufacturing method according to any one of (1) to (6), wherein the forming the active layer opposite to the gate and the source and drain of the thin film transistor comprises:
  • the top metal film is formed, and at least a source and a drain of the thin film transistor are formed by one patterning process.
  • a photoresist is coated on the two layers of the film which are sequentially formed, and the photoresist is divided into a semi-reserved area, a completely reserved area, and a completely removed area, and is developed by one exposure in accordance with the division of the above-mentioned area to remove the completely removed area.
  • a photoresist and leaving a photoresist having a thickness of a completely remaining region that is greater than a thickness of the semi-retained region;
  • the top metal film of the semi-retained region is etched away using the hydrogen peroxide-based etching solution to form a source and a drain.
  • An array substrate comprising: a pixel unit in the form of an array disposed on a substrate, and comprising, in each pixel unit: a thin film transistor and a passivation layer covering the thin film transistor; wherein the thin film transistor comprises: a gate electrode, a gate insulating layer, an active layer of a metal oxide semiconductor material, and a source/drain; wherein the gate insulating layer and the active layer are further provided with a gate insulating layer and The first isolation layer is in contact with the active layer; and the material of the first isolation layer is a non-metal oxide material containing no hydrogen.
  • a display comprising the array substrate of (10) or (11).

Abstract

公开了一种阵列基板的制造方法及阵列基板、显示器。所述制造方法包括：在衬底（100）上形成薄膜晶体管的栅极（11a）；制作金属氧化物半导体薄膜和顶层金属薄膜，并对所述金属氧化物半导体薄膜和所述顶层金属薄膜进行构图工艺，以分别形成与所述栅极相对的有源层（13）以及薄膜晶体管的源极（11b）和漏极（11c）；以及制作覆盖所述源极（11b）、漏极（11c）的钝化层（14），其中在对所述顶层金属薄膜进行构图的工艺中，使用双氧水基刻蚀液刻蚀所述顶层金属薄膜，且该刻蚀液的pH值在6-8之间。

Description

阵列基板的制造方法及阵列基板、 显示器 技术领域
本发明的实施例涉及阵列基板的制造方法及阵列基板、 显示器。 背景技术
随着显示技术的飞速发展， 人们对显示器的分辨率、 响应时间等特性要 求也越来越高。 在这种情况下， 随着显示器的尺寸越来越大以及 3D等显示 技术的发展，对设置在显示器阵列基板上的薄膜晶体管（ Thin Film Transistor, TFT ) 的迁移率要求越来越高。
TFT包括： 栅极、 栅绝缘层、 有源层、 源极和漏极。 上述 TFT的迁移率 实际上是指 TFT的有源层中载流子（电子和空穴）在单位电场作用下的平均 漂移速度。 目前， 用非晶硅制作有源层已经不能满足对迁移率的要求， 人们 已经将目光投向了具有较高迁移率的金属氧化物材料。 现有技术中将金属氧 化物作为有源层材料的 TFT的制造过程中， 主要有如下问题： 传统工艺进行 源 /漏极的构图工艺时会使用酸来刻蚀图案， 而金属氧化物材料一般不耐酸， 从而传统工艺会腐蚀部分有源层， 影响到器件的性能。 为了解决这一问题， 通常釆用一层耐酸腐蚀的刻蚀阻挡层覆盖有源层的沟道区域， 以保护有源层 不被腐蚀。 但这就需要增加一次构图工艺， 导致工艺复杂。 发明内容
本发明的一个实施例提供一种阵列基板的制造方法， 包括： 在衬底基板 上制作底层金属薄膜， 并通过构图工艺至少形成薄膜晶体管的栅极； 制作覆 盖所述栅极的栅绝缘层； 制作金属氧化物半导体薄膜和顶层金属薄膜， 并对 所述金属氧化物半导体薄膜和所述顶层金属薄膜进行构图工艺， 以分别形成 与所述栅极相对的有源层以及薄膜晶体管的源极和漏极； 以及制作覆盖所述 源极、 漏极的钝化层， 在所述漏极的位置形成连通像素电极的过孔， 其中在 对所述顶层金属薄膜进行构图的工艺中， 使用双氧水基刻蚀液刻蚀所述顶层 金属薄膜， 且该刻蚀液的 pH值在 6-8之间。 本发明的另一个实施例提供一种阵列基板， 包括： 在衬底基板上设置的 阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管以及覆盖该薄 膜晶体管的钝化层； 其中， 薄膜晶体管包括： 依次设置的栅极、 栅绝缘层、 金属氧化物半导体材料的有源层、 源极 /漏极； 其中， 所述栅绝缘层和有源层 之间还设置有用于防止所述栅绝缘层和所述有源层接触的第一隔离层； 且所 述第一隔离层的材料为不含氢的非金属氧化物材料。
本发明的再一个实施例提供一种显示器， 包括根据本发明实施例的阵列 基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为实施例一提供的一种阵列基板的结构示意图；
图 2为实施例一提供的另一阵列基板的结构示意图；
图 3为实施例一提供的又一阵列基板的结构示意图；
图 4为实施例二提供的一种阵列基板的结构示意图；
图 5A-图 5G为制作图 4所示阵列基板的步骤示意图；
图 6为实施例二提供的另一阵列基板的结构示意图； 以及
图 7为实施例二提供的又一阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
参考图 1所示的阵列基板的结构图， 该阵列基板包括： 在衬底基板 100 上设置的阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管、 覆 盖该薄膜晶体管的钝化层 14及与该薄膜晶体管呈水平设置的像素电极 15。 薄膜晶体管包括： 依次设置的栅极 l la、 栅绝缘层 12、 金属氧化物半导体材 料的有源层 13、 源极 lib/漏极 11c; 并且薄膜晶体管的漏极 11c通过钝化层 14上的过孔和像素电极 15相连。
由于现有制作工艺会腐蚀金属氧化物半导体材料的有源层， 故本发明实 施例提供了一种制造上述阵列基板结构的方法， 以保护有源层。
参考图 1 , 本发明实施例提供的阵列基板的制造方法包括：
S101 : 在衬底基板 100上制作底层金属薄膜， 并通过一次构图工艺至少 形成薄膜晶体管的栅极 11a;
所述底层金属薄膜的材料可以是钼， 铝， 铜， 铬等任一金属， 也可以是 含有这些金属的合金。
在本发明所有实施例中， 构图工艺可以包括： 涂覆光刻胶、 曝光、 显影、 刻蚀等工艺。 曝光工艺需要使用掩膜板来控制光刻胶在不同区域的曝光度。 在阵列基板的整个制造过程中， 通常将使用掩膜板的个数作为构图工艺的次 数； 也就是说， 进行一次构图工艺即为使用一次掩膜板完成构图。
S102: 制作覆盖所述栅极的栅绝缘层 12;
栅绝缘层 12的材料可以是目前常用的 SiNx (氮化硅 )材料。
S103: 制作金属氧化物半导体薄膜， 并通过一次构图工艺在与所述栅极 11a相对的位置形成有源层 13;
金属氧化物半导体的材料可以是任意能够作为半导体的金属氧化物， 例 如， 可以是 IGZO (含有铟、 镓、 辞的金属氧化物）或 IZO (含有铟、 辞的 金属氧化物）等。
S104: 制作顶层金属薄膜， 并通过一次构图工艺至少形成薄膜晶体管的 源极 lib和漏极 11c; 在本次构图工艺中所使用的刻蚀液的成分包括： 双氧 水、 顶层金属离子络合剂、 双氧水的稳定剂、 以及表面活性剂； 且该刻蚀液 的 pH值在 6-8之间；
顶层金属薄膜的材料可以是钼， 铝， 铜， 铬等任一金属， 也可以是含有 其中至少一种金属的合金。 在发明实施例中考虑到对显示器分辨率以及开关 时延特性的较高要求， 因为铜的电阻率低， 就使得充电的时间短， 并且用铜 做源 /漏极， 像素可以做的小一点， 即单位面积的像素增多了， 从而可以提高 显示器的分辨率。 故本实施例中优选铜或铜合金作为顶层金属薄膜的材料。 所述顶层金属络合剂在本发明实施例中是指可以和顶层金属离子形成络合离 子的化合物。 在本发明实施例中顶层金属选用铜或铜合金的情况下， 顶层金 属离子络合剂选用铜离子络合剂。
另外， 根据多次实验得到的经验值， 在本发明实施例中对于该双氧水基 刻蚀液的成分， 所述双氧水的含量例如可以在 5%-20%之间， 所述表面活性 剂的含量可以在 1%-10%之间， 所述顶层金属离子络合剂的含量根据所需要 刻蚀掉的顶层金属的量而定， 一般的所述顶层金属离子络合剂的含量为 1%-25%之间。 具体的， 对于顶层金属络合剂的含量控制， 可以是先在刻蚀 液中添加一部分（例如含量为 50% )顶层金属络合剂， 并根据溶进刻蚀液中 的顶层金属离子的含量以及完成顶层金属薄膜刻蚀的程度， 后续添加顶层金 属络合离子。 顶金属离子络合剂可以根据顶金属薄膜的材料而选择任何合适 的络合剂， 双氧水的稳定剂和表面活性剂也可以选择任何合适的试剂， 这里 不再赘述。
S105: 制作覆盖所述源极、 漏极的钝化层 14, 并通过一次构图工艺在所 述漏极 11c的位置形成连通像素电极 15的过孔。
钝化层 14的材料可以是目前常用的 SiNx (氮化硅 )材料。
形成图 1所示的阵列基板的方法还可以包括步骤 S106。
S106: 制作覆盖 S105 中过孔的透明导电薄膜， 并通过一次构图工艺形 成像素电极 15。
透明导电薄膜的材料可以是通常使用的 ITO (氧化铟锡） 。
本发明实施例提供的阵列基板的制造方法， 通过使用双氧水基刻蚀液刻 蚀顶层金属薄膜， 且双氧水基刻蚀液 pH值为 6-8之间， 就使得双氧水基刻 蚀液通过氧化和络合的方式来对顶层金属薄膜进行构图工艺， 并且刻蚀液中 的氧化物不会对下面的金属氧化物半导体产生反应， 也就不会改变金属氧化 物的半导体特性等。
由于现有技术中在制作栅绝缘层时， 主要是用硅烷等气体通过化学气相 沉积的方法制备， 这就使得制备完成的栅绝缘层中存在 H元素。 因此， 为了 防止栅绝缘层中的 H元素进入金属氧化物半导体材料的有源层中， 参考图 2 所示的阵列基板包括： 在衬底基板 100上设置的阵列形式的像素单元， 且在 每个像素单元中包括： 薄膜晶体管以及覆盖该薄膜晶体管的钝化层 14。 薄膜 晶体管包括： 依次设置的栅极 l la、 栅绝缘层 12、 金属氧化物半导体材料的 有源层 13、 源极 l ib/漏极 l lc。 所述栅绝缘层 12和有源层 13之间还设置有 用于防止所述栅绝缘层 12和所述有源层 13接触的第一隔离层 21。第一隔离 层 21的材料为不含氢的非金属氧化物材料。
在本发明所有实施例中不含氢的非金属氧化物材料例如可以是 Si02 (二 氧化硅）等材料。
制造图 2所示的阵列基板， 需要在上述制造图 1所示阵列基板的各步骤 的基础上， 进一步在步骤 S102和 S103之间， 还包括： S102a;
SI 02a: 制作不含氢的非金属氧化物薄膜，并通过一次构图工艺在与所述 栅极 11a相对的位置形成用于防止所述栅绝缘层 12和所述有源层 13接触的 第一隔离层 21。
例如， 在形成有栅绝缘层 12的基板上沉积不含氢的非金属氧化物材料， 形成薄膜； 并在栅极 11a相对的位置形成比有源层 13外围大的图案， 以防止 栅绝缘层 12和有源层 13的接触。这样就可以有效的防止栅绝缘层 12中的 H 元素进入到金属氧化物半导体材料中， 从而保护了有源层 13 , 防止薄膜晶体 管的特性劣化， 并改善薄膜晶体管的响应时间。
与制备栅绝缘层类似， 现有技术中在制作钝化层时， 也主要是用硅烷等 气体通过化学气相沉积的方法制备，这就使得制备完成的钝化层中存在 H元 素。 因此， 为了防止钝化层 14中的 H元素进入金属氧化物半导体材料的有 源层 13中， 参考图 3 , 在图 2所示阵列基板的基础上， 还包括： 所述薄膜晶 体管和所述覆盖该薄膜晶体管的钝化层 14之间还设置有用于防止所述薄膜 晶体管的有源层 13和所述钝化层 14接触的第二隔离层 22;且所述第二隔离 层 22的材料为不含氢的非金属氧化物材料。
制造图 3所示的阵列基板， 需要在上述制造图 2所示阵列基板的各步骤 的基础上， 进一步在步骤 S104和 S105之间， 还包括： S104a;
SI 04a: 制作不含氢的非金属氧化物的薄膜，并通过一次构图工艺在与所 述栅极 11a相对的位置形成用于防止所述有源层 13和所述钝化层 14接触的 第二隔离层 22。
例如， 在形成源、 漏极 11c的基板上沉积不含氢的非金属氧化物材料， 形成薄膜； 并在栅极 11a相对的位置形成能够覆盖有源层 13的沟道区域（即 没有被源、 漏极覆盖的有源层 13区域） 的图案， 以防止所述有源层 13和所 述钝化层 14接触。这样就可以有效的防止钝化层 14中的 H元素进入到金属 氧化物半导体材料中， 从而保护了有源层 13, 防止薄膜晶体管的特性劣化， 并改善薄膜晶体管的响应时间。
需要说明的是， 第二隔离层 22的图案可以与有源层 13沟道区域的图案 相同， 当然也可以与比沟道区域的图案略大。 若第二隔离层的图案大到不仅 覆盖了沟道区域还覆盖整个漏极的图案， 则在 S105 中制作过孔时， 需要打 通钝化层以及该第二隔离层， 以使得漏极和像素电极相接触。
实施例二
参考图 4所示的阵列基板的结构图， 该阵列基板包括： 在衬底基板 100 上设置的阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管以及 覆盖该薄膜晶体管的钝化层 14、 像素电极 15。 其中， 薄膜晶体管包括： 依次 设置的栅极 lla、栅绝缘层 12、金属氧化物半导体材料的有源层 13、源极 l ib/ 漏极 11c;并且薄膜晶体管的漏极 11c通过钝化层 14上的过孔和像素电极 15 相连。 有源层 13和源极 l lb、 漏极 11c是通过同一层构图工艺形成的。 描述， 在本实施例中不加赘述。
本发明实施例提供的上述阵列基板的制造方法， 包括：
S201 : 在衬底基板 100上制作底层金属薄膜， 并通过一次构图工艺至少 形成薄膜晶体管的栅极 11a;
S202: 制作覆盖所述栅极的栅绝缘层 12, 参考图 5A所示的结构。
S203: 依次制作金属氧化物半导体薄膜和顶层金属薄膜， 并通过一次构 图工艺至少形成有源层 13及源极 lib, 漏极 11c;
此步骤可以包括： 在依次制作的两层薄膜上涂覆光刻胶， 且该光刻胶分 为半保留区域（图中用 B标识）、 完全保留区域（图中用 A标识）和完全去 除区域（图中用 C标识） ， 并按照上述区域的划分通过一次曝光显影， 除掉 完全去除区域的光刻胶且留下完全保留区域的厚度比半保留区域厚度大的光 刻胶， 参考图 5B所示的结构； 使用双氧水基刻蚀液刻蚀掉完全去除区域的 顶层金属薄膜， 参考图 5C所示的结构； 使用不与顶层金属反应的含酸刻蚀 液刻蚀掉完全去除区域的金属氧化物薄膜， 形成有源层 13, 参考图 5D所示 的结构； 灰化所留下的光刻胶， 以便除掉半保留区域的光刻胶且留下部分完 全保留区域的光刻胶， 参考图 5E所示的结构； 使用所述双氧水基刻蚀液刻 蚀掉半保留区域的顶层金属薄膜，形成源、漏极 11c,参考图 5F所示的结构； 去除剩下的光刻胶， 参考图 5G所示的结构；
其中， 所述双氧水基刻蚀液的成分包括： 双氧水、顶层金属离子络合剂、 双氧水的稳定剂， 以及表面活性剂； 且该刻蚀液的 pH值在 6-8之间； 所述 双氧水的含量例如在 5%-20%之间， 所述表面活性剂的含量例如在 1%-10% 之间， 所述顶层金属离子络合剂的含量例如在 1%-25%之间。
另外， 所述顶层金属例如为铜或铜合金。
S204: 制作覆盖所述源极、 漏极的钝化层 14, 在所述漏极的位置形成连 通像素电极的过孔。
形成图 4所示的阵列基板还可以包括步骤 S205。
S205: 制作覆盖 S105 中过孔的透明导电薄膜， 并通过一次构图工艺形 成像素电极 15。
其中， 透明导电薄膜的材料可以是通常使用的 ITO (氧化铟锡） 。
本发明实施例提供的阵列基板的制造方法， 通过使用双氧水基刻蚀液刻 蚀顶层金属薄膜， 且双氧水基刻蚀液 pH值为 6-8之间， 就使得双氧水基刻 蚀液通过氧化和络合的方式来对顶层金属薄膜进行构图工艺， 并且刻蚀液中 的氧化物不会对下面的金属氧化物半导体产生反应， 也就不会改变金属氧化 物的半导体特性等。
更进一步的， 为了防止栅绝缘层 12中的 H元素进入金属氧化物半导体 材料的有源层 13中，故参考图 6所示的阵列基板包括：在衬底基板 100上设 置的阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管以及覆盖 该薄膜晶体管的钝化层 14; 其中， 薄膜晶体管包括： 依次设置的栅极 l la、 栅绝缘层 12、 金属氧化物半导体材料的有源层 13、 源极 llb、 漏极 11c; 所 述栅绝缘层 12和有源层 13之间还设置有用于防止所述栅绝缘层 12和所述有 源层 13接触的第一隔离层 21;且所述第一隔离层 21的材料为不含氢的非金 属氧化物材料。
制造图 6所示的阵列基板， 需要在上述制造图 4所示阵列基板的各步骤 的基础上， 进一步在步骤 S202和 S203之间包括： S202a;
S202a: 制作不含氢的非金属氧化物的薄膜，并通过一次构图工艺在与所 述栅极 11a相对的位置形成用于防止所述栅绝缘层 12和所述有源层 13接触 的第一隔离层 21。
具体可参考实施例一中的 S102a。
更进一步的， 为了防止钝化层 14中的 H元素进入金属氧化物半导体材 料的有源层 13中， 故参考图 7 , 在图 6所示阵列基板的基础上， 还包括： 所 述薄膜晶体管和所述覆盖该薄膜晶体管的钝化层 14之间还设置有用于防止 所述薄膜晶体管的有源层 13和所述钝化层 14接触的第二隔离层 22;且所述 第二隔离层 22的材料为不含氢的非金属氧化物材料。
制造图 7所示的阵列基板， 需要在上述制造图 6所示阵列基板的各步骤 的基础上， 进一步在步骤 S203和 S204之间还包括： S203a;
S203a: 制作不含氢的非金属氧化物的薄膜，并通过一次构图工艺在与所 述栅极 11a相对的位置形成用于防止所述有源层 13和所述钝化层 14接触的 第二隔离层 22。
此步骤可参考步骤 S104a。
需要说明的是， 对于第二隔离层 22的图案可以与有源层 13沟道区域的 图案相同， 当然也可以与比沟道区域的图案略大； 若第二隔离层的图案大到 不仅覆盖了沟道区域还覆盖整个漏极的图案， 则在 S204 中制作过孔时， 需 要打通钝化层以及该第二隔离层， 以使得漏极和像素电极相接触。
本发明实施例通过第一隔离层 21有效的防止栅绝缘层 12中的 H元素进 入到金属氧化物半导体材料中， 并且通过第二隔离层 22有效的防止钝化层 14中的 H元素进入到金属氧化物半导体材料中， 从而进一步保护有源层 13 不被腐蚀。
本发明实施例提供了一种显示器， 该显示器可以包括上述实施例一或实 施例二中所述的任一种阵列基板。 例如： 该显示器可以是液晶显示器。
本发明实施例提供的阵列基板的制造方法及阵列基板、 显示器， 通过使 用双氧水基刻蚀液刻蚀顶层金属薄膜， 且双氧水基刻蚀液 pH值为 6-8之间， 就使得双氧水基刻蚀液不会与金属氧化物半导体反应，从而保护 TFT的有源 层不被腐蚀； 并且进一步的， 由于现有技术中栅绝缘层的材料中含有氢（H ) 元素， 为了避免 H进入有源层而导致有源层的特性变差， 通过使用不含氢的 非金属氧化物材料制作第一隔离层以防止上述不良的发生， 可以进一步保护 有源层。 ( 1 )一种阵列基板的制造方法， 包括：
在衬底基板上制作底层金属薄膜， 并通过构图工艺至少形成薄膜晶体管 的栅极；
制作覆盖所述栅极的栅绝缘层；
制作金属氧化物半导体薄膜和顶层金属薄膜 , 并对所述金属氧化物半导 体薄膜和所述顶层金属薄膜进行构图工艺， 以分别形成与所述栅极相对的有 源层以及薄膜晶体管的源极和漏极； 以及
制作覆盖所述源极、 漏极的钝化层， 在所述漏极的位置形成连通像素电 极的过孔，
其中在对所述顶层金属薄膜进行构图的工艺中， 使用双氧水基刻蚀液刻 蚀所述顶层金属薄膜， 且该刻蚀液的 pH值在 6-8之间。
( 2 )根据 ( 1 )所述的制造方法， 其中所述双氧水基刻蚀液的成分包括： 双氧水、 顶层金属离子络合剂、 双氧水的稳定剂以及表面活性剂。
( 3 )根据（ 1 )或（ 2 )所述的制造方法， 其中， 在所述刻蚀液中， 所述 双氧水的含量在 5%-20%之间， 所述表面活性剂的含量在 1%-10%之间， 所 述顶层金属离子络合剂的含量在 1%-25%之间。
( 4 )根据（ 1 )至（ 3 )中任一项所述的制造方法， 在制作完成所述栅绝 缘层之后以及制作金属氧化物半导体薄膜之前， 还包括：
制作不含氢的非金属氧化物的薄膜， 并通过一次构图工艺在与所述栅极 相对的位置形成用于防止所述栅绝缘层和所述有源层接触的第一隔离层。
( 5 )根据（ 1 )至（ 4 )中任一项所述的制造方法， 在制作完成薄膜晶体 管的源极和漏极之后以及制作钝化层之前， 还包括：
制作不含氢的非金属氧化物的薄膜， 并通过一次构图工艺在与所述栅极 相对的位置形成用于防止所述有源层和所述钝化层接触的第二隔离层。
( 6 )根据（ 1 )至（ 5 )中任一项所述的制造方法， 其中 , 所述顶层金属 为铜或铜合金。 ( 7 )根据（ 1 )至（ 6 )中任一项所述的制造方法， 其中形成与所述栅极 相对的有源层以及薄膜晶体管的源极和漏极的步骤包括：
制作所述金属氧化物半导体薄膜， 并通过一次构图工艺在与所述栅极相 对的位置形成有源层； 以及
制作所述顶层金属薄膜， 并通过一次构图工艺至少形成薄膜晶体管的源 极和漏极。
( 8 )根据（ 1 )至（ 6 )中任一项所述的制造方法， 其中形成与所述栅极 相对的有源层以及薄膜晶体管的源极和漏极的步骤包括：
依次制作所述金属氧化物半导体薄膜和所述顶层金属薄膜；
在依次制作的两层薄膜上涂覆光刻胶， 且该光刻胶分为半保留区域、 完 全保留区域和完全去除区域， 并按照上述区域的划分通过一次曝光显影， 除 掉完全去除区域的光刻胶且留下完全保留区域的厚度比半保留区域厚度大的 光刻胶；
使用所述双氧水基刻蚀液刻蚀掉完全去除区域的顶层金属薄膜； 使用不与顶层金属反应的含酸刻蚀液刻蚀掉完全去除区域的金属氧化物 薄膜， 形成有源层；
灰化所留下的光刻胶， 以便除掉半保留区域的光刻胶且留下部分完全保 留区域的光刻胶； 以及
使用所述双氧水基刻蚀液刻蚀掉半保留区域的顶层金属薄膜， 形成源、 漏极。
( 9 )根据（6 )所述的制造方法， 其中所述顶层金属离子络合剂为铜离 子络合剂。
( 10 )—种阵列基板， 包括： 在衬底基板上设置的阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管以及覆盖该薄膜晶体管的钝化层； 其 中， 薄膜晶体管包括： 依次设置的栅极、 栅绝缘层、 金属氧化物半导体材料 的有源层、 源极 /漏极； 其中， 所述栅绝缘层和有源层之间还设置有用于防止 所述栅绝缘层和所述有源层接触的第一隔离层； 且所述第一隔离层的材料为 不含氢的非金属氧化物材料。
( 11 )根据（10 )所述的阵列基板， 其中， 所述薄膜晶体管和所述覆盖 该薄膜晶体管的钝化层之间还设置有用于防止所述薄膜晶体管的有源层和所 述钝化层接触的第二隔离层； 且所述第二隔离层的材料为不含氢的非金属氧 化物材料。
( 12 )一种显示器， 包括（ 10 )或 （ 11 )所述的阵列基板。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的制造方法， 包括：
在衬底基板上制作底层金属薄膜， 并通过构图工艺至少形成薄膜晶体管 的栅极；
制作覆盖所述栅极的栅绝缘层；
制作金属氧化物半导体薄膜和顶层金属薄膜 , 并对所述金属氧化物半导 体薄膜和所述顶层金属薄膜进行构图工艺， 以分别形成与所述栅极相对的有 源层以及薄膜晶体管的源极和漏极； 以及
制作覆盖所述源极、 漏极的钝化层， 在所述漏极的位置形成连通像素电 极的过孔，
其中在对所述顶层金属薄膜进行构图的工艺中， 使用双氧水基刻蚀液刻 蚀所述顶层金属薄膜， 且该刻蚀液的 pH值在 6-8之间。
2、根据权利要求 1所述的制造方法，其中所述双氧水基刻蚀液的成分包 括： 双氧水、 顶层金属离子络合剂、 双氧水的稳定剂以及表面活性剂。
3、根据权利要求 1或 2所述的制造方法， 其中， 在所述刻蚀液中， 所述 双氧水的含量在 5%-20%之间， 所述表面活性剂的含量在 1%-10%之间， 所 述顶层金属离子络合剂的含量在 1%-25%之间。
4、根据权利要求 1至 3中任一项所述的制造方法，在制作完成所述栅绝 缘层之后以及制作金属氧化物半导体薄膜之前， 还包括：
制作不含氢的非金属氧化物的薄膜， 并通过一次构图工艺在与所述栅极 相对的位置形成用于防止所述栅绝缘层和所述有源层接触的第一隔离层。
5、根据权利要求 1至 4中任一项所述的制造方法，在制作完成薄膜晶体 管的源极和漏极之后以及制作钝化层之前， 还包括：
制作不含氢的非金属氧化物的薄膜， 并通过一次构图工艺在与所述栅极 相对的位置形成用于防止所述有源层和所述钝化层接触的第二隔离层。
6、根据权利要求 1至 5中任一项所述的制造方法， 其中， 所述顶层金属 为铜或铜合金。
7、根据权利要求 1至 6中任一项所述的制造方法，其中形成与所述栅极 相对的有源层以及薄膜晶体管的源极和漏极的步骤包括： 制作所述金属氧化物半导体薄膜， 并通过一次构图工艺在与所述栅极相 对的位置形成有源层； 以及
制作所述顶层金属薄膜， 并通过一次构图工艺至少形成薄膜晶体管的源 极和漏极。
8、根据权利要求 1至 6中任一项所述的制造方法，其中形成与所述栅极 相对的有源层以及薄膜晶体管的源极和漏极的步骤包括：
依次制作所述金属氧化物半导体薄膜和所述顶层金属薄膜；
在依次制作的两层薄膜上涂覆光刻胶， 且该光刻胶分为半保留区域、 完 全保留区域和完全去除区域， 并按照上述区域的划分通过一次曝光显影， 除 掉完全去除区域的光刻胶且留下完全保留区域的厚度比半保留区域厚度大的 光刻胶；
使用所述双氧水基刻蚀液刻蚀掉完全去除区域的顶层金属薄膜； 使用不与顶层金属反应的含酸刻蚀液刻蚀掉完全去除区域的金属氧化物 薄膜， 形成有源层；
灰化所留下的光刻胶， 以便除掉半保留区域的光刻胶且留下部分完全保 留区域的光刻胶； 以及
使用所述双氧水基刻蚀液刻蚀掉半保留区域的顶层金属薄膜， 形成源、 漏极。
9、根据权利要求 6所述的制造方法，其中所述顶层金属离子络合剂为铜 离子络合剂。
10、 一种阵列基板， 包括： 在衬底基板上设置的阵列形式的像素单元， 且在每个像素单元中包括： 薄膜晶体管以及覆盖该薄膜晶体管的钝化层； 其 中， 薄膜晶体管包括： 依次设置的栅极、 栅绝缘层、 金属氧化物半导体材料 的有源层、 源极 /漏极； 其中， 所述栅绝缘层和有源层之间还设置有用于防止 所述栅绝缘层和所述有源层接触的第一隔离层； 且所述第一隔离层的材料为 不含氢的非金属氧化物材料。
11、根据权利要求 10所述的阵列基板， 其中， 所述薄膜晶体管和所述覆 盖该薄膜晶体管的钝化层之间还设置有用于防止所述薄膜晶体管的有源层和 所述钝化层接触的第二隔离层； 且所述第二隔离层的材料为不含氢的非金属 氧化物材料。 、 一种显示器， 包括权利要求 10或 11所述的阵列基板。
PCT/CN2012/084966 2012-02-28 2012-11-21 阵列基板的制造方法及阵列基板、显示器 WO2013127202A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US13/991,371 US9099440B2 (en) 2012-02-28 2012-11-21 Manufacturing method of array substrate, array substrate and display
EP12844653.1A EP2822030B1 (en) 2012-02-28 2012-11-21 Manufacturing method for array substrate, array substrate and display
KR1020137012238A KR101530459B1 (ko) 2012-02-28 2012-11-21 어레이 기판의 제조방법, 어레이 기판 및 디스플레이
JP2014557974A JP6092260B2 (ja) 2012-02-28 2012-11-21 アレイ基板の製造方法及びアレイ基板、ディスプレー

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210048821.3 2012-02-28
CN201210048821.3A CN102629591B (zh) 2012-02-28 2012-02-28 一种阵列基板的制造方法及阵列基板、显示器

Publications (1)

Publication Number Publication Date
WO2013127202A1 true WO2013127202A1 (zh) 2013-09-06

Family

ID=46587819

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/084966 WO2013127202A1 (zh) 2012-02-28 2012-11-21 阵列基板的制造方法及阵列基板、显示器

Country Status (6)

Country Link
US (1) US9099440B2 (zh)
EP (1) EP2822030B1 (zh)
JP (1) JP6092260B2 (zh)
KR (1) KR101530459B1 (zh)
CN (1) CN102629591B (zh)
WO (1) WO2013127202A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629591B (zh) * 2012-02-28 2015-10-21 京东方科技集团股份有限公司 一种阵列基板的制造方法及阵列基板、显示器
CN102891108B (zh) * 2012-10-24 2015-12-02 京东方科技集团股份有限公司 一种阵列基板的制造方法
CN103715094B (zh) 2013-12-27 2017-02-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104183605A (zh) * 2014-08-06 2014-12-03 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN104157699B (zh) * 2014-08-06 2019-02-01 北京大学深圳研究生院 一种背沟道刻蚀型薄膜晶体管及其制备方法
CN104218095B (zh) 2014-09-01 2016-05-25 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
KR102402599B1 (ko) 2015-12-16 2022-05-26 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법
CN106960797A (zh) * 2017-04-28 2017-07-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法和阵列基板的制备方法
CN108183132A (zh) * 2017-12-27 2018-06-19 深圳市华星光电半导体显示技术有限公司 一种igzo薄膜晶体管制备方法
CN109037350A (zh) * 2018-08-01 2018-12-18 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制备方法、阵列基板
CN109192704A (zh) * 2018-09-05 2019-01-11 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN111508895B (zh) * 2020-04-30 2023-04-14 成都京东方显示科技有限公司 阵列基板、显示面板以及阵列基板的制作方法
CN113097134B (zh) * 2021-04-09 2022-07-15 广州新视界光电科技有限公司 一种阵列基板的制备方法及阵列基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794737A (zh) * 2008-12-26 2010-08-04 株式会社半导体能源研究所 半导体器件及其制造方法
US20110114942A1 (en) * 2009-11-13 2011-05-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN102157563A (zh) * 2011-01-18 2011-08-17 上海交通大学 金属氧化物薄膜晶体管制备方法
CN102629591A (zh) * 2012-02-28 2012-08-08 京东方科技集团股份有限公司 一种阵列基板的制造方法及阵列基板、显示器

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379824B1 (ko) 2000-12-20 2003-04-11 엘지.필립스 엘시디 주식회사 식각용액 및 식각용액으로 패턴된 구리배선을 가지는전자기기용 어레이기판
JP2004031791A (ja) * 2002-06-27 2004-01-29 Mitsubishi Chemicals Corp タングステン合金のエッチング液及びエッチング方法
KR100499376B1 (ko) 2003-10-10 2005-07-04 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
US8530359B2 (en) * 2003-10-20 2013-09-10 Novellus Systems, Inc. Modulated metal removal using localized wet etching
CN101098989A (zh) * 2005-03-29 2008-01-02 三菱化学株式会社 铜的蚀刻液以及蚀刻方法
US7976723B2 (en) 2007-05-17 2011-07-12 International Business Machines Corporation Method for kinetically controlled etching of copper
US7682882B2 (en) * 2007-06-20 2010-03-23 Samsung Electronics Co., Ltd. Method of manufacturing ZnO-based thin film transistor
TW200938660A (en) 2007-11-22 2009-09-16 Idemitsu Kosan Co Etching solution composition
JP5213422B2 (ja) * 2007-12-04 2013-06-19 キヤノン株式会社 絶縁層を有する酸化物半導体素子およびそれを用いた表示装置
CN103258727B (zh) * 2007-12-21 2016-08-03 和光纯药工业株式会社 蚀刻剂、蚀刻方法及蚀刻剂制备液
KR101681483B1 (ko) * 2008-09-12 2016-12-02 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
JP4752925B2 (ja) * 2009-02-04 2011-08-17 ソニー株式会社 薄膜トランジスタおよび表示装置
EP2256814B1 (en) * 2009-05-29 2019-01-16 Semiconductor Energy Laboratory Co, Ltd. Oxide semiconductor device and method for manufacturing the same
KR101213708B1 (ko) * 2009-06-03 2012-12-18 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
CN102472938B (zh) * 2009-07-23 2016-03-30 东友精细化工有限公司 液晶显示装置用阵列基板的制造方法
KR101126509B1 (ko) 2009-07-23 2012-03-29 노벨러스 시스템즈, 인코포레이티드 등방성 구리 식각을 위한 식각 조성물
KR102197397B1 (ko) 2009-12-18 2020-12-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액정 표시 장치 및 전자 기기
KR101636998B1 (ko) * 2010-02-12 2016-07-08 삼성디스플레이 주식회사 박막 트랜지스터 및 그 제조 방법
DE112011101069B4 (de) 2010-03-26 2018-05-03 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung und Verfahren zur Herstellung der Halbleitervorrichtung
KR101281463B1 (ko) * 2010-07-06 2013-07-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그를 이용한 액정표시장치
US20140151682A1 (en) * 2010-07-15 2014-06-05 Sharp Kabushiki Kaisha Circuit board, display device, and process for production of circuit board
WO2012024114A2 (en) * 2010-08-20 2012-02-23 Applied Materials, Inc. Methods for forming a hydrogen free silicon containing dielectric film
KR20120063809A (ko) * 2010-12-08 2012-06-18 삼성전자주식회사 박막 트랜지스터 표시판

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794737A (zh) * 2008-12-26 2010-08-04 株式会社半导体能源研究所 半导体器件及其制造方法
US20110114942A1 (en) * 2009-11-13 2011-05-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN102157563A (zh) * 2011-01-18 2011-08-17 上海交通大学 金属氧化物薄膜晶体管制备方法
CN102629591A (zh) * 2012-02-28 2012-08-08 京东方科技集团股份有限公司 一种阵列基板的制造方法及阵列基板、显示器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2822030A4 *

Also Published As

Publication number Publication date
CN102629591A (zh) 2012-08-08
EP2822030A1 (en) 2015-01-07
JP2015515120A (ja) 2015-05-21
US20140054586A1 (en) 2014-02-27
CN102629591B (zh) 2015-10-21
KR101530459B1 (ko) 2015-06-19
US9099440B2 (en) 2015-08-04
EP2822030A4 (en) 2015-06-24
KR20130124506A (ko) 2013-11-14
JP6092260B2 (ja) 2017-03-08
EP2822030B1 (en) 2019-05-22

Similar Documents

Publication Publication Date Title
WO2013127202A1 (zh) 阵列基板的制造方法及阵列基板、显示器
US9768306B2 (en) Array substrate and display device
JP6078063B2 (ja) 薄膜トランジスタデバイスの製造方法
US9455324B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
JP2007157916A (ja) Ｔｆｔ基板及びｔｆｔ基板の製造方法
WO2016029541A1 (zh) 薄膜晶体管及其的制备方法、阵列基板和显示装置
JP6437574B2 (ja) 薄膜トランジスタおよびその製造方法、アレイ基板、並びに表示装置
WO2017008497A1 (zh) 氧化物薄膜晶体管的制备方法
WO2015143839A1 (zh) 氧化物薄膜晶体管阵列基板的制造方法
WO2018113214A1 (zh) 薄膜晶体管及其制作方法、显示基板、显示装置
US20160284741A1 (en) Array substrate fabricating method
WO2015067054A1 (zh) 互补式薄膜晶体管及其制备方法、阵列基板和显示装置
WO2015165174A1 (zh) 一种薄膜晶体管及其制作方法、显示基板、显示装置
US9159746B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
WO2014169544A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2016026207A1 (zh) 阵列基板及其制作方法和显示装置
WO2015180357A1 (zh) 阵列基板及其制作方法和显示装置
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
TWI471948B (zh) 氧化物薄膜電晶體製程方法
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置
CN105990332B (zh) 薄膜晶体管基板及其显示面板
JP2008098642A (ja) 薄膜トランジスタ基板の製造方法
JP2008098642A5 (zh)
CN110998811B (zh) 一种薄膜晶体管及其制造方法与薄膜晶体管阵列
CN105374827A (zh) 显示设备和用于制造该显示设备的方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2012844653

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20137012238

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 13991371

Country of ref document: US

ENP Entry into the national phase

Ref document number: 2014557974

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12844653

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE