WO2017008497A1 - 氧化物薄膜晶体管的制备方法 - Google Patents

氧化物薄膜晶体管的制备方法 Download PDF

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Publication number
WO2017008497A1
WO2017008497A1 PCT/CN2016/072012 CN2016072012W WO2017008497A1 WO 2017008497 A1 WO2017008497 A1 WO 2017008497A1 CN 2016072012 W CN2016072012 W CN 2016072012W WO 2017008497 A1 WO2017008497 A1 WO 2017008497A1
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photoresist
drain electrode
source
thin film
oxidation resistant
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PCT/CN2016/072012
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English (en)
French (fr)
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姚琪
张锋
曹占锋
何晓龙
张斌
李正亮
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京东方科技集团股份有限公司
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Priority to US15/308,991 priority Critical patent/US9812472B2/en
Publication of WO2017008497A1 publication Critical patent/WO2017008497A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating an oxide thin film transistor.
  • thin film transistors for driving and controlling pixels have also been developed, and have been developed from amorphous silicon thin film transistors and low temperature polysilicon thin film transistors to oxide thin film transistors.
  • the oxide thin film transistor is excellent in characteristics such as electron mobility, on-state current, and switching characteristics.
  • the oxide thin film transistor has the advantages of less characteristic unevenness, low material and process cost, low process temperature, available coating process, high light transmittance, and large band gap. Therefore, the oxide thin film transistor can be used for displays requiring fast response and large current, such as high frequency, high resolution, large size liquid crystal displays, and organic light emitting displays.
  • an oxide thin film transistor having an etch barrier layer needs to be prepared by four patterning processes using four masks. That is, the first mask is used to form the gate through the first patterning process; the gate insulating layer is formed; the second mask is used to form the active layer through the second patterning process; and the third mask is used to pass the third time
  • the patterning process forms an etch barrier layer; and the source electrode and the drain electrode are formed by a fourth patterning process using a fourth mask. Due to the need to prepare an etch barrier, the production cost is increased and the risk of yield reduction is increased.
  • FIG. 1(a) to 1(c) are flow charts of preparing an oxide thin film transistor using a back channel etching process according to a technique.
  • the preparation of an oxide thin film transistor by a back channel etching process requires three masks to be completed by three patterning processes. That is, the gate 02 is formed by the first patterning process using the first mask (as shown in FIG. 1(a)); the gate insulating layer 03 is formed (as shown in FIG. 1(b)); The template forms the active layer 04 through the second patterning process (as shown in FIG. 1(b)); the source electrode 05 and the drain electrode 06 are formed by the third patterning process using the third mask (FIG. 1(c) Shown).
  • the oxide thin film transistor can be simplified. Preparation process to reduce preparation costs.
  • a method of fabricating an oxide thin film transistor includes forming a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode.
  • Forming the active layer, the source electrode, and the drain electrode includes: sequentially forming an oxide semiconductor film and a source/drain electrode metal film on the substrate, the entire surface of the oxide semiconductor film and the source leakage
  • the epipolar metal film is in direct contact; and the oxide semiconductor film and the source/drain electrode metal film are patterned using a two-tone mask to form the active layer, the source electrode, and the drain electrode by one patterning process.
  • the patterning the oxide semiconductor film and the source/drain electrode metal film with a two-tone mask to form an active layer, a source electrode, and a drain electrode by one patterning process include: a metal film at the source/drain electrode Forming a photoresist layer thereon; exposing and developing the photoresist layer to form a photoresist completely reserved portion, a photoresist portion remaining portion, and a photoresist completely removed portion, wherein the photoresist completely remains portion Corresponding to a region where the source electrode and the drain electrode are to be formed, the photoresist portion remaining portion corresponds to a region between the source electrode and the drain electrode where a channel is to be formed, the photoresist portion The thickness of the photoresist in the reserved region is smaller than the thickness of the photoresist in the completely remaining portion of the photoresist, and the completely removed region of the photoresist corresponds to other regions; the first etching process is performed to remove the photoresist Completely removing the source
  • the source/drain electrode metal film is formed of Cu or a Cu alloy, and the second etching process uses a fluorine-free etchant.
  • the Cu alloy is a CuMo alloy, a CuMn alloy, a CuTa alloy, a CuCa alloy, a CuMg alloy, or a CuMgAl alloy.
  • the fluorine-free etching liquid is a fluorine-free H 2 O 2 -based etching liquid.
  • the method further includes forming a first anti-oxidation cap layer covering the source electrode and a second anti-oxidation cap layer covering the drain electrode.
  • Forming the active layer, the source electrode, the drain electrode, The first oxidation resistant cap layer and the second oxidation resistant cap layer include: sequentially forming an oxide semiconductor film, a source/drain electrode metal film, and an oxidation resistant film on the base substrate; and adopting the two-tone mask Patterning the oxide semiconductor film, the source/drain electrode metal film, and the oxidation resistant film to form the active layer, the source electrode, the drain electrode, and the first anti-etching by a patterning process An oxide cap layer and the second oxidation resistant cap layer.
  • the patterning the oxide semiconductor film, the source/drain electrode metal film, and the oxidation resistant film with the two-tone mask to form the active layer, the source electrode, and the source electrode by a patterning process comprises: forming a photoresist layer on the anti-oxidation film, exposing and developing the photoresist layer to form a photoresist completely remaining portion, a photoresist portion remaining portion, and a photoresist completely removed portion, wherein the photoresist completely remaining portion corresponds to a region where the source electrode and the drain electrode are to be formed, the photolithography
  • the glue portion remaining portion corresponds to a region between the source electrode and the drain electrode where a channel is to be formed, and a photoresist of the photoresist portion remaining region has a thickness smaller than that of the photoresist completely retained portion a thickness of the glue, the photoresist completely removed region corresponds to other regions; performing a first
  • the source/drain electrode metal film is formed of Cu or a Cu alloy, and the third etching process uses a fluorine-free etchant.
  • the Cu alloy is a CuMo alloy, a CuMn alloy, a CuTa alloy, a CuCa alloy, a CuMg alloy, or a CuMgAl alloy.
  • the fluorine-free etching liquid is a fluorine-free H 2 O 2 -based etching liquid.
  • the first etching process and the second etching process are wet etching processes, and an etching rate of the second etching process is smaller than an etching rate of the first etching process.
  • the first oxidation resistant cap layer and the second oxidation resistant cap layer are formed of Mo or MoNb.
  • the first anti-oxidation cap layer and the second anti-oxidation cap layer are made of an oxide semiconductor material form.
  • the method further includes plasma treating the first anti-oxidation cap layer and/or the second anti-oxidation cap layer.
  • the method further includes: forming a protective layer to cover the first anti-oxidation cap layer, the second anti-oxidation cap layer, the source electrode, the drain electrode, the active layer, the gate An insulating layer and the base substrate; and forming a first via hole in the protective layer to plasma treat the first oxidation resistant cap layer through the first via hole, and/or in the protection A second via is formed in the layer to plasma treat the second oxidation resistant cap layer through the second via.
  • forming the first via in the protective layer, forming a second via in the protective layer, and performing the first anti-oxidation cap layer and/or the second anti-oxidation cap layer Plasma treatment is carried out in the same dry etching apparatus.
  • the atmosphere in which the plasma treatment is performed is selected from one or more of He, SF 6 and H 2 .
  • the first oxidation resistant cap layer, the second oxidation resistant cap layer, and the active layer are formed of the same material.
  • the pattern of the first oxidation resistant cap layer is the same as the pattern of the source electrode, and the pattern of the second oxidation resistant cap layer is the same as the pattern of the drain electrode.
  • 1(a) to 1(c) are flow diagrams of preparing an oxide thin film transistor using a back channel etching process according to a technique
  • 2(a) to 2(g) illustrate a method of fabricating an oxide thin film transistor according to an embodiment of the present invention
  • 3(a) to 3(g) illustrate variations of a method of fabricating an oxide thin film transistor according to an embodiment of the present invention
  • 4(a) and 4(b) illustrate a method of fabricating an array substrate in accordance with an embodiment of the present invention.
  • Embodiments of the present invention provide a method of fabricating an oxide thin film transistor.
  • the method includes: forming a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, wherein forming the active layer, the source electrode, and the drain electrode comprises: sequentially forming an oxide on the substrate substrate a semiconductor film and a source/drain electrode metal film, the entire surface of the oxide semiconductor film is in direct contact with the source/drain electrode metal film; and the oxide semiconductor film and the source/drain electrode metal are patterned using a two-tone mask
  • the thin film forms the active layer, the source electrode, and the drain electrode by one patterning process.
  • the method of fabricating an oxide thin film transistor according to an embodiment of the present invention since the entire surface of the oxide semiconductor film is in direct contact with the source/drain electrode metal film, a back channel etching process may be employed to avoid preparation of an etch barrier. Floor. Further, in the method of fabricating an oxide thin film transistor according to an embodiment of the present invention, since a two-tone mask is employed, the active layer, the source electrode, and the drain electrode may be simultaneously formed by one patterning process Thus, the fabrication of the thin film transistor can be completed with only two masks.
  • the method of fabricating an oxide thin film transistor according to an embodiment of the present invention organically combines a back channel etching process and a two-tone mask process, and can further reduce the number of masks while avoiding the formation of an etch barrier layer. This simplifies the manufacturing process, reduces production costs, and improves product yield.
  • an oxide thin film transistor according to an embodiment of the present invention will be described with reference to the accompanying drawings Carry out a detailed description. It should be noted that the method for fabricating an oxide thin film transistor according to an embodiment of the present invention can be used for preparing a bottom gate type oxide thin film transistor, a top gate type oxide thin film transistor, or other types of oxide thin film transistors, and the bottom is only bottom.
  • a gate oxide thin film transistor is described as an example.
  • FIGS. 2(a) to 2(g) illustrate a method of fabricating an oxide thin film transistor according to an embodiment of the present invention.
  • a method of manufacturing a thin film transistor according to an embodiment of the present invention includes the following steps.
  • Step S1 forming a gate electrode
  • a gate metal thin film 20 is formed on the base substrate 10, and the gate metal thin film 20 is patterned by a single-tone mask to form the gate electrode 21.
  • the base substrate 10 may be a glass substrate, a quartz substrate, an organic substrate, or the like.
  • the gate metal thin film 20 may be formed of an alloy such as Cr, W, Cu, Ti, Ta, Mo, Al, or the like.
  • the gate metal film 20 is formed of, for example, a low-resistivity Cu or Cu alloy.
  • the Cu alloy is a CuMo alloy, a CuMn alloy, a CuTa alloy, a CuCa alloy, a CuMg alloy, a CuMgAl alloy, or the like.
  • the process of patterning the gate metal film 20 with a single-tone mask to form the gate electrode 21 is a conventional patterning process, which will not be described herein.
  • Step S2 forming a gate insulating layer
  • a gate insulating layer 30 is formed to cover the gate electrode 21 and the base substrate 10.
  • the gate insulating layer 30 is formed of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or the like by plasma enhanced chemical vapor deposition, sputtering, or the like.
  • Step S3 forming an active layer, a source electrode, and a drain electrode
  • an oxide semiconductor film 40 and a source/drain electrode metal film 50 are sequentially formed on the gate insulating layer 30, the entire surface of the oxide semiconductor film 40 and the The source/drain electrode metal film 50 is in direct contact; and the oxide semiconductor film 40 and the source/drain electrode metal film 50 are patterned using a two-tone mask to form the active layer 41, the source electrode 51, and the drain electrode by one patterning process 52.
  • the oxide semiconductor thin film 40 may be a thin film composed of at least two elements of an oxygen element and an element such as In (indium), Ga (gallium), Zn (zinc), or Sn (tin).
  • the oxide semiconductor thin film 40 may be an IGZO (indium gallium zinc oxide) thin film, an IZO (indium zinc oxide) thin film, an InSnO (indium tin oxide) thin film, an InGaSnO (indium gallium oxide) thin film, or the like.
  • the thickness of the oxide semiconductor film 40 is to Preferred to
  • the source/drain electrode metal thin film 50 may be formed of a metal such as Cr, W, Cu, Ti, Ta, Mo, Al, or an alloy such as aluminum lanthanum.
  • the source/drain electrode metal film 50 is formed of, for example, a low-resistivity Cu or Cu alloy.
  • the Cu alloy is a CuMo alloy, a CuMn alloy, a CuTa alloy, a CuCa alloy, a CuMg alloy, a CuMgAl alloy, or the like.
  • the two-tone mask is a halftone mask or a gray tone mask.
  • the patterning of the oxide semiconductor film 40 and the source/drain metal film 50 by a two-tone mask to form the active layer 41, the source electrode 51 and the drain electrode 52 by one patterning process include:
  • the thickness of the photoresist is smaller than the thickness of the photoresist in the completely remaining portion of the photoresist, and the photoresist completely removed region corresponds to other regions, as shown in FIG. 2(d);
  • the source/drain electrode metal film 50 is formed of, for example, a low-resistivity Cu or Cu alloy.
  • a display device such as a liquid crystal display device, an organic light emitting display device, or the like, by patterning the source/drain electrode metal film 50, a data line directly connected or integrally formed with the source electrode 51 may be simultaneously and in the same layer as the source electrode 51 and the drain electrode 52.
  • the source/drain electrode metal film 50 is made of low resistivity Cu or When the Cu alloy is formed, the data line, the source electrode 51, and the drain electrode 52 excellent in conductivity can be simultaneously obtained, which is very advantageous for a large-sized display device.
  • the second etching process is performed, for example, by using a fluorine-free etching solution to remove the source leakage of the photoresist portion remaining region.
  • An epipolar metal film 50 is formed to form the source electrode 51 and the drain electrode 50. The inventors have found that the source-drain electrode metal film 50 of the remaining portion of the photoresist portion can be sufficiently etched by using a fluorine-free etchant, and damage to the active layer 41 can be effectively reduced or even avoided.
  • the fluorine-free etching liquid is a fluorine-free H 2 O 2 -based etching liquid; the fluorine-free H 2 O 2 -based etching liquid is an etching liquid containing no fluorine-containing H 2 O 2 as a main component, for example, in the etching liquid.
  • the proportion of fluorine-free H 2 O 2 is about 5% to 30%.
  • the fluorine-free H 2 O 2 -based etching liquid is a neutral fluorine-free H 2 O 2 etching liquid.
  • the first etching process described above is a wet etching process and, for example, an acid etching solution is used.
  • the method of fabricating the oxide thin film transistor according to the embodiment of the present invention can be completed by the above steps S1, S2 and S3.
  • the method of fabricating an oxide thin film transistor according to an embodiment of the present invention does not require the preparation of an etch barrier layer, which organically combines a back channel etch process and a two-tone mask process, and can further reduce the formation of an etch barrier while avoiding The number of reticle simplifies the manufacturing process, reduces manufacturing costs, and improves product yield.
  • a method for preparing an oxide thin film transistor according to an embodiment of the present invention uses a Cu or a Cu alloy to form a source/drain electrode metal film, thereby obtaining a source electrode and a drain electrode having excellent conductivity characteristics, which is advantageous for an oxide thin film transistor.
  • the method for fabricating a thin film transistor uses a fluorine-free etching solution to etch and remove a source/drain electrode metal film of a portion of the photoresist remaining portion, which can sufficiently etch and remove the source and drain of the remaining portion of the photoresist portion.
  • the ultra-metal thin film can effectively reduce or even avoid damage to the active layer and improve the characteristics of the oxide thin film transistor.
  • the oxide thin film transistor In order to further improve the characteristics of the oxide thin film transistor, it is generally required to anneal the oxide thin film transistor a plurality of times or form a protective layer such as SiO 2 on the oxide thin film transistor.
  • a protective layer such as SiO 2
  • the source electrode 51 and the drain electrode 52 may be more or less oxidized, and the source electrode 51 and the drain electrode 52 are made of a low-resistivity Cu or Cu alloy. Oxidation is more pronounced in the case of formation.
  • the method of fabricating a thin film transistor according to an embodiment of the present invention further includes: forming a first oxidation resistant cap layer 61 covering the source electrode 51 and a second oxidation resistant cap layer 62 covering the drain electrode 52. .
  • a first oxidation resistant cap layer 61 covering the source electrode 51 and a second oxidation resistant cap layer 62 covering the drain electrode 52.
  • 3(a) to 3(g) show a modification of a method of manufacturing an oxide thin film transistor in which a first oxidation resistant cap layer 61 and a second oxidation resistant cap layer 62 are formed, according to an embodiment of the present invention.
  • a modification of the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention includes the following steps.
  • Step S11 forming a gate electrode
  • step is the same as the above step S1, and reference may be made to FIG. 2(a) and FIG. 2(b), and details are not described herein again.
  • Step S22 forming a gate insulating layer
  • this step is the same as step S2 above, and can be seen in FIG. 2(c), and details are not described herein again.
  • Step S33 forming an active layer, a source electrode, a drain electrode, a first oxidation resistant cap layer, and a second oxidation resistant cap layer.
  • an oxide semiconductor film 40, a source/drain electrode metal film 50, and an oxidation resistant film 60 are sequentially formed on the gate insulating layer 30; and the two-tone mask is employed.
  • the template is patterned to form the oxide semiconductor film 40, the source/drain electrode metal film 50, and the oxidation resistant film 60 to form the active layer 41, the source electrode 51, and the drain electrode 52 by one patterning process.
  • the two-tone mask is a halftone mask or a gray tone mask.
  • the oxide semiconductor film 40, the source/drain electrode metal film 50, and the oxidation resistant film 60 are patterned by using the two-tone mask to form the active layer 41 by a patterning process.
  • the source electrode 51, the drain electrode 52, the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62 comprise:
  • the thickness of the photoresist is smaller than the thickness of the photoresist in the completely remaining portion of the photoresist, and the photoresist completely removed region corresponds to other regions, as shown in FIG. 3(b);
  • the photoresist of the completely remaining portion of the photoresist is removed as shown in FIG. 3(f).
  • the source/drain electrode metal film 50 can be formed of a low-resistivity Cu or Cu alloy, whereby source and drain electrodes excellent in conductivity characteristics can be obtained, which is advantageous for application of an oxide thin film transistor to a large-sized display. Device.
  • the third etching process uses, for example, a fluorine-free etching solution to etch away the source of the photoresist portion remaining region. The electrode metal film 50 is drained to form the source electrode 51 and the drain electrode 50.
  • the fluorine-free etching liquid is a fluorine-free H 2 O 2 -based etching liquid; the fluorine-free H 2 O 2 -based etching liquid is an etching liquid containing no fluorine-containing H 2 O 2 as a main component, for example, in the etching liquid.
  • the proportion of fluorine-free H 2 O 2 is about 5% to 30%.
  • the fluorine-free H 2 O 2 -based etching liquid is a neutral fluorine-free H 2 O 2 etching liquid.
  • the first etching process and the second etching process in the above step S33 are both a wet etching process, and an acid-based etching liquid is used, for example.
  • the etch rate of the second etch process is less than the etch rate of the first etch process.
  • the oxidation resistant film 60, the source/drain metal film 50, and the oxide semiconductor film 40 in the completely removed region of the photoresist can be quickly and efficiently removed in the first etching process.
  • the second etching process the oxidation resistant film 60 of the photoresist portion remaining region can be effectively removed while preventing the etching solution from penetrating the source/drain electrode metal film 50 located in the remaining portion of the photoresist portion.
  • the active layer 41 is damaged, thereby balancing efficiency and quality.
  • the process difficulty can be reduced and the process efficiency can be improved.
  • step S33 since the second etching process and the third etching process both use the photoresist which is completely retained by the photoresist as a mask, the first anti-etch formed in the second etching process
  • the pattern of the oxide cap layer 61 and the pattern of the second oxidation resistant cap layer 62 are respectively the same as those of the source electrode 51 and the drain electrode 52 formed in the third etching process.
  • the first anti-oxidation cap layer 61 and the second anti-oxidation cap layer 62 have a thickness of to Preferred to
  • the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62 are formed of Mo, MoNb, or the like.
  • the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62 are formed of an oxide semiconductor material; in this case, the oxidation resistant film 60 is an oxide semiconductor film.
  • the oxidation-resistant film 60 is an oxide semiconductor film, the following advantageous effects can be obtained: (1) the adhesion of the oxide semiconductor film to the photoresist is good, and the first, second, and third etchings are performed as described above. The glue phenomenon does not occur in the process; (2) the galvanic effect between the oxide semiconductor film and the source/drain electrode metal film 50 (for example, formed of Cu or Cu alloy) is small, and a good etching slope angle is easily formed. Conducive to the subsequent process.
  • the oxide semiconductor material forming the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62 may be composed of oxygen and In (indium), Ga (gallium), Zn (zinc), Sn ( At least two elements of elements such as tin).
  • the oxide semiconductor material may be IGZO, IZO, InSnO, InGaSnO, or the like.
  • the oxidation resistant film 60 is an oxide semiconductor film, and the inventors of the present invention found The amount of oxygen introduced when the oxide semiconductor film is prepared is extremely small, and has little influence on the source/drain electrode metal film 50.
  • a modification of the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention further includes: The first anti-oxidation cap layer 61 and/or the second anti-oxidation cap layer 62 are subjected to plasma treatment. In this way, the first anti-oxidation cap layer 61 and/or the second anti-oxidation cap layer 62 can be converted from a semiconductor to a conductor, facilitating electrical connection between the source electrode 51 and/or the drain electrode 52 and the external line.
  • both of the second oxidation resistant cap layers 62 are plasma treated.
  • the source electrode 51 and the data line are generally Directly connected or integrally formed, the first anti-oxidation cap layer 61 covering the source electrode 51 may not be subjected to plasma treatment.
  • a modification of the method of fabricating a thin film transistor according to an embodiment of the present invention further includes: forming a protective layer 70 to cover the first anti-oxidation cap layer 61, the second anti-oxidation cap a layer 62, the source electrode 51, the drain electrode 52, the active layer 41, the gate insulating layer 30, and the base substrate 10; and forming a first via 71 in the protective layer 70
  • the first anti-oxidation cap layer 61 is plasma-treated through the first via 71, and/or a second via 72 is formed in the protective layer 70 to pass through the second via 72
  • the second anti-oxidation cap layer 62 is subjected to plasma treatment.
  • the protective layer 70 may protect the thin film transistor from the external environment, and the protective layer 70 is formed of silicon oxide, silicon nitride, or silicon oxynitride.
  • the first via 71 is formed in the protective layer 70
  • the second via 72 is formed in the protective layer 70
  • the oxidation resistant cap layer 62 is subjected to plasma treatment in the same dry etching apparatus. Thereby, the process difficulty can be simplified and the process efficiency can be improved.
  • the atmosphere for plasma treatment of the first oxidation resistant cap layer 61 and/or the second oxidation resistant cap layer 62 is selected from one or more of He, SF 6 and H 2 .
  • the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62 may be formed of an oxide semiconductor material, and the active layer 41 is obtained by patterning the oxide semiconductor film 40. It can thus be seen that the first anti-oxidation cap layer 61, the second anti-oxidation cap layer 62 and the active layer 41 can be formed of the same material, such as IGZO. As a result, equipment investment and raw material types can be reduced, and process costs can be reduced. In consideration of the respective functions of the active layer 41 and the oxidation resistant cap layers 61 and 62, for example, the thickness of the active layer 41 is smaller than the thickness of the oxidation resistant cap layers 61 and 62.
  • the oxidation resistant film 60 formed of IGZO and the oxide semiconductor thin film 40 formed of IGZO sandwich a source/drain electrode metal film 50 formed of Cu or a Cu alloy therebetween, thereby passing through the above-described step S33
  • the patterning process can obtain the first anti-oxidation cap layer 61 and the second anti-oxidation cap layer 62 formed of IGZO, the source electrode 51 and the drain electrode 52 formed of Cu or a Cu alloy, and the active layer 41 formed of IGZO. .
  • a modification of the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention can obtain the same technical effects as the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention as described above.
  • a first anti-oxidation cap layer covering the source electrode and a second anti-oxidation cap layer covering the drain electrode are formed, It is possible to prevent the source electrode and the drain electrode from being oxidized.
  • the method of fabricating the oxide thin film transistor according to the embodiment of the present invention can be well compatible with the method of fabricating the array substrate of the display device.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an organic light emitting display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • an embodiment of the present invention further provides a method of fabricating an array substrate.
  • the array substrate includes a display area and a peripheral area surrounding the display area.
  • a plurality of gate lines and a plurality of data lines cross each other to form a plurality of sub-pixels arranged in a matrix, and pixel electrodes and pixels are formed in each sub-pixel.
  • Electrode-connected thin film transistor is a method of fabricating an array substrate.
  • a method of fabricating an array substrate according to an embodiment of the present invention includes the following steps.
  • Step S111 forming a gate, a gate line, and a gate pad
  • the gate metal film 20 is patterned using a single-tone mask to simultaneously form the gate electrode 21, the gate line (not shown), and the gate pad 22 .
  • This step S111 differs from the above-described steps S1 and S11 in that the pattern of the single-tone mask is changed.
  • the gate line is connected to the gate electrode 21, and the gate line pad 22 is located in a peripheral region of the array substrate, and the gate line pad 22 is connected to the gate line to connect the gate line to the driving circuit.
  • Step S222 forming a gate insulating layer
  • a gate insulating layer 30 is formed to cover the gate electrode 21, the gate line, the gate line pad 22, and the base substrate 10.
  • Step S333 forming an active layer, a source electrode, a drain electrode, a data line, and a data line pad.
  • the oxide semiconductor film 40 and the source/drain electrode metal film 50 are patterned using a two-tone mask to form the active layer 41 and the source electrode by one patterning process. 51.
  • the step S333 differs from the above step S3 in that the pattern of the two-tone mask is changed such that the photoresist completely remains corresponding to the region where the source and drain electrodes are to be formed, the region where the data line is to be formed, and The area where the data line pads are formed.
  • the data line is connected to the source electrode 51, and the data line pad 90 is located in the peripheral area of the array substrate, and the data line pad 90 is connected to the data line to connect the data line to the driving circuit.
  • the data line pad 90 has a two-layer structure including a semiconductor layer 42.
  • the metal layer 53, the semiconductor layer 42 is formed in the same layer and the same material as the active layer 41, and the metal layer 53 is formed in the same layer and the same material as the source electrode 51 and the drain electrode 52.
  • the data line is also a two-layer structure, one layer is formed in the same layer as the active layer 41, and the other layer is formed in the same layer as the source electrode 51 and the drain electrode 52.
  • the first anti-oxidation cap layer 61 and the second anti-oxidation cap layer may also be formed in this step S333.
  • the oxide semiconductor film 40, the source/drain electrode metal film 50, and the oxidation resistant film are patterned using a two-tone mask to form an active layer by one patterning process. 41.
  • the data line pad 90 has a three-layer structure including a semiconductor layer 42, a metal layer 53, and an oxidation resistant layer 63.
  • the semiconductor layer 42 is in the same layer as the active layer 41. The material is formed.
  • the metal layer 53 is formed in the same layer and the same material as the source electrode 51 and the drain electrode 52.
  • the oxidation resistant layer 63 is formed in the same layer and the same material as the first oxidation resistant cap layer 61 and the second oxidation resistant cap layer 62.
  • the data line is also a three-layer structure, one layer is formed in the same layer as the active layer 41, and the same layer is formed in the same layer as the source electrode 51 and the drain electrode 52, and the first layer is formed with the same material.
  • the oxide cap layer 61 and the second oxidation resistant cap layer 62 are formed in the same layer and in the same material.
  • Step S444 forming a protective layer and via holes
  • a protective layer 70 is formed, and the protective layer 70 is patterned to form a second via 72, a third via 73, and a fourth via 74.
  • the second via 72 exposes the drain electrode 52
  • the third via 73 exposes the gate pad 22
  • the fourth via 74 exposes the data line pad 74.
  • Step S555 forming a pixel electrode
  • a pixel electrode 80 is formed, which is connected to the drain electrode 52 through the second via 72.
  • the pixel electrode 80 is formed of a transparent conductive material such as ITO.
  • the method for fabricating the array substrate according to the embodiment of the present invention may further include: performing plasma treatment on the second oxidation resistant cap layer 62 through the second via hole 72.
  • the oxidation resistant layer 63 in the data line pad 90 can also be plasma treated. Specific details of the plasma treatment can be referred to the above description, and will not be described herein.
  • the system for fabricating an array substrate according to an embodiment of the present invention can be completed by the above steps S111 to S555.
  • Preparation method A method of fabricating an array substrate according to an embodiment of the present invention is based on a method of fabricating an oxide thin film transistor according to an embodiment of the present invention, and thus the same technical effects as those of an oxide thin film transistor according to an embodiment of the present invention can be obtained. I will not repeat them here.

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Abstract

一种氧化物薄膜晶体管的制备方法。该氧化物薄膜晶体管的制备方法包括：形成栅极(21)、栅绝缘层(30)、有源层(41)、源电极(51)和漏电极(52)。形成所述有源层(41)、所述源电极(51)和所述漏电极(52)包括：在衬底基板(10)上依次形成氧化物半导体薄膜(40)和源漏电极金属薄膜(50)，所述氧化物半导体薄膜(40)的整个表面与所述源漏电极金属薄膜(50)直接接触；以及采用双色调掩模板图案化所述氧化物半导体薄膜(40)和所述源漏电极金属薄膜(50)以通过一次构图工艺形成所述有源层(41)、所述源电极(51)和所述漏电极(52)。

Description

氧化物薄膜晶体管的制备方法 技术领域
本发明的实施例涉及氧化物薄膜晶体管的制备方法。
背景技术
近年来，随着显示技术的快速发展，用于驱动并控制像素的薄膜晶体管也得到了发展，已由非晶硅薄膜晶体管和低温多晶硅薄膜晶体管发展到氧化物薄膜晶体管。
氧化物薄膜晶体管的电子迁移率、开态电流、开关特性等特性优良。此外，氧化物薄膜晶体管还具有特性不均现象少、材料和工艺成本低、工艺温度低、可利用涂布工艺、透光率高、带隙大等优点。因此，氧化物薄膜晶体管可以用于需要快速响应和较大电流的显示器，如高频、高分辨率、大尺寸的液晶显示器以及有机发光显示器等。
通常，具有蚀刻阻挡层的氧化物薄膜晶体管需要采用四块掩模板通过四次构图工艺来制备。即：采用第一块掩模板通过第一次构图工艺形成栅极；形成栅绝缘层；采用第二块掩模板通过第二次构图工艺形成有源层；采用第三块掩模板通过第三次构图工艺形成蚀刻阻挡层；并且采用第四块掩模板通过第四次构图工艺形成源电极和漏电极。由于需要制备蚀刻阻挡层，增加了生产成本并增加了良率降低的风险。
目前，出现了不采用蚀刻阻挡层的背沟道蚀刻工艺。图1(a)至图1(c)为根据一种技术的采用背沟道蚀刻工艺制备氧化物薄膜晶体管的流程图。如图1(a)至图1(c)所示，采用背沟道蚀刻工艺制备氧化物薄膜晶体管需要采用三块掩模板通过三次构图工艺来完成。即：采用第一块掩模板通过第一次构图工艺形成栅极02(如图1(a)所示)；形成栅绝缘层03(如图1(b)所示)；采用第二块掩模板通过第二次构图工艺形成有源层04(如图1(b)所示)；采用第三块掩模板通过第三次构图工艺形成源电极05和漏电极06(如图1(c)所示)。
如果能够进一步减少掩模板的数量，则可以简化氧化物薄膜晶体管的制 备工艺，降低制备成本。
发明内容
根据本发明的实施例，提供一种氧化物薄膜晶体管的制备方法。该氧化物薄膜晶体管的制备方法包括：形成栅极、栅绝缘层、有源层、源电极和漏电极。形成所述有源层、所述源电极和所述漏电极包括：在衬底基板上依次形成氧化物半导体薄膜和源漏电极金属薄膜，所述氧化物半导体薄膜的整个表面与所述源漏电极金属薄膜直接接触；以及采用双色调掩模板图案化所述氧化物半导体薄膜和所述源漏电极金属薄膜以通过一次构图工艺形成所述有源层、所述源电极和所述漏电极。
例如，所述采用双色调掩模板图案化所述氧化物半导体薄膜和所述源漏电极金属薄膜以通过一次构图工艺形成有源层、源电极和漏电极包括：在所述源漏电极金属薄膜上形成光刻胶层；对所述光刻胶层进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极和所述漏电极的区域，所述光刻胶部分保留部分对应于所述源电极和所述漏电极之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域；进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述源漏金属薄膜和所述氧化物半导体薄膜，以形成所述有源层；进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶；进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜，以形成所述源电极和所述漏电极；以及去除所述光刻胶完全保留部分的光刻胶。
例如，所述源漏电极金属薄膜由Cu或Cu合金形成，且所述第二次蚀刻工艺采用无氟蚀刻液。
例如，所述Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金或CuMgAl合金。
例如，所述无氟蚀刻液为无氟H2O2系蚀刻液。
例如，所述方法还包括：形成覆盖所述源电极的第一抗氧化盖层和覆盖所述漏电极的第二抗氧化盖层。形成所述有源层、所述源电极、所述漏电极、 所述第一抗氧化盖层和所述第二抗氧化盖层包括：在所述衬底基板上依次形成氧化物半导体薄膜、源漏电极金属薄膜和抗氧化薄膜；以及采用所述双色调掩模板图案化所述氧化物半导体薄膜、所述源漏电极金属薄膜和所述抗氧化薄膜以通过一次构图工艺形成所述有源层、所述源电极、所述漏电极、所述第一抗氧化盖层和所述第二抗氧化盖层。
例如，所述采用所述双色调掩模板图案化所述氧化物半导体薄膜、所述源漏电极金属薄膜和所述抗氧化薄膜以通过一次构图工艺形成所述有源层、所述源电极、所述漏电极、所述第一抗氧化盖层和所述第二抗氧化盖层包括：在所述抗氧化薄膜上形成光刻胶层，对所述光刻胶层进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极和所述漏电极的区域，所述光刻胶部分保留部分对应于所述源电极和所述漏电极之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域；进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述抗氧化薄膜、所述源漏金属薄膜和所述氧化物半导体薄膜，以形成所述有源层；进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶；进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述抗氧化薄膜，以形成所述第一抗氧化盖层和所述第二抗氧化盖层；进行第三次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜，以形成所述源电极和所述漏电极；以及去除所述光刻胶完全保留部分的光刻胶。
例如，所述源漏电极金属薄膜由Cu或Cu合金形成，且所述第三次蚀刻工艺采用无氟蚀刻液。
例如，所述Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金或CuMgAl合金。
例如，所述无氟蚀刻液为无氟H2O2系蚀刻液。
例如，所述第一次蚀刻工艺和所述第二次蚀刻工艺为湿法蚀刻工艺，且所述第二次蚀刻工艺的蚀刻速率小于所述第一次蚀刻工艺的蚀刻速率。
例如，所述第一抗氧化盖层和所述第二抗氧化盖层由Mo或MoNb形成。
例如，所述第一抗氧化盖层和所述第二抗氧化盖层由氧化物半导体材料 形成。
例如，所述方法还包括：对所述第一抗氧化盖层和/或所述第二抗氧化盖层进行等离子体处理。
例如，所述方法还包括：形成保护层以覆盖所述第一抗氧化盖层、所述第二抗氧化盖层、所述源电极、所述漏电极、所述有源层、所述栅绝缘层和所述衬底基板；以及在所述保护层中形成第一过孔以通过所述第一过孔对所述第一抗氧化盖层进行等离子体处理，和/或在所述保护层中形成第二过孔以通过所述第二过孔对所述第二抗氧化盖层进行等离子体处理。
例如，在所述保护层中形成所述第一过孔、在所述保护层中形成第二过孔、以及对所述第一抗氧化盖层和/或所述第二抗氧化盖层进行等离子体处理在同一干刻设备中进行。
例如，进行所述等离子处理的气氛选自He、SF6和H2中的一种或几种。
例如，所述第一抗氧化盖层、所述第二抗氧化盖层和所述有源层由相同的材料形成。
例如，所述第一抗氧化盖层的图案与所述源电极的图案相同，并且所述第二抗氧化盖层的图案与所述漏电极的图案相同。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1(a)至图1(c)为根据一种技术的采用背沟道蚀刻工艺制备氧化物薄膜晶体管的流程图；
图2(a)至图2(g)示出了根据本发明实施例的氧化物薄膜晶体管的制备方法；
图3(a)至图3(g)示出了根据本发明实施例的氧化物薄膜晶体管的制备方法的变形；以及
图4(a)和图4(b)示出了根据本发明实施例的阵列基板的制备方法。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明的实施例提供一种氧化物薄膜晶体管的制备方法。该方法包括：形成栅极、栅绝缘层、有源层、源电极和漏电极，其中形成所述有源层、所述源电极和所述漏电极包括：在衬底基板上依次形成氧化物半导体薄膜和源漏电极金属薄膜，所述氧化物半导体薄膜的整个表面与所述源漏电极金属薄膜直接接触；以及采用双色调掩模板图案化所述氧化物半导体薄膜和所述源漏电极金属薄膜以通过一次构图工艺形成有源层、源电极和漏电极。
在根据本发明实施例的氧化物薄膜晶体管的制备方法中，由于所述氧化物半导体薄膜的整个表面与所述源漏电极金属薄膜直接接触，所以可以采用背沟道蚀刻工艺而避免制备蚀刻阻挡层。进一步地，在根据本发明实施例的氧化物薄膜晶体管的制备方法中，由于采用了双色调掩模板，所以所述有源层、所述源电极和所述漏电极可以通过一次构图工艺同时形成，从而只需两块掩模板即可完成薄膜晶体管的制备。因此，根据本发明实施例的氧化物薄膜晶体管的制备方法将背沟道蚀刻工艺和双色调掩模工艺有机地结合在了一起，能够在避免制作蚀刻阻挡层的同时进一步减少掩模板的数量，从而简化了制作工艺、降低了制作成本、提高了产品良率。
下面，将结合附图对根据本发明实施例的氧化物薄膜晶体管的制备方法 进行详细的描述。需要说明的是，根据本发明实施例的氧化物薄膜晶体管的制备方法可以用于制备底栅型氧化物薄膜晶体管、顶栅型氧化物薄膜晶体管或其他类型的氧化物薄膜晶体管，下面仅以底栅型氧化物薄膜晶体管为例进行描述。
图2(a)至2(g)示出了根据本发明实施例的氧化物薄膜晶体管的制备方法。例如，如图2(a)至2(g)所示，根据本发明实施例的薄膜晶体管的制备方法包括如下步骤。
步骤S1：形成栅极；
如图2(a)和2(b)所示，在衬底基板10上形成栅极金属薄膜20，采用单色调掩模板图案化栅极金属薄膜20以形成栅极21。
例如，衬底基板10可以为玻璃基板、石英基板、有机物基板等。例如，栅极金属薄膜20可以采用Cr、W、Cu、Ti、Ta、Mo、Al等金属或铝钕等合金形成。进一步地，为了获得导电特性优良的栅极21，栅极金属膜20例如由低电阻率的Cu或Cu合金形成。例如，Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金、CuMgAl合金等。
采用单色调掩模板图案化栅极金属薄膜20以形成栅极21的工艺为常规的图案化工艺，在此不再赘述。
步骤S2：形成栅绝缘层；
如图2(c)所示，形成栅绝缘层30以覆盖栅极21和衬底基板10。例如，栅绝缘层30采用等离子体增强化学气相沉积、溅射等方法由氮化硅，氧化硅，氮氧化硅、氧化铝等形成。
步骤S3：形成有源层、源电极和漏电极；
例如，如图2(c)至2(g)所示，在栅绝缘层30上依次形成氧化物半导体薄膜40和源漏电极金属薄膜50，所述氧化物半导体薄膜40的整个表面与所述源漏电极金属薄膜50直接接触；并且采用双色调掩模板图案化所述氧化物半导体薄膜40和所述源漏电极金属薄膜50以通过一次构图工艺形成有源层41、源电极51和漏电极52。
例如，所述氧化物半导体薄膜40可以为由氧元素和In(铟)、Ga(镓)、Zn(锌)、Sn(锡)等元素中的至少两种元素构成的薄膜。例如，所述氧化物半导体薄膜40可以为IGZO(氧化铟镓锌)薄膜、IZO(氧化铟锌)薄膜、 InSnO(氧化铟锡)薄膜、InGaSnO(氧化铟镓锡)薄膜等。例如，氧化物半导体薄膜40的厚度为
Figure PCTCN2016072012-appb-000001
至
Figure PCTCN2016072012-appb-000002
优选为
Figure PCTCN2016072012-appb-000003
至
Figure PCTCN2016072012-appb-000004
例如，所述源漏电极金属薄膜50可以采用Cr、W、Cu、Ti、Ta、Mo、Al等金属或铝钕等合金形成。进一步地，为了获得导电特性优良的源电极51和漏电极52，所述源漏电极金属薄膜50例如由低电阻率的Cu或Cu合金形成。例如，Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金、CuMgAl合金等。
例如，双色调掩模板为半色调掩模板或灰色调掩模板。
例如，所述采用双色调掩模板图案化所述氧化物半导体薄膜40和所述源漏电极金属薄膜50以通过一次构图工艺形成有源层41、源电极51和漏电极52包括：
在所述源漏电极金属薄膜上形成光刻胶层PR，如图2(c)所示；
对所述光刻胶层PR进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极51和所述漏电极52的区域，所述光刻胶部分保留部分对应于所述源电极51和所述漏电极52之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域，如图2(d)所示；
进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述源漏金属薄膜50和所述氧化物半导体薄膜40，以形成所述有源层41，如图2(e)所示；
进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶，如图2(f)所示；
进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，以形成所述源电极51和所述漏电极50，如图2(g)所示；以及
去除所述光刻胶完全保留部分的光刻胶，如图2(g)所示。
如上所述，为了获得导电特性优良的源电极51和漏电极52，所述源漏电极金属薄膜50例如由低电阻率的Cu或Cu合金形成。对于诸如液晶显示装置、有机发光显示装置等的显示装置，通过图案化源漏电极金属薄膜50，与源电极51直接连接或一体形成的数据线可以与源电极51和漏电极52同时且同层形成；在此情形下，如果源漏电极金属薄膜50采用低电阻率的Cu或 Cu合金形成，则可以同时获得导电特性优良的数据线、源电极51和漏电极52，这对于大尺寸的显示装置而言是非常有利的。
进一步地，在所述源漏电极金属薄膜50由Cu或Cu合金形成的情形下，上述第二次蚀刻工艺例如采用无氟蚀刻液来蚀刻去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，以形成所述源电极51和所述漏电极50。发明人发现采用无氟蚀刻液既可以充分地蚀刻去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，又可以有效地减少甚至避免对有源层41的损伤。例如，所述无氟蚀刻液为无氟H2O2系蚀刻液；无氟H2O2系蚀刻液是以无氟H2O2为主要成分的蚀刻液，例如在该种蚀刻液中无氟H2O2所占的比例约为5％至30％。进一步地，例如，无氟H2O2系蚀刻液为中性无氟H2O2蚀刻液。
例如，上述第一次蚀刻工艺为湿法蚀刻工艺并例如采用酸系蚀刻液。
通过上述步骤S1、S2和S3即可完成根据本发明实施例的氧化物薄膜晶体管的制备方法。根据本发明实施例的氧化物薄膜晶体管的制备方法不用制备蚀刻阻挡层，其将背沟道蚀刻工艺和双色调掩模工艺有机地结合在了一起，能够在避免制作蚀刻阻挡层的同时进一步减少掩模板的数量，从而简化了制作工艺、降低了制作成本、提高了产品良率。进一步地，根据本发明实施例的氧化物薄膜晶体管的制备方法采用Cu或Cu合金形成源漏电极金属薄膜，由此可以获得导电特性优良的源电极和漏电极，有利于氧化物薄膜晶体管应用于大尺寸的显示装置。进一步地，根据本发明实施例的薄膜晶体管的制备方法采用无氟蚀刻液来蚀刻去除光刻胶部分保留区域的源漏电极金属薄膜，既可以充分地蚀刻去除光刻胶部分保留区域的源漏电极金属薄膜，又可以有效地减少甚至避免对有源层的损伤，提高了氧化物薄膜晶体管的特性。
为了进一步提高氧化物薄膜晶体管的特性，通常需要对氧化物薄膜晶体管进行多次退火或在氧化物薄膜晶体管上形成例如SiO2的保护层。在进行多次退火或形成例如SiO2的保护层时，源电极51和漏电极52可能会被或多或少地氧化，而在源电极51和漏电极52由低电阻率的Cu或Cu合金形成的情形下氧化是比较明显的。为了避免这一问题，根据本发明实施例的薄膜晶体管的制备方法还包括：形成覆盖所述源电极51的第一抗氧化盖层61和覆盖所述漏电极52的第二抗氧化盖层62。通过形成第一抗氧化盖层61和第二抗氧化盖层62，可以有效地防止源电极51和漏电极52被氧化。
图3(a)至3(g)示出了根据本发明实施例的氧化物薄膜晶体管的制备方法的变形，其中形成了第一抗氧化盖层61和第二抗氧化盖层62。例如，根据本发明实施例的氧化物薄膜晶体管的制备方法的变形包括如下步骤。
步骤S11：形成栅极；
例如，该步骤与上述步骤S1相同，可以参见图2(a)和图2(b)，在此不再赘述。
步骤S22：形成栅绝缘层；
例如，该步骤与上述步骤S2相同，可以参见图2(c)，在此不再赘述。
步骤S33：形成有源层、源电极、漏电极、第一抗氧化盖层和第二抗氧化盖层。
例如，如图3(a)至图3(f)所示，在栅绝缘层30上依次形成氧化物半导体薄膜40、源漏电极金属薄膜50和抗氧化薄膜60；并且采用所述双色调掩模板图案化所述氧化物半导体薄膜40、所述源漏电极金属薄膜50和所述抗氧化薄膜60以通过一次构图工艺形成所述有源层41、所述源电极51、所述漏电极52、所述第一抗氧化盖层61和所述第二抗氧化盖层62。
例如，双色调掩模板为半色调掩模板或灰色调掩模板。
例如，所述采用所述双色调掩模板图案化所述氧化物半导体薄膜40、所述源漏电极金属薄膜50和所述抗氧化薄膜60以通过一次构图工艺形成所述有源层41、所述源电极51、所述漏电极52、所述第一抗氧化盖层61和所述第二抗氧化盖层62包括：
在所述抗氧化薄膜60上形成光刻胶层PR，如图3(a)所示；
对所述光刻胶层PR进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极和所述漏电极的区域，所述光刻胶部分保留部分对应于所述源电极和所述漏电极之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域，如图3(b)所示；
进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述抗氧化薄膜60、所述源漏金属薄膜50和所述氧化物半导体薄膜40，以形成所述有源层41，如图3(c)所示；
进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶，如图3(d)所示；
进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述抗氧化薄膜60，以形成所述第一抗氧化盖层61和所述第二抗氧化盖层62，如图3(e)所示；
进行第三次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，以形成所述源电极51和所述漏电极52，如图3(f)所示；以及
去除所述光刻胶完全保留部分的光刻胶，如图3(f)所示。
例如，如上所述，源漏电极金属薄膜50可以由低电阻率的Cu或Cu合金形成，由此可以获得导电特性优良的源电极和漏电极，有利于氧化物薄膜晶体管应用于大尺寸的显示装置。进一地，在所述源漏电极金属薄膜50由Cu或Cu合金形成的情形下，上述第三次蚀刻工艺例如采用无氟蚀刻液来蚀刻去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，以形成所述源电极51和所述漏电极50。如上所述，发明人发现采用无氟蚀刻液既可以充分地蚀刻去除所述光刻胶部分保留区域的所述源漏电极金属薄膜50，又可以有效地减少甚至避免对有源层41的损伤。例如，所述无氟蚀刻液为无氟H2O2系蚀刻液；无氟H2O2系蚀刻液是以无氟H2O2为主要成分的蚀刻液，例如在该种蚀刻液中无氟H2O2所占的比例约为5％至30％。进一步地，例如，无氟H2O2系蚀刻液为中性无氟H2O2蚀刻液。
例如，上述步骤S33中的第一次蚀刻工艺和第二次蚀刻工艺均为湿法蚀刻工艺，并采用例如酸系蚀刻液。例如，所述第二次蚀刻工艺的蚀刻速率小于所述第一次蚀刻工艺的蚀刻速率。这样一来，既可以在第一次蚀刻工艺中快速、有效地去除所述光刻胶完全去除区域的所述抗氧化薄膜60、所述源漏金属薄膜50和所述氧化物半导体薄膜40，又可以在第二次蚀刻工艺中有效去除所述光刻胶部分保留区域的所述抗氧化薄膜60并同时防止蚀刻液刻穿位于所述光刻胶部分保留区域的源漏电极金属薄膜50而损伤有源层41，从而兼顾了效率和质量。另外，由于第一次蚀刻工艺和第二次蚀刻工艺仅在蚀刻速率上进行了调整，因此可以降低工艺难度，提高工艺效率。
在上述步骤S33中，由于第二次蚀刻工艺和第三次蚀刻工艺均采用光刻胶完全保留部分的光刻胶作为掩模，因此在第二次蚀刻工艺中形成的第一抗 氧化盖层61的图案和第二抗氧化盖层62的图案分别与第三次蚀刻工艺中形成的源电极51的图案和漏电极52的图案相同。
例如，所述第一抗氧化盖层61和所述第二抗氧化盖层62厚度为
Figure PCTCN2016072012-appb-000005
至
Figure PCTCN2016072012-appb-000006
优选为
Figure PCTCN2016072012-appb-000007
至
Figure PCTCN2016072012-appb-000008
例如，所述第一抗氧化盖层61和所述第二抗氧化盖层62由Mo、MoNb等形成。
例如，所述第一抗氧化盖层61和所述第二抗氧化盖层62由氧化物半导体材料形成；在此情形下，抗氧化薄膜60为氧化物半导体薄膜。例如，抗氧化薄膜60为氧化物半导体薄膜时可以带来以下有益效果：(1)氧化物半导体薄膜与光刻胶的结合力好，在上述的第一次、第二次及第三次蚀刻工艺中不会发生掉胶现象；(2)氧化物半导体薄膜与源漏电极金属薄膜50(例如，由Cu或Cu合金形成)之间的原电池效应小，容易形成较好的蚀刻坡度角，有利于后续工艺的进行。例如，形成所述第一抗氧化盖层61和所述第二抗氧化盖层62的氧化物半导体材料可以为由氧元素和In(铟)、Ga(镓)、Zn(锌)、Sn(锡)等元素中的至少两种元素构成。例如，氧化物半导体材料可以为IGZO、IZO、InSnO、InGaSnO等。
需要说明的是，在所述第一抗氧化盖层61和所述第二抗氧化盖层62由氧化物半导体材料形成的情形下抗氧化薄膜60为氧化物半导体薄膜，本发明的发明人发现，制备该氧化物半导体薄膜时引入的氧量非常小，对源漏电极金属薄膜50几乎没有影响。
例如，在所述第一抗氧化盖层61和所述第二抗氧化盖层62由氧化物半导体材料形成的情形下，根据本发明实施例的氧化物薄膜晶体管的制备方法的变形还包括：对所述第一抗氧化盖层61和/或所述第二抗氧化盖层62进行等离子体处理。这样一来，可以将第一抗抗氧化盖层61和/或第二抗氧化盖层62由半导体转化成导体，有利于源电极51和/或漏电极52与外部线路之间的电连接。
需要说明的是，需要根据具体应用来确定是仅对第一抗氧化盖层61进行等离子处理、或仅对第二抗氧化盖层62进行等离子体处理、或者对第一抗氧化盖层61和第二抗氧化盖层62两者进行等离子体处理。例如，对于诸如液晶显示装置、有机发光显示装置等的显示装置而言，通常源电极51与数据线 直接连接或一体形成，所以可以不对覆盖源电极51的第一抗氧化盖层61进行等离子体处理。
例如，如图3(g)所示，根据本发明实施例的薄膜晶体管的制备方法的变形还包括：形成保护层70以覆盖所述第一抗氧化盖层61、所述第二抗氧化盖层62、所述源电极51、所述漏电极52、所述有源层41、所述栅绝缘层30和所述衬底基板10；以及在所述保护层70中形成第一过孔71以通过所述第一过孔71对所述第一抗氧化盖层61进行等离子体处理，和/或在所述保护层70中形成第二过孔72以通过所述第二过孔72对所述第二抗氧化盖层62进行等离子体处理。例如，保护层70可以保护薄膜晶体管免受外部环境的影响，并且保护层70由氧化硅、氮化硅或氮氧化硅形成。例如，在所述保护层70中形成所述第一过孔71、在所述保护层70中形成第二过孔72、以及对所述第一抗氧化盖层61和/或所述第二抗氧化盖层62进行等离子体处理在同一干刻设备中进行。由此，可以简化工艺难度，提高工艺效率。
例如，对所述第一抗氧化盖层61和/或所述第二抗氧化盖层62进行等离子体处理的气氛选自He、SF6和H2中的一种或几种。
基于上面的描述，第一抗氧化盖层61和第二抗氧化盖层62可以由氧化物半导体材料形成，而有源层41是图案化氧化物半导体薄膜40得到的。因此可见，第一抗氧化盖层61、第二抗氧化盖层62和有源层41可以由相同的材料形成，例如IGZO。由此，可以减少设备投入和原材料种类，降低工艺成本。考虑到有源层41和抗氧化盖层61和62各自的功能，例如有源层41的厚度小于抗氧化盖层61和62的厚度。例如，在一个示例中，由IGZO形成的抗氧化薄膜60和由IGZO形成的氧化物半导体薄膜40将由Cu或Cu合金形成的源漏电极金属薄膜50夹持在它们之间，从而通过上述步骤S33的图案化工艺可以得到由IGZO形成的第一抗氧化盖层61和第二抗氧化盖层62、由Cu或Cu合金形成的源电极51和漏电极52、以及由IGZO形成的有源层41。
根据本发明实施例的氧化物薄膜晶体管的制备方法的变形可以获得与如上所述的根据本发明实施例的氧化物薄膜晶体管的制备方法相同的技术效果。除此之外，在根据本发明实施例的氧化物薄膜晶体管的制备方法的变形中，形成了覆盖源电极的第一抗氧化盖层和覆盖漏电极的第二抗氧化盖层， 可以防止源电极和漏电极被氧化。
需要说明的是，根据本发明实施例的氧化物薄膜晶体管的制备方法可以与显示装置的阵列基板的制备方法很好地兼容。例如，显示装置可以为液晶面板、有机发光显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
基于根据本发明实施例的氧化物薄膜晶体管的制备方法，本发明的实施例还提供一种阵列基板的制备方法。该阵列基板包括显示区域和围绕显示区域的周边区域，在显示区域中多条栅线与多条数据线彼此交叉形成呈矩阵排列的多个子像素，在每个子像素中形成有像素电极和与像素电极连接的薄膜晶体管。
例如，根据本发明实施例的阵列基板的制备方法包括如下步骤。
步骤S111：形成栅极、栅线和栅线焊垫
例如，如图2(a)和图2(b)所示，采用单色调掩模板图案化栅极金属薄膜20，以同时形成栅极21、栅线(未示出)以及栅线焊垫22。该步骤S111与上述步骤S1和S11的区别在于对单色调掩模板的图案进行了改变。
例如，栅线与栅极21连接，栅线焊垫22位于阵列基板的周边区域，该栅线焊垫22与栅线连接以将栅线连接到驱动电路。
步骤S222：形成栅绝缘层
例如，如图2(c)所示，形成栅绝缘层30以覆盖栅极21、栅线、栅线焊垫22和衬底基板10。
步骤S333：形成有源层、源电极、漏电极、数据线和数据线焊垫。
例如，如图2(c)至图2(g)所示，采用双色调掩模板图案化氧化物半导体薄膜40和源漏电极金属薄膜50，以通过一次构图工艺形成有源层41、源电极51、漏电极52、数据线(未示出)、数据线焊垫90。该步骤S333与上述步骤S3的区别在于对双色调掩模板的图案进行了改变，以使得光刻胶完全保留部分对应于要形成源电极和漏电极的区域、要形成数据线的区域、以及要形成数据线焊垫的区域。
例如，数据线与源电极51连接，数据线焊垫90位于阵列基板的周边区域，该数据线焊垫90与数据线连接以将数据线连接到驱动电路。
例如，如图2(g)所示，数据线焊垫90为双层结构，包括半导体层42 和金属层53，半导体层42与有源层41同层、同材料形成，金属层53与源电极51和漏电极52同层、同材料形成。相似地，数据线也为双层结构，一层与有源层41同层、同材料形成，另一层与源电极51和漏电极52同层、同材料形成。
另外，需要说明的是，在该步骤S333中还可以形成第一抗氧化盖层61和第二抗氧化盖层。例如，如图3(a)至图3(f)所示，采用双色调掩模板图案化氧化物半导体薄膜40、源漏电极金属薄膜50和抗氧化薄膜，以通过一次构图工艺形成有源层41、源电极51、漏电极52、数据线(未示出)、数据线焊垫90、第一抗氧化盖层61和第二抗氧化盖层62。在该情形下，如图3(f)所示，数据线焊垫90为三层结构，包括半导体层42、金属层53和抗氧化层63，半导体层42与有源层41同层、同材料形成，金属层53与源电极51和漏电极52同层、同材料形成，抗氧化层63与第一抗氧化盖层61和第二抗氧化盖层62同层、同材料形成。相似地，数据线也为三层结构，一层与有源层41同层、同材料形成，另一层与源电极51和漏电极52同层、同材料形成，再一层与第一抗氧化盖层61和第二抗氧化盖层62同层、同材料形成。
步骤S444：形成保护层及过孔
例如，如图4(a)所示，形成保护层70，并对保护层70图案化以形成第二过孔72、第三过孔73和第四过孔74。第二过孔72露出漏电极52，第三过孔73露出栅线焊垫22，而第四过孔74露出数据线焊垫74。
步骤S555：形成像素电极
例如，如图4(b)所示，形成像素电极80，该像素电极80通过第二过孔72与漏电极52连接。例如，像素电极80由透明导电材料(例如，ITO)形成。
需要说明的是，在步骤S444之后且在步骤S555之前，根据本发明实施例的阵列基板的制备方法还可以包括：通过第二过孔72对第二抗氧化盖层62进行等离子体处理。与此同时，还可以对数据线焊垫90中的抗氧化层63进行等离子体处理。等离子体处理的具体细节可以参见上面的描述，在此不再赘述。
通过上述步骤S111至S555即可完成根据本发明实施例的阵列基板的制 备方法。根据本发明实施例的阵列基板的制备方法以根据本发明实施例的氧化物薄膜晶体管的制备方法为基础，因而可以取得与根据本发明实施例的氧化物薄膜晶体管的制备方法相同的技术效果，在此不再赘述。
以上所述仅是本发明的示范性实施例，而非用于限制本发明的保护范围，本发明的保护范围由权利要求确定。
本申请要求于2015年7月15日递交的第201510415622.5号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种氧化物薄膜晶体管的制备方法，包括：形成栅极、栅绝缘层、有源层、源电极和漏电极，其中
    形成所述有源层、所述源电极和所述漏电极包括：
    在衬底基板上依次形成氧化物半导体薄膜和源漏电极金属薄膜，所述氧化物半导体薄膜的整个表面与所述源漏电极金属薄膜直接接触；以及
    采用双色调掩模板图案化所述氧化物半导体薄膜和所述源漏电极金属薄膜以通过一次构图工艺形成所述有源层、所述源电极和所述漏电极。
  2. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，其中所述采用双色调掩模板图案化所述氧化物半导体薄膜和所述源漏电极金属薄膜以通过一次构图工艺形成有源层、源电极和漏电极包括：
    在所述源漏电极金属薄膜上形成光刻胶层；
    对所述光刻胶层进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极和所述漏电极的区域，所述光刻胶部分保留部分对应于所述源电极和所述漏电极之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域；
    进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述源漏金属薄膜和所述氧化物半导体薄膜，以形成所述有源层；
    进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶；
    进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜，以形成所述源电极和所述漏电极；以及
    去除所述光刻胶完全保留部分的光刻胶。
  3. 根据权利要求2所述的氧化物薄膜晶体管的制备方法，其中所述源漏电极金属薄膜由Cu或Cu合金形成，且所述第二次蚀刻工艺采用无氟蚀刻液。
  4. 根据权利要求3所述的氧化物薄膜晶体管的制备方法，其中所述Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金或CuMgAl合金。
  5. 根据权利要求3所述的氧化物薄膜晶体管的制备方法，其中所述无氟蚀刻液为无氟H2O2系蚀刻液。
  6. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，还包括：形成覆盖所述源电极的第一抗氧化盖层和覆盖所述漏电极的第二抗氧化盖层，
    其中形成所述有源层、所述源电极、所述漏电极、所述第一抗氧化盖层和所述第二抗氧化盖层包括：
    在所述衬底基板上依次形成氧化物半导体薄膜、源漏电极金属薄膜和抗氧化薄膜；以及
    采用所述双色调掩模板图案化所述氧化物半导体薄膜、所述源漏电极金属薄膜和所述抗氧化薄膜以通过一次构图工艺形成所述有源层、所述源电极、所述漏电极、所述第一抗氧化盖层和所述第二抗氧化盖层。
  7. 根据权利要求6所述的氧化物薄膜晶体管的制备方法，其中所述采用所述双色调掩模板图案化所述氧化物半导体薄膜、所述源漏电极金属薄膜和所述抗氧化薄膜以通过一次构图工艺形成所述有源层、所述源电极、所述漏电极、所述第一抗氧化盖层和所述第二抗氧化盖层包括：
    在所述抗氧化薄膜上形成光刻胶层，对所述光刻胶层进行曝光、显影以形成光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，其中所述光刻胶完全保留部分对应于要形成所述源电极和所述漏电极的区域，所述光刻胶部分保留部分对应于所述源电极和所述漏电极之间要形成沟道的区域，所述光刻胶部分保留区域的光刻胶的厚度小于所述光刻胶完全保留部分的光刻胶的厚度，所述光刻胶完全去除区域对应于其他区域；
    进行第一次蚀刻工艺，去除所述光刻胶完全去除区域的所述抗氧化薄膜、所述源漏金属薄膜和所述氧化物半导体薄膜，以形成所述有源层；
    进行灰化工艺，去除所述光刻胶部分保留区域的光刻胶；
    进行第二次蚀刻工艺，去除所述光刻胶部分保留区域的所述抗氧化薄膜，以形成所述第一抗氧化盖层和所述第二抗氧化盖层；
    进行第三次蚀刻工艺，去除所述光刻胶部分保留区域的所述源漏电极金属薄膜，以形成所述源电极和所述漏电极；以及
    去除所述光刻胶完全保留部分的光刻胶。
  8. 根据权利要求7所述的氧化物薄膜晶体管的制备方法，其中所述源漏 电极金属薄膜由Cu或Cu合金形成，且所述第三次蚀刻工艺采用无氟蚀刻液。
  9. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中所述Cu合金为CuMo合金、CuMn合金、CuTa合金、CuCa合金、CuMg合金或CuMgAl合金。
  10. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中所述无氟蚀刻液为无氟H2O2系蚀刻液。
  11. 根据权利要求7所述的氧化物薄膜晶体管的制备方法，其中所述第一次蚀刻工艺和所述第二次蚀刻工艺为湿法蚀刻工艺，且所述第二次蚀刻工艺的蚀刻速率小于所述第一次蚀刻工艺的蚀刻速率。
  12. 根据权利要求6所述的氧化物薄膜晶体管的制备方法，其中所述第一抗氧化盖层和所述第二抗氧化盖层由Mo或MoNb形成。
  13. 根据权利要求6所述的氧化物薄膜晶体管的制备方法，其中所述第一抗氧化盖层和所述第二抗氧化盖层由氧化物半导体材料形成。
  14. 根据权利要求13所述的氧化物薄膜晶体管的制备方法，还包括：对所述第一抗氧化盖层和/或所述第二抗氧化盖层进行等离子体处理。
  15. 根据权利要求14所述的氧化物薄膜晶体管的制备方法，还包括：
    形成保护层以覆盖所述第一抗氧化盖层、所述第二抗氧化盖层、所述源电极、所述漏电极、所述有源层、所述栅绝缘层和所述衬底基板；以及
    在所述保护层中形成第一过孔以通过所述第一过孔对所述第一抗氧化盖层进行等离子体处理，和/或在所述保护层中形成第二过孔以通过所述第二过孔对所述第二抗氧化盖层进行等离子体处理。
  16. 根据权利要求15所述的氧化物薄膜晶体管的制备方法，其中在所述保护层中形成所述第一过孔、在所述保护层中形成第二过孔、以及对所述第一抗氧化盖层和/或所述第二抗氧化盖层进行等离子体处理在同一干刻设备中进行。
  17. 根据权利要求14所述的氧化物薄膜晶体管的制备方法，其中进行所述等离子处理的气氛选自He、SF6和H2中的一种或几种。
  18. 根据权利要求13-17任一项所述的氧化物薄膜晶体管的制备方法，其中所述第一抗氧化盖层、所述第二抗氧化盖层和所述有源层由相同的材料形成。
  19. 根据权利要求6-17任一项所述的氧化物薄膜晶体管的制备方法，其中所述第一抗氧化盖层的图案与所述源电极的图案相同，并且所述第二抗氧化盖层的图案与所述漏电极的图案相同。
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