WO2013131380A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

Info

Publication number
WO2013131380A1
WO2013131380A1 PCT/CN2012/084698 CN2012084698W WO2013131380A1 WO 2013131380 A1 WO2013131380 A1 WO 2013131380A1 CN 2012084698 W CN2012084698 W CN 2012084698W WO 2013131380 A1 WO2013131380 A1 WO 2013131380A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
photoresist
film
metal
Prior art date
Application number
PCT/CN2012/084698
Other languages
English (en)
French (fr)
Inventor
戴天明
姚琪
张锋
曹占锋
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/981,165 priority Critical patent/US9368635B2/en
Publication of WO2013131380A1 publication Critical patent/WO2013131380A1/zh
Priority to US15/151,396 priority patent/US9768306B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Indium gallium zinc oxide is a hotspot of current research on oxide semiconductor materials. Its carrier mobility can reach 10cm/Vs, which is more than 10 times that of amorphous silicon. For large area and ultrafine The panel can improve the response speed and reduce the size of the Thin Film Transistor (TFT). At present, it is in an Organic Light-Emitting Diode (OLED) or Liquid Crystal Display (LCD). It has been widely used. However, since IGZO materials are easily affected by external conditions such as moisture, oxygen, etc., the material properties change.
  • OLED Organic Light-Emitting Diode
  • LCD Liquid Crystal Display
  • the current mass production is mainly LTPS (Low Temperature Polycrystalline Silicon), which has been mass-produced by Samsung, but due to the ELA process, a large number of existing equipment needs to be modified and equipment investment increased.
  • LTPS Low Temperature Polycrystalline Silicon
  • An OLED backplane using an oxide semiconductor material, a top gate structure is used, and an etch barrier layer technique is used to avoid the influence of source and drain (SD) etching liquid on the IGZO material, and the mask substrate method is used to manufacture the array substrate ( Mask )
  • SD source and drain
  • Mask The number of processes (or patterning processes) is generally 6 to 7 times. Summary of the invention
  • Embodiments of the present invention can reduce the number of mask processes and reduce process costs.
  • An aspect of the invention provides a method for fabricating an array substrate, comprising the steps of: S1: forming a pattern including a semiconductor layer, a gate insulating layer, a gate, and a gate line on a substrate;
  • a metal diffusion layer is formed on the semiconductor layer pattern not covered by the gate insulating layer, and other regions form a barrier layer;
  • step S3 forming a passivation layer on the substrate after step S2;
  • the step SI may include:
  • Coating the photoresist on the oxide semiconductor film exposing and developing the photoresist by using a mask, leaving the photoresist in the pattern region of the semiconductor layer, etching the exposed oxide semiconductor film, and Removing the remaining photoresist to form a semiconductor layer pattern;
  • Forming an insulating film and a gate metal film on the substrate after forming the semiconductor layer pattern Forming an insulating film and a gate metal film on the substrate after forming the semiconductor layer pattern; coating a photoresist on the gate metal film, exposing and developing the photoresist with a mask, and retaining the gate insulating layer, a photoresist in the gate and gate pattern regions, etching the exposed gate metal film to expose the insulating film;
  • the exposed insulating film is etched away by dry etching, and the remaining photoresist is removed to form a gate insulating layer, a gate electrode, and a gate line pattern.
  • the step S1 may include:
  • the photoresist of the gate insulating layer, the gate electrode and the gate pattern region is retained by the ashing process, and the photoresist in the remaining region is removed;
  • the gate metal film and the insulating film in which the photoresist region is not present are removed by wet etching, dry etching, and the remaining photoresist is removed to form a semiconductor layer, a gate insulating layer, a gate electrode, and a gate line pattern.
  • the material of the oxide semiconductor thin film may be: IGZO or ZnO.
  • the semiconductor layer may have a thickness of 10 to 5000 ⁇ .
  • the gate insulating layer may have a thickness of 200 to 20000 ⁇ .
  • the step S2 may include:
  • the metal thin film may have a thickness of 20 to 200 ⁇ .
  • the metal thin film may be an aluminum thin film.
  • the aluminum film may have an annealing temperature of 100 to 400 ° C and an annealing time of 20 to 200 minutes.
  • the step S4 may include:
  • Coating a photoresist on the passivation layer exposing and developing the photoresist through a double-tuning mask, removing the photoresist in the via region, and retaining light in the source drain and the data line pattern region Etching the exposed passivation layer to form a via hole to expose the metal diffusion layer at the via hole; removing the photoresist of the source drain and the data line pattern region by an ashing process, sequentially forming a source/drain metal film And a pixel electrode film, the source/drain metal film is in contact with the metal diffusion layer;
  • the remaining photoresist on the passivation layer and the source/drain metal film and the pixel electrode film attached to the photoresist are removed by ground stripping to form source drain, data line and pixel electrode patterns.
  • the material of the pixel electrode may be: ITO or IZO.
  • the present invention also provides an array substrate, comprising: a semiconductor layer formed on a transparent substrate, a gate insulating layer, a gate, a barrier layer, a passivation layer, a source/drain electrode, and a pixel electrode, the gate insulating layer and the gate a pole is sequentially formed on the semiconductor layer, the gate insulating layer and the gate are located at an intermediate position of the semiconductor layer and have the same shape and size, and a region of the semiconductor layer not covered by the gate insulating layer is further formed a metal diffusion layer, the barrier layer including a portion covering the gate insulating layer and the gate and a portion located around the semiconductor layer, the passivation layer covering the semiconductor layer, the gate insulating layer, the gate, and the first a barrier layer, the source/drain electrode is connected to the metal diffusion layer, and the pixel electrode and the drain electrode are in contact.
  • the source/drain electrodes may be positioned over the passivation layer, and the metal diffusion layer is connected through via holes on the passivation layer.
  • the semiconductor layer may be a metal oxide semiconductor, such as
  • the metal diffusion layer may be an A1 diffusion layer.
  • the barrier layer may be a non-conductive metal oxide.
  • the metal oxide may be A1 2 0 3 .
  • the present invention also provides a display device comprising the array substrate of any of the above.
  • the method for fabricating the array substrate of the embodiment of the present invention effectively reduces the number of masks, reduces the cost, and utilizes an oxide such as alumina as a barrier layer of the oxide semiconductor, thereby effectively improving the stability of the TFT.
  • FIG. 1 is a cross-sectional view showing a pattern of forming an oxide semiconductor layer on a glass substrate in a method of fabricating an array substrate according to Embodiment 1 of the present invention
  • Figure 2 is a cross-sectional view showing a gate insulating layer and a gate pattern formed on the substrate subsequent to Figure 1;
  • Figure 3 is a cross-sectional view showing a metal diffusion layer and a barrier layer formed on the substrate subsequent to Figure 2;
  • Figure 4 is after Figure 3.
  • Figure 5 is a cross-sectional view showing the photoresist before exposure and development on the passivation layer of Figure 4;
  • Figure 6 is a cross-sectional view of the via pattern formed after Figure 5;
  • FIG. 7 is a cross-sectional view showing a region in which a source and a drain pattern are formed by ashing a photoresist after FIG. 6;
  • FIG. 8 is a cross-sectional view showing a source/drain and a pixel electrode pattern after FIG. 7;
  • FIG. 9 is a cross-sectional view showing an oxide semiconductor film, an insulating film, and a gate metal film formed on a glass substrate in an array substrate manufacturing method according to Embodiment 2 of the present invention.
  • Figure 10 is a cross-sectional view showing a photoresist coated on a substrate subsequent to Figure 9 and developed by exposure through a double-tuned mask;
  • Figure 11 is a cross-sectional view showing the photoresist-covered oxide semiconductor film, the insulating film and the gate metal film etched away on the basis of Figure 10;
  • Figure 12 is a cross-sectional view showing a photoresist in which only the gate insulating layer, the gate electrode and the gate line pattern region are left in the ashing process on the basis of Figure 11;
  • Figure 13 is a cross-sectional view showing the photoresist-covered insulating film and the gate metal film etched away on the basis of Figure 12 and the remaining photoresist is removed. detailed description
  • the array substrate of the embodiment of the present invention includes, for example, a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining a plurality of pixel units arranged in a matrix, each of the pixel units including a thin film as a switching element A transistor and a pixel electrode for controlling the arrangement of the liquid crystal.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • an oxide semiconductor layer pattern 2 is formed on the glass substrate 1.
  • the glass substrate 1 is an example of a substrate as a substrate, and may be replaced with other usable substrates such as a quartz substrate, a plastic substrate, or the like.
  • a cross-sectional view of the oxide semiconductor layer pattern 2 is formed on a glass substrate.
  • an oxide semiconductor film is deposited on the glass substrate 1, and the material of the oxide semiconductor may be IGZO or ZnO, and the thickness thereof is, for example, 105000 A; a photoresist is coated on the oxide semiconductor film, and a mask pair is used.
  • the photoresist is subjected to exposure development processing to retain the photoresist of the semiconductor layer pattern region 100; the exposed oxide semiconductor film is etched away, and the remaining photoresist is removed to form the oxide semiconductor layer pattern 2.
  • a gate insulating layer pattern 4 and a gate pattern 5 are formed on the oxide semiconductor layer pattern 2.
  • the oxide semiconductor layer pattern 2 is formed.
  • the insulating film and the gate metal film are sequentially deposited on the substrate, and the material of the insulating film may be silicon nitride, silicon oxide, or aluminum oxide.
  • the material of the gate metal may be an alloy of metal such as aluminum or copper or aluminum, and the like.
  • the thickness of the film may be 200 20000A; the photoresist is coated on the gate metal film, and the photoresist is exposed and developed by the mask, and the photoresist of the gate insulating layer, the gate and the gate pattern region 101 is retained.
  • Etching the exposed gate metal film since the etched metal is usually wet-etched with an acidic reagent, and the insulating film is exposed after wet etching; the exposed insulating film is etched away by dry etching, and the retained film is removed.
  • a photoresist is formed to form a gate insulating layer pattern 4, a gate pattern 5, and a gate line pattern. Since the material of the oxide semiconductor is IGZO or ZnO which is easily affected by the etching liquid, the above etching process is carried out in two steps of wet etching and dry etching.
  • a metal diffusion layer and a barrier layer are formed as shown in FIG.
  • a metal film is deposited by sputtering, in this embodiment, an A1 film having a thickness of 20 200 A; for example, the obtained metal film is annealed in an oxygen atmosphere at a temperature of 100 to 400 ° C for a time of 20 min. 200 min, so that A1 directly covering the IGZO or ZnO oxide semiconductor layer pattern 2 is diffused into the oxide semiconductor layer pattern 2 to form the metal A1 diffusion layer 3, which is not directly covered in the oxide semiconductor layer pattern
  • the A1 film on 2 is annealed to form an A1 2 0 3 barrier layer 6.
  • an A1 2 0 3 layer 6 is formed on the gate insulating layer pattern 4, the gate pattern 5, and the glass substrate 1.
  • the A1 2 0 3 is a dense protective layer which can effectively block the oxide semiconductor ( Degradation such as IGZO).
  • a passivation layer 7 is formed, and a material for forming the passivation layer 7 is coated (e.g., spin-coated) on the substrate to cover the pattern formed in the first three steps.
  • a material for forming the passivation layer 7 is coated (e.g., spin-coated) on the substrate to cover the pattern formed in the first three steps.
  • the material of the passivation layer 7 in this embodiment is an acrylate.
  • a passivation layer 7 is coated with a layer of H photoresist 10; after exposure and development through a double-tuned mask (half-tone mask or gray-tone mask), the via is made.
  • the photoresist of the region 102 is completely developed, and the thickness of the photoresist of the source/drain pattern region 103 is h, h is less than H; as shown in FIG. 6, the via hole 11 is formed by dry etching at the via region 102, When the via 11 is etched, all the passivation layers exposed at the via region 102 are etched away, so that the metal A1 diffusion layer 3 at the via region 102 is exposed; as shown in FIG. 7, the source drain pattern is removed by an ashing process.
  • Photoresist at region 103 A photoresist of a certain thickness (H - h ) is left on the passivation layer 7 except for the via hole 11 and other regions of the source/drain pattern region 103; as shown in FIG. 8, a source/drain metal film and a pixel electrode film are sequentially deposited, The source/drain metal film is contacted with the metal A1 diffusion layer 3 through the via hole 11.
  • the material of the source/drain metal film may be an alloy of a metal such as aluminum, copper, gold or silver or a metal such as aluminum bismuth.
  • the material of the pixel electrode film may be ITO.
  • a transparent conductive material such as IZO
  • the source and drain metal films and the pixel electrode film are formed to form a source drain (including the source electrode 81 and the drain electrode 82) pattern, a data line pattern (not shown), and a pixel electrode pattern 9.
  • the array substrate shown in Fig. 8 is formed.
  • the array substrate produced by the method of the present embodiment can be widely used for, for example, an LCD display panel and an OLED display panel.
  • the above pixel electrode pattern 9 is connected to the anode of the OLED.
  • the above process of fabricating the array substrate of the present invention uses a total of three patterning (or mask) processes, which reduces the process flow and reduces the process cost compared to the conventional masking process of using more than four masks.
  • the use of alumina as a barrier layer for an oxide semiconductor effectively improves the stability of the TFT.
  • Another method for fabricating the above array substrate in this embodiment is as follows.
  • an oxide semiconductor film, an insulating film, and a gate metal film are sequentially deposited on the glass substrate 1.
  • the glass substrate 1 is an example of a substrate as a substrate, and may be replaced with other usable substrates such as a quartz substrate, a plastic substrate, or the like.
  • the material of the oxide semiconductor film may be IGZO or ZnO and has a thickness of 10 5000 A.
  • the material of the insulating film may be silicon nitride, silicon oxide, or aluminum oxide.
  • the material of the gate metal may be an alloy of a metal such as aluminum or copper or a metal such as aluminum bismuth.
  • the thickness of the insulating film is 200 to 20000 ⁇ .
  • the photoresist 12 is coated on the gate metal film, and the photoresist 12 is exposed and developed through a double-adjusting mask (halftone mask or gray tone mask) to retain the metal.
  • the photoresist 12 of the diffusion layer pattern region 104, the gate insulating layer, the gate and the gate pattern region 101, and the thickness of the photoresist 12 of the metal diffusion layer pattern region 104 is smaller than the gate insulating layer, the gate and the gate pattern region Corresponding photoresist 12 removes photoresist 12 from the remaining regions.
  • the photoresist 12 of the gate insulating layer, the gate and the gate pattern region 101 is left by the ashing process, and the remaining region of the photoresist 12 is removed.
  • Fig. 12 is a schematic cross-sectional view showing a pattern of a semiconductor layer 2, a gate insulating layer 4, a gate electrode 5, and a gate line (not shown) formed on a glass substrate 1.
  • the photoresist may be coated with a positive or negative photoresist.
  • the etching liquid composition for etching the oxide semiconductor includes:
  • the etching liquid used for etching the gate mainly includes:
  • the ratio is not limited to the above ratios, Addl and Add2 are added reagents, oxide semiconductors
  • the etching solution does not corrode the gate electrode, and the etching solution of the gate metal does not cause corrosion to the oxide semiconductor.
  • the embodiment provides an array substrate, which can be obtained by the method of Embodiment 1 or Embodiment 2, and has a structure as shown in FIG. 8, comprising: a semiconductor layer 2 formed on the glass substrate 1, and a gate.
  • the gate insulating layer 4 and the gate electrode 5 are sequentially formed on the semiconductor layer 2.
  • the gate insulating layer 4 and the gate electrode 5 are located at an intermediate position of the semiconductor layer 2 and are identical in shape and size.
  • a region of the semiconductor layer 2 that is not covered by the gate insulating layer 4 is also formed with a metal diffusion layer 2.
  • the formation process is as described in Embodiment 1 or Embodiment 2, and a metal thin film is deposited on the semiconductor layer 2, preferably A1 (because A1 has good diffusibility and can form a dense protective layer after oxidation), A1 is oxidized, and A1 on the surface of the semiconductor layer 2 is diffused into the oxide semiconductor layer 2 to form a metal A1 diffusion layer 3, which is not directly covered by the oxide semiconductor
  • the A1 film on the bulk layer pattern 2 is oxidized and annealed to form an A1 2 0 3 barrier layer 6, and the barrier layer 6 is located around the semiconductor layer 2 and covers the gate insulating layer 4 and the gate electrode 5 to protect the semiconductor layer 2 from degradation.
  • A1 is also deposited on the surface of the gate insulating layer 4 and the gate 5 at the time of preparation, the surface of the gate insulating layer 4 and the gate 5 after oxidation annealing is also covered with a barrier layer of A1 2 0 3 .
  • the passivation layer 7 covers the semiconductor layer 2, the gate insulating layer 4, the gate electrode 5, and the barrier layer 6 (a barrier layer including the periphery of the semiconductor layer 2 and the surfaces of the gate insulating layer 4 and the gate electrode 5), and the source/drain electrode 8 is connected to the metal A1.
  • the diffusion layer 3, the pixel electrode 9 and the drain electrode are in contact.
  • the source-drain electrodes (including the source electrode 81 and the drain electrode 82) are located above the passivation layer 7 due to the above-described unique fabrication process, and the metal A1 diffusion layer 3 is connected through the via holes 11 on the passivation layer. Specifically, the source electrode 81 and the drain electrode 82 are connected to the metal diffusion layer 3 at both ends of the semiconductor layer 2, respectively.
  • the semiconductor layer is preferably a metal oxide semiconductor such as IGZO or the like in addition to the ordinary semiconductor.
  • the barrier layer may be other non-conductive materials other than the non-conductive metal oxide such as A1 2 0 3 described above.
  • the array substrate produced by the method of the above embodiment 1 or 2 has the advantage of low cost.
  • the array substrate provided in this embodiment effectively improves the stability of the TFT by using an oxide such as alumina as a barrier layer of the oxide semiconductor.
  • a display device including the array substrate in Embodiment 3 is provided.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板制作方法，包括以下步骤：S1：在基板（1）上形成包括半导体层（2）、栅绝缘层（4）、栅极（5）和栅线的图形；S2：在步骤S1之后的基板（1）上，未被所述栅绝缘层（4）覆盖的半导体层（2）图形上形成金属扩散层（3），其它区域形成阻挡层（6）；S3：在步骤S2之后的基板（1）上形成钝化层（7）；S4：在所述钝化层（7）上形成过孔（11）、源漏极（81，82）、数据线和像素电极（9）的图形，所述源漏极（81，82）通过所述过孔（11）连接所述金属扩散层（3）。该方法减少了工艺流程，降低了工艺成本。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法和显示装置。 背景技术
铟镓辞氧化物（ indium gallium zinc oxide, IGZO )为现阶段氧化物半导 体材料的研究热点，其载流子迁移率能达到 10cm/Vs,是非晶硅的 10倍以上， 对于大面积和超精细的面板， 其能很好的提高响应速度， 减小薄膜晶体管 ( Thin Film Transistor, TFT ) 大小， 现阶段在有机发光二极管 （Organic Light-Emitting Diode, OLED )或液晶显示器（ Liquid Crystal Display, LCD ) 中已经得到广泛的釆用。但是， 由于 IGZO材料很容易受到外界条件如水汽， 氧等的影响而导致材料特性发生变化。
对于一般的背板（即阵列基板） ， 现阶段量产的主要为 LTPS (低温多 晶硅）， 已于三星公司量产，但是其由于 ELA工艺需对现有设备进行大量的 改造和增加设备投资。 釆用氧化物半导体材料的 OLED背板， 多釆用顶栅结 构，并通过刻蚀阻挡层技术来避免源漏 ( SD )刻蚀液对于 IGZO材料的影响， 制造该阵列基板方法使用掩模（mask )工艺 （或构图工艺） 的次数一般为 6 次到 7次。 发明内容
本发明的实施例可减少掩模工艺的次数， 降低工艺成本。
本发明的一个方面提供了一种阵列基板制作方法， 包括以下步骤： S1 : 在基板上形成包括半导体层、 栅绝缘层、 栅极和栅线的图形；
S2: 在步骤 S1之后的基板上， 未被所述栅绝缘层覆盖的半导体层图形 上形成金属扩散层， 其它区域形成阻挡层；
S3: 在步骤 S2之后的基板上形成钝化层；
S4: 在所述钝化层上形成过孔、 源漏极、 数据线和像素电极的图形， 所 述源漏极通过所述过孔连接所述金属扩散层。 在该方法中， 例如， 所述步骤 SI可以包括：
在所述基板上形成氧化物半导体薄膜；
在所述氧化物半导体薄膜上涂覆光刻胶， 釆用掩膜板对光刻胶进行曝光 显影处理， 保留半导体层图形区域的光刻胶， 将暴露的氧化物半导体薄膜刻 蚀掉， 并除去保留的光刻胶， 以形成半导体层图形；
在形成半导体层图形后的基板上依次形成绝缘薄膜和栅金属薄膜； 在所述栅金属薄膜上涂覆光刻胶， 釆用掩膜板对光刻胶进行曝光显影处 理， 保留栅绝缘层、 栅极和栅线图形区域的光刻胶， 将暴露的栅金属薄膜刻 蚀掉， 暴露出绝缘薄膜；
通过干刻的方式刻蚀掉暴露出的绝缘薄膜， 并除去保留的光刻胶， 以形 成栅绝缘层、 栅极和栅线图形。
在该方法中， 例如， 所述步骤 S1可以包括：
在所述基板上依次形成氧化物半导体薄膜、 绝缘薄膜和栅金属薄膜； 在栅金属薄膜上涂覆光刻胶， 通过双调掩膜板对所述光刻胶进行曝光显 影处理， 保留金属扩散层图形区域、 栅绝缘层、 栅极和栅线图形区域的光刻 胶， 且金属扩散层图形区域的光刻胶的厚度小于栅绝缘层、 栅极和栅线图形 区域对应的光刻胶， 去掉其余区域的光刻胶；
依次通过湿刻、 干刻、 湿刻， 刻蚀掉不存在光刻胶区域的栅金属薄膜、 绝缘薄膜和氧化物半导体薄膜；
通过灰化工艺， 保留栅绝缘层、 栅极和栅线图形区域的光刻胶， 去掉其 余区域的光刻胶；
依次通过湿刻、干刻去除掉不存在光刻胶区域的栅金属薄膜和绝缘薄膜， 并除去保留的光刻胶， 以形成半导体层、 栅绝缘层、 栅极和栅线图形。
在该方法中，例如，所述氧化物半导体薄膜的材料可以为： IGZO或 ZnO。 在该方法中， 例如， 所述半导体层的厚度可以为 10~5000A。
在该方法中， 例如， 所述栅绝缘层的厚度可以为 200~20000A。
在该方法中， 例如， 所述步骤 S2可以包括：
通过溅射沉积一层金属薄膜；
在氧气气氛下退火， 使得直接覆盖在所述半导体层图形上的金属扩散进 所述半导体层图形， 以形成金属扩散层， 未直接覆盖在所述半导体层图形上 的金属薄膜退火形成金属氧化物阻挡层。
在该方法中， 例如， 所述金属薄膜的厚度可以为 20~200A。
在该方法中， 例如， 所述金属薄膜可以为铝薄膜。
在该方法中， 例如， 所述铝薄膜的退火温度可以为 100~400°C , 退火时 间为 20~200min。
在该方法中， 例如， 所述步骤 S4可以包括：
在所述钝化层涂覆光刻胶， 通过双调掩膜板对所述光刻胶进行曝光显影 处理， 去掉过孔区域的光刻胶， 且保留源漏极和数据线图形区域的光刻胶； 刻蚀掉暴露出的钝化层形成过孔， 使露出过孔处的金属扩散层； 通过灰化工艺去除源漏极和数据线图形区域的光刻胶， 依次形成源漏金 属薄膜和像素电极薄膜 , 使源漏金属薄膜接触所述金属扩散层；
通过离地剥离的方式去除钝化层上剩余的光刻胶及附着在光刻胶上的源 漏金属薄膜和像素电极薄膜， 以形成源漏极、 数据线和像素电极图形。
在该方法中， 例如， 所述像素电极的材料可以为： ITO或 IZO。
本发明还提供了一种阵列基板， 包括： 形成于透明基板之上的半导体层、 栅绝缘层、 栅极、 阻挡层、 钝化层、 源漏电极和像素电极， 所述栅绝缘层和 栅极依次形成于所述半导体层上， 所述栅绝缘层与所述栅极位于所述半导体 层的中间位置且形状与大小一致， 所述半导体层上未被栅绝缘层覆盖的区域 还形成有金属扩散层， 所述阻挡层包括覆盖所述栅绝缘层和栅极的部分以及 位于所述半导体层四周的部分， 所述钝化层覆盖所述半导体层、 栅绝缘层、 栅极和第一阻挡层， 所述源漏电极连接所述金属扩散层， 所述像素电极和漏 电极接触。
在该阵列基板中， 例如， 所述源漏电极可以位于所述钝化层之上， 且通 过钝化层上的过孔连接所述金属扩散层。
在该阵列基板中， 例如， 所述半导体层可以为金属氧化物半导体， 如
IGZO等。
在该阵列基板中， 例如， 所述金属扩散层可以为 A1扩散层。
在该阵列基板中， 例如， 所述阻挡层可以为非导电的金属氧化物。
在该阵列基板中， 例如， 所述金属氧化物可以为 A1203。
本发明还提供了一种显示装置， 包括上述任一项所述的阵列基板。 本发明实施例的阵列基板制作方法有效地减少的掩模的次数， 降低的成 本， 并利用氧化物（比如氧化铝）作为氧化物半导体的阻挡层， 有效地提高 了 TFT的稳定性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是本发明实施例 1的一种阵列基板制作方法中在玻璃基板上形成氧 化物半导体层图形的截面图；
图 2是在图 1之后的基板上形成栅绝缘层和栅极图形的截面图； 图 3是在图 2之后的基板上形成金属扩散层和阻挡层的截面图； 图 4是在图 3之后的基板上形成钝化层的截面图；
图 5是在图 4中钝化层上形成过孔前光刻胶曝光显影后的截面图； 图 6是在图 5之后形成过孔图形的截面图；
图 7是在图 6之后对光刻胶进行灰化处理露出源漏极图形区域的截面图； 图 8是在图 7之后形成源漏极、 像素电极图形的截面图；
图 9是本发明实施例 2的一种阵列基板制作方法中在玻璃基板上形成氧 化物半导体薄膜、 绝缘薄膜和栅金属薄膜的截面图；
图 10是在图 9之后的基板上涂覆光刻胶并通过双调掩膜板曝光显影后的 截面图；
图 11是在图 10的基础上刻蚀掉无光刻胶覆盖的氧化物半导体薄膜、 绝 缘薄膜和栅金属薄膜后的截面图；
图 12是在图 11的基础上进行灰化工艺只保留栅绝缘层、 栅极和栅线图 形区域的光刻胶的截面图；
图 13是在图 12的基础上刻蚀掉无光刻胶覆盖的绝缘薄膜和栅金属薄膜 并去掉剩余光刻胶后的截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接" 或者 "相 连" 等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的 连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用 于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系 也相应地改变。
本发明实施例的阵列基板例如包括多条栅线和多条数据线， 这些栅线和 数据线彼此交叉由此限定了排列为矩阵的多个像素单元， 每个像素单元包括 作为开关元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个 像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数 据线电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的 描述主要针对单个或多个像素单元进行,但是其他像素单元可以相同地形成。
实施例 1
本实施例的阵列基板制作过程具体描述如下。
首先， 在玻璃基板 1上形成氧化物半导体层图形 2。 玻璃基板 1是作为 基底的基板的一个示例， 可以替换为其他可使用的基板， 例如石英基板、 塑 料基板等。如图 1所示，为玻璃基板上形成氧化物半导体层图形 2的截面图。 例如， 在玻璃基板 1上在沉积氧化物半导体薄膜， 氧化物半导体的材料可以 为 IGZO或 ZnO,其厚度例如在 10 5000A;在氧化物半导体薄膜上涂覆光刻 胶， 釆用掩膜板对光刻胶进行曝光显影处理， 保留半导体层图形区域 100的 光刻胶； 将暴露的氧化物半导体薄膜刻蚀掉， 并除去保留的光刻胶， 以形成 氧化物半导体层图形 2。
其次， 在氧化物半导体层图形 2上形成栅绝缘层图形 4和栅极图形 5。 如图 2所示， 为形成栅绝缘层图形 4和栅极图形 5 (栅线和栅极同时形成， 图中未示出栅线） 的截面图， 例如， 在形成有氧化物半导体层图形 2的基板 上依次沉积绝缘薄膜和栅金属薄膜，绝缘薄膜的材料可以为氮化硅，氧化硅， 或者氧化铝等， 栅金属的材料可以为铝、 铜等金属或铝钕等金属的合金， 绝 缘薄膜的厚度可以为 200 20000A; 在栅金属薄膜上涂覆光刻胶， 釆用掩膜 板对光刻胶进行曝光显影处理， 保留栅绝缘层、 栅极和栅线图形区域 101的 光刻胶； 将暴露的栅金属薄膜刻蚀掉， 由于刻蚀金属通常釆用酸性试剂进行 湿刻， 湿刻后暴露出绝缘薄膜； 通过干刻的方式刻蚀掉暴露出的绝缘薄膜， 并除去保留的光刻胶， 以形成栅绝缘层图形 4、 栅极图形 5和栅线图形。 由 于氧化物半导体的材料为 IGZO或 ZnO容易受到刻蚀液的影响， 因此上述刻 蚀过程中， 分成湿刻和干刻两步进行。
然后， 形成金属扩散层和阻挡层， 如图 3所示。 通过溅射沉积一层金属 薄膜， 本实施例中为 A1薄膜， 厚度可以为 20 200A; 例如， 将所得到的金 属薄膜， 在氧气气氛下退火， 温度为 100~400°C , 时间为 20min~200min, 使 得直接覆盖在 IGZO或 ZnO氧化物半导体层图形 2上的 A1扩散进氧化物半 导体层图形 2, 以形成金属 A1扩散层 3 , 未直接覆盖在氧化物半导体层图形
2上的 A1薄膜退火形成 A1203阻挡层 6。 如图 3中， 栅绝缘层图形 4、 栅极 图形 5及玻璃基板 1上都形成了一个 A1203层 6, A1203是一层致密的保护层 能有效的阻止氧化物半导体（如 IGZO ) 的退化。
接下来， 形成钝化层 7, 在基板上涂覆 (如旋涂）一层用于形成钝化层 7 的材料使其覆盖前三步形成的图形即可。 如图 4所示， 为形成钝化层 7的截 面图， 本实施例中的钝化层 7的材料为丙烯酸酯。
形成钝化层后在钝化层 7上形成过孔、源漏极、数据线及像素电极图形， 形成过程例 ¾口 ¾口下。
如图 5所示，在钝化层 7上涂覆一层厚度为 H光刻胶 10;通过双调掩膜 板（半调掩膜板或灰调掩膜板）曝光显影后， 使得过孔区域 102的光刻胶完 全被显影掉， 源漏极图形区域 103的光刻胶的厚度为 h, h小于 H; 如图 6 所示， 在过孔区域 102处进行干刻形成过孔 11 , 刻蚀过孔 11时刻蚀掉过孔 区域 102处暴露出的所有钝化层， 使得过孔区域 102处的金属 A1扩散层 3 暴露出来；如图 7所示，通过灰化工艺去除源漏极图形区域 103处的光刻胶， 钝化层 7上除过孔 11和源漏极图形区域 103的其它区域仍保留一定厚度（H - h )的光刻胶； 如图 8所示， 依次沉积源漏金属薄膜和像素电极薄膜， 使源 漏金属薄膜通过过孔 11接触金属 A1扩散层 3, 源漏金属薄膜的材料可以为 铝、铜、金、银等金属或铝钕等金属的合金，像素电极薄膜的材料可以为 ITO、 IZO等透明导电材料； 通过离地剥离的方式去除钝化层 7上剩余的光刻胶及 附着在光刻胶上的源漏金属薄膜和像素电极薄膜， 保留源漏极图形区域 103 处沉积的源漏金属薄膜和像素电极薄膜，以形成源漏极（包括源电极 81和漏 电极 82 ) 图形、 数据线图形 （图中未示出）和像素电极图形 9。 最终形成图 8所示的阵列基板。
釆用本实施例的方法制作阵列基板例如可以广泛地用于 LCD显示面板 和 OLED显示面板。 在用于 OLED显示面板时， 上述像素电极图形 9连接 OLED的阳极。
本发明制作阵列基板的上述过程一共釆用了 3次构图 （或掩模）工艺， 相对于传统的釆用 4次以上的掩模的制作工艺减少了工艺流程， 降低了工艺 成本。 并利用氧化铝作为氧化物半导体的阻挡层， 有效地提高了 TFT的稳定 性。
实施例 2
本实施例中上述阵列基板的另一种制作方法， 具体如下。
如图 9所示， 在玻璃基板 1上依次沉积氧化物半导体薄膜、 绝缘薄膜和 栅金属薄膜。 玻璃基板 1是作为基底的基板的一个示例， 可以替换为其他可 使用的基板， 例如石英基板、 塑料基板等。 氧化物半导体薄膜的材料可以为 IGZO或 ZnO,其厚度在 10 5000 A。绝缘薄膜的材料可以为氮化硅，氧化硅， 或者氧化铝等， 栅金属的材料可以为铝、 铜等金属或铝钕等金属的合金， 绝 缘薄膜的厚度为 200~20000A。
如图 10所示， 在栅金属薄膜上涂覆光刻胶 12, 通过双调掩膜板（半调 掩膜板或灰调掩膜板）对光刻胶 12进行曝光、显影处理，保留金属扩散层图 形区域 104、 栅绝缘层、 栅极和栅线图形区域 101的光刻胶 12 , 且金属扩散 层图形区域 104的光刻胶 12的厚度小于栅绝缘层、栅极和栅线图形区域对应 的光刻胶 12, 去掉其余区域的光刻胶 12。
依次通过湿刻、干刻、 湿刻工艺， 刻蚀掉不存在光刻胶 12的区域的栅金 属薄膜、 绝缘薄膜和氧化物半导体薄膜， 刻蚀后如图 11所示。
如图 12所示， 通过灰化工艺， 保留栅绝缘层、 栅极和栅线图形区域 101 的光刻胶 12, 去掉其余区域的光刻胶 12。
依次通过湿刻、干刻去除掉不存在光刻胶 12的区域的栅金属薄膜和绝缘 薄膜， 并除去保留的光刻胶 12, 以形成半导体层、 栅绝缘层、 栅极和栅线图 形。 图 12为在玻璃基板 1上形成半导体层 2、栅绝缘层 4、栅极 5和栅线（图 中未示出） 图形的截面示意图。
形成如图 13 (实施例 1中图 2 ) 的层级结构之后， 后续的制作过程和实 施例 1相同， 此处不再赘述。
本实施例中，在玻璃基板 1上制作半导体层 2、栅绝缘层 4、栅极 5和栅 线（图中未示出） 图形的过程中只釆用了 1次掩模， 整个制作过程中只釆用 了 2次掩模， 相对于实施例 1减少了工艺流程， 降低了工艺成本。
上述实施例 1和实施例 2中， 光刻胶可以釆用正性或负性光刻胶。
用于刻蚀氧化物半导体的刻蚀液成分包括：
¾SO4:CH3COOH:HNO3:¾O=10:5:15:70 wt%。
用于刻蚀栅极的刻蚀液的主要包括：
H3P04： CH3COOH:HN03： Addl： Add2： ¾0=63 :17.4:4.5:1 :0.1 :14 wt% 其比例不仅仅只限于以上比例， Addl和 Add2为添加试剂， 氧化物半导 体的刻蚀液不会对栅极造成腐蚀， 栅金属的刻蚀液也不会对氧化物半导体造 成腐蚀。
实施例 3
本实施例提供了一种阵列基板， 该阵列基板可由上述实施例 1或实施例 2的方法制得， 其结构如图 8所示， 包括： 形成于玻璃基板 1之上的半导体 层 2、 栅绝缘层 4、 栅极 5、 阻挡层 6、 钝化层 7、 源漏电极 8和像素电极 9。
栅绝缘层 4和栅极 5依次形成于半导体层 2上。 栅绝缘层 4与栅极 5位 于半导体层 2的中间位置且形状与大小一致。 半导体层 2上未被栅绝缘层 4 覆盖的区域还形成有金属扩散层 2。 其形成过程如实施例 1或实施例 2中所 述， 在半导体层 2上沉积一层金属薄膜， 优选为 A1 (因为 A1的扩散性较好， 且氧化后能形成致密的保护层） ， 对 A1进行氧化， 半导体层 2表面的 A1扩 散进氧化物半导体层 2, 以形成金属 A1扩散层 3 , 未直接覆盖在氧化物半导 体层图形 2上的 A1薄膜氧化退火后形成 A1203阻挡层 6, 阻挡层 6则位于半 导体层 2的四周并覆盖栅绝缘层 4和栅极 5 , 以保护半导体层 2不退化。 由 于制备时在栅绝缘层 4和栅极 5的表面也沉积有 A1, 因此经过氧化退火后栅 绝缘层 4和栅极 5的表面也覆盖有 A1203的阻挡层。
钝化层 7覆盖半导体层 2、 栅绝缘层 4、 栅极 5和阻挡层 6 (包括半导体 层 2四周和栅绝缘层 4和栅极 5的表面的阻挡层 ) , 源漏电极 8连接金属 A1 扩散层 3 , 像素电极 9和漏电极接触。 本实施例中， 由于上述特有的制作过 程， 源漏电极（包括源电极 81和漏电极 82 )位于钝化层 7之上， 且通过钝 化层上的过孔 11连接金属 A1扩散层 3。 具体的， 源电极 81和漏电极 82分 别连接位于半导体层 2两端的金属扩散层 3。
本实施例中， 半导体层除普通半导体外， 优选为金属氧化物半导体， 如 IGZO等。所述阻挡层除了可以为上述所述的等非导电的 A1203等金属氧化物 夕卜， 还可以为其他非导电的材料。
釆用上述实施例 1或 2的方法制得的阵列基板具有成本低的优点。 本实 施例提供的阵列基板， 由于釆用了氧化物 (比如氧化铝）作为氧化物半导体 的阻挡层， 有效地提高了 TFT的稳定性。
实施例 4
本实施例中提供了一种显示装置， 包括实施例 3中的阵列基板。 所述显 示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板制作方法， 包括以下步骤：
S1 : 在基板上形成包括半导体层、 栅绝缘层、 栅极和栅线的图形； S2: 在步骤 S1之后的基板上， 未被所述栅绝缘层覆盖的半导体层图形 上形成金属扩散层， 其它区域形成阻挡层；
S3: 在步骤 S2之后的基板上形成钝化层；
S4: 在所述钝化层上形成过孔、 源漏极、 数据线和像素电极的图形， 所 述源漏极通过所述过孔连接所述金属扩散层。
2、 如权利要求 1所述的阵列基板制作方法， 其中， 所述步骤 S1包括： 在所述基板上形成氧化物半导体薄膜；
在所述氧化物半导体薄膜上涂覆光刻胶， 釆用掩膜板对光刻胶进行曝光 显影处理， 保留半导体层图形区域的光刻胶， 将暴露的氧化物半导体薄膜刻 蚀掉， 并除去保留的光刻胶， 以形成半导体层图形；
在形成半导体层图形后的基板上依次形成绝缘薄膜和栅金属薄膜； 在所述栅金属薄膜上涂覆光刻胶， 釆用掩膜板对光刻胶进行曝光显影处 理， 保留栅绝缘层、 栅极和栅线图形区域的光刻胶， 将暴露的栅金属薄膜刻 蚀掉， 暴露出绝缘薄膜；
通过干刻的方式刻蚀掉暴露出的绝缘薄膜， 并除去保留的光刻胶， 以形 成栅绝缘层、 栅极和栅线图形。
3、 如权利要求 1所述的阵列基板制作方法， 其中， 所述步骤 S1包括： 在所述基板上依次形成氧化物半导体薄膜、 绝缘薄膜和栅金属薄膜； 在栅金属薄膜上涂覆光刻胶， 通过双调掩膜板对所述光刻胶进行曝光显 影处理， 保留金属扩散层图形区域、 栅绝缘层、 栅极和栅线图形区域的光刻 胶， 且金属扩散层图形区域的光刻胶的厚度小于栅绝缘层、 栅极和栅线图形 区域对应的光刻胶， 去掉其余区域的光刻胶；
依次通过湿刻、 干刻、 湿刻， 刻蚀掉不存在光刻胶区域的栅金属薄膜、 绝缘薄膜和氧化物半导体薄膜；
通过灰化工艺， 保留栅绝缘层、 栅极和栅线图形区域的光刻胶， 去掉其 余区域的光刻胶； 依次通过湿刻、干刻去除掉不存在光刻胶区域的栅金属薄膜和绝缘薄膜， 并除去保留的光刻胶， 以形成半导体层、 栅绝缘层、 栅极和栅线图形。
4、如权利要求 2或 3所述的阵列基板制作方法， 其中， 所述氧化物半导 体薄膜的材料为 IGZO或 ZnO。
5、 如权利要求 2-4任一所述的阵列基板制作方法， 其中， 所述半导体层 的厚度为 10~5000A。
6、 如权利要求 2-5任一所述的阵列基板制作方法， 其中， 所述栅绝缘层 的厚度为 200~20000A。
7、 如权利要求 1-6任一所述的阵列基板制作方法， 其中， 所述步骤 S2 包括：
溅射沉积一层金属薄膜；
在氧气气氛下退火， 使得直接覆盖在所述半导体层图形上的金属扩散进 所述半导体层图形， 以形成金属扩散层， 未直接覆盖在所述半导体层图形上 的金属薄膜退火形成金属氧化物阻挡层。
8、如权利要求 7所述的阵列基板制作方法， 其中， 所述金属薄膜的厚度 为 20~200A。
9、如权利要求 7或 8所述的阵列基板制作方法， 其中， 所述金属薄膜为 铝薄膜。
10、 如权利要求 7-9任一所述的阵列基板制作方法， 其中， 所述铝薄膜 的退火温度为 100~400°C , 退火时间为 20~200min。
11、 如权利要求 1-10任一所述的阵列基板制作方法， 其中， 所述步骤 S4包括：
在所述钝化层涂覆光刻胶， 通过双调掩膜板对所述光刻胶进行曝光显影 处理， 去掉过孔区域的光刻胶， 且保留源漏极和数据线图形区域的光刻胶； 刻蚀掉暴露出的钝化层形成过孔， 使露出过孔处的金属扩散层； 通过灰化工艺去除源漏极和数据线图形区域的光刻胶， 依次沉积源漏金 属薄膜和像素电极薄膜 , 使源漏金属薄膜接触所述金属扩散层；
通过离地剥离的方式去除钝化层上剩余的光刻胶及附着在光刻胶上的源 漏金属薄膜和像素电极薄膜， 以形成源漏极、 数据线和像素电极图形。
12、如权利要求 11所述的阵列基板制作方法， 其中， 所述像素电极的材 料为： ITO或 IZO。
13、 一种阵列基板， 包括： 形成于基板之上的半导体层、 栅绝缘层、 栅 极、 阻挡层、 钝化层、 源漏电极和像素电极，
其中， 所述栅绝缘层和栅极依次形成于所述半导体层上， 所述栅绝缘层 与所述栅极位于所述半导体层的中间位置且形状与大小一致， 所述半导体层 上未被栅绝缘层覆盖的区域还形成有金属扩散层， 所述阻挡层包括覆盖所述 栅绝缘层和栅极的部分以及位于所述半导体层四周的部分， 所述钝化层覆盖 所述半导体层、 栅绝缘层、 栅极和第一阻挡层， 所述源漏电极连接所述金属 扩散层， 所述像素电极和漏电极接触。
14、如权利要求 13所述的阵列基板， 其中， 所述源漏电极位于所述钝化 层之上， 且通过钝化层上的过孔连接所述金属扩散层。
15、 如权利要求 13或 14所述的阵列基板， 其中， 所述半导体层为金属 氧化物半导体。
16、 如权利要求 13~15中任一项所述的阵列基板， 其中， 所述金属扩散 层为 A1扩散层。
17、 如权利要求 13~16中任一项所述的阵列基板， 其中， 所述阻挡层为 非导电的金属氧化物。
18、 如权利要求 17所述的阵列基板， 其中， 所述金属氧化物为 A1203。
19、 一种显示装置， 包括如权利要求 13~18中任一项所述的阵列基板。
PCT/CN2012/084698 2012-03-08 2012-11-15 阵列基板及其制作方法和显示装置 WO2013131380A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/981,165 US9368635B2 (en) 2012-03-08 2012-11-15 Array substrate, method for manufacturing the same and display device
US15/151,396 US9768306B2 (en) 2012-03-08 2016-05-10 Array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210060352.7A CN102646632B (zh) 2012-03-08 2012-03-08 阵列基板及其制作方法和显示装置
CN201210060352.7 2012-03-08

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/981,165 A-371-Of-International US9368635B2 (en) 2012-03-08 2012-11-15 Array substrate, method for manufacturing the same and display device
US15/151,396 Division US9768306B2 (en) 2012-03-08 2016-05-10 Array substrate and display device

Publications (1)

Publication Number Publication Date
WO2013131380A1 true WO2013131380A1 (zh) 2013-09-12

Family

ID=46659381

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/084698 WO2013131380A1 (zh) 2012-03-08 2012-11-15 阵列基板及其制作方法和显示装置

Country Status (3)

Country Link
US (2) US9368635B2 (zh)
CN (1) CN102646632B (zh)
WO (1) WO2013131380A1 (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646632B (zh) * 2012-03-08 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
KR102012918B1 (ko) * 2012-12-14 2019-08-22 삼성전자주식회사 전자기기
CN103646966B (zh) * 2013-12-02 2016-08-31 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN111081734A (zh) * 2014-03-17 2020-04-28 松下电器产业株式会社 薄膜晶体管元件基板及其制造方法、和有机el显示装置
CN104078424B (zh) * 2014-06-30 2017-02-15 京东方科技集团股份有限公司 低温多晶硅tft阵列基板及其制备方法、显示装置
CN106537567B (zh) * 2014-07-16 2019-08-27 株式会社日本有机雷特显示器 晶体管、显示装置和电子设备
JP2016111105A (ja) * 2014-12-03 2016-06-20 株式会社Ｊｏｌｅｄ 薄膜トランジスタ及びその製造方法、並びに、表示装置
CN105097845A (zh) 2015-08-24 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN105632896B (zh) * 2016-01-28 2018-06-15 深圳市华星光电技术有限公司 制造薄膜晶体管的方法
CN105742186A (zh) * 2016-03-09 2016-07-06 京东方科技集团股份有限公司 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置
CN107437562B (zh) * 2016-05-27 2020-11-27 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN106298956A (zh) * 2016-09-08 2017-01-04 武汉华星光电技术有限公司 氧化物薄膜晶体管的制备方法
CN107170807B (zh) * 2017-05-11 2020-07-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN107293493A (zh) 2017-06-06 2017-10-24 武汉华星光电技术有限公司 铟镓锌氧化物薄膜晶体管的制作方法
CN107359126B (zh) * 2017-07-11 2020-03-10 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板
CN107403758B (zh) * 2017-08-09 2022-09-23 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN107706199B (zh) * 2017-09-30 2020-05-05 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管阵列基板的制作方法
US20190267402A1 (en) * 2018-02-26 2019-08-29 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and manufacturing method for the same
US20190363109A1 (en) * 2018-05-28 2019-11-28 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate, preparation method thereof, and display device
CN109256397B (zh) * 2018-09-20 2021-09-21 合肥鑫晟光电科技有限公司 显示基板及其制备方法、显示装置
CN109860118B (zh) * 2018-12-18 2021-01-15 深圳市华星光电技术有限公司 一种阵列基板及其制备方法
CN110148601B (zh) * 2019-05-31 2022-12-20 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN110828578B (zh) * 2019-10-16 2022-11-08 Tcl华星光电技术有限公司 薄膜晶体管及其制备方法与显示装置
CN111048525A (zh) * 2019-11-27 2020-04-21 Tcl华星光电技术有限公司 阵列基板的制备方法及阵列基板
CN111276527A (zh) * 2020-02-20 2020-06-12 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN113972225A (zh) * 2021-10-26 2022-01-25 福建华佳彩有限公司 Oled面板的双层ltpo背板结构
CN115332272B (zh) * 2022-10-14 2023-01-24 广州华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196668A (zh) * 2006-12-07 2008-06-11 三菱电机株式会社 显示装置及其制造方法
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
CN102244034A (zh) * 2010-05-14 2011-11-16 北京京东方光电科技有限公司 阵列基板及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100463193C (zh) * 2006-11-03 2009-02-18 北京京东方光电科技有限公司 一种tft阵列结构及其制造方法
KR101415561B1 (ko) * 2007-06-14 2014-08-07 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그의 제조 방법
CN102023401B (zh) * 2009-09-18 2014-04-16 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102214700A (zh) * 2011-06-02 2011-10-12 上海大学 应用于氧化物薄膜晶体管阵列湿法刻蚀的阻挡层
KR101934978B1 (ko) * 2011-08-04 2019-01-04 삼성디스플레이 주식회사 박막 트랜지스터 및 박막 트랜지스터 표시판
CN102646632B (zh) * 2012-03-08 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US9331165B2 (en) * 2012-11-02 2016-05-03 Boe Technology Group Co., Ltd. Thin-film transistor (TFT), manufacturing method thereof, array substrate, display device and barrier layer
KR102281846B1 (ko) * 2015-01-02 2021-07-26 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196668A (zh) * 2006-12-07 2008-06-11 三菱电机株式会社 显示装置及其制造方法
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
CN102244034A (zh) * 2010-05-14 2011-11-16 北京京东方光电科技有限公司 阵列基板及其制造方法

Also Published As

Publication number Publication date
CN102646632B (zh) 2014-04-02
US9368635B2 (en) 2016-06-14
US20170243979A1 (en) 2017-08-24
CN102646632A (zh) 2012-08-22
US9768306B2 (en) 2017-09-19
US20140070206A1 (en) 2014-03-13

Similar Documents

Publication Publication Date Title
WO2013131380A1 (zh) 阵列基板及其制作方法和显示装置
US20140120657A1 (en) Back Channel Etching Oxide Thin Film Transistor Process Architecture
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
US20150221669A1 (en) Thin FilmTransistor, Array Substrate, And Manufacturing Method Thereof
WO2017008497A1 (zh) 氧化物薄膜晶体管的制备方法
JP2014529099A (ja) 有機薄膜トランジスタのアレイ基板及び、その製造方法、並びに表示装置
WO2018113214A1 (zh) 薄膜晶体管及其制作方法、显示基板、显示装置
WO2013127202A1 (zh) 阵列基板的制造方法及阵列基板、显示器
TW201622158A (zh) 薄膜電晶體以及其製作方法
WO2013026375A1 (zh) 薄膜晶体管阵列基板及其制造方法和电子器件
KR20150004536A (ko) 박막 트랜지스터를 포함하는 표시 기판 및 이의 제조 방법
WO2015043082A1 (zh) 薄膜晶体管及其制造方法、阵列基板及显示装置
WO2018077065A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示面板
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
WO2013181915A1 (zh) Tft阵列基板及其制造方法和显示装置
CN103117224A (zh) 一种薄膜晶体管和阵列基板的制作方法
US8703514B2 (en) Active array substrate and method for manufacturing the same
WO2015192549A1 (zh) 阵列基板、其制作方法以及显示装置
CN108711548B (zh) 金属氧化物薄膜晶体管及其制作方法、显示器
CN108573928B (zh) 一种tft阵列基板的制备方法及tft阵列基板、显示面板
CN110112072B (zh) 阵列基板的制造方法和阵列基板
CN109037151B (zh) 一种阵列基板的制备方法
WO2017024718A1 (zh) 薄膜晶体管的制作方法和阵列基板的制作方法
WO2014117444A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13981165

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12870354

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12870354

Country of ref document: EP

Kind code of ref document: A1