CN102646632A - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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CN102646632A
CN102646632A CN2012100603527A CN201210060352A CN102646632A CN 102646632 A CN102646632 A CN 102646632A CN 2012100603527 A CN2012100603527 A CN 2012100603527A CN 201210060352 A CN201210060352 A CN 201210060352A CN 102646632 A CN102646632 A CN 102646632A
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CN102646632B (zh
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戴天明
姚琪
张锋
曹占锋
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种阵列基板制作方法，涉及显示技术领域，包括以下步骤：S1：在基板上形成包括半导体层、栅绝缘层、栅极和栅线的图形；S2：在步骤S1之后的基板上，未被所述栅绝缘层覆盖的半导体层图形上形成金属扩散层，其它区域形成阻挡层；S3：在步骤S2之后的基板上形成钝化层；S4：在所述钝化层上形成过孔、源漏极、数据线和像素电极的图形，所述源漏极通过所述过孔连接所述金属扩散层。还公开了一种阵列基板和显示装置。本发明相对于传统的4次以上的mask制作工艺减少了工艺流程，降低了工艺成本。

Description

阵列基板及其制作方法和显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制作方法和显示装置。
背景技术
铟镓锌氧化物(indium gallium zinc oxide，IGZO)为现阶段氧化物半导体材料的研究热点，其载流子迁移率能达到10，是非晶硅的10倍以上，对于大面积和超精细的面板，其能很好的提高响应速度，减小薄膜晶体管(Thin Film Transistor，TFT)大小，现阶段在有机发光二极管(Organic Light-Emitting Diode，OLED)或液晶显示器(LiquidCrystal Display，LCD)中已经得到广泛的采用，但是由于其材料很容易受到外界条件如水汽，氧等的影响而导致材料特性发生变化。
对于一般的背板(即阵列基板)，现阶段量产的主要为LTPS(低温多晶硅)，已于三星公司量产，但是其由于ELA工艺需对现有设备进行大量的改造和增加设备投资。采用氧化物半导体材料的OLED背板，多采用顶栅结构，并通过刻蚀阻挡层技术来实现源漏(SD)刻蚀液对于IGZO材料的影响，其阵列基板的mask次数一般为6次到7次。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是：如何减少mask次数，降低工艺成本。
(二)技术方案
为解决上述技术问题，本发明提供了一种阵列基板制作方法，包括以下步骤：
S1：在基板上形成包括半导体层、栅绝缘层、栅极和栅线的图形；
S2：在步骤S1之后的基板上，未被所述栅绝缘层覆盖的半导体层图形上形成金属扩散层，其它区域形成阻挡层；
S3：在步骤S2之后的基板上形成钝化层；
S4：在所述钝化层上形成过孔、源漏极、数据线和像素电极的图形，所述源漏极通过所述过孔连接所述金属扩散层。
其中，所述过程S1具体包括：
在所述基板上沉积氧化物半导体薄膜；
在所述氧化物半导体薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留半导体层图形区域的光刻胶，将暴露的氧化物半导体薄膜刻蚀掉，并除去保留的光刻胶，以形成半导体层图形；
在形成半导体层图形后的基板上依次沉积绝缘薄膜和栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留栅绝缘层、栅极和栅线图形区域的光刻胶，将暴露的栅金属薄膜刻蚀掉，暴露出绝缘薄膜；
通过干刻的方式刻蚀掉暴露出的绝缘薄膜，并除去保留的光刻胶，以形成栅绝缘层、栅极和栅线图形。
其中，所述过程S1具体包括：
在所述基板上依次沉积氧化物半导体薄膜、绝缘薄膜和栅金属薄膜；
在栅金属薄膜上涂覆光刻胶，通过双调掩膜板对所述光刻胶进行曝光显影处理，保留金属扩散层图形区域、栅绝缘层、栅极和栅线图形区域的光刻胶，且金属扩散层图形区域的光刻胶的厚度小于栅绝缘层、栅极和栅线图形区域对应的光刻胶，去掉其余区域的光刻胶；
依次通过湿刻、干刻、湿刻，刻蚀掉不存在光刻胶区域的栅金属薄膜、绝缘薄膜和氧化物半导体薄膜；
通过灰化工艺，保留栅绝缘层、栅极和栅线图形区域的光刻胶，去掉其余区域的光刻胶；
依次通过湿刻、干刻去除掉不存在光刻胶区域的栅金属薄膜和绝缘薄膜，并除去保留的光刻胶，以形成半导体层、栅绝缘层、栅极和栅线图形。
其中，所述氧化物半导体薄膜的材料为：IGZO或ZnO。
其中，所述半导体层的厚度为
Figure BDA0000141761890000031
其中，所述栅绝缘层的厚度为
其中，所述过程S2具体包括：
通过溅射沉积一层金属薄膜；
在氧气气氛下退火，使得直接覆盖在所述半导体层图形上的金属扩散进所述半导体层图形，以形成金属扩散层，未直接覆盖在所述半导体层图形上的金属薄膜退火形成金属氧化物阻挡层。
其中，所述金属薄膜的厚度为
Figure BDA0000141761890000033
其中，所述金属薄膜为铝薄膜。
其中，所述铝薄膜的退火温度为100～400℃，退火时间为20～200min。
其中，所述过程S4具体包括：
在所述钝化层涂覆光刻胶，通过双调掩膜板对所述光刻胶进行曝光显影处理，去掉过孔区域的光刻胶，且保留源漏极和数据线图形区域的光刻胶；
刻蚀掉暴露出的钝化层形成过孔，使露出过孔处的金属扩散层；
通过灰化工艺去除源漏极和数据线图形区域的光刻胶，依次沉积源漏金属薄膜和像素电极薄膜，使源漏金属薄膜接触所述金属扩散层；
通过离地剥离的方式去除钝化层上剩余的光刻胶及附着在光刻胶上的源漏金属薄膜和像素电极薄膜，以形成源漏极、数据线和像素电极图形。
其中，所述像素电极的材料为：ITO或IZO。
本发明还提供了一种阵列基板，包括：形成于透明基板之上的半导体层、栅绝缘层、栅极、阻挡层、钝化层、源漏电极和像素电极，所述栅绝缘层和栅极依次形成于所述半导体层上，所述栅绝缘层与所述栅极位于所述半导体层的中间位置且形状与大小一致，所述半导体层上未被栅绝缘层覆盖的区域还形成有金属扩散层，所述阻挡层包括覆盖所述栅绝缘层和栅极的部分以及位于所述半导体层四周的部分，所述钝化层覆盖所述半导体层、栅绝缘层、栅极和第一阻挡层，所述源漏电极连接所述金属扩散层，所述像素电极和漏电极接触。
其中，所述源漏电极位于所述钝化层之上，且通过钝化层上的过孔连接所述金属扩散层。
其中，所述半导体层为金属氧化物半导体，如IGZO等。
其中，所述金属扩散层为Al扩散层。
其中，所述阻挡层为非导电的金属氧化物。
其中，所述金属氧化物为Al2O3。
本发明还提供了一种显示装置，其特征在于，包括上述任一项所述的阵列基板。
(三)有益效果
本发明的阵列基板制作方法有效地减少的mask的次数，降低的成本，并利用氧化物(比如氧化铝)作为氧化物半导体的阻挡层，有效地提高了TFT的稳定性。
附图说明
图1是本发明实施例1的一种阵列基板制作方法中在玻璃基板上形成氧化物半导体层图形的截面图；
图2是在图1之后的基板上形成栅绝缘层和栅极图形的截面图；
图3是在图2之后的基板上形成金属扩散层和阻挡层的截面图；
图4是在图3之后的基板上形成钝化层的截面图；
图5是在图4中钝化层上形成过孔前光刻胶曝光显影后的截面图；
图6是在图5之后形成过孔图形的截面图；
图7是在图6之后对光刻胶进行灰化处理露出源漏极图形区域的截面图；
图8是在图7之后形成源漏极、像素电极图形的截面图；
图9是本发明实施例2的一种阵列基板制作方法中在玻璃基板上形成氧化物半导体薄膜、绝缘薄膜和栅金属薄膜的截面图；
图10是在图9之后的基板上涂覆光刻胶并通过双调掩膜板曝光显影后的截面图；
图11是在图10的基础上刻蚀掉无光刻胶覆盖的氧化物半导体薄膜、绝缘薄膜和栅金属薄膜后的截面图；
图12是在图11的基础上进行灰化工艺只保留栅绝缘层、栅极和栅线图形区域的光刻胶的截面图；
图13是在图12的基础上刻蚀掉无光刻胶覆盖的绝缘薄膜和栅金属薄膜并去掉剩余光刻胶后的截面图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例1
本实施例的阵列基板制作过程具体描述如下：
首先，在玻璃基板1上形成氧化物半导体层图形2。如图1所示，为玻璃基板上形成氧化物半导体层图形2的截面图，形成过程为：在玻璃基板1上在沉积氧化物半导体薄膜，氧化物半导体的材料为IGZO或ZnO，其厚度在
Figure BDA0000141761890000051
在氧化物半导体薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留半导体层图形区域100的光刻胶；将暴露的氧化物半导体薄膜刻蚀掉，并除去保留的光刻胶，以形成氧化物半导体层图形2。
其次，在氧化物半导体层图形2上形成栅绝缘层图形4和栅极图形5。如图2所示，为形成栅绝缘层图形4和栅极图形5(栅线和栅极同时形成，图中未示出栅线)的截面图，形成过程为：在形成有氧化物半导体层图形2的基板上依次沉积绝缘薄膜和栅金属薄膜，绝缘薄膜的材料可以为氮化硅，氧化硅，或者氧化铝等，栅金属的材料可以为铝、铜等金属或铝钕等金属的合金，绝缘薄膜的厚度为
Figure BDA0000141761890000061
在栅金属薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留栅绝缘层、栅极和栅线图形区域101的光刻胶；将暴露的栅金属薄膜刻蚀掉，由于刻蚀金属通常采用酸性试剂进行湿刻，湿刻后暴露出绝缘薄膜；通过干刻的方式刻蚀掉暴露出的绝缘薄膜，并除去保留的光刻胶，以形成栅绝缘层图形4、栅极图形5和栅线图形。由于氧化物半导体的材料为IGZO或ZnO容易受到刻蚀液的影响，因此上述刻蚀过程中，分成湿刻和干刻两步进行。
然后，形成金属扩散层和阻挡层，如图3所示，形成过程为：通过溅射沉积一层金属薄膜，本实施例中为Al薄膜，厚度为
Figure BDA0000141761890000062
在氧气气氛下退火，温度为100～400℃，时间为20min～200min，使得直接覆盖在IGZO或ZnO氧化物半导体层图形2上的Al扩散进氧化物半导体层图形2，以形成金属Al扩散层3，未直接覆盖在氧化物半导体层图形2上的Al薄膜退火形成Al2O3阻挡层6。如图3中，栅绝缘层图形4、栅极图形5及玻璃基板1上都形成了一层Al2O3，Al2O3是一层致密的保护层能有效的阻止氧化物半导体如：IGZO的退化。
接下来，形成钝化层7，在基板上涂覆(如：旋涂)一层用于形成钝化层7的材料使其覆盖前三步形成的图形即可。如图4所示，为形成钝化层7的截面图，本实施例中的钝化层7的材料为丙烯酸酯。
形成钝化层后在钝化层7上形成过孔、源漏极、数据线及像素电极图形，具体形成过程如下：
如图5所示，在钝化层7上涂覆一层厚度为H光刻胶10；通过双调掩膜板(半调掩膜板和灰调掩膜板)曝光显影后，使得过孔区域102的光刻胶完全被显影掉，源漏极图形区域103的光刻胶的厚度为h，h小于H；如图6所示，在过孔区域102处进行干刻形成过孔11，刻蚀过孔11时刻蚀掉过孔区域102处暴露出的所有钝化层，使得过孔区域102处的金属Al扩散层3暴露出来；如图7所示，通过灰化工艺去除源漏极图形区域103处的光刻胶，钝化层7上除过孔11和源漏极图形区域103的其它区域仍保留一定厚度(H-h)光刻胶；如图8所示，依次沉积源漏金属薄膜和像素电极薄膜，使源漏金属薄膜通过过孔11接触金属Al扩散层3，源漏金属薄膜的材料可以为铝、铜、金、银等金属或铝钕等金属的合金，像素电极薄膜的材料可以为ITO或IZO；通过离地剥离的方式去除钝化层7上剩余的光刻胶及附着在光刻胶上的源漏金属薄膜和像素电极薄膜，保留源漏极图形区域103处沉积的源漏金属薄膜和像素电极薄膜，以形成源漏极(包括源电极81和漏电极82)图形、数据线图形(图中未示出)和像素电极图形9。最终形成图8所示的阵列基板。
采用本发明方法制作阵列基板可以广泛地用于LCD显示面板和OLED显示面板，在用于OLED显示面板时，上述像素电极图形9连接OLED的阳极。
本发明制作阵列基板的上述过程一共采用了3次mask工艺，相对于传统的4次以上的mask制作工艺减少了工艺流程，降低了工艺成本。并利用氧化铝作为氧化物半导体的阻挡层，有效地提高了TFT的稳定性。
实施例2
本实施例中上述阵列基板的另一种制作方法，具体如下：
如图9所示，在玻璃基板1上依次沉积氧化物半导体薄膜、绝缘薄膜和栅金属薄膜。氧化物半导体薄膜的材料为IGZO或ZnO，其厚度在
Figure BDA0000141761890000071
绝缘薄膜的材料可以为氮化硅，氧化硅，或者氧化铝等，栅金属的材料可以为铝、铜等金属或铝钕等金属的合金，绝缘薄膜的厚度为
Figure BDA0000141761890000081
如图10所示，在栅金属薄膜上涂覆光刻胶12，通过双调掩膜板(半调掩膜板或灰调掩膜板)对光刻胶12进行曝光显影处理，保留金属扩散层图形区域104、栅绝缘层、栅极和栅线图形区域101的光刻胶12，且金属扩散层图形区域104的光刻胶12的厚度小于栅绝缘层、栅极和栅线图形区域对应的光刻胶12，去掉其余区域的光刻胶12。
依次通过湿刻、干刻、湿刻，刻蚀掉不存在光刻胶12的区域的栅金属薄膜、绝缘薄膜和氧化物半导体薄膜，刻蚀后如图11所示。
如图12所示，通过灰化工艺，保留栅绝缘层、栅极和栅线图形区域101的光刻胶12，去掉其余区域的光刻胶12。
依次通过湿刻、干刻去除掉不存在光刻胶12的区域的栅金属薄膜和绝缘薄膜，并除去保留的光刻胶12，以形成半导体层、栅绝缘层、栅极和栅线图形，如图12所示，为在玻璃基板1上形成半导体层2、栅绝缘层4、栅极5和栅线(图中未示出)图形的截面示意图。
形成如图13(实施例1中图2)的层级结构之后，后续的制作过程和实施例1相同，此处不再赘述。
本实施例中，在玻璃基板1上制作半导体层2、栅绝缘层4、栅极5和栅线(图中未示出)图形的过程中只采用了1次mask，整个制作过程中只采用了2次mask，相对于实施例1减少了工艺流程，降低了工艺成本。
上述实施例1和实施例2中刻蚀掉氧化物半导体的刻蚀液大概成分为′H2SO4∶CH3COOH∶HNO3∶H2O＝10∶5∶15∶70wt％；
刻蚀掉栅极的刻蚀液的主要成分为：H3PO4∶CH3COOH∶HNO3∶Add1∶Add2∶H2O＝63∶17.4∶4.5∶1∶0.1∶14wt％
其比例不仅仅只限于以上比例，Add1和Add2为添加试剂，氧化物半导体的刻蚀液不会对栅极造成腐蚀，栅金属的刻蚀液也不会对氧化物半导体造成腐蚀。
实施例3
本实施例提供了一种阵列基板，该阵列基板可由上述实施例1或实施例2的方法制得，其结构如图8所示，包括：形成于玻璃基板1之上的半导体层2、栅绝缘层4、栅极5、阻挡层6、钝化层7、源漏电极8和像素电极9。栅绝缘层4和栅极5依次形成于半导体层2上。栅绝缘层4与栅极5位于半导体层2的中间位置且形状与大小一致。半导体层2上未被栅绝缘层4覆盖的区域还形成有金属扩散层2。其形成过程如实施例1或实施例2中所述，在半导体层2上沉积一层金属薄膜，优选为Al(因为Al的扩散性较好，且氧化后能形成致密的保护层)，对Al进行氧化，半导体层2表面的Al扩散进氧化物半导体层2，以形成金属Al扩散层3，未直接覆盖在氧化物半导体层图形2上的Al薄膜氧化退火后形成Al2O3阻挡层6，阻挡层6则位于半导体层2的四周并覆盖栅绝缘层4和栅极5，以保护半导体层2不退化。由于制备时在栅绝缘层4和栅极5的表面也沉积有Al，因此经过氧化退火后栅绝缘层4和栅极5的表面也覆盖有Al2O3的阻挡层。
钝化层7覆盖半导体层2、栅绝缘层4、栅极5和阻挡层6(包括半导体层2四周和栅绝缘层4和栅极5的表面的阻挡层)，源漏电极8连接金属Al扩散层3，像素电极9和漏电极接触。本实施例中，由于上述特有的制作过程，源漏电极(包括源电极81和漏电极82)位于钝化层7之上，且通过钝化层上的过孔11连接金属Al扩散层3。具体的，源电极81和漏电极82分别连接位于半导体层2两端的金属扩散层3。
本实施例中，半导体层除普通半导体外，优选为金属氧化物半导体，如IGZO等。所述阻挡层除了可以为上述所述的等非导电的Al2O3等金属氧化物外，还可以为其他非导电的材料。
采用上述实施例1或2的方法制得的阵列基板具有成本低的优点。本实施例提供的阵列基板，由于采用了氧化物(比如氧化铝)作为氧化物半导体的阻挡层，有效地提高了TFT的稳定性。
实施例4
本实施例中提供了一种显示装置，包括实施例3中的阵列基板。所述显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (19)

1.一种阵列基板制作方法，其特征在于，包括以下步骤：
S1：在基板上形成包括半导体层、栅绝缘层、栅极和栅线的图形；
S2：在步骤S1之后的基板上，未被所述栅绝缘层覆盖的半导体层图形上形成金属扩散层，其它区域形成阻挡层；
S3：在步骤S2之后的基板上形成钝化层；
S4：在所述钝化层上形成过孔、源漏极、数据线和像素电极的图形，所述源漏极通过所述过孔连接所述金属扩散层。
2.如权利要求1所述的阵列基板制作方法，其特征在于，所述过程S1具体包括：
在所述基板上沉积氧化物半导体薄膜；
在所述氧化物半导体薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留半导体层图形区域的光刻胶，将暴露的氧化物半导体薄膜刻蚀掉，并除去保留的光刻胶，以形成半导体层图形；
在形成半导体层图形后的基板上依次沉积绝缘薄膜和栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影处理，保留栅绝缘层、栅极和栅线图形区域的光刻胶，将暴露的栅金属薄膜刻蚀掉，暴露出绝缘薄膜；
通过干刻的方式刻蚀掉暴露出的绝缘薄膜，并除去保留的光刻胶，以形成栅绝缘层、栅极和栅线图形。
3.如权利要求1所述的阵列基板制作方法，其特征在于，所述过程S1具体包括：
在所述基板上依次沉积氧化物半导体薄膜、绝缘薄膜和栅金属薄膜；
在栅金属薄膜上涂覆光刻胶，通过双调掩膜板对所述光刻胶进行曝光显影处理，保留金属扩散层图形区域、栅绝缘层、栅极和栅线图形区域的光刻胶，且金属扩散层图形区域的光刻胶的厚度小于栅绝缘层、栅极和栅线图形区域对应的光刻胶，去掉其余区域的光刻胶；
依次通过湿刻、干刻、湿刻，刻蚀掉不存在光刻胶区域的栅金属薄膜、绝缘薄膜和氧化物半导体薄膜；
通过灰化工艺，保留栅绝缘层、栅极和栅线图形区域的光刻胶，去掉其余区域的光刻胶；
依次通过湿刻、干刻去除掉不存在光刻胶区域的栅金属薄膜和绝缘薄膜，并除去保留的光刻胶，以形成半导体层、栅绝缘层、栅极和栅线图形。
4.如权利要求2或3所述的阵列基板制作方法，其特征在于，所述氧化物半导体薄膜的材料为：IGZO或ZnO。
5.如权利要求2或3所述的阵列基板制作方法，其特征在于，所述半导体层的厚度为
Figure FDA0000141761880000021
6.如权利要求2或3所述的阵列基板制作方法，其特征在于，所述栅绝缘层的厚度为
7.如权利要求1所述的阵列基板制作方法，其特征在于，所述过程S2具体包括：
溅射沉积一层金属薄膜；
在氧气气氛下退火，使得直接覆盖在所述半导体层图形上的金属扩散进所述半导体层图形，以形成金属扩散层，未直接覆盖在所述半导体层图形上的金属薄膜退火形成金属氧化物阻挡层。
8.如权利要求7所述的阵列基板制作方法，其特征在于，所述金属薄膜的厚度为
Figure FDA0000141761880000023
9.如权利要求7或8所述的阵列基板制作方法，其特征在于，所述金属薄膜为铝薄膜。
10.如权利要求9所述的阵列基板制作方法，其特征在于，所述铝薄膜的退火温度为100～400℃，退火时间为20～200min。
11.如权利要求1所述的阵列基板制作方法，其特征在于，所述过程S4具体包括：
在所述钝化层涂覆光刻胶，通过双调掩膜板对所述光刻胶进行曝光显影处理，去掉过孔区域的光刻胶，且保留源漏极和数据线图形区域的光刻胶；
刻蚀掉暴露出的钝化层形成过孔，使露出过孔处的金属扩散层；
通过灰化工艺去除源漏极和数据线图形区域的光刻胶，依次沉积源漏金属薄膜和像素电极薄膜，使源漏金属薄膜接触所述金属扩散层；
通过离地剥离的方式去除钝化层上剩余的光刻胶及附着在光刻胶上的源漏金属薄膜和像素电极薄膜，以形成源漏极、数据线和像素电极图形。
12.如权利要求11所述的阵列基板制作方法，其特征在于，所述像素电极的材料为：ITO或IZO。
13.一种阵列基板，包括：形成于透明基板之上的半导体层、栅绝缘层、栅极、阻挡层、钝化层、源漏电极和像素电极，其特征在于，所述栅绝缘层和栅极依次形成于所述半导体层上，所述栅绝缘层与所述栅极位于所述半导体层的中间位置且形状与大小一致，所述半导体层上未被栅绝缘层覆盖的区域还形成有金属扩散层，所述阻挡层包括覆盖所述栅绝缘层和栅极的部分以及位于所述半导体层四周的部分，所述钝化层覆盖所述半导体层、栅绝缘层、栅极和第一阻挡层，所述源漏电极连接所述金属扩散层，所述像素电极和漏电极接触。
14.如权利要求13所述的阵列基板，其特征在于，所述源漏电极位于所述钝化层之上，且通过钝化层上的过孔连接所述金属扩散层。
15.如权利要求13所述的阵列基板，其特征在于，所述半导体层为金属氧化物半导体。
16.如权利要求13～15中任一项所述的阵列基板，其特征在于，所述金属扩散层为Al扩散层。
17.如权利要求13～15中任一项所述的阵列基板，其特征在于，所述阻挡层为非导电的金属氧化物。
18.如权利要求17所述的阵列基板，其特征在于，所述金属氧化物为Al2O3。
19.一种显示装置，其特征在于，包括如权利要求13～18中任一项所述的阵列基板。
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