WO2017152552A1 - 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 - Google Patents

薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 Download PDF

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WO2017152552A1
WO2017152552A1 PCT/CN2016/088071 CN2016088071W WO2017152552A1 WO 2017152552 A1 WO2017152552 A1 WO 2017152552A1 CN 2016088071 W CN2016088071 W CN 2016088071W WO 2017152552 A1 WO2017152552 A1 WO 2017152552A1
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photoresist
layer
region
source
forming
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PCT/CN2016/088071
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English (en)
French (fr)
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郭会斌
张小祥
王静
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/527,410 priority Critical patent/US10141423B2/en
Publication of WO2017152552A1 publication Critical patent/WO2017152552A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor, an array substrate, a display device, a method of manufacturing the thin film transistor, and a method of manufacturing the array substrate.
  • TFT-LCDs thin-film transistor liquid crystal displays
  • the prior art In the manufacture of the thin film transistor, in order to avoid corrosion of the active layer on the region corresponding to the channel when etching the source and drain metal between the source electrode and the drain electrode, the prior art often removes the active layer.
  • the first photoresist layer retains the photoresist over the region corresponding to the channel; then, after forming the source/drain metal layer, the second photoresist layer is coated over the source/drain metal layer, and the source and drain metal are retained a photoresist over a region corresponding to the source/drain electrode and a photoresist over a region corresponding to the channel, so that the photoresist remaining over the active layer can protect the active layer when etching the source drain metal layer Not being etched; finally, simultaneously stripping the photoresist over the region corresponding to the source and drain electrodes of the source/drain metal layer, the photoresist in the second photoresist layer over the region corresponding to the channel, and corresponding to the channel
  • An object of the present invention is to provide a thin film transistor and a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device for solving the stripping of a photoresist due to the presence of a source/drain metal layer when the photoresist remaining over the active layer is peeled off Incompletely affecting the characteristics of thin film transistors.
  • Embodiments of the present invention provide a method of manufacturing a thin film transistor, including: forming a protective layer in a region between source and drain electrodes to be formed over an active layer; forming a source and drain over an active layer on which the protective layer is formed a metal layer; coating a photoresist on the source/drain metal layer, and forming a photoresist retention region and a photoresist non-retention region, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, the photoresist The non-retained area corresponds to the other areas; the source/drain metal layer corresponding to the photoresist non-retained area is etched away to form the source-drain electrodes, and the protective layer above the active layer is exposed; and the source-drain electrodes are removed a photoresist and the protective layer.
  • the protective layer may be a positive photoresist or a negative photoresist.
  • the thickness of the protective layer may be to
  • the thickness of the protective layer may be any thickness of the protective layer.
  • the method may further include forming an active layer, and forming the active layer may include: forming a semiconductor layer; coating a photoresist on the semiconductor layer, and forming a photoresist completely reserved region a photoresist partial retention region corresponding to a region between source and drain electrodes to be formed, and a photoresist non-retention region corresponding to the active layer a region of the source/drain electrode to be formed above, the photoresist non-retained region corresponding to a region other than the active layer region; etching a semiconductor layer corresponding to the photoresist non-retained region by an etching process; and adopting ashing The process removes the photoresist from the remaining portion of the photoresist.
  • the method can also include forming an ohmic contact layer over the active layer.
  • the method may further include sequentially forming a gate and a gate insulating layer before forming the active layer.
  • Embodiments of the present invention also provide a thin film transistor fabricated according to the above method.
  • the embodiment of the invention further provides a method for manufacturing an array substrate, comprising the method of any one of the above.
  • the method may further include: sequentially forming a gate and a gate insulating layer. After removing the photoresist and the protective layer over the source and drain electrodes, the method may further include: forming a passivation layer on the source and drain electrodes, and A first conductive layer is formed on the passivation layer.
  • a second conductive layer may be formed while forming the gate.
  • Embodiments of the present invention also provide an array substrate prepared according to the above method.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • a photoresist retention region and a photoresist non-retention region are formed when exposing the photoresist over the metal drain layer, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, and photolithography
  • the glue non-retained area corresponds to the channel region and other regions between the source and drain electrodes to be formed, and then the metal above the channel region is simultaneously etched while etching the source and drain metal layers, exposing the remaining over the active layer.
  • FIG. 1 is a process flow diagram in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic view showing a process of fabricating a gate of a thin film transistor according to an embodiment of the present invention.
  • 3 to 5 are schematic views showing a process of manufacturing an active layer of a thin film transistor according to an embodiment of the present invention.
  • 6 to 9 are schematic views showing a process of manufacturing a source-drain electrode of a thin film transistor according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural view of an array substrate according to an embodiment of the invention.
  • FIG. 11 is a schematic structural view of an array substrate according to an embodiment of the invention.
  • FIG. 12 is a schematic structural view of an array substrate according to an embodiment of the invention.
  • an embodiment of the present invention provides a method for manufacturing a thin film transistor.
  • the method includes the following steps S1 to S3.
  • Step S1 includes: forming a protective layer on a region between the source and drain electrodes to be formed over the active layer, forming a source/drain metal layer over the active layer on which the protective layer is formed, and coating a photoresist on the source/drain metal layer And forming a photoresist retention region and a photoresist non-retention region, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, and the photoresist non-retention region corresponds to other regions.
  • Step S2 includes etching away a source/drain metal layer corresponding to the photoresist non-retained region to form a source/drain electrode, and exposing the protective layer above the active layer.
  • Step S3 includes removing the photoresist and the protective layer over the source and drain electrodes.
  • the protective layer may protect a region of the active layer corresponding to the channel when the source and drain electrodes are formed by etching, so as to prevent the region of the active layer corresponding to the channel from being corroded by the etching solution. Affects TFT characteristics. By first etching away the material of the region between the source and drain electrodes of the source and drain metal layers, exposing the protective layer above the active layer, and further removing the photoresist over the source and drain electrodes and the protective layer, The protective layer is removed more thoroughly, and the influence of the material of the residual protective layer on the characteristics of the TFT is avoided.
  • the protective layer material may be a photoresist, so that a protective layer may be formed together when the active layer is formed, simplifying Process flow, simple operation and reduced cost.
  • the protective layer may also be formed by other materials and processes, as long as it can protect the active layer, and details are not described herein.
  • the protective layer material is used as a photoresist as an example for description.
  • the photoresist described in the embodiments of the present invention may be a positive photoresist or a negative photoresist. After the positive photoresist is exposed, the illuminated area is soluble in the developer. After exposure to the negative photoresist, the illuminated area is insoluble in the developer.
  • FIGS. 2 through 9 a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 2 through 9.
  • the gate electrode 200 is formed on the base substrate 100.
  • a gate metal layer is formed on the base substrate 100 by a sputtering process, which may be a single layer structure or a multilayer structure.
  • the photoresist is then coated and the gate 200 is formed by processes such as exposure, development, etching, and the like.
  • a gate insulating layer 300 is formed over the gate electrode 200, and an active layer 400 is formed over the gate insulating layer 300.
  • a gate insulating layer 300 is formed over a gate 200 by a plasma enhanced chemical vapor deposition (PECVD) process or an atmospheric pressure chemical vapor deposition (CVD) process; and formed by a sputtering process over the gate insulating layer 300.
  • PECVD plasma enhanced chemical vapor deposition
  • CVD atmospheric pressure chemical vapor deposition
  • a photoresist 500 is coated over the semiconductor layer 401, and the photoresist is exposed and developed to form a photoresist completely remaining region 501, a photoresist portion remaining region 502, and a photoresist.
  • Area 503 is not reserved.
  • the photoresist completely reserved region 501 corresponds to a region between the source and drain electrodes to be formed
  • the photoresist portion reserved region 502 corresponds to a region above the active layer where a source/drain electrode is to be formed
  • the photoresist non-reserved region 503 corresponds to An area outside the active layer area.
  • the semiconductor layer corresponding to the photoresist non-retained region 503 is removed by an etching process, and then the photoresist of the photoresist portion remaining region 502 is removed by an ashing process or an ultraviolet irradiation and etching process to form an active layer. 400.
  • the photoresist remaining in the photoresist completely remaining region 501 above the active layer 400 can serve as a protective layer of the active layer 400, so that the region corresponding to the channel of the active layer 400 forms a source leakage by etching. Extremely protected from the etching solution, as shown in Figure 5.
  • the principle of the ashing process is: in a closed oxygen environment, at a certain temperature, oxygen is allowed to react with the photoresist, because the photoresist is an organic substance that easily reacts with oxygen to become water and carbon dioxide, so The thickness of the thinned photoresist is controlled by precisely controlling the time, temperature, and oxygen concentration.
  • the ashing process plays a certain role in reducing the photoresist of the photoresist completely remaining region 501.
  • the photoresist completely retains the thickness of the photoresist of the region 501, that is, the thickness of the protective layer is to
  • the thickness of the protective layer is less than
  • the protective layer is too thin to provide good protection, so that the etching solution causes a certain degree of corrosion to the region of the active layer corresponding to the channel.
  • the thickness of the protective layer is greater than
  • the process of removing the protective layer and related parameters such as time and temperature are required to be high, thereby increasing the process difficulty.
  • the thickness of the protective layer is When the active layer is well protected, the process is more difficult.
  • the manner of forming the active layer 400 and the protective layer is not limited to the above steps.
  • the photoresist may be coated on the active layer 400 by exposure. And the development process, leaving only the photoresist on the active layer corresponding to the region between the source and drain electrodes.
  • source and drain electrodes are formed over the active layer 400.
  • the source/drain metal layer 600 is formed by magnetron sputtering, thermal evaporation, or other film forming process, and the source/drain metal layer 600 may be a single layer structure or a multilayer structure.
  • a photoresist is coated over the source/drain metal layer 600, and a photoresist retention region 602 and a photoresist non-retention region 601 are formed by exposure and development.
  • the photoresist retention region 602 corresponds to a region where source and drain electrodes are to be formed, and the photoresist non-retention region 601 corresponds to other regions.
  • the source/drain metal layer corresponding to the photoresist non-retained region 601 is etched away, and the protective layer 501 above the active layer is exposed between the source and drain electrodes.
  • the photoresist of the photoresist retention region 602 over the protective layer 501 and the source/drain metal layer 600 is simultaneously stripped to form a source 702 and a drain 701.
  • a protective layer is formed on a region between the source and drain electrodes above the active layer, and the protective layer can protect the trench when forming the source and drain electrodes by etching.
  • the active layer corresponding to the channel prevents the active layer from being corroded by the etching solution and affects the characteristics of the TFT.
  • the source and drain metal layer materials in the region between the source and drain electrodes are etched first, the protective layer above the active layer is exposed, and the photoresist over the source and drain electrodes and the protection are When the layers are removed together, the protective layer can be removed more thoroughly, and the influence of the residual protective layer material on the TFT characteristics is avoided.
  • Embodiments of the present invention also provide a thin film transistor according to the above thin film crystal
  • the manufacturing method of the tube is manufactured. It can be understood that the thin film transistor also has the above technical effects.
  • Embodiments of the present invention also provide a method of fabricating an array substrate, including the foregoing method of fabricating a thin film transistor, and further comprising: forming a passivation layer over the source and drain electrodes; and forming a first conductive layer over the passivation layer.
  • a plasma-enhanced chemical vapor deposition (PECVD) process or an atmospheric pressure chemical vapor deposition (CVD) process, magnetron sputtering, thermal evaporation, or other film formation process is used to form a blunt over the source and drain electrodes.
  • the material of the passivation layer 800 may include an oxide, a nitride or an oxynitride such as SiNx, SiOx or Si(ON)x.
  • the passivation layer 800 may have a single layer structure or a two-layer structure composed of silicon nitride and silicon oxide.
  • the passivation layer 800 is patterned, a passivation layer via is formed over the drain electrode 701, and a transparent conductive layer is deposited over the passivation layer 800 by magnetron sputtering, thermal evaporation or other film forming process.
  • the transparent conductive layer may include ITO or IZO, and the transparent conductive layer is patterned by a patterning process.
  • the transparent conductive layer is formed as a pixel electrode 900 after the patterning process, and the pixel electrode 900 is electrically connected to the drain electrode 701 through the passivation layer via.
  • a protective layer is formed on a region between the source and drain electrodes above the active layer, and the protective layer can be protected and channeled when etching the source and drain electrodes.
  • Corresponding active layer prevents the active layer from being corroded by the etching solution and affects the characteristics of the TFT.
  • the source and drain metal layer materials in the region between the source and drain electrodes are etched first, the protective layer above the active layer is exposed, and the photoresist over the source and drain electrodes and the protection are When the layers are removed together, the protective layer can be removed more thoroughly, and the influence of the residual protective layer material on the TFT characteristics is avoided.
  • the embodiment of the invention further provides an array substrate which is manufactured according to the manufacturing method of the above array substrate. It can be understood that the array substrate also has the above technical effects.
  • the embodiment of the present invention further provides a method for manufacturing a thin film transistor, which is different from the method for manufacturing a thin film transistor of the foregoing embodiment in that after the active layer 400 and the protective layer 501 are formed, PECVD or the like is passed thereon.
  • Process deposition The N+a-Si layer is removed and the corresponding portion is removed when etching the source/drain metal layer in a subsequent process to form the ohmic contact layer 901, as shown in FIG.
  • the formation methods of the other film layers are the same as those in the foregoing embodiment, and are not described herein again.
  • the embodiment of the present invention further provides a method for manufacturing an array substrate, which is different from the method for manufacturing an array substrate of the foregoing embodiment in that magnetron sputtering, thermal evaporation, or magnetization is used before the gate insulating layer 300 is formed.
  • Other film forming processes deposit a transparent conductive layer 201 on the base substrate 100 as shown in FIG.
  • the transparent conductive layer 201 may include ITO or IZO, and the transparent conductive layer may be a common electrode.
  • the transparent conductive layer 201 and the gate electrode 200 may be formed in the same patterning process.
  • the other manufacturing processes in this embodiment are the same as those in the foregoing embodiments, and are not described herein again.
  • the embodiment of the invention further provides a display device, which comprises the array substrate in the above embodiment.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

提供了薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置。所述制造薄膜晶体管的方法包括：在有源层（400）上方待形成的源漏电极之间的区域形成保护层（501），在形成有保护层（501）的有源层（400）上方形成源漏金属层（600），在所述源漏金属层（600）上涂覆光刻胶，以及形成光刻胶保留区域（602）和光刻胶不保留区域（601），其中所述光刻胶保留区域（602）对应于待形成的源漏电极的区域，所述光刻胶不保留区域（601）对应于其他区域；刻蚀掉与所述光刻胶不保留区域（601）对应的源漏金属层（600），以形成源漏电极，并且露出所述有源层（400）上方的所述保护层（501）；以及去除所述源漏电极上方的光刻胶和所述保护层（501）。

Description

薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 技术领域
本发明涉及液晶显示技术领域，特别涉及薄膜晶体管、阵列基板、显示装置、制造薄膜晶体管的方法和制造阵列基板的方法。
背景技术
随着液晶技术的发展，高品质、低功耗、无辐射的薄膜晶体管液晶显示器(TFT-LCD)已成为市场的主流。
在制造薄膜晶体管时，为了避免在刻蚀源电极和漏电极之间的源漏金属时刻蚀液对有源层的与沟道对应的区域产生腐蚀，现有技术中往往在去除有源层上方的第一光刻胶层时保留与沟道对应的区域上方的光刻胶；然后在形成源漏金属层之后，在源漏金属层上方涂覆第二光刻胶层，以及保留源漏金属层的与源漏电极对应的区域上方的光刻胶和与沟道对应的区域上方的光刻胶，从而在刻蚀源漏金属层时有源层上方保留的光刻胶可以保护有源层不被腐蚀；最后再同时剥离源漏金属层的与源漏电极对应的区域上方的光刻胶、与沟道对应的区域上方的第二光刻胶层中的光刻胶和与沟道对应的区域上方的第一光刻胶层中的光刻胶。
但这种方法存在一个问题，由于有源层上的第一光刻胶层中的光刻胶被源漏金属层等膜层覆盖，最后剥离光刻胶时很容易造成剥离不彻底等问题，从而影响薄膜晶体管特性。
发明内容
本发明的目的是提供薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置，用以解决在剥离有源层上方保留的光刻胶时由于源漏金属层的存在导致光刻胶剥离不彻底而影响薄膜晶体管特性的问题。
本发明实施例提供一种制造薄膜晶体管的方法，其包括：在有源层上方待形成的源漏电极之间的区域形成保护层；在形成有所述保护层的有源层上方形成源漏金属层；在源漏金属层上涂覆光刻胶，以及形成光刻胶保留区域和光刻胶不保留区域，其中光刻胶保留区域对应于待形成的源漏电极的区域，光刻胶不保留区域对应于其他区域；刻蚀掉与光刻胶不保留区域对应的源漏金属层，以形成源漏电极，并且露出有源层上方的所述保护层；以及去除源漏电极上方的光刻胶和所述保护层。
所述保护层可以为正性光刻胶或负性光刻胶。
所述保护层的厚度范围可以为
Figure PCTCN2016088071-appb-000001
至
Figure PCTCN2016088071-appb-000002
所述保护层的厚度可以为
Figure PCTCN2016088071-appb-000003
在形成所述保护层之前，所述方法还可以包括形成有源层，形成有源层可以包括：形成半导体层；在所述半导体层上涂覆光刻胶，以及形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中所述光刻胶完全保留区域对应于待形成的源漏电极之间的区域，所述光刻胶部分保留区域对应于有源层上方待形成的源漏电极的区域，所述光刻胶不保留区域对应于有源层区域以外的区域；采用刻蚀工艺刻蚀与光刻胶不保留区域对应的半导体层；以及采用灰化工艺去除光刻胶部分保留区域的光刻胶。
所述方法还可以包括：在所述有源层上方形成欧姆接触层。
所述方法还可以包括：在形成所述有源层之前依次形成栅极和栅绝缘层。
本发明实施例还提供一种薄膜晶体管，所述薄膜晶体管根据上述方法制造。
本发明实施例还提供一种制造阵列基板的方法，包括上述任意一种的方法。
在形成有源层之前，所述方法还可以包括：依次形成栅极和栅绝缘层。在去除所述源漏电极上方的光刻胶和所述保护层之后，所述方法还可以包括：在所述源漏电极上形成钝化层，以及在所 述钝化层上形成第一导电层。
在形成所述栅极的同时可以形成第二导电层。
本发明实施例还提供了一种阵列基板，其根据上述方法制备。
本发明实施例还提供一种显示装置，包括上述阵列基板。
上述技术方案中，在曝光源漏金属层上方的光刻胶时形成光刻胶保留区域和光刻胶不保留区域，其中光刻胶保留区域对应于待形成的源漏电极的区域，光刻胶不保留区域对应于待形成的源漏电极之间的沟道区域和其他区域，随后在刻蚀源漏金属层时同时刻蚀掉沟道区域上方的金属，曝露出有源层上方保留的一定厚度的光刻胶，随后在最后剥离光刻胶时，所述光刻胶上方由于不再覆盖有其他膜层，使得剥离彻底，不会有残留，从而使得薄膜晶体管的特性不受影响。
附图说明
图1为根据本发明实施例的工艺流程图。
图2为示出根据本发明实施例的制造薄膜晶体管的栅极的过程的示意图。
图3至图5为示出根据本发明实施例的制造薄膜晶体管的有源层的过程的示意图。
图6至图9为示出根据本发明实施例的制造薄膜晶体管的源漏电极的过程的示意图。
图10为根据本发明实施例的阵列基板的结构示意图。
图11为根据本发明实施例的阵列基板的结构示意图。
图12为根据本发明实施例的阵列基板的结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实例用于说明本发明的原理，但不用来限制本发明的范围。
如图1所示，本发明实施例提供了一种制造薄膜晶体管的方 法，其包括以下步骤S1至步骤S3。
步骤S1包括：在有源层上方待形成的源漏电极之间的区域形成保护层，在形成有保护层的有源层上方形成源漏金属层，在源漏金属层上涂覆光刻胶，以及形成光刻胶保留区域和光刻胶不保留区域，其中光刻胶保留区域对应于待形成的源漏电极的区域，光刻胶不保留区域对应于其他区域。
步骤S2包括：刻蚀掉与光刻胶不保留区域对应的源漏金属层，以形成源漏电极，并且露出有源层上方的所述保护层。
步骤S3包括：去除所述源漏电极上方的光刻胶和所述保护层。
在本发明实施例中，所述保护层可以在刻蚀形成源漏电极时保护有源层的与沟道对应的区域，避免有源层的与沟道对应的区域受到刻蚀液的腐蚀，影响TFT特性。通过先刻蚀掉源漏金属层的源漏电极之间的区域的材料，暴露出有源层上方的保护层，再将源漏电极上方的光刻胶和所述保护层一并去除，可以使所述保护层去除得更彻底，避免了残留的保护层的材料对TFT特性的影响。
具体地，由于在制作有源层时要在半导体层上方涂覆一层光刻胶，因此所述保护层材料可以为光刻胶，这样可以在制作有源层时一并形成保护层，简化工艺流程，操作简单，降低了成本。当然，所述保护层也可以采用其他材料和工艺形成，只要能够起到保护有源层的作用即可，这里不再赘述。本发明实施例中均以保护层材料为光刻胶为例进行说明。
需要说明的是，本发明实施例中所述的光刻胶可以是正性光刻胶，也可以是负性光刻胶。正性光刻胶在经过曝光之后，光照区域可溶于显影液。负性光刻胶在经过曝光之后，光照区域不溶于显影液。
具体地，将参照图2至图9说明根据本发明实施例的制造薄膜晶体管的方法。
首先，在衬底基板100上形成栅极200。
如图2所示，在衬底基板100上通过溅射工艺形成一层栅金属层，其可以为单层结构或者多层结构。然后涂覆光刻胶，通过曝光、显影、刻蚀等工艺形成栅极200。
然后，在栅极200上方形成栅绝缘层300，以及在栅绝缘层300上方形成有源层400。
如图3所示，在栅极200上方采用等离子体增强化学气相沉积(PECVD)工艺或常压化学气相沉积(CVD)工艺形成栅绝缘层300；以及在栅绝缘层300上方通过溅射工艺形成一层半导体层401。
如图4所示，在半导体层401上方涂覆一层光刻胶500，并对光刻胶进行曝光、显影之后形成光刻胶完全保留区域501、光刻胶部分保留区域502和光刻胶不保留区域503。光刻胶完全保留区域501对应于待形成的源漏电极之间的区域，光刻胶部分保留区域502对应于有源层上方待形成源漏电极的区域，光刻胶不保留区域503对应于有源层区域以外的区域。
然后，通过刻蚀工艺去除与光刻胶不保留区域503对应的半导体层，随后通过灰化工艺或者紫外照射和刻蚀工艺去除光刻胶部分保留区域502的光刻胶，以形成有源层400。此时有源层400上方保留的光刻胶完全保留区域501的光刻胶就可以作为有源层400的保护层，使有源层400的与沟道对应的区域在通过刻蚀形成源漏电极时免受刻蚀液的影响，如图5所示。
灰化工艺的原理为：在密闭的氧气环境中，在一定温度下，让氧气与光刻胶反应，因为光刻胶是有机物很容易与氧气发生化学反应，从而变成水与二氧化碳，因此可以通过精确控制时间、温度、氧气浓度来控制减薄光刻胶的厚度。
灰化工艺会对光刻胶完全保留区域501的光刻胶起到一定减薄作用，灰化工艺后光刻胶完全保留区域501的光刻胶厚度，即保护层的厚度范围为
Figure PCTCN2016088071-appb-000004
至
Figure PCTCN2016088071-appb-000005
当保护层的厚度小于
Figure PCTCN2016088071-appb-000006
时，会在通过刻蚀形成源漏电极时由于保护层太薄而无法起到良好的保护作用，使刻蚀液对有源层的与沟道对应的区域造成一定 程度的腐蚀。当保护层的厚度大于
Figure PCTCN2016088071-appb-000007
时，对去除保护层的工艺以及相关参数，如时间、温度等要求较高，从而增加了工艺难度。当保护层的厚度为
Figure PCTCN2016088071-appb-000008
时，可以良好的保护有源层，工艺的难度也比较合适。
需要说明的是，形成上述有源层400和保护层的方式并不局限于上述步骤，例如，还可以在形成有源层400后，再在有源层400上涂覆光刻胶，通过曝光和显影工艺，只保留有源层上与源漏电极之间的区域对应的光刻胶。
接着，在有源层400上方形成源漏电极。
如图6所示，有源层400形成之后，通过磁控溅射、热蒸发或其他成膜工艺形成源漏金属层600，源漏金属层600可以是单层结构或多层结构。
如图7所示，在源漏金属层600上方涂覆光刻胶，通过曝光、显影，形成光刻胶保留区域602和光刻胶不保留区域601。光刻胶保留区域602对应于待形成源漏电极的区域，光刻胶不保留区域601对应于其他区域。
如图8所示，刻蚀掉与光刻胶不保留区域601对应的源漏金属层，此时源漏电极之间就露出了有源层上方的保护层501。
如图9所示，同时剥离保护层501和源漏金属层600上方光刻胶保留区域602的光刻胶，以形成源极702和漏极701。源极702和漏极701之间的部分在TFT打开时形成导电沟道。
综上所述，本发明实施例提供的制造薄膜晶体管的方法中，在有源层上方源漏电极之间的区域形成保护层，该保护层可以在通过刻蚀形成源漏电极时保护与沟道对应的有源层，避免该有源层受到刻蚀液的腐蚀，影响TFT特性。此外，在形成源漏电极时，先刻蚀掉源漏电极之间的区域的源漏金属层材料，暴露出有源层上方的保护层，再将源漏电极上方的光刻胶和所述保护层一并去除，可以使所述保护层去除得更彻底，避免了残留的保护层材料对TFT特性的影响。
本发明实施例还提供一种薄膜晶体管，其根据上述薄膜晶体 管的制造方法制造。可以理解的是，该薄膜晶体管也具有上述技术效果。
本发明实施例还提供一种阵列基板的制造方法，其包括前述的制造薄膜晶体管的方法，并且还包括：在源漏电极上方形成钝化层；以及在钝化层上方形成第一导电层。
具体地，如图10所示，采用等离子体增强化学气相沉积(PECVD)工艺或常压化学气相沉积(CVD)工艺、磁控溅射、热蒸发或其他成膜工艺在源漏电极上方形成钝化层800，钝化层800的材料可以包括氧化物、氮化物或氮氧化物，例如SiNx，SiOx或Si(ON)x。钝化层800可以为单层结构，也可是采用氮化硅和氧化硅构成的双层结构。
随后，对钝化层800进行构图工艺，在漏电极701上方形成钝化层过孔，并采用磁控溅射、热蒸发或其他成膜工艺在钝化层800上方沉积一层透明导电层，该透明导电层可以包括ITO或者IZO，并通过构图工艺对该透明导电层进行图案化。具体地，如图10所示，该透明导电层经过构图工艺之后形成为像素电极900，像素电极900通过钝化层过孔与漏电极701电性连接。
综上所述，本发明实施例提供的制造阵列基板的方法中，在有源层上方源漏电极之间的区域形成保护层，该保护层可以在刻蚀形成源漏电极时保护与沟道对应的有源层，避免该有源层受到刻蚀液的腐蚀，影响TFT特性。此外，在形成源漏电极时，先刻蚀掉源漏电极之间的区域的源漏金属层材料，暴露出有源层上方的保护层，再将源漏电极上方的光刻胶和所述保护层一并去除，可以使所述保护层去除得更彻底，避免了残留的保护层材料对TFT特性的影响。
本发明实施例还提供一种阵列基板，其根据上述阵列基板的制造方法制造。可以理解的是，该阵列基板也具有上述技术效果。
本发明实施例还提供了一种制造薄膜晶体管的方法，该方法与前述实施例的制造薄膜晶体管的方法的不同之处在于，形成有源层400与保护层501之后，在其上通过PECVD等工艺沉积 N+a-Si层，并在后续工艺中刻蚀源漏金属层时去除相应的部分，以形成欧姆接触层901，如图11所示。其他膜层的形成方法均与前述实施例中的形成方法相同，这里不再赘述。
本发明实施例还提供了一种制造阵列基板的方法，该方法与前述实施例的制造阵列基板的方法的不同之处在于，在形成栅绝缘层300之前，采用磁控溅射、热蒸发或其他成膜工艺在衬底基板100上沉积透明导电层201，如图12所示。该透明导电层201可以包括ITO或者IZO，该透明导电层可以为公共电极。例如，该透明导电层201与栅极200可以在同一构图工艺中形成。本实施例中其他制作工艺均与前述实施例中的制造工艺相同，此处不再赘述。
本发明实施例还提供一种显示装置，所述显示装置包括上述实施例中的阵列基板。
所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种制造薄膜晶体管的方法，包括：
    在有源层上方待形成的源漏电极之间的区域形成保护层；
    在形成有所述保护层的有源层上方形成源漏金属层；
    在所述源漏金属层上涂覆光刻胶，以及形成光刻胶保留区域和光刻胶不保留区域，其中所述光刻胶保留区域对应于待形成的源漏电极的区域，所述光刻胶不保留区域对应于其他区域；
    刻蚀掉与所述光刻胶不保留区域对应的源漏金属层，以形成源漏电极，并且露出所述有源层上方的所述保护层；以及
    去除所述源漏电极上方的光刻胶和所述保护层。
  2. 如权利要求1所述的方法，其中，所述保护层为正性光刻胶或负性光刻胶。
  3. 如权利要求1所述的方法，其中，所述保护层的厚度范围为
    Figure PCTCN2016088071-appb-100001
    至
    Figure PCTCN2016088071-appb-100002
  4. 如权利要求3所述的方法，其中，所述保护层的厚度为
    Figure PCTCN2016088071-appb-100003
  5. 如权利要求1至4中任一项所述的方法，其中，在形成所述保护层之前，所述方法还包括形成有源层，形成有源层包括：
    形成半导体层；
    在所述半导体层上涂覆光刻胶，以及形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中所述光刻胶完全保留区域对应于待形成的源漏电极之间的区域，所述光刻胶部分保留区域对应于所述有源层上方待形成的源漏电极的区域，所述光刻胶不保留区域对应于有源层区域以外的区域；
    采用刻蚀工艺刻蚀与光刻胶不保留区域对应的半导体层；以 及
    采用灰化工艺去除所述光刻胶部分保留区域的光刻胶。
  6. 如权利要求5所述的方法，还包括：在所述有源层上方形成欧姆接触层。
  7. 如权利要求5或6所述的方法，还包括：在形成所述有源层之前依次形成栅极和栅绝缘层。
  8. 一种薄膜晶体管，所述薄膜晶体管根据权利要求1至7中任意一项所述的方法制造。
  9. 一种制造阵列基板的方法，包括如权利要求1至6中任一项所述的方法。
  10. 如权利要求9所述的方法，其中，
    在形成所述有源层之前，所述方法还包括：依次形成栅极和栅绝缘层，并且
    在去除所述源漏电极上方的光刻胶和所述保护层之后，所述方法还包括：在所述源漏电极上形成钝化层，以及在所述钝化层上形成第一导电层。
  11. 如权利要求10所述的方法，其中，在形成所述栅极的同时形成第二导电层。
  12. 一种阵列基板，所述阵列基板根据权利要求9至11中任一项所述的方法制备。
  13. 一种显示装置，包括如权利要求12所述的阵列基板。
PCT/CN2016/088071 2016-03-09 2016-07-01 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 WO2017152552A1 (zh)

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CN107093582A (zh) * 2017-04-28 2017-08-25 京东方科技集团股份有限公司 显示面板的制造方法和显示面板
CN107706116A (zh) * 2017-09-15 2018-02-16 惠科股份有限公司 主动阵列开关的制造方法
CN108666325B (zh) 2018-05-24 2021-01-22 京东方科技集团股份有限公司 一种tft基板的制备方法、tft基板及显示装置
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