WO2017152552A1 - 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 - Google Patents
薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 Download PDFInfo
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- WO2017152552A1 WO2017152552A1 PCT/CN2016/088071 CN2016088071W WO2017152552A1 WO 2017152552 A1 WO2017152552 A1 WO 2017152552A1 CN 2016088071 W CN2016088071 W CN 2016088071W WO 2017152552 A1 WO2017152552 A1 WO 2017152552A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 156
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 117
- 239000011241 protective layer Substances 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 25
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- 238000000576 coating method Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 30
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- 239000004065 semiconductor Substances 0.000 claims description 10
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- 239000000463 material Substances 0.000 description 10
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
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- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Definitions
- the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor, an array substrate, a display device, a method of manufacturing the thin film transistor, and a method of manufacturing the array substrate.
- TFT-LCDs thin-film transistor liquid crystal displays
- the prior art In the manufacture of the thin film transistor, in order to avoid corrosion of the active layer on the region corresponding to the channel when etching the source and drain metal between the source electrode and the drain electrode, the prior art often removes the active layer.
- the first photoresist layer retains the photoresist over the region corresponding to the channel; then, after forming the source/drain metal layer, the second photoresist layer is coated over the source/drain metal layer, and the source and drain metal are retained a photoresist over a region corresponding to the source/drain electrode and a photoresist over a region corresponding to the channel, so that the photoresist remaining over the active layer can protect the active layer when etching the source drain metal layer Not being etched; finally, simultaneously stripping the photoresist over the region corresponding to the source and drain electrodes of the source/drain metal layer, the photoresist in the second photoresist layer over the region corresponding to the channel, and corresponding to the channel
- An object of the present invention is to provide a thin film transistor and a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device for solving the stripping of a photoresist due to the presence of a source/drain metal layer when the photoresist remaining over the active layer is peeled off Incompletely affecting the characteristics of thin film transistors.
- Embodiments of the present invention provide a method of manufacturing a thin film transistor, including: forming a protective layer in a region between source and drain electrodes to be formed over an active layer; forming a source and drain over an active layer on which the protective layer is formed a metal layer; coating a photoresist on the source/drain metal layer, and forming a photoresist retention region and a photoresist non-retention region, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, the photoresist The non-retained area corresponds to the other areas; the source/drain metal layer corresponding to the photoresist non-retained area is etched away to form the source-drain electrodes, and the protective layer above the active layer is exposed; and the source-drain electrodes are removed a photoresist and the protective layer.
- the protective layer may be a positive photoresist or a negative photoresist.
- the thickness of the protective layer may be to
- the thickness of the protective layer may be any thickness of the protective layer.
- the method may further include forming an active layer, and forming the active layer may include: forming a semiconductor layer; coating a photoresist on the semiconductor layer, and forming a photoresist completely reserved region a photoresist partial retention region corresponding to a region between source and drain electrodes to be formed, and a photoresist non-retention region corresponding to the active layer a region of the source/drain electrode to be formed above, the photoresist non-retained region corresponding to a region other than the active layer region; etching a semiconductor layer corresponding to the photoresist non-retained region by an etching process; and adopting ashing The process removes the photoresist from the remaining portion of the photoresist.
- the method can also include forming an ohmic contact layer over the active layer.
- the method may further include sequentially forming a gate and a gate insulating layer before forming the active layer.
- Embodiments of the present invention also provide a thin film transistor fabricated according to the above method.
- the embodiment of the invention further provides a method for manufacturing an array substrate, comprising the method of any one of the above.
- the method may further include: sequentially forming a gate and a gate insulating layer. After removing the photoresist and the protective layer over the source and drain electrodes, the method may further include: forming a passivation layer on the source and drain electrodes, and A first conductive layer is formed on the passivation layer.
- a second conductive layer may be formed while forming the gate.
- Embodiments of the present invention also provide an array substrate prepared according to the above method.
- the embodiment of the invention further provides a display device comprising the above array substrate.
- a photoresist retention region and a photoresist non-retention region are formed when exposing the photoresist over the metal drain layer, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, and photolithography
- the glue non-retained area corresponds to the channel region and other regions between the source and drain electrodes to be formed, and then the metal above the channel region is simultaneously etched while etching the source and drain metal layers, exposing the remaining over the active layer.
- FIG. 1 is a process flow diagram in accordance with an embodiment of the present invention.
- FIG. 2 is a schematic view showing a process of fabricating a gate of a thin film transistor according to an embodiment of the present invention.
- 3 to 5 are schematic views showing a process of manufacturing an active layer of a thin film transistor according to an embodiment of the present invention.
- 6 to 9 are schematic views showing a process of manufacturing a source-drain electrode of a thin film transistor according to an embodiment of the present invention.
- FIG. 10 is a schematic structural view of an array substrate according to an embodiment of the invention.
- FIG. 11 is a schematic structural view of an array substrate according to an embodiment of the invention.
- FIG. 12 is a schematic structural view of an array substrate according to an embodiment of the invention.
- an embodiment of the present invention provides a method for manufacturing a thin film transistor.
- the method includes the following steps S1 to S3.
- Step S1 includes: forming a protective layer on a region between the source and drain electrodes to be formed over the active layer, forming a source/drain metal layer over the active layer on which the protective layer is formed, and coating a photoresist on the source/drain metal layer And forming a photoresist retention region and a photoresist non-retention region, wherein the photoresist retention region corresponds to a region of the source/drain electrode to be formed, and the photoresist non-retention region corresponds to other regions.
- Step S2 includes etching away a source/drain metal layer corresponding to the photoresist non-retained region to form a source/drain electrode, and exposing the protective layer above the active layer.
- Step S3 includes removing the photoresist and the protective layer over the source and drain electrodes.
- the protective layer may protect a region of the active layer corresponding to the channel when the source and drain electrodes are formed by etching, so as to prevent the region of the active layer corresponding to the channel from being corroded by the etching solution. Affects TFT characteristics. By first etching away the material of the region between the source and drain electrodes of the source and drain metal layers, exposing the protective layer above the active layer, and further removing the photoresist over the source and drain electrodes and the protective layer, The protective layer is removed more thoroughly, and the influence of the material of the residual protective layer on the characteristics of the TFT is avoided.
- the protective layer material may be a photoresist, so that a protective layer may be formed together when the active layer is formed, simplifying Process flow, simple operation and reduced cost.
- the protective layer may also be formed by other materials and processes, as long as it can protect the active layer, and details are not described herein.
- the protective layer material is used as a photoresist as an example for description.
- the photoresist described in the embodiments of the present invention may be a positive photoresist or a negative photoresist. After the positive photoresist is exposed, the illuminated area is soluble in the developer. After exposure to the negative photoresist, the illuminated area is insoluble in the developer.
- FIGS. 2 through 9 a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 2 through 9.
- the gate electrode 200 is formed on the base substrate 100.
- a gate metal layer is formed on the base substrate 100 by a sputtering process, which may be a single layer structure or a multilayer structure.
- the photoresist is then coated and the gate 200 is formed by processes such as exposure, development, etching, and the like.
- a gate insulating layer 300 is formed over the gate electrode 200, and an active layer 400 is formed over the gate insulating layer 300.
- a gate insulating layer 300 is formed over a gate 200 by a plasma enhanced chemical vapor deposition (PECVD) process or an atmospheric pressure chemical vapor deposition (CVD) process; and formed by a sputtering process over the gate insulating layer 300.
- PECVD plasma enhanced chemical vapor deposition
- CVD atmospheric pressure chemical vapor deposition
- a photoresist 500 is coated over the semiconductor layer 401, and the photoresist is exposed and developed to form a photoresist completely remaining region 501, a photoresist portion remaining region 502, and a photoresist.
- Area 503 is not reserved.
- the photoresist completely reserved region 501 corresponds to a region between the source and drain electrodes to be formed
- the photoresist portion reserved region 502 corresponds to a region above the active layer where a source/drain electrode is to be formed
- the photoresist non-reserved region 503 corresponds to An area outside the active layer area.
- the semiconductor layer corresponding to the photoresist non-retained region 503 is removed by an etching process, and then the photoresist of the photoresist portion remaining region 502 is removed by an ashing process or an ultraviolet irradiation and etching process to form an active layer. 400.
- the photoresist remaining in the photoresist completely remaining region 501 above the active layer 400 can serve as a protective layer of the active layer 400, so that the region corresponding to the channel of the active layer 400 forms a source leakage by etching. Extremely protected from the etching solution, as shown in Figure 5.
- the principle of the ashing process is: in a closed oxygen environment, at a certain temperature, oxygen is allowed to react with the photoresist, because the photoresist is an organic substance that easily reacts with oxygen to become water and carbon dioxide, so The thickness of the thinned photoresist is controlled by precisely controlling the time, temperature, and oxygen concentration.
- the ashing process plays a certain role in reducing the photoresist of the photoresist completely remaining region 501.
- the photoresist completely retains the thickness of the photoresist of the region 501, that is, the thickness of the protective layer is to
- the thickness of the protective layer is less than
- the protective layer is too thin to provide good protection, so that the etching solution causes a certain degree of corrosion to the region of the active layer corresponding to the channel.
- the thickness of the protective layer is greater than
- the process of removing the protective layer and related parameters such as time and temperature are required to be high, thereby increasing the process difficulty.
- the thickness of the protective layer is When the active layer is well protected, the process is more difficult.
- the manner of forming the active layer 400 and the protective layer is not limited to the above steps.
- the photoresist may be coated on the active layer 400 by exposure. And the development process, leaving only the photoresist on the active layer corresponding to the region between the source and drain electrodes.
- source and drain electrodes are formed over the active layer 400.
- the source/drain metal layer 600 is formed by magnetron sputtering, thermal evaporation, or other film forming process, and the source/drain metal layer 600 may be a single layer structure or a multilayer structure.
- a photoresist is coated over the source/drain metal layer 600, and a photoresist retention region 602 and a photoresist non-retention region 601 are formed by exposure and development.
- the photoresist retention region 602 corresponds to a region where source and drain electrodes are to be formed, and the photoresist non-retention region 601 corresponds to other regions.
- the source/drain metal layer corresponding to the photoresist non-retained region 601 is etched away, and the protective layer 501 above the active layer is exposed between the source and drain electrodes.
- the photoresist of the photoresist retention region 602 over the protective layer 501 and the source/drain metal layer 600 is simultaneously stripped to form a source 702 and a drain 701.
- a protective layer is formed on a region between the source and drain electrodes above the active layer, and the protective layer can protect the trench when forming the source and drain electrodes by etching.
- the active layer corresponding to the channel prevents the active layer from being corroded by the etching solution and affects the characteristics of the TFT.
- the source and drain metal layer materials in the region between the source and drain electrodes are etched first, the protective layer above the active layer is exposed, and the photoresist over the source and drain electrodes and the protection are When the layers are removed together, the protective layer can be removed more thoroughly, and the influence of the residual protective layer material on the TFT characteristics is avoided.
- Embodiments of the present invention also provide a thin film transistor according to the above thin film crystal
- the manufacturing method of the tube is manufactured. It can be understood that the thin film transistor also has the above technical effects.
- Embodiments of the present invention also provide a method of fabricating an array substrate, including the foregoing method of fabricating a thin film transistor, and further comprising: forming a passivation layer over the source and drain electrodes; and forming a first conductive layer over the passivation layer.
- a plasma-enhanced chemical vapor deposition (PECVD) process or an atmospheric pressure chemical vapor deposition (CVD) process, magnetron sputtering, thermal evaporation, or other film formation process is used to form a blunt over the source and drain electrodes.
- the material of the passivation layer 800 may include an oxide, a nitride or an oxynitride such as SiNx, SiOx or Si(ON)x.
- the passivation layer 800 may have a single layer structure or a two-layer structure composed of silicon nitride and silicon oxide.
- the passivation layer 800 is patterned, a passivation layer via is formed over the drain electrode 701, and a transparent conductive layer is deposited over the passivation layer 800 by magnetron sputtering, thermal evaporation or other film forming process.
- the transparent conductive layer may include ITO or IZO, and the transparent conductive layer is patterned by a patterning process.
- the transparent conductive layer is formed as a pixel electrode 900 after the patterning process, and the pixel electrode 900 is electrically connected to the drain electrode 701 through the passivation layer via.
- a protective layer is formed on a region between the source and drain electrodes above the active layer, and the protective layer can be protected and channeled when etching the source and drain electrodes.
- Corresponding active layer prevents the active layer from being corroded by the etching solution and affects the characteristics of the TFT.
- the source and drain metal layer materials in the region between the source and drain electrodes are etched first, the protective layer above the active layer is exposed, and the photoresist over the source and drain electrodes and the protection are When the layers are removed together, the protective layer can be removed more thoroughly, and the influence of the residual protective layer material on the TFT characteristics is avoided.
- the embodiment of the invention further provides an array substrate which is manufactured according to the manufacturing method of the above array substrate. It can be understood that the array substrate also has the above technical effects.
- the embodiment of the present invention further provides a method for manufacturing a thin film transistor, which is different from the method for manufacturing a thin film transistor of the foregoing embodiment in that after the active layer 400 and the protective layer 501 are formed, PECVD or the like is passed thereon.
- Process deposition The N+a-Si layer is removed and the corresponding portion is removed when etching the source/drain metal layer in a subsequent process to form the ohmic contact layer 901, as shown in FIG.
- the formation methods of the other film layers are the same as those in the foregoing embodiment, and are not described herein again.
- the embodiment of the present invention further provides a method for manufacturing an array substrate, which is different from the method for manufacturing an array substrate of the foregoing embodiment in that magnetron sputtering, thermal evaporation, or magnetization is used before the gate insulating layer 300 is formed.
- Other film forming processes deposit a transparent conductive layer 201 on the base substrate 100 as shown in FIG.
- the transparent conductive layer 201 may include ITO or IZO, and the transparent conductive layer may be a common electrode.
- the transparent conductive layer 201 and the gate electrode 200 may be formed in the same patterning process.
- the other manufacturing processes in this embodiment are the same as those in the foregoing embodiments, and are not described herein again.
- the embodiment of the invention further provides a display device, which comprises the array substrate in the above embodiment.
- the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
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Abstract
Description
Claims (13)
- 一种制造薄膜晶体管的方法,包括:在有源层上方待形成的源漏电极之间的区域形成保护层;在形成有所述保护层的有源层上方形成源漏金属层;在所述源漏金属层上涂覆光刻胶,以及形成光刻胶保留区域和光刻胶不保留区域,其中所述光刻胶保留区域对应于待形成的源漏电极的区域,所述光刻胶不保留区域对应于其他区域;刻蚀掉与所述光刻胶不保留区域对应的源漏金属层,以形成源漏电极,并且露出所述有源层上方的所述保护层;以及去除所述源漏电极上方的光刻胶和所述保护层。
- 如权利要求1所述的方法,其中,所述保护层为正性光刻胶或负性光刻胶。
- 如权利要求1至4中任一项所述的方法,其中,在形成所述保护层之前,所述方法还包括形成有源层,形成有源层包括:形成半导体层;在所述半导体层上涂覆光刻胶,以及形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域,其中所述光刻胶完全保留区域对应于待形成的源漏电极之间的区域,所述光刻胶部分保留区域对应于所述有源层上方待形成的源漏电极的区域,所述光刻胶不保留区域对应于有源层区域以外的区域;采用刻蚀工艺刻蚀与光刻胶不保留区域对应的半导体层;以 及采用灰化工艺去除所述光刻胶部分保留区域的光刻胶。
- 如权利要求5所述的方法,还包括:在所述有源层上方形成欧姆接触层。
- 如权利要求5或6所述的方法,还包括:在形成所述有源层之前依次形成栅极和栅绝缘层。
- 一种薄膜晶体管,所述薄膜晶体管根据权利要求1至7中任意一项所述的方法制造。
- 一种制造阵列基板的方法,包括如权利要求1至6中任一项所述的方法。
- 如权利要求9所述的方法,其中,在形成所述有源层之前,所述方法还包括:依次形成栅极和栅绝缘层,并且在去除所述源漏电极上方的光刻胶和所述保护层之后,所述方法还包括:在所述源漏电极上形成钝化层,以及在所述钝化层上形成第一导电层。
- 如权利要求10所述的方法,其中,在形成所述栅极的同时形成第二导电层。
- 一种阵列基板,所述阵列基板根据权利要求9至11中任一项所述的方法制备。
- 一种显示装置,包括如权利要求12所述的阵列基板。
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CN107093582A (zh) * | 2017-04-28 | 2017-08-25 | 京东方科技集团股份有限公司 | 显示面板的制造方法和显示面板 |
CN107706116A (zh) * | 2017-09-15 | 2018-02-16 | 惠科股份有限公司 | 主动阵列开关的制造方法 |
CN108666325B (zh) | 2018-05-24 | 2021-01-22 | 京东方科技集团股份有限公司 | 一种tft基板的制备方法、tft基板及显示装置 |
CN112897454B (zh) * | 2021-01-20 | 2024-02-23 | 杭州士兰集成电路有限公司 | Mems器件及其制造方法 |
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CN102646632A (zh) * | 2012-03-08 | 2012-08-22 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法和显示装置 |
CN102779784A (zh) * | 2012-06-15 | 2012-11-14 | 上海大学 | 薄膜晶体管阵列基板制造方法 |
CN103441100A (zh) * | 2013-08-22 | 2013-12-11 | 合肥京东方光电科技有限公司 | 显示基板及其制造方法、显示装置 |
US9024318B2 (en) * | 2011-12-22 | 2015-05-05 | Innocom Technology (Shenzhen) Co., Ltd. | Thin film transistor substrate manufacturing method thereof, display |
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TWI471948B (zh) * | 2012-10-18 | 2015-02-01 | Chunghwa Picture Tubes Ltd | 氧化物薄膜電晶體製程方法 |
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CN104319278A (zh) * | 2014-10-22 | 2015-01-28 | 京东方科技集团股份有限公司 | 阵列基板、显示面板和阵列基板的制作方法 |
CN105161541A (zh) * | 2015-08-04 | 2015-12-16 | 京东方科技集团股份有限公司 | 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 |
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CN102646632A (zh) * | 2012-03-08 | 2012-08-22 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法和显示装置 |
CN102779784A (zh) * | 2012-06-15 | 2012-11-14 | 上海大学 | 薄膜晶体管阵列基板制造方法 |
CN103441100A (zh) * | 2013-08-22 | 2013-12-11 | 合肥京东方光电科技有限公司 | 显示基板及其制造方法、显示装置 |
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