CN107706116A - 主动阵列开关的制造方法 - Google Patents
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Abstract
本发明提供了一种主动阵列开关的制造方法,主动阵列开关的制造方法,包括:于一基板上形成一栅极图形后形成一栅极绝缘层覆盖栅极图形;于栅极绝缘层上形成一半导体层并于其上形成一具有多个厚度的第一光阻层,其中栅极图形中间上方的第一光阻层的厚度大于栅极图形两侧上方的第一光阻层的厚度;移除部份半导体层,以形成一半导体图形;对第一光阻层进行干式蚀刻制程,使只有栅极图形中间上方留下来的第一光阻层仍覆盖部分所述半导体图形;于半导体图形和栅极绝缘层上形成一源极和一漏极;以及移除源极、漏极与栅极图形中间上方的全部光阻层。
Description
技术领域
本发明涉及一种主动阵列开关的制造方法,特别是涉及一种能有效保护半导体层不受源漏极蚀刻液体影响的主动阵列开关的制造方法。
背景技术
驱动显示面板的主动阵列开关半导体层目前主要有非晶硅(a-Si),氧化物(Oxide)和多晶硅(Poly-Si)等。相对于非晶硅,氧化物半导体具有较高的迁移率,较低的漏电;虽多晶硅主动阵列开关迁移率更高,但其成本较高且不合适于目前主流产品的生产线。
氧化物半导体主动阵列开关常用的结构有ESL(蚀刻阻挡),BCE(背沟道蚀刻),Co-planner Self-Align Top Gate(共平面顶栅自对准型)以及Dual Gate(双栅机)等结构。虽然ESL(蚀刻阻挡)结构制程相对容易,但其需要进行多次黄光制程,因此BCE(背沟道蚀刻)结构成为可进行大规模低成本量产的较佳选择。
然而BCE(背沟道蚀刻)结构的主动阵列开关制程中,难点之一是源漏极电极蚀刻液体会对氧化物半导体层造成不可恢复的损伤,影响主动阵列开关电性能,甚至直接导致主动阵列开关无半导体特性。
发明内容
为了解决上述技术问题,本发明的目的在于提供一种主动阵列开关的制造方法,特别是涉及一种能有效保护半导体层不受源漏极蚀刻液体影响的主动阵列开关的制造方法。
近年来,由于半导体制程技术的进步,主动阵列开关的制造越趋容易、快速。主动阵列开关广泛应用于诸如计算机芯片、手机芯片或是主动阵列开关液晶显示器(thin filmtransistor liquid crystal displayer,TFT LCD)等电子产品中。以主动阵列开关液晶显示器为例,主动阵列开关作为储存电容(storage capacitor)充电或放电的开关。
一般而言,主动阵列开关依照半导体层的材料可分为非晶硅主动阵列开关(Amorphous Silicon Transistor)以及多晶硅主动阵列开关(Low TemperaturePolycrystalline Transistor)。同时,为了因应市场对于液晶显示器的需求增加,新的主动阵列开关技术研发也有更多的投入。其中,已研发出一种以诸如氧化锌(ZnO)等的金属氧化物为半导体层的主动阵列开关,其电性特性已追上非晶硅主动阵列开关,且在组件的表现上也已经有相当不错的成果。然而,以氧化锌作为半导体层的主动阵列开关为例,在后续形成源极与漏极的制程中,氧化锌容易受到诸如电浆、蚀刻液以及去光阻液等物质的损害,而改变半导体层的薄膜性质,进而影响主动阵列开关的组件特性。
因此本发明提供了一种主动阵列开关的制造方法,包括:于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;于所述栅极绝缘层上形成一半导体层;于所述半导体层上形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;移除部份所述半导体层,以形成一半导体图形;对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,并使位于所述栅极图形上方的所述第一光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形;于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;将所述第二光阻层图案化成一源极图形与一漏极图形;图案化所述第二金属层,以形成一源极和一漏极;以及移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
在本发明的一实施例中,形成所述具有多个厚度的第一光阻层的步骤包括:于所述半导体层上形成一感光材料层,使用一半色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
在本发明的一实施例中,形成所述具有多个厚度的第一光阻层的步骤包括:于所述半导体层上形成一感光材料层,使用灰色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
在本发明的一实施例中,所述半导体层为金属氧化物半导体层,所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在本发明的一实施例中,所述金属氧化物半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
在本发明的一实施例中,于所述半导体层与所述第一光阻层之间形成一绝缘材料层。
在本发明的上述实施例中,所述绝缘材料层为无机绝缘材料层,如氧化硅或氮化硅。
在本发明的上述实施例中,所述绝缘材料层为有机绝缘材料层,如聚甲基丙烯酸甲酯或聚乙烯酚。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。本发明提供了一种主动阵列开关的制造方法,其特征在于,包括:于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;于所述栅极绝缘层上形成一半导体层;于所述半导体层上形成一形成一绝缘材料层;于所述绝缘材料层上形成一感光材料层;使用一光罩对所述感光材料层进行一曝光制程;进行一显影制程形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;移除部份所述半导体层,以形成一半导体图形;对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形;于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;将所述第二光阻层图案化成一源极图形与一漏极图形;图案化所述第二金属层,以形成一源极和一漏极。
移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
经过本发明的改进之后,可于主动阵列开关的BCE制程中,保留栅极图形上方(TFT背沟道处)半导体层上的第一光阻层,再进行正常源漏极的成膜蚀刻制程,在源漏极移除第二光阻层之同时溶解栅极图形上方的第一光阻层。此方法能有效保护TFT背沟道的半导体图形不受源漏极蚀刻液体的影响,以得到稳定的主动阵列开关电性能。
附图说明
图1A是本发明实施例所述半导体的成膜示意图。
图1B是本发明实施例所述的形成第一光阻层示意图。
图1C是本发明实施例所述的形成半导体图形示意图。
图1D是本发明实施例所述进行干式蚀刻制程示意图。
图1E是本发明实施例所述形成第二金属层及第二光阻层示意图。
图1F是本发明实施例所述移除全部光阻层示意图。
图1G是本发明一实施例所述主动阵列开关的制造方法流程图。
图2是本发明包括绝缘材料层的另一实施例示意图。
图3是本发明另一实施例所述主动阵列开关的制造方法流程图。
具体实施方式
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。
附图和说明被认为在本质上是示出性的,而不是限制性的。在图中,结构相似的单元是以相同标号表示。另外,为了理解和便于描述,附图中示出的每个组件的尺寸和厚度是任意示出的,但是本发明不限于此。
在附图中,为了清晰起见,夸大了层、膜、面板、区域等的厚度。在附图中,为了理解和便于描述,夸大了一些层和区域的厚度。将理解的是,当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时,所述组件可以直接在所述另一组件上,或者也可以存在中间组件。
另外,在说明书中,除非明确地描述为相反的,否则词语“包括”将被理解为意指包括所述组件,但是不排除任何其它组件。此外,在说明书中,“在......上”意指位于目标组件上方或者下方,而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的一种主动阵列开关的制造方法,其具体实施方式、结构、特征及其功效,详细说明如后。
本发明是提供一种主动阵列开关的制造方法,使半导体层上覆盖有第一光阻层,以保护半导体层形成的半导体图形。本发明提出一种主动阵列开关的制造方法,其包括下列步骤。敬请参阅图1A至图1G,本发明提供的一种主动阵列开关1的制造方法首先如图1A所示,于一基板10上形成一第一金属层,并图案化所述第一金属层成多个栅极图形11,再于所述基板10上形成一栅极绝缘层12,以覆盖所述栅极图形11,然后于所述栅极绝缘层12上形成一半导体层13。
在一实施例中,所述半导体层13为金属氧化物半导体层,所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在上述实施例中,所述金属氧化物半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
接下来如图1B所示,于所述半导体层13上形成一具有多个厚度的第一光阻层14,其中,位于所述栅极图形11中间上方的所述第一光阻层14的厚度大于位于所述栅极图形11两侧上方的所述第一光阻层14的厚度。
在一实施例中,形成所述具有多个厚度的第一光阻层14的步骤包括:于所述半导体层13上形成一感光材料层,使用一半色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
在一实施例中,形成所述具有多个厚度的第一光阻层14的步骤包括:于所述半导体层13上形成一感光材料层,使用灰色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
接下来如图1C所示,移除部份所述半导体层13,以形成一半导体图形13'。
接下来如图1D所示,对所述第一光阻层14进行干式蚀刻制程(如电浆蚀刻),移除位于所述栅极图形11两侧上方的所述第一光阻层14的厚度,并使位于所述栅极图形11中间上方的所述第一光阻层14干式蚀刻后留下来的剩余厚度(第一光阻层14')仍覆盖部分所述半导体图形13'。
接下来如图1E所示,于所述半导体图形13'和所述栅极绝缘层12上依序形成一第二金属层15及一第二光阻层16,并将所述第二光阻层16图案化成一源极图形与一漏极图形。
最后如图1F所示,图案化所述第二金属层15,以成一源极17和一漏极18,并移除所述源极17与所述漏极18上方全部的所述第二光阻层16,且同时移除所述栅极图形11中间上方的全部所述第一光阻层14'。
亦即,本发明提供一种主动阵列开关的制造方法S1,其包括下列步骤:
步骤S101:于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;
步骤S102:于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;
步骤S103:于所述栅极绝缘层上形成一半导体层;
步骤S104:于所述半导体层上形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;
步骤S105:移除部份所述半导体层,以形成一半导体图形;
步骤S106:对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,并使位于所述栅极图形上方的所述第一光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形;
步骤S107:于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;
步骤S108:将所述第二光阻层图案化成一源极图形与一漏极图形;
步骤S109:图案化所述第二金属层,以形成一源极和一漏极;以及
步骤S110:移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
其制造方法大致如图1A至图1F,惟于所述半导体层13与所述第一光阻层14之间形成一绝缘材料层19。
亦即,如图1A所示,于一基板10上形成一第一金属层,并图案化所述第一金属层成一栅极图形11,再于所述基板10上形成一栅极绝缘层12,以覆盖所述栅极图形11,然后于所述栅极绝缘层12上形成一半导体层13。
然后在半导体层13上先形成一绝缘材料层19(如图2所示),用以保护本发明所使用的金属材质半导体层,其中所述绝缘材料层为无机绝缘材料层,如氧化硅或氮化硅;或可为有机绝缘材料层,如聚甲基丙烯酸甲酯或聚乙烯酚。
接下来则如图1B所示,于所述半导体层13上形成一具有多个厚度的第一光阻层14,其中所述栅极图形11中间上方的所述第一光阻层14的厚度大于所述栅极图形11两侧上方的所述第一光阻层14的厚度。
再如图1C所示移除部份所述半导体层13,以形成一半导体图形13'。
续如图1D、图1E以及图1F所示,对所述第一光阻层14进行干式蚀刻制程(如电浆蚀刻),移除位于所述栅极图形11两侧上方的所述第一光阻层14的厚度,并使位于所述栅极图形11中间上方的所述第一光阻层14干式蚀刻后留下来的剩余厚度(第一光阻层14')仍覆盖部分所述半导体图形13';于所述半导体图形13'和所述栅极绝缘层12上依序形成一第二金属层15及一第二光阻层16,并将所述第二光阻层16图案化成一源极图形与一漏极图形;最后图案化所述第二金属层15以形成一源极17和一漏极18,并移除所述源极17与所述漏极18上方全部的所述第二光阻层16,且同时移除所述栅极图形11中间上方的全部所述第一光阻层14'。
最后形成如图2的结构,亦即于基板10上形成有一栅极图形11,所述基板10与所述栅极图形11上形成有一栅极绝缘层12以覆盖所述栅极图形11,而在栅极图形11的中间上方因光阻层的罩幕效果保留形成一半导体图形13',并于所述半导体图形13'上覆盖有一以有机或无机材料形成的绝缘材料层19,而在栅极图形11两侧上方则是为以第二金属层形成的源极17与漏极18。
同时,本发明的目的及解决其技术问题还可采用如图3的流程技术措施进一步实现。本发明提供了一种主动阵列开关的制造方法S2,其特征在于,包括:
步骤S201:于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;
步骤S202:于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;
步骤S203:于所述栅极绝缘层上形成一半导体层;
步骤S204:于所述半导体层上形成一形成一绝缘材料层;
步骤S205:于所述绝缘材料层上形成一感光材料层;
步骤S206:使用一光罩对所述感光材料层进行一曝光制程;
步骤S207:进行一显影制程形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;
步骤S208:移除部份所述半导体层,以形成一半导体图形;
步骤S209:对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形;
步骤S210:于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;
步骤S211:将所述第二光阻层图案化成一源极图形与一漏极图形;
步骤S212:图案化所述第二金属层,以形成一源极和一漏极;以及
步骤S213:移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
经过本发明的改进之后,可于主动阵列开关1的BCE制程中,保留栅极图形11上方(TFT背沟道处)半导体层13上的第一光阻层14,再进行正常源漏极的成膜蚀刻制程,在源漏极移除第二光阻层16的同时溶解栅极图形11上方的第一光阻层14'。此方法能有效保护TFT背沟道的半导体图形13'不受源漏极蚀刻液体的影响,以得到稳定的主动阵列开关1电性能。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例;但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词,除非其前后文意显示出其它意思。
以上所述,仅是本发明的实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以具体实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (10)
1.一种主动阵列开关的制造方法,其特征在于,包括:
于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;
于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;
于所述栅极绝缘层上形成一半导体层;
于所述半导体层上形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形中间上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;
移除部份所述半导体层,以形成一半导体图形;
对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形;
于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;
将所述第二光阻层图案化成一源极图形与一漏极图形;
图案化所述第二金属层,以形成一源极和一漏极;以及
移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
2.如权利要求1所述的主动阵列开关的制造方法,其特征在于,形成所述具有多个厚度的第一光阻层的步骤包括:于所述半导体层上形成一感光材料层,使用一半色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
3.如权利要求1所述的主动阵列开关的制造方法,其特征在于,形成所述具有多个厚度的第一光阻层的步骤包括:于所述半导体层上形成一感光材料层,使用灰色调式光罩对所述感光材料层进行一曝光制程,以及进行一显影制程。
4.如权利要求1所述的主动阵列开关的制造方法,其特征在于,所述半导体层为金属氧化物半导体层。
5.如权利要求4所述的主动阵列开关的制造方法,其特征在于,所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
6.如权利要求5所述的主动阵列开关的制造方法,其特征在于,所述金属氧化物半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
7.如权利要求1所述的主动阵列开关的制造方法,其特征在于,于所述半导体层与所述第一光阻层之间形成一绝缘材料层。
8.如权利要求7所述的主动阵列开关的制造方法,其特征在于,所述绝缘材料层为无机绝缘材料层。
9.如权利要求7所述的主动阵列开关的制造方法,其特征在于,所述绝缘材料层为有机绝缘材料层。
10.一种主动阵列开关的制造方法,其特征在于,包括:
于一基板上形成一第一金属层,并图案化所述第一金属层成一栅极图形;
于所述基板上形成一栅极绝缘层,以覆盖所述栅极图形;
于所述栅极绝缘层上形成一半导体层;
于所述半导体层上形成一形成一绝缘材料层;
于所述绝缘材料层上形成一感光材料层;
使用一光罩对所述感光材料层进行一曝光制程;
进行一显影制程形成一具有多个厚度的第一光阻层,其中,位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度;
移除部份所述半导体层,以形成一半导体图形;
对所述第一光阻层进行干式蚀刻制程,移除位于所述栅极图形两侧上方的所述第一光阻层的厚度,留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形;
于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层;
将所述第二光阻层图案化成一源极图形与一漏极图形;
图案化所述第二金属层,以形成一源极和一漏极;以及
移除所述源极与所述漏极上方全部的所述第二光阻层,且同时移除所述栅极图形上方的全部所述第一光阻层。
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WO2020000630A1 (zh) * | 2018-06-25 | 2020-01-02 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及其制作方法、显示面板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7470571B2 (en) * | 2004-07-27 | 2008-12-30 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor array substrate and method of producing the same |
CN102646633A (zh) * | 2011-11-28 | 2012-08-22 | 友达光电股份有限公司 | 阵列基板及其制作方法 |
CN103928405A (zh) * | 2014-03-28 | 2014-07-16 | 深圳市华星光电技术有限公司 | 一种tft阵列基板的制造方法 |
CN105742186A (zh) * | 2016-03-09 | 2016-07-06 | 京东方科技集团股份有限公司 | 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101562152B (zh) * | 2009-05-21 | 2011-11-30 | 深圳华映显示科技有限公司 | 主动元件阵列基板的制造方法 |
CN102496617A (zh) * | 2011-10-06 | 2012-06-13 | 友达光电股份有限公司 | 主动元件阵列基板及其制造方法 |
TWI463534B (zh) * | 2012-02-10 | 2014-12-01 | E Ink Holdings Inc | ㄧ種主動陣列基板的製造方法 |
KR102161585B1 (ko) * | 2013-12-27 | 2020-10-05 | 엘지디스플레이 주식회사 | 어레이 기판의 제조방법 |
CN105140177A (zh) * | 2015-07-22 | 2015-12-09 | 京东方科技集团股份有限公司 | 阵列基板的制备方法,阵列基板、显示面板、显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7470571B2 (en) * | 2004-07-27 | 2008-12-30 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor array substrate and method of producing the same |
CN102646633A (zh) * | 2011-11-28 | 2012-08-22 | 友达光电股份有限公司 | 阵列基板及其制作方法 |
CN103928405A (zh) * | 2014-03-28 | 2014-07-16 | 深圳市华星光电技术有限公司 | 一种tft阵列基板的制造方法 |
CN105742186A (zh) * | 2016-03-09 | 2016-07-06 | 京东方科技集团股份有限公司 | 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020000630A1 (zh) * | 2018-06-25 | 2020-01-02 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及其制作方法、显示面板 |
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