CN108231795B - 阵列基板、制作方法、显示面板及显示装置 - Google Patents

阵列基板、制作方法、显示面板及显示装置 Download PDF

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CN108231795B
CN108231795B CN201810003159.7A CN201810003159A CN108231795B CN 108231795 B CN108231795 B CN 108231795B CN 201810003159 A CN201810003159 A CN 201810003159A CN 108231795 B CN108231795 B CN 108231795B
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layer
source
insulating layer
active layer
thin film
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CN108231795A (zh
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杨维
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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Abstract

本发明公开了一种阵列基板，包括两种薄膜晶体管，具体包括形成在衬底上的第一有源层；覆盖所述第一有源层上的第一栅绝缘层；形成在所述第一栅绝缘层上同层设置的第一栅极和第二栅极；覆盖所述第一栅极和第二栅极的第二栅绝缘层；形成在所述第二删绝缘层上的第二有源层和第二源漏极，所述第二源漏极与所述第二有源层电连接；覆盖所述第二有源层和第二源漏极的层间绝缘层；形成在所述层间绝缘层上的第一源漏极，所述第一源漏极与所述第一有源层电连接。本实施例提供的阵列基板、制作方法和显示装置能减少制备两种薄膜晶体管过程中的掩模数量，并解决工艺不兼容的问题。

Description

阵列基板、制作方法、显示面板及显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板、制作方法、显示面板及显示装置。
背景技术
近年来，低温多晶硅薄膜晶体管(LTPS TFT)和氧化物薄膜晶体管(Oxide TFT)在显示行业备受关注，各具优势，不分伯仲。LTPS TFT具有迁移率高，充电快的优势，OxideTFT具有漏电流低的优势。如果能将这两种材料的优势结合在一起，显示产品的用户体验将有大步提升。但是，由于需要把LTPS和Oxide这两种工艺结合到一起，工艺制程就会不可避免的变得复杂，即需要使用较多的Mask工艺。为了降低生产成本，需要减少LTPS+Oxide TFT结构中的Mask数量，但由于LTPS TFT和Oxide TFT工艺制程可能存在工艺不兼容性等问题，使得减少Mask数量变得非常困难。
发明内容
为了解决上述问题至少之一，本发明第一方面提供一种阵列基板，包括：
一种阵列基板，包括两种薄膜晶体管，具体包括
形成在衬底上的第一有源层；
覆盖所述第一有源层上的第一栅绝缘层；
形成在所述第一栅绝缘层上同层设置的第一栅极和第二栅极；
覆盖所述第一栅极和第二栅极的第二栅绝缘层；
形成在所述第二删绝缘层上的第二有源层和第二源漏极，所述第二源漏极与所述第二有源层电连接；
覆盖所述第二有源层和第二源漏极的层间绝缘层；
形成在所述层间绝缘层上的第一源漏极，所述第一源漏极与所述第一有源层电连接。
进一步地，所述第一有源层、第一栅极和第一源漏极构成低温多晶硅薄膜晶体管；所述第二有源层、第二栅极和第二源漏极构成氧化物薄膜晶体管。
进一步地，还包括形成在所述第一栅绝缘层上的第一金属层，所述第一金属层与所述第一栅极同层设置；以及
形成在所述第二栅绝缘层上的与所述第一金属层位置相对应的第二金属层，所述第二金属层与所述第二源漏极同层设置。
进一步地，还包括形成在所述第二栅绝缘层上的与所述第一栅极位置相对应的第三金属层，所述第三金属层与所述第二源漏极同层设置。
进一步地，所述层间绝缘层上还包括与所述第一源漏极同层设置的辅助金属，该辅助金属与所述第二源漏极电连接。
本发明第二方面提供一种阵列基板的制作方法，包括：
S101：在衬底上形成第一有源层；
S103：在所述第一有源层上形成第一栅绝缘层；
S105：在所述第一栅绝缘层上同时形成第一栅极和第二栅极；
S107：形成覆盖所述第一栅极和第二栅极的第二栅绝缘层；
S109：在所述第二栅绝缘层上形成第二有源层；
S111：在所述第二栅绝缘层上形成第二源漏极，所述第二源漏极与所述第二有源层电连接；
S113：形成覆盖所述第二栅绝缘层、第二有源层和第二源漏极的层间绝缘层；
S115：在所述层间绝缘层上形成第一源漏极，所述第一源漏极与所述第一有源层电连接
进一步地，在步骤S105中，在形成所述第一栅极的同时形成第一金属层；并且在步骤S111中，在形成所述第二源漏极的同时形成第二金属层。
进一步地，在步骤S115中，在形成所述第一源漏极的同时形成辅助金属，所述辅助与所述第二源漏极电连接。
本发明第三方面提供一种显示面板，包括：
第一方面所述的阵列基板、液晶和彩膜基板；
或者：
第一方面所述的阵列基板和背板。
本发明第四方面提供一种显示装置，包括第三方面所述的显示面板。
本发明的有益效果如下：
在本发明的阵列基板中，通过调整LTPS+Oxide TFT的结构，既有效地减少了LTPS+Oxide TFT结构中的Mask数量，又解决了LTPS TFT和Oxide TFT工艺制程中的工艺不兼容性问题。
附图说明
下面结合附图对本发明的具体实施方式作进一步详细的说明。
图1示出现有LTPS+Oxide TFT结构的截面图；
图2示出现有另一个LTPS+Oxide TFT结构的截面图；
图3示出本发明的一个实施例的阵列基板制备的流程图；
图4-11示出本发明的一个实施例的阵列基板制备流程中各阶段对应的截面图；
图12示出本发明的另一个实施例的阵列基板的截面图；
图13示出本发明的另一个实施例的阵列基板的截面图。
具体实施方式
为了更清楚地说明本发明，下面结合优选实施例和附图对本发明做进一步的说明。附图中相似的部件以相同的附图标记进行表示。本领域技术人员应当理解，下面所具体描述的内容是说明性的而非限制性的，不应以此限制本发明的保护范围。
目前将低温多晶硅薄膜晶体管和氧化物薄膜晶体管结构结合在一起的现有工艺制程是在LTPS TFT制作的基础上，增加4道Oxide TFT掩模(Mask)工艺，以形成LTPS+OxideTFT结构，即氧化物薄膜晶体管栅绝缘层掩模、有源层掩模、源漏极掩模和钝化层掩模。
如图1所示，左侧为低温多晶硅薄膜晶体管的结构(LTPS TFT)，右侧为氧化物薄膜晶体管(oxide TFT)的结构，需要说明的是，本附图为示意图，用于表示薄膜晶体管的层结构关系，图中所示的波浪线仅用于区分两种薄膜晶体管，而非本发明保护内容，如下示意图均以此表示，不再赘述。在衬底10上依次设置低温多晶硅薄膜晶体管的有源层11、栅绝缘层20、栅极12和层间绝缘层40；在层间绝缘层上设置低温多晶硅薄膜晶体管的源漏极13和14的同时，同层设置氧化物薄膜晶体管的栅极22，即利用一道掩模工艺制备低温多晶硅薄膜晶体管的源漏极和氧化物薄膜晶体管的栅极；然后再依次设置氧化物薄膜晶体管的栅绝缘层30、有源层21、源漏极23和24，和钝化层50，共增加4道掩模工艺。
为了进一步减少LTPS+Oxide TFT结构的工艺制程，目前，在LTPS TFT的基础上对Oxide TFT结构进行了调整，只需要增加2道Oxide TFT Mask就能形成LTPS+Oxide TFT结构，即增加氧化物薄膜晶体管有源层掩模和钝化层掩模，也就是将氧化物薄膜晶体管的栅绝缘层与低温多晶硅薄膜晶体管的层间绝缘层共用，氧化物薄膜晶体管的源漏极与低温多晶硅薄膜晶体管源漏极共用。
具体地，如图2所示，左侧为低温多晶硅薄膜晶体管的结构，右侧为氧化物薄膜晶体管的结构。在衬底10上设置低温多晶硅薄膜晶体管的有源层11，在衬底10和低温多晶硅薄膜晶体管的有源层11上设置栅绝缘层20。在栅绝缘层20上使用一道掩模工艺同层设置低温多晶硅薄膜晶体管的栅极12和氧化物薄膜晶体管的栅极22，即两种薄膜晶体管的栅极利用一道掩模；在栅绝缘层20和栅极上设置层间绝缘层30，在层间绝缘层30上设置氧化物薄膜晶体管的有源层21，通过一道掩模工艺同层设置低温多晶硅薄膜晶体管的源漏极13和14，和氧化物薄膜晶体管的源漏极23和24，即两种薄膜晶体管的源漏极利用一道掩模；最后在源漏极上设置钝化层50以完成LTPS+Oxide TFT的制备。
这种结构虽然减少了两道掩模工艺，但在制备过程中存在工艺不兼容的问题，即：在制备低温多晶硅薄膜晶体管的源漏极前需要进行氢氟酸清洗去除低温多晶硅薄膜晶体管有源层11表面的氧化层，以确保低温多晶硅薄膜晶体管的有源层11与源漏极金属13和14形成良好的欧姆接触；然而氢氟酸清洗会将之前形成的氧化物薄膜晶体管的有源层21图案完全刻蚀掉，导致氧化物薄膜晶体管特性异常。
为了解决上述问题，同时进一步减少掩模的使用次数，如图3所示，本发明的一个实施例提供了一种阵列基板的制作方法，包括：
S101：在衬底10上形成第一有源层11。
如图4所示，本发明的阵列基板的衬底可以为玻璃或聚酰亚胺，本实施例以玻璃衬底进行说明。
在一个优选的实施例中，可以在玻璃衬底10上设置缓冲层，用于防止衬底内的物质在后续工艺中例如半导体层晶化过程中扩散到衬底基板上的各膜层结构中，影响阵列基板的品质。
在衬底10上沉积一层a-si，经过准分子激光退火(ELA)工艺形成p-si，并利用掩模形成第一有源层11，即低温多晶硅薄膜晶体管的有源层。由于用于形成多晶半导体层的退火处理可能会损坏氧化物的半导体层，因此需要在设置氧化物薄膜晶体管的有源层的金属氧化物之前完成制造低温多晶硅薄膜晶体管的有源层的退火处理。
S103：在所述第一有源层11上形成第一栅绝缘层20。
如图5所示，在低温多晶硅薄膜晶体管的有源层11上覆盖第一栅绝缘层20，作为低温多晶硅薄膜晶体管的栅绝缘层。同时第一栅绝缘层20还可以作为氧化物薄膜晶体管的栅极下方的额外缓冲层。
S105：在所述第一栅绝缘层20上同时形成第一栅极12和第二栅极22。
如图6所示，在第一栅绝缘层20上沉积栅金属层，利用掩模形成第一栅极12和第二栅极22，分别对应低温多晶硅薄膜晶体管的栅极和氧化物薄膜晶体管的栅极，即两种薄膜晶体管同层设置栅极以减少LTPS+Oxide TFT制备过程中的掩模数量。
在一个优选的实施例中，如图12所示，利用该掩模在形成所述第一栅极12的同时还形成第一金属层31，所述第一金属层31为所述阵列基板的存储电容的第一金属电极板，该存储电容在OLED像素电路中用于补偿驱动薄膜晶体管的阈值电压，该结构可以充分利用已有掩模工艺，降低制作成本。
S107：形成覆盖所述第一栅极12和第二栅极22上的第二栅绝缘层30。
如图7所示，通过在第一栅极12和第二栅极22上覆盖第二栅绝缘层30作为氧化物薄膜晶体管的栅绝缘层。虽然绝缘层的特定功能在薄膜晶体管中可能有所不同，但是在背板上形成氧化物薄膜晶体管所使用的一些绝缘层也能够用作低温多晶硅薄膜晶体管的绝缘层，反之亦然。在本实施例中，低温多晶硅薄膜晶体管和氧化物薄膜晶体管共用第二栅绝缘层以减少LTPS+Oxide TFT制备过程中的掩模数量。
S109：在所述第二栅绝缘层30上形成第二有源层21。
如图8所示，在第二栅绝缘层30上沉积一层氧化铟镓锌IGZO，通过掩模形成第二有源层21，即氧化物薄膜晶体管的有源层。氧化铟镓锌(IGZO)是一种新型半导体材料，具有比a-si更高的电子迁移率，单层IGZO可用于氧化物薄膜晶体管中作为沟道材料，在本实施例中，单层IGZO作为氧化物薄膜晶体管中的有源层。进一步的，本发明的氧化物薄膜晶体管的有源层还可以使用IGZTO、IZO、ZnO、ZnON、ITZO等金属氧化物材料。
S111：在所述第二栅绝缘层30上形成第二源漏极23和24，所述第二源漏极23和24与所述第二有源层21电连接。
如图9所示，在第二栅绝缘层30和第二有源层21上沉积栅金属层，经掩模形成第二源漏极23和24，即氧化物薄膜晶体管的源漏极，所述栅金属层可以作为氧化物薄膜晶体管的电极，与氧化物薄膜晶体管的有源层21电连接。
在一个优选的实施例中，如图12所示，利用该掩模在形成所述第一源漏极23和24的同时还形成与所述第一金属层位置相对应的第二金属层32，所述第二金属层32为所述阵列基板的存储电容的第二金属电极板，所述存储电容在OLED像素电路中用于补偿驱动薄膜晶体管的阈值电压，该结构可以充分利用已有掩模工艺，降低制作成本。
在一个优选的实施例中，如图13所示，利用该掩模在形成所述第一源漏极23和24的同时还形成与所述第一栅极位置相对应的第三金属层33，所述第三金属层33为所述阵列基板的存储电容的第二金属电极板，与所述第一栅极形成所述阵列基板的存储电容，所述存储电容在OLED像素电路中用于补偿驱动薄膜晶体管的阈值电压，该结构可以充分利用已有掩模工艺，降低制作成本。
S113：形成覆盖所述第二栅绝缘层30、第二有源层21和第二源漏极23和24的层间绝缘层40；
如图10所示，在第二栅绝缘层30、第二有源层21和第二源漏极23和24上覆盖一层绝缘层40，作为低温多晶硅薄膜晶体管的层间绝缘层，并且用作氧化物薄膜晶体管的钝化层，即两种薄膜晶体管共用层间绝缘层。虽然绝缘层的特定功能在薄膜晶体管中可能有所不同，但是在背板上形成低温多晶硅薄膜晶体管所使用的一些绝缘层也能够用作氧化物薄膜晶体管的绝缘层，反之亦然。
在所述层间绝缘层40上中使用掩模形成第一过孔，第一过孔贯通所述层间绝缘层40、第二栅绝缘层30和第一栅绝缘层20，露出第一有源层11。
在一个优选的实施例中，如图12所示，在该步骤中使用掩模还形成第二过孔，所述第二过孔贯通层间绝缘层40，露出第二源漏极23和24。
通过该第一过孔和第二过孔进行氢氟酸清洗，氢氟酸通过第一过孔能够去除第一有源层11表面的氧化物，使第一有源层11与后续沉积的源漏金属有良好的欧姆接触。同时因为该结构中第二源漏极23和24(氧化物薄膜晶体管的源漏极)对第二有源层21(氧化物薄膜晶体管的有源层)的保护以避免IGZO被氢氟酸药液刻蚀，从而解决LTPS+Oxide TFT制备过程中工艺不兼容的问题。
S115：在所述层间绝缘层上形成第一源漏极13和14，所述第一源漏极13和14与所述第一有源层11电连接。
如图11所示，利用掩模对源漏金属层进行图案化形成第一源漏极13和14，即低温多晶硅薄膜晶体管的源极和漏极，第一源漏极13和14与第一有源层11的位置相对应，通过第一过孔与第一有源层11电连接。
在一个优选的实施例中，如图12所示，利用该步骤中的掩模在第二过孔对应的位置上还形成辅助金属41和42，所述辅助金属41和42通过第二过孔与氧化物薄膜晶体管的源漏极23和24电连接。
其中所述第一有源层、第一栅极和第一源漏极构成低温多晶硅薄膜晶体管，所述第二有源层、第二栅极和第二源漏极构成氧化物薄膜晶体管。
本实施例中第一有源层为所述低温多晶硅薄膜晶体管的有源层，所述第一栅极和第一源漏极与所述第一有源层的位置相对应，为所述低温多晶硅薄膜晶体管栅极和源漏极；第二有源层为所述氧化物薄膜晶体管有源层，所述第二栅极和第二源漏极与所述第二有源层的位置相对应，为所述氧化物薄膜晶体管栅极和源漏极。
需要说明的是，上述制作方法的步骤仅用于本实施例的示意性说明，并不做具体的限定，本领域技术人员可以在本发明揭露的技术范围内进行变化和替换。
经过上述工艺步骤，得到如图11所示的阵列基板，包括包括两种薄膜晶体管，具体包括形成在衬底上的第一有源层；覆盖所述第一有源层上的第一栅绝缘层；形成在所述第一栅绝缘层上同层设置的第一栅极和第二栅极；覆盖所述第一栅极和第二栅极的第二栅绝缘层；形成在所述第二删绝缘层上的第二有源层和第二源漏极，所述第二源漏极与所述第二有源层电连接；覆盖所述第二有源层和第二源漏极的层间绝缘层；形成在所述层间绝缘层上的第一源漏极，所述第一源漏极与所述第一有源层电连接。
进一步地，所述第一有源层、第一栅极和第一源漏极构成低温多晶硅薄膜晶体管；所述第二有源层、第二栅极和第二源漏极构成氧化物薄膜晶体管。
进一步地，如图12所示，在第一栅绝缘层20上还同层设置了第一金属层31，所述第一金属层31为所述阵列基板的存储电容的第一金属电极板，在所述第二栅绝缘层30上还同层设置了第二金属层32，所述第二金属层32为所述阵列基板的存储电容的第二金属电极板，该存储电容在OLED像素电路中用于补偿驱动薄膜晶体管的阈值电压。
本实施例通过调整LTPS+Oxide TFT的结构，将低温多晶硅薄膜晶体管的栅极、阵列基板的存储电容的第一金属电极板和氧化物薄膜晶体管的栅极同层设置，将低温多晶硅薄膜晶体管的栅绝缘层和氧化物薄膜晶体管的栅绝缘层共用，将阵列基板的存储电容的第二金属电极板和氧化物薄膜晶体管的源漏极同层设置，以及将低温多晶硅薄膜晶体管的层间绝缘层和氧化物薄膜晶体管的钝化层共用，以减少LTPS+Oxide TFT的掩模数量，并解决了两种晶体管制备过程中工艺不兼容的问题。
进一步地，在LCD阵列基板中，由于低温多晶硅薄膜晶体管具有迁移率高，充电快的优势，一般用于非显示区内周边驱动电路的驱动晶体管DTFT；而氧化物薄膜晶体管因具有漏电流低的优势一般用于显示区内的开关晶体管STFT，从而有利于实现像素低频驱动以降低功耗。
在OLED阵列基板中，由于OLED像素电路采用多个薄膜晶体管+存储电容的结构，因此低温多晶硅薄膜晶体管和氧化物薄膜晶体管均可作为驱动晶体管DTFT或开关晶体管STFT。
进一步地，所述阵列基板中低温多晶硅薄膜晶体管和氧化物薄膜晶体管的数量是可变的。所述阵列基板包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管，在不同的应用场景下可以根据实际需求设置低温多晶硅薄膜晶体管和氧化物薄膜晶体管的数量。本领域技术人员应当明了，图11和图12仅为示例性的描述两种不同的薄膜晶体管组合制备的结构，并不局限于阵列基板所包含薄膜晶体管的数量。
本发明的另一个实施例提供了一种显示面板。
当该显示面板为LCD显示面板时，包括上述阵列基板、液晶和彩膜基板。
当该显示面板为OLED显示面板时，包括上述阵列基板和背板。
本发明的另一个实施例提供了一种显示装置，包括上述实施例中提供的显示面板。该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定，对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动，这里无法对所有的实施方式予以穷举，凡是属于本发明的技术方案所引伸出的显而易见的变化或变动仍处于本发明的保护范围之列。

Claims (10)

1.一种阵列基板，包括两种薄膜晶体管，其特征在于，具体包括
形成在衬底上的第一有源层；
覆盖所述第一有源层上的第一栅绝缘层；
形成在所述第一栅绝缘层上同层设置的第一栅极和第二栅极；
覆盖所述第一栅极和第二栅极的第二栅绝缘层；
形成在所述第二栅绝缘层上的第二有源层和第二源漏极，所述第二源漏极与所述第二有源层电连接，其中，所述第二源漏极部分覆盖所述第二有源层；
覆盖所述第二有源层和第二源漏极的层间绝缘层；
形成露出所述第一有源层的第一过孔和露出所述第二源漏极的第二过孔；
形成在所述层间绝缘层上的第一源漏极，所述第一源漏极通过所述第一过孔与所述第一有源层电连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述第一有源层、第一栅极和第一源漏极构成低温多晶硅薄膜晶体管；所述第二有源层、第二栅极和第二源漏极构成氧化物薄膜晶体管。
3.根据权利要求1所述的阵列基板，其特征在于，还包括
形成在所述第一栅绝缘层上的第一金属层，所述第一金属层与所述第一栅极同层设置；
形成在所述第二栅绝缘层上的与所述第一金属层位置相对应的第二金属层，所述第二金属层与所述第二源漏极同层设置。
4.根据权利要求1所述的阵列基板，其特征在于，还包括形成在所述第二栅绝缘层上的与所述第一栅极位置相对应的第三金属层，所述第三金属层与所述第二源漏极同层设置。
5.根据权利要求1所述的阵列基板，其特征在于，所述层间绝缘层上还包括与所述第一源漏极同层设置的辅助金属，所述辅助金属与所述第二源漏极电连接。
6.一种阵列基板的制作方法，其特征在于，包括：
S101：在衬底上形成第一有源层；
S103：在所述第一有源层上形成第一栅绝缘层；
S105：在所述第一栅绝缘层上同时形成第一栅极和第二栅极；
S107：形成覆盖所述第一栅极和第二栅极的第二栅绝缘层；
S109：在所述第二栅绝缘层上形成第二有源层；
S111：在所述第二栅绝缘层上形成第二源漏极，所述第二源漏极与所述第二有源层电连接，其中，所述第二源漏极部分覆盖所述第二有源层；
S113：形成覆盖所述第二栅绝缘层、第二有源层和第二源漏极的层间绝缘层；
S114：形成露出所述第一有源层的第一过孔和露出所述第二源漏极的第二过孔；
S115：在所述层间绝缘层上形成第一源漏极，所述第一源漏极通过所述第一过孔与所述第一有源层电连接。
7.根据权利要求6所述的制作方法，其特征在于，
在步骤S105中，在形成所述第一栅极的同时形成第一金属层；并且
在步骤S111中，在形成所述第二源漏极的同时形成第二金属层。
8.根据权利要求6所述的制作方法，其特征在于，
在步骤S115中，在形成所述第一源漏极的同时形成辅助金属，所述辅助金属与所述第二源漏极电连接。
9.一种显示面板，其特征在于，包括：
如权利要求1-5中任一项所述的阵列基板、液晶和彩膜基板；
或者
如权利要求1-5中任一项所述的阵列基板和背板。
10.一种显示装置，其特征在于，包括权利要求9所述的显示面板。
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