WO2018045822A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2018045822A1
WO2018045822A1 PCT/CN2017/092781 CN2017092781W WO2018045822A1 WO 2018045822 A1 WO2018045822 A1 WO 2018045822A1 CN 2017092781 W CN2017092781 W CN 2017092781W WO 2018045822 A1 WO2018045822 A1 WO 2018045822A1
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active layer
gate
layer
forming
drain
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PCT/CN2017/092781
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English (en)
French (fr)
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彭宽军
廖峰
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京东方科技集团股份有限公司
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Priority to US15/751,131 priority Critical patent/US20200091198A1/en
Publication of WO2018045822A1 publication Critical patent/WO2018045822A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • outdoor wearable display devices are popular with users.
  • outdoor wearable display devices need to meet various requirements such as low power consumption, sensor integration, and narrow bezel.
  • the display device generally includes a package substrate and an array substrate.
  • the array substrate is divided into a display area and a non-display area (also referred to as a peripheral area) surrounding the display area; in the non-display area, a LTPS TFT (Low Temperature Poly-silicon-Thin Film Transistor) technology is implemented.
  • the narrow bezel is integrated with the sensor circuit; in the display region, since the amorphous Oxide TFT (Oxide Thin Film Transistor) has a small leakage current (I off ), the amorphous Oxide TFT technology is used to implement the pixel. Low frequency drive to reduce power consumption. However, amorphous Oxide TFTs are less stable.
  • a microcrystalline Oxide TFT can be used instead of the amorphous Oxide TFT.
  • the current fabrication process of the LTPS TFT and the microcrystalline Oxide TFT fabrication process are performed separately, with low process integration and high production cost.
  • a method of fabricating an array substrate comprising:
  • the material of the first active layer is polysilicon
  • the material of the second active layer is an amorphous metal oxide;
  • the step of forming the second active layer is forming the first active layer, and is at least first active Performing ion implantation after the layer to be doped is performed, or before forming the first active layer;
  • the material of the second active layer is changed from an amorphous state to a microcrystalline state.
  • the activation process is a thermal activation process.
  • the using an activation process to activate ions implanted in the first active layer and to change a material of the second active layer from an amorphous state to a microcrystalline state comprises:
  • the ambient temperature at which the array substrate is placed is adjusted to 550 ° C - 650 ° C for 0.5 h - 1.0 h.
  • the method further includes:
  • the gate metal layer comprising: a first gate and a second gate; wherein the first gate corresponds to a position of the first active layer, and the second gate Corresponding to the position of the second active layer;
  • the source/drain metal layer includes: a first source and a first drain, a second source, and a second drain; the first source and the first drain respectively
  • the first active layer is electrically connected
  • the second source and the second drain are electrically connected to the second active layer, respectively.
  • the array substrate is divided into: a display area and a non-display area surrounding the display area;
  • the first active layer, the first gate, the first source, and the first a drain is formed in the non-display area;
  • the second active layer, the second gate, the second source, and the second drain are both formed in the display region.
  • performing at least ion implantation into the to-be-doped region of the first active layer is specifically:
  • Ion implantation is performed only to the region to be doped of the first active layer.
  • the ion implantation comprises plasma bombardment.
  • the metal oxide of the second active layer is zinc oxide, or a metal oxide in which at least one of indium, gallium, tin, and magnesium is doped in the zinc oxide.
  • the method is performed in the following steps: forming a first active layer, forming a gate metal layer, performing ion implantation on at least a doped region of the first active layer, forming a second active layer, and adopting The activation process forms a source/drain metal layer.
  • the method further includes:
  • a gate insulating layer is formed after the forming the first active layer and before the forming the gate metal layer, the gate insulating layer covering the first active layer.
  • the method further includes:
  • an interlayer dielectric layer is formed, the interlayer dielectric layer covering the gate metal layer .
  • an array substrate is provided, which is formed by the fabrication method described in any of the above.
  • a display device comprising: the array substrate described above.
  • CMOS complementary metal oxide semiconductor
  • An embodiment of the present disclosure provides an array substrate and a method of fabricating the same, and a device including the array substrate.
  • the method for fabricating the array substrate can activate the ions implanted by the first active layer by using an activation process.
  • the process and the amorphous transformation of Oxide TFT are integrated into the microcrystalline state process, which has the characteristics of high process integration and low production cost compared with the prior art.
  • FIG. 1 is a flow chart 1 of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a second flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • This embodiment provides a method for fabricating an array substrate, and the method includes:
  • a first active layer the material of the first active layer is polysilicon; the specific method for forming the first active layer is not limited herein.
  • an amorphous silicon film may be formed first, and then amorphous silicon is formed. The film is subjected to laser irradiation to convert amorphous silicon (a-silicon) crystals into polycrystalline silicon (p-silicon) to form a polycrystalline silicon film.
  • S02 performing ion implantation on at least a region to be doped of the first active layer to form a doping region for electrically connecting with a corresponding source and drain; here, a method for implanting ions and implanting ions
  • the type is not limited.
  • boron ions may be implanted into the first active layer by plasma bombardment to form a P-type TFT; or, plasma ion bombardment may be used to implant phosphorus ions into the first active layer to form an N-type.
  • the TFT may of course be implanted with other ions by other methods.
  • only the above is taken as an example.
  • the material of the second active layer is an amorphous metal oxide; the specific material of the metal oxide is not limited herein, and may be determined according to actual conditions. It should be noted that, according to the state of the crystal, the metal oxide can be classified into an amorphous state, a microcrystalline state, or the like, and a TFT formed using a microcrystalline metal oxide is formed compared to an amorphous metal oxide.
  • the TFT has lower leakage current, better IV (current-voltage) characteristics, and better stability.
  • S03 may be performed after S01 and S02, or may be performed before S01 and S02, and is not limited herein.
  • S03 may be selected after S01 and S02.
  • At S02 at least ion implantation into the region to be doped of the first active layer, and after S03, forming the second active layer, S04, using an activation process to activate ions implanted in the first active layer,
  • the material of the second active layer changes from an amorphous state to a microcrystalline state (ie, from an a-metal oxide to a uc-metal oxide).
  • the material of the second active layer can be changed from an amorphous state to a microcrystalline state while the ions implanted by the first active layer are activated by an activation process;
  • the ion activation process of the LTPS TFT and the process of converting the amorphous state of the Oxide TFT into a microcrystalline state are integrated, and the process integration is high and the production cost is low compared with the prior art.
  • the foregoing method further includes:
  • the gate metal layer includes: a first gate and a second gate; wherein, the first gate corresponds to a position of the first active layer, and the second gate corresponds to a position of the second active layer .
  • the specific method of forming the gate metal layer is not limited.
  • the first gate and the second gate may be formed by one patterning process, and the materials of the first gate and the second gate may be Al (aluminum), Mo (molybdenum), Cr ( Metals such as chromium), Cu (copper), and Ti (titanium).
  • the first gate may be formed over the first active layer (top gate structure) or may be formed under the first active layer (bottom gate structure); the second gate may be formed on the second active layer
  • the upper (top gate structure) may also be formed under the second active layer (bottom gate structure).
  • the source/drain metal layer includes: a first source and a first drain, a second source, and a second drain; the first source and the first drain and the first active layer respectively Electrically connected, the second source and the second drain are electrically connected to the second active layer, respectively.
  • the specific method of forming the source and drain metal layers is not limited.
  • the first source, the first drain, the second source, and the second drain may be formed by one patterning process, and the material of the source/drain metal layer may be Al (aluminum) or Mo ( Metals such as molybdenum), Cr (chromium), Cu (copper), and Ti (titanium).
  • the TFT may be a top gate structure (ie, the gate is formed over the active layer) or a bottom gate structure (ie, the gate is formed under the active layer), which is not limited herein.
  • the TFT formed by the first active layer, the first gate, the first source, and the first drain is referred to as a first thin film transistor TFT1
  • the TFT formed by the source and the second drain is referred to as a second thin film transistor TFT2.
  • the TFT 1 is a top gate TFT including a first active layer 11, a first gate 12, a first source 13 and a first drain 14; and the TFT 2 is a bottom gate TFT, which includes a second The source layer 21, the second gate 22, the second source 23, and the second drain 24.
  • the manufacturing process of the above method may be sequentially: S01, forming the first active layer 11, S05, forming a gate metal layer, That is, the first gate electrode 12 and the second gate electrode 22, S02, at least ion implantation into the region to be doped of the first active layer 11 to form doped regions 111, 112, S03, forming the second active layer 21, S04, Using an activation process, S06, forming a source/drain metal layer, including a first source 13 and a first drain 14, a second source 23 and a second drain 24.
  • the above-mentioned TFT1 and TFT2 may be other structures, and the embodiments of the present disclosure and the drawings are all described by taking the structure shown in FIG. 2 as an example.
  • the array substrate is divided into: a display area 3 and a non-display area 4 surrounding the display area; a first active layer 11, a first gate 12, a first source 13 and a first
  • the drain 14 ie, TFT1 is formed in the non-display area 4; in the non-display area, a gate line driving circuit (also referred to as a GOA circuit), a data line driving circuit, or a sensor or the like is generally provided, and the TFT1 is applied to these.
  • the driver circuit or the Multiplexer facilitates the integration of narrow bezel and sensor circuitry.
  • the second active layer 21, the second gate 22, the second source 23, and the second drain 24 are both formed in the display region 3, facilitating pixel low frequency driving to reduce power consumption.
  • TFT1 and TFT2 can also be used to form a CMOS (Complementary Metal Oxide Semiconductor) device, for example, a CMOS inverter or the like, which is not limited herein, and is specifically determined according to actual conditions.
  • CMOS Complementary Metal Oxide Semiconductor
  • performing ion implantation on at least the to-be-doped region of the first active layer is: performing ion implantation only on the to-doped region of the first active layer, wherein The doped region is for electrically connecting to the first source and the first drain.
  • S04 using an activation process, so that the ions implanted in the first active layer are activated, and the material of the second active layer is changed from an amorphous state to a microcrystalline state, including:
  • the ambient temperature at which the array substrate is placed is adjusted to 550 ° C - 650 ° C for 0.5 h - 1.0 h. That is, the activation process mainly uses a high temperature activation process to complete ion activation of the doped region of the first active layer and amorphous to microcrystalline transformation of the material of the second active layer.
  • the ambient temperature may be about 600 ° C, and the duration may be about 1.0 h, depending on the actual situation.
  • the metal oxide may be zinc oxide (ZnO) or a metal oxide doped with at least one of indium, gallium, tin, and magnesium in the zinc oxide, for example, indium gallium.
  • ITZO indium tin zinc oxide
  • MIZO magnesium indium zinc oxide
  • IZO indium zinc oxide
  • the method is performed in the following order: S01, forming the first active layer 11, S05, forming a gate metal layer, that is, the first gate 12 and the second gate 22, S02, at least to the first active
  • the layer to be doped is ion-implanted to form doped regions 111, 112, S03, form a second active layer 21, S04, using an activation process, S06, forming a source-drain metal layer, including a first source 13 and a first drain
  • the pole 14, the second source 23 and the second drain 24 are formed to form the structure shown in FIG. It should be noted that, in the structure shown in FIG.
  • the doped regions 111, 112 of the first active layer 11 refer to portions that are not blocked by the first gate 12; due to the blocking effect of the first gate 12, the above fabrication is performed. In the order, ion implantation into only the doping regions 111, 112 of the first active layer 11 can be easily performed.
  • the foregoing method further includes:
  • the gate insulating layer 5 covering the first active layer 11 to protect The first active layer 11.
  • the specific formation of the gate insulating layer 5 is not limited.
  • the gate insulating layer 5 may be formed by a CVD (Chemical Vapor Deposition) method.
  • the material of the gate insulating layer 5 may be silicon oxide or nitride. Insulating materials such as silicon and organic materials.
  • the interlayer dielectric layer 6 covers the gate metal layers (ie, the first gate electrode 12 and the second gate electrode 22) to protect the gate metal layer.
  • the material of the interlayer dielectric layer may be an insulating material such as silicon oxide, silicon nitride or an organic material.
  • the array substrate may further include the substrate 7 shown in FIG. 2, and both the TFT 1 and the TFT 2 are formed on the substrate 7; of course, in order to generate an electric field, the array substrate may further include a pixel electrode and/or a common electrode; further, In order to prevent the first active layer of the TFT1 from being affected by light, the array substrate may further include a light Shield or the like disposed under the first active layer of the TFT1, and only the structure related to the invention is described in detail herein. The rest of the structure can be referred to the prior art.
  • This embodiment provides an array substrate formed by the manufacturing method of any one of the first embodiments.
  • the array substrate has the characteristics of high process integration and low production cost.
  • the array substrate may be a common array substrate or a COA (Color Filter on Array) substrate.
  • the COA substrate refers to a substrate on which the color film layer is formed on the array substrate, which is not limited herein.
  • the array substrate By adjusting the order of the fabrication methods in the first embodiment, an array substrate of a plurality of structures can be formed.
  • An array substrate of a specific structure is provided below. Referring to FIG. 2, the array substrate includes: a substrate 7, a first active layer 11 (including doped regions 111, 112) disposed sequentially on the substrate 7, and a gate insulating layer covering the first active layer 11. 5.
  • a gate metal layer (a first gate 12 and a second gate 22), an interlayer dielectric layer 6 covering the gate metal layer, and a source/drain metal layer
  • the source/drain metal layer comprises: a first source 13 and a first a drain 14, a second source 23 and a second drain 24, the first source 13 and the first drain 14 pass through the vias penetrating the interlayer dielectric layer 6 and the gate insulating layer 5 and the first active layer 11 Electrically connected, the second source 23 and the second drain 24 are in direct contact with the second active layer 21 to achieve electrical connection.
  • the array substrate further includes: a flat layer 8 covering the source and drain metal layers, the flat layer having planarization and insulation,
  • the material may be an organic insulating material.
  • the embodiment provides a display device, including the array substrate provided in the second embodiment.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display product such as a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device. component.
  • the display device has the characteristics of high process integration, low production cost, low power consumption and high stability.
  • the size and application scenario of the display device are not limited herein; it may be a large-size display device, or may be a small-sized, wearable display device, such as a wristband, etc.; it may be applied indoors or applied. Outdoors, due to the low power consumption of the display device, the application is more advantageous in the outdoor.

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Abstract

公开了一种阵列基板及其制作方法、显示装置，涉及显示技术领域。阵列基板的制作方法包括：形成第一有源层；第一有源层的材料为多晶硅；至少向第一有源层的待掺杂区进行离子注入以形成掺杂区，掺杂区用于与对应的源极和漏极电连接；形成第二有源层；第二有源层的材料为非晶态的金属氧化物；在至少向第一有源层的待掺杂区进行离子注入、且在形成第二有源层之后，采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态。

Description

阵列基板及其制作方法、显示装置
交叉引用
本公开要求2016年9月12日提交的、发明名称为“一种阵列基板及其制作方法、显示装置”的中国专利申请No.201610817595.9的优先权权益，该中国专利申请的全部内容通过引用结合在此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
目前，户外可穿戴显示装置受到用户的欢迎。为了提高用户体验度，户外可穿戴显示装置需要满足低功耗、传感器集成、窄边框等各种要求。
显示装置一般包括：封装基板和阵列基板。阵列基板分为显示区域和包围显示区域的非显示区域(也可称为周边区域)；在非显示区域，采用LTPS TFT(Low Temperature Poly-silicon-Thin Film Transistor，低温多晶硅薄膜晶体管)技术以实现窄边框和传感器电路集成；在显示区域，由于非晶态的Oxide TFT(Oxide Thin Film Transistor，氧化物薄膜晶体管)具有较小的漏电流(Ioff)，采用非晶态的Oxide TFT技术实现像素低频驱动以降低功耗。但是非晶态的Oxide TFT稳定性较差。为了提高稳定性，可以采用微晶态的Oxide TFT替代非晶态的Oxide TFT。但是，目前LTPS TFT的制作工艺与微晶态的Oxide TFT的制作工艺是单独进行的，工艺集成度低，生产成本高。
发明内容
本公开的实施例采用如下技术方案：
一方面，提供了一种阵列基板的制作方法，所述方法包括：
形成第一有源层；所述第一有源层的材料为多晶硅；
至少向所述第一有源层的待掺杂区进行离子注入以形成掺杂区，所述掺杂区用于与对应的源极和漏极电连接；
形成第二有源层；所述第二有源层的材料为非晶态的金属氧化物；所述形成第二有源层的步骤在形成第一有源层、且至少向第一有源层的待掺杂区进行离子注入之后进行，或者在形成第一有源层之前进行；
在至少向所述第一有源层的待掺杂区进行离子注入、且在形成所述第二有源层之后，采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态。
可选的，所述活化工艺为热活化工艺。
可选的，所述采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态包括：
将所述阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。
可选的，所述方法还包括：
形成栅金属层，所述栅金属层包括：第一栅极和第二栅极；其中，所述第一栅极与所述第一有源层的位置对应，所述第二栅极与所述第二有源层位置对应；
形成源漏金属层，所述源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；所述第一源极和所述第一漏极分别与所述第一有源层电连接，所述第二源极和所述第二漏极分别与所述第二有源层电连接。
可选的，所述阵列基板分为：显示区域和包围所述显示区域的非显示区域；
所述第一有源层、所述第一栅极、所述第一源极和所述第 一漏极均形成在所述非显示区域；
所述第二有源层、所述第二栅极、所述第二源极和所述第二漏极均形成在所述显示区域。
可选的，所述至少向所述第一有源层的待掺杂区进行离子注入具体为：
仅向所述第一有源层的待掺杂区进行离子注入。
可选的，所述离子注入包括等离子体轰击。
可选的，所述第二有源层的金属氧化物为氧化锌、或者是在所述氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物。
可选的，所述方法的制作顺序依次为：形成第一有源层、形成栅金属层、至少向所述第一有源层的掺杂区进行离子注入、形成第二有源层、采用活化工艺、形成源漏金属层。
可选的，所述方法还包括：
在所述形成第一有源层之后、且在所述形成栅金属层之前，形成栅绝缘层，所述栅绝缘层覆盖所述第一有源层。
可选的，所述方法还包括：
在所述至少向所述第一有源层的待掺杂区进行离子注入之后、且在形成第二有源层之前，形成层间介质层，所述层间介质层覆盖所述栅金属层。
另一方面，提供了一种阵列基板,采用上述任一项所述的制作方法形成。
再一方面，提供了一种显示装置，包括：上述的阵列基板。
再一方面，提供了一种互补金属氧化物半导体(CMOS)器件，包括：上述的阵列基板。
本公开的实施例提供了一种阵列基板及其制作方法、包括所述阵列基板的器件，通过该阵列基板的制作方法，可以在采用活化工艺将第一有源层注入的离子活化的同时，完成第二有源层的材料从非晶态转变为微晶态；即将LTPS TFT的离子活 化工艺和Oxide TFT的非晶态转变为微晶态的工艺集成在一起，相较于现有技术，具有工艺集成度高，生产成本低的特点。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种阵列基板的制作方法流程图一；
图2为本公开实施例提供的一种阵列基板的结构示意图；
图3为本公开实施例提供的一种阵列基板的制作方法流程图二。
附图标记：
1-第一薄膜晶体管TFT1；2-第二薄膜晶体管TFT2；3-显示区域；4-非显示区域；5-栅绝缘层；6-层间介质层；7-衬底；8-平坦层；11-第一有源层；111,112-掺杂区；12-第一栅极；13-第一源极；14-第一漏极；21-第二有源层；22-第二栅极；23-第二源极；24-第二漏极。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为 对本公开的限制。
实施例一
本实施例提供了一种阵列基板的制作方法，该方法包括：
S01、形成第一有源层；第一有源层的材料为多晶硅；这里对于形成第一有源层的具体方法不做限定，示例的，可以先形成非晶硅薄膜，然后对非晶硅薄膜进行激光照射以使非晶硅(a-硅)结晶转化成多晶硅(p-硅)，进而形成多晶硅薄膜。
S02、至少向第一有源层的待掺杂区进行离子注入以形成掺杂区，该掺杂区用于与对应的源极和漏极电连接；这里，对于注入离子的方法和注入离子的类型不做限定。示例的，可以采用等离子体轰击的方法向第一有源层注入硼离子，以形成P型TFT；或者，还可以采用等离子体轰击的方法向第一有源层注入磷离子，以形成N型TFT，当然还可以是采用其他方法注入其他离子，这里仅以上述为例进行说明。
S03、形成第二有源层；第二有源层的材料为非晶态的金属氧化物；这里对于金属氧化物的具体材料不做限定，具体可以根据实际情况而定。需要说明的是，按照晶体的状态，可将金属氧化物分为非晶态、微晶态等，采用微晶态的金属氧化物形成的TFT相较于采用非晶态的金属氧化物形成的TFT具有更低的漏电流、更好的I-V(电流-电压)特性以及更好的稳定性。
需要说明的是，上述S03可以是在S01和S02之后进行，也可以是在S01和S02之前进行，这里不做限定。为了避免离子注入对于形成第二有源层的影响，参考图1所示，可以选择在S01和S02之后进行S03。
在S02、至少向第一有源层的待掺杂区进行离子注入、且在S03、形成第二有源层之后，S04、采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态(即从a-金属氧化物转变为uc-金属氧化物)。
通过上述制作方法，可以在采用活化工艺将第一有源层注入的离子活化的同时，完成第二有源层的材料从非晶态转变为微晶态； 即将LTPS TFT的离子活化工艺和Oxide TFT的非晶态转变为微晶态的工艺集成在一起，相较于现有技术，具有工艺集成度高，生产成本低的特点。
可选的，上述方法还包括：
S05、形成栅金属层，栅金属层包括：第一栅极和第二栅极；其中，第一栅极与第一有源层的位置对应，第二栅极与第二有源层位置对应。这里对于形成栅金属层的具体方法不做限定。示例的，考虑到降低成本，可以通过一次构图工艺形成第一栅极和第二栅极，该第一栅极和第二栅极的材料可以是Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属。第一栅极可以形成在第一有源层之上(顶栅结构)，也可以形成在第一有源层之下(底栅结构)；第二栅极可以形成在第二有源层之上(顶栅结构)，也可以形成在第二有源层之下(底栅结构)。
S06、形成源漏金属层，源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；第一源极和第一漏极分别与第一有源层电连接，第二源极和第二漏极分别与第二有源层电连接。这里对于形成源漏金属层的具体方法不做限定。示例的，考虑到降低成本，可以通过一次构图工艺形成第一源极、第一漏极、第二源极和第二漏极，该源漏金属层的材料可以是Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属。
需要说明的是，上述S05、S06与S01-S04的制作顺序根据实际所要形成的TFT的结构有关。该TFT可以是顶栅结构(即栅极形成在有源层之上)，也可以是底栅结构(即栅极形成在有源层之下)，这里不做限定。为了便于描述，将第一有源层、第一栅极、第一源极和第一漏极形成的TFT称为第一薄膜晶体管TFT1，将第二有源层、第二栅极、第二源极和第二漏极形成的TFT称为第二薄膜晶体管TFT2。参考图2所示，TFT1为顶栅TFT，其包括第一有源层11、第一栅极12、第一源极13和第一漏极14；TFT2为底栅TFT，其包括第二有源层21、第二栅极22、第二源极23和第二漏极24。若要形成如图2所示的结构，则上述方法的制作顺序可以依次为：S01、形成第一有源层11，S05、形成栅金属层， 即第一栅极12和第二栅极22，S02、至少向第一有源层11的待掺杂区进行离子注入以形成掺杂区111,112，S03、形成第二有源层21，S04、采用活化工艺，S06、形成源漏金属层，包括第一源极13和第一漏极14，第二源极23和第二漏极24。当然，上述TFT1和TFT2还可以是其他结构，本公开实施例以及附图均以图2所示的结构为例进行说明。
可选的，参考图2所示，上述阵列基板分为：显示区域3和包围显示区域的非显示区域4；第一有源层11、第一栅极12、第一源极13和第一漏极14(即TFT1)均形成在非显示区域4；在非显示区域中，一般会设置栅线驱动电路(又称GOA电路)、数据线驱动电路或者是传感器等，将上述TFT1应用在这些驱动电路或者是Multiplexer(多路复用器)中，有利于实现窄边框和传感器电路集成。第二有源层21、第二栅极22、第二源极23和第二漏极24(即TFT2)均形成在显示区域3，有利于实现像素低频驱动以降低功耗。另外，上述TFT1和TFT2还可用于形成CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件，例如：CMOS反相器等，这里不做限定，具体根据实际情况而定。
可选的，为了保证导通效果，S02、至少向第一有源层的待掺杂区进行离子注入具体为：仅向第一有源层的待掺杂区进行离子注入，其中，所形成的掺杂区用于与第一源极和第一漏极电连接。
可选的，S04、采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态包括：
将阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。即该活化工艺主要是采用高温活化工艺以完成第一有源层的掺杂区的离子活化和第二有源层的材料的非晶态到微晶态的转变。示例的，该环境温度可以是约600℃，持续时间可以是约1.0h，具体可以根据实际情况而定。
可选的，金属氧化物可以为氧化锌(ZnO)，或者是在氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物，例如：铟镓 锌氧化物(IGZO)、铟锡锌氧化物(ITZO)、镁铟锌氧化物(MIZO)、铟锌氧化物(IZO)等。当然，还可以是在氧化锌中掺杂有其他金属，这里仅以上述为例进行说明。
可选的，上述方法的制作顺序依次为：S01、形成第一有源层11，S05、形成栅金属层，即第一栅极12和第二栅极22，S02、至少向第一有源层的待掺杂区进行离子注入以形成掺杂区111,112，S03、形成第二有源层21，S04、采用活化工艺，S06、形成源漏金属层，包括第一源极13和第一漏极14，第二源极23和第二漏极24，以形成图2所示的结构。需要说明的是，图2所示的结构中，第一有源层11的掺杂区111,112是指未被第一栅极12遮挡的部分；由于第一栅极12的遮挡作用，通过上述制作顺序，可以很容易地实现仅向第一有源层11的掺杂区111,112进行离子注入。
可选的，参考图3所示，上述方法还包括：
在S01、形成第一有源层11之后、且在S05、形成栅金属层之前，S07、形成如图2所示的栅绝缘层5，栅绝缘层5覆盖第一有源层11，以保护第一有源层11。这里对于栅绝缘层5的具体形成方式不做限定，示例的，可以采用CVD(Chemical Vapor Deposition，化学气相沉积)法形成栅绝缘层5，该栅绝缘层5的材料可以是氧化硅、氮化硅及有机材料等绝缘材料。
在S02、至少向所述第一有源层11的待掺杂区进行离子注入之后、且在S03、形成第二有源层12之前，S08、形成如图2所示的层间介质层6(又称ILD层)，层间介质层6覆盖栅金属层(即第一栅极12和第二栅极22)，以保护栅金属层。该层间介质层的材料可以是氧化硅、氮化硅及有机材料等绝缘材料。
上述阵列基板还可以包括图2所示的衬底7，TFT1和TFT2均形成在衬底7上；当然，为了能够产生电场，上述阵列基板还可以包括像素电极和/或公共电极；进一步的，为了避免TFT1的第一有源层受光线影响，上述阵列基板还可以包括设置在TFT1的第一有源层之下的遮光层(Light Shield)等，这里仅详细介绍与发明点相关的结构，其余结构可参考现有技术。
实施例二
本实施例提供了一种阵列基板，该阵列基板采用实施例一提供的任一项的制作方法形成。该阵列基板具有工艺集成度高，生产成本低的特点。该阵列基板可以是普通的阵列基板，也可以是COA(Color Filter on Array)基板，COA基板指把彩膜层做在阵列基板上的基板，这里不做限定。
通过调整实施例一中制作方法的顺序，可以形成多种结构的阵列基板。下面提供一具体结构的阵列基板。参考图2所示，该阵列基板包括：衬底7，在衬底7上依次设置的第一有源层11(包括掺杂区111，112)、覆盖第一有源层11的栅绝缘层5、栅金属层(第一栅极12和第二栅极22)、覆盖栅金属层的层间介质层6、源漏金属层，其中，源漏金属层包括：第一源极13和第一漏极14、第二源极23和第二漏极24，第一源极13和第一漏极14通过贯穿层间介质层6和栅绝缘层5的过孔与第一有源层11电连接，第二源极23和第二漏极24与第二有源层21直接接触实现电连接。当然，为了便于后续膜层的制作，例如像素电极、公共电极等，参考图2所示，上述阵列基板还包括：覆盖源漏金属层的平坦层8，该平坦层具有平坦化和绝缘作用，其材料可以是有机绝缘材料。
实施例三
本实施例提供了一种显示装置，包括：实施例二提供的阵列基板。上述显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。该显示装置具有工艺集成度高，生产成本低，功耗低，稳定性高的特点。另外，这里对于该显示装置的尺寸和应用场景不做限定；其可以是大尺寸显示装置，还可以是小尺寸、可穿戴显示装置，例如：手环等；其可以应用在室内，也可以应用在户外，由于该显示装置具有功耗低的特点，应用在户外更显优势。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技 术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板的制作方法，所述方法包括：
    形成第一有源层；所述第一有源层的材料为多晶硅；
    至少向所述第一有源层的待掺杂区进行离子注入以形成掺杂区，所述掺杂区用于与对应的源极和漏极电连接；
    形成第二有源层；所述第二有源层的材料为非晶态的金属氧化物；所述形成第二有源层的步骤在形成第一有源层、且至少向第一有源层的待掺杂区进行离子注入之后进行，或者在形成第一有源层之前进行；
    在至少向所述第一有源层的待掺杂区进行离子注入、且在形成所述第二有源层之后，采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态。
  2. 根据权利要求1所述的制作方法，其中所述活化工艺为热活化工艺。
  3. 根据权利要求1或2所述的制作方法，其中所述采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态包括：
    将所述阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。
  4. 根据权利要求1至3中任一项所述的制作方法，其中所述方法还包括：
    形成栅金属层，所述栅金属层包括：第一栅极和第二栅极；其中，所述第一栅极与所述第一有源层的位置对应，所述第二栅极与所述第二有源层位置对应；
    形成源漏金属层，所述源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；所述第一源极和所述第一漏极分别与所述第一有源层电连接，所述第二源极和所述第二漏极分别与所述第二有源层电连接。
  5. 根据权利要求4所述的制作方法，其中所述阵列基板 分为：显示区域和包围所述显示区域的非显示区域；
    所述第一有源层、所述第一栅极、所述第一源极和所述第一漏极均形成在所述非显示区域；
    所述第二有源层、所述第二栅极、所述第二源极和所述第二漏极均形成在所述显示区域。
  6. 根据权利要求1至5中任一项所述的制作方法，其中所述至少向所述第一有源层的待掺杂区进行离子注入具体为：
    仅向所述第一有源层的待掺杂区进行离子注入。
  7. 根据权利要求1至6中任一项所述的制作方法，其中所述离子注入包括等离子体轰击。
  8. 根据权利要求1至7中任一项所述的制作方法，其中所述金属氧化物为氧化锌、或者是在所述氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物。
  9. 根据权利要求1-8任一项所述的制作方法，其中所述方法的制作顺序依次为：形成第一有源层、形成栅金属层、至少向所述第一有源层的掺杂区进行离子注入、形成第二有源层、采用活化工艺、形成源漏金属层。
  10. 根据权利要求9所述的制作方法，其中所述方法还包括：
    在所述形成第一有源层之后、且在所述形成栅金属层之前，形成栅绝缘层，所述栅绝缘层覆盖所述第一有源层。
  11. 根据权利要求9或10所述的制作方法，其中所述方法还包括：
    在所述至少向所述第一有源层的待掺杂区进行离子注入之后、且在形成第二有源层之前，形成层间介质层，所述层间介质层覆盖所述栅金属层。
  12. 一种阵列基板，其采用权利要求1-11任一项所述的制作方法形成。
  13. 一种显示装置，其包括：权利要求12所述的阵列基板。
  14. 一种互补金属氧化物半导体(CMOS)器件，其包括：权 利要求12所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2019318862B2 (en) * 2018-08-07 2021-12-09 Boe Technology Group Co., Ltd. Array substrate and display device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298648A (zh) * 2016-09-12 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN106952928B (zh) * 2017-03-30 2018-10-23 深圳市华星光电技术有限公司 一种tft背板的制作方法及tft背板
CN107123654A (zh) * 2017-05-26 2017-09-01 京东方科技集团股份有限公司 阵列基板及其制备方法和显示装置
CN108376672B (zh) 2018-03-15 2020-12-04 京东方科技集团股份有限公司 阵列基板及其制备方法，以及显示装置
CN109887936B (zh) 2019-03-25 2021-01-29 合肥京东方光电科技有限公司 阵列基板及其制作方法
CN110993613A (zh) * 2019-11-27 2020-04-10 武汉华星光电技术有限公司 阵列基板及其制造方法
CN111081719A (zh) * 2019-12-12 2020-04-28 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN112331680A (zh) * 2020-11-13 2021-02-05 武汉华星光电技术有限公司 阵列基板及其制备方法
CN112951845A (zh) * 2021-01-25 2021-06-11 武汉华星光电技术有限公司 阵列基板
CN113611712B (zh) * 2021-07-29 2023-10-17 武汉华星光电技术有限公司 阵列基板、显示面板及其制作方法
CN114927532B (zh) * 2022-04-27 2023-04-21 惠科股份有限公司 阵列基板及其制作方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050074930A1 (en) * 2003-10-07 2005-04-07 Chi-Lin Chen Method of forming poly-silicon thin film transistors
US20080230770A1 (en) * 2007-03-20 2008-09-25 Young-Soo Yoon Organic light-emitting display panel and method of manufacturing the same
CN104867921A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板及利用该薄膜晶体管基板的显示装置
CN106298648A (zh) * 2016-09-12 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070173040A1 (en) * 2006-01-09 2007-07-26 Freescale Semiconductor, Inc. Method of reducing an inter-atomic bond strength in a substance
KR101082174B1 (ko) * 2009-11-27 2011-11-09 삼성모바일디스플레이주식회사 유기전계발광 표시 장치 및 그의 제조 방법
TWI611463B (zh) * 2016-06-29 2018-01-11 友達光電股份有限公司 金屬氧化物半導體層的結晶方法及半導體結構
CN106169481B (zh) * 2016-07-20 2019-04-05 武汉华星光电技术有限公司 柔性阵列基板及其制备方法、柔性显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050074930A1 (en) * 2003-10-07 2005-04-07 Chi-Lin Chen Method of forming poly-silicon thin film transistors
US20080230770A1 (en) * 2007-03-20 2008-09-25 Young-Soo Yoon Organic light-emitting display panel and method of manufacturing the same
CN104867921A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板及利用该薄膜晶体管基板的显示装置
CN106298648A (zh) * 2016-09-12 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2019318862B2 (en) * 2018-08-07 2021-12-09 Boe Technology Group Co., Ltd. Array substrate and display device
US11658186B2 (en) 2018-08-07 2023-05-23 Boe Technology Group Co., Ltd. Array substrate and display device

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