CN106298648A - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
CN106298648A
CN106298648A CN201610817595.9A CN201610817595A CN106298648A CN 106298648 A CN106298648 A CN 106298648A CN 201610817595 A CN201610817595 A CN 201610817595A CN 106298648 A CN106298648 A CN 106298648A
Authority
CN
China
Prior art keywords
active layer
grid
array base
base palte
doped region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610817595.9A
Other languages
English (en)
Inventor
彭宽军
廖峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610817595.9A priority Critical patent/CN106298648A/zh
Publication of CN106298648A publication Critical patent/CN106298648A/zh
Priority to US15/751,131 priority patent/US20200091198A1/en
Priority to PCT/CN2017/092781 priority patent/WO2018045822A1/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种阵列基板及其制作方法、显示装置，涉及显示技术领域，通过该阵列基板的制作方法，可以将LTPS TFT的离子活化工艺和Oxide TFT的非晶态转变为微晶态的工艺集成在一起。一种阵列基板的制作方法，该方法包括：形成第一有源层；第一有源层的材料为多晶硅；至少向第一有源层的掺杂区进行离子注入，掺杂区用于与对应的源极和漏极电连接；形成第二有源层；第二有源层的材料为非晶态的金属氧化物；在至少向第一有源层的掺杂区进行离子注入、且在形成第二有源层之后，采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态。本发明适用于阵列基板、以及包括该阵列基板的显示装置的制作。

Description

一种阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
目前，户外可穿戴显示装置受到用户的欢迎。为了提高用户体验度，户外可穿戴显示装置需要满足低功耗、传感器集成、窄边框等各种要求。
显示装置一般包括：封装基板和阵列基板。阵列基板分为显示区域和包围显示区域的非显示区域(也可称为周边区域)；在非显示区域，采用LTPS TFT(Low TemperaturePoly-silicon-Thin Film Transistor，低温多晶硅薄膜晶体管)技术以实现窄边框和传感器电路集成；在显示区域，由于非晶态的Oxide TFT(Oxide Thin Film Transistor，氧化物薄膜晶体管)具有较小的漏电流(Ioff)，采用非晶态的Oxide TFT技术实现像素低频驱动以降低功耗。但是非晶态的Oxide TFT稳定性较差。为了提高稳定性，可以采用微晶态的OxideTFT替代非晶态的Oxide TFT。但是，目前LTPS TFT的制作工艺与微晶态的Oxide TFT的制作工艺是单独进行，工艺集成度低，生产成本高。
发明内容
本发明的实施例提供一种阵列基板及其制作方法、显示装置，通过该阵列基板的制作方法，可以将LTPS TFT的离子活化工艺和Oxide TFT的非晶态转变为微晶态的工艺集成在一起。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供了一种阵列基板的制作方法，所述方法包括：
形成第一有源层；所述第一有源层的材料为多晶硅；
至少向所述第一有源层的掺杂区进行离子注入，所述掺杂区用于与对应的源极和漏极电连接；
形成第二有源层；所述第二有源层的材料为非晶态的金属氧化物；
在至少向所述第一有源层的掺杂区进行离子注入、且在形成所述第二有源层之后，采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态。
可选的，所述方法还包括：
形成栅金属层，所述栅金属层包括：第一栅极和第二栅极；其中，所述第一栅极与所述第一有源层的位置对应，所述第二栅极与所述第二有源层位置对应；
形成源漏金属层，所述源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；所述第一源极和所述第一漏极分别与所述第一有源层电连接，所述第二源极和所述第二漏极分别与所述第二有源层电连接。
可选的，所述阵列基板分为：显示区域和包围所述显示区域的非显示区域；
所述第一有源层、所述第一栅极、所述第一源极和所述第一漏极均形成在所述非显示区域；
所述第二有源层、所述第二栅极、所述第二源极和所述第二漏极均形成在所述显示区域。
可选的，所述采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态包括：
可选的，所述至少向所述第一有源层的掺杂区进行离子注入具体为：
仅向所述第一有源层的掺杂区进行离子注入。
将所述阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。
可选的，所述金属氧化物为氧化锌、或者是在所述氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物。
可选的，所述方法的制作顺序依次为：形成第一有源层、形成栅金属层、至少向所述第一有源层的掺杂区进行离子注入、形成第二有源层、采用活化工艺、形成源漏金属层。
可选的，所述方法还包括：
在所述形成第一有源层之后、且在所述形成栅金属层之前，形成栅绝缘层，所述栅绝缘层覆盖所述第一有源层；
在所述至少向所述第一有源层的掺杂区进行离子注入之后、且在形成第二有源层之前，形成层间介质层，所述层间介质层覆盖所述栅金属层。
另一方面，提供了一种阵列基板,采用上述任一项所述的制作方法形成。
再一方面，提供了一种显示装置，包括：上述所述的阵列基板。
本发明的实施例提供了一种阵列基板及其制作方法、显示装置，通过该阵列基板的制作方法，可以在采用活化工艺将第一有源层注入的离子活化的同时，完成第二有源层的材料从非晶态转变为微晶态；即将LTPS TFT的离子活化工艺和Oxide TFT的非晶态转变为微晶态的工艺集成在一起，相较于现有技术，具有工艺集成度高，生产成本低的特点。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种阵列基板的制作方法流程图一；
图2为根据图1制作形成的一种阵列基板的结构示意图；
图3为本发明实施例提供的一种阵列基板的制作方法流程图二。
附图标记：
1-第一薄膜晶体管TFT1；2-第二薄膜晶体管TFT2；3-显示区域；4-非显示区域；5-栅绝缘层；6-层间介质层；7-衬底；8-平坦层；11-第一有源层；12-第一栅极；13-第一源极；14-第一漏极；21-第二有源层；22-第二栅极；23-第二源极；24-第二漏极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
实施例一
本发明实施例提供了一种阵列基板的制作方法，该方法包括：
S01、形成第一有源层；第一有源层的材料为多晶硅；这里对于形成第一有源层的具体方法不做限定，示例的，可以先形成非晶硅薄膜，然后对非晶硅薄膜进行激光照射以使非晶硅(a-硅)结晶转化成多晶硅(p-硅)，进而形成多晶硅薄膜。
S02、至少向第一有源层的掺杂区进行离子注入，该掺杂区用于与对应的源极和漏极电连接；这里，对于注入离子的方法和注入离子的类型不做限定。示例的，可以采用等离子体轰击的方法向第一有源层注入硼离子，以形成P型TFT；或者，还可以采用等离子体轰击的方法向第一有源层注入磷离子，以形成N型TFT，当然还可以是采用其他方法注入其他离子，这里仅以上述为例进行说明。
S03、形成第二有源层；第二有源层的材料为非晶态的金属氧化物；这里对于金属氧化物的具体材料不做限定，具体可以根据实际情况而定。需要说明的是，按照晶体的状态，可将金属氧化物分为非晶态、微晶态等，采用微晶态的金属氧化物形成的TFT相较于采用非晶态的金属氧化物形成的TFT具有更低的漏电流、更好的I-V(电流-电压)特性以及更好的稳定性。
需要说明的是，上述S03可以是在S01和S02之后进行，也可以是在S01和S02之前进行，这里不做限定。为了避免离子注入对于形成第二有源层的影响，参考图1所示，可以选择在S01和S02之后进行S03。
在S02、至少向第一有源层的掺杂区进行离子注入、且在S03、形成第二有源层之后，S04、采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态(即从a-金属氧化物转变为uc-金属氧化物)。
通过上述制作方法，可以在采用活化工艺将第一有源层注入的离子活化的同时，完成第二有源层的材料从非晶态转变为微晶态；即将LTPS TFT的离子活化工艺和OxideTFT的非晶态转变为微晶态的工艺集成在一起，相较于现有技术，具有工艺集成度高，生产成本低的特点。
可选的，上述方法还包括：
S05、形成栅金属层，栅金属层包括：第一栅极和第二栅极；其中，第一栅极与第一有源层的位置对应，第二栅极与第二有源层位置对应。这里对于形成栅金属层的具体方法不做限定。示例的，考虑到降低成本，可以通过一次构图工艺形成第一栅极和第二栅极，该第一栅极和第二栅极的材料可以是Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属。
S06、形成源漏金属层，源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；第一源极和第一漏极分别与第一有源层电连接，第二源极和第二漏极分别与第二有源层电连接。这里对于形成源漏金属层的具体方法不做限定。示例的，考虑到降低成本，可以通过一次构图工艺形成第一源极、第一漏极、第二源极和第二漏极，该源漏金属层的材料可以是Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属。
需要说明的是，上述S05、S06与S01-S04的制作顺序根据实际所要形成的TFT的结构有关。该TFT可以是顶栅结构(即栅极形成在有源层之上)，也可以是底栅结构(即栅极形成在有源层之下)，这里不做限定。为了便于描述，将第一有源层、第一栅极、第一源极和第一漏极形成的TFT称为第一薄膜晶体管TFT1，将第二有源层、第二栅极、第二源极和第二漏极形成的TFT称为第二薄膜晶体管TFT2。参考图2所示，TFT1为顶栅TFT，其包括第一有源层11、第一栅极12、第一源极13和第一漏极14；TFT2为底栅TFT，其包括第二有源层21、第二栅极22、第二源极23和第二漏极24。若要形成如图2所示的结构，则上述方法的制作顺序可以依次为：S01、形成第一有源层，S05、形成栅金属层，S02、至少向第一有源层的掺杂区进行离子注入，S03、形成第二有源层，S04、采用活化工艺，S06、形成源漏金属层。当然，上述TFT1和TFT2还可以是其他结构，本发明实施例以及附图均以图2所示的结构为例进行说明。
可选的，参考图2所示，上述阵列基板分为：显示区域3和包围显示区域的非显示区域4；第一有源层11、第一栅极12、第一源极13和第一漏极14(即TFT1)均形成在非显示区域4；在非显示区域中，一般会设置栅线驱动电路(又称GOA电路)、数据线驱动电路或者是传感器等，将上述TFT1应用在这些驱动电路或者是Multiplexer(多路复用器)中，有利于实现窄边框和传感器电路集成。第二有源层21、第二栅极22、第二源极23和第二漏极24(即TFT2)均形成在显示区域3，有利于实现像素低频驱动以降低功耗。另外，上述TFT1和TFT2还可用于形成CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件，例如：CMOS反相器等，这里不做限定，具体根据实际情况而定。
可选的，为了保证导通效果，S02、至少向第一有源层的掺杂区进行离子注入具体为：仅向第一有源层的掺杂区进行离子注入，其中，该掺杂区用于与第一源极和第一漏极电连接。
可选的，S04、采用活化工艺，以使得第一有源层中注入的离子活化、第二有源层的材料从非晶态转变为微晶态包括：
将阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。即该活化工艺主要是采用高温活化工艺以完成第一有源层的掺杂区的离子活化和第二有源层的材料的非晶态到微晶态的转变。示例的，该环境温度可以是600℃，持续时间可以是1.0h，具体可以根据实际情况而定。
可选的，为了降低成本，金属氧化物可以为氧化锌(ZnO)，或者是在氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物，例如：铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)、镁铟锌氧化物(MIZO)、铟锌氧化物(IZO)等。当然，还可以是在氧化锌中掺杂有其他金属，这里仅以上述为例进行说明。
可选的，上述方法的制作顺序依次为：S01、形成第一有源层，S05、形成栅金属层，S02、至少向第一有源层的掺杂区进行离子注入，S03、形成第二有源层，S04、采用活化工艺，S06、形成源漏金属层，以形成图2所示的结构。需要说明的是，图2所示的结构中，第一有源层的掺杂区是指未被第一栅极遮挡的部分；由于第一栅极的遮挡作用，通过上述制作顺序，可以很容易地实现仅向第一有源层的掺杂区进行离子注入。
可选的，参考图3所示，上述方法还包括：
在S01、形成第一有源层之后、且在S05、形成栅金属层之前，S07、形成如图2所示的栅绝缘层5，栅绝缘层5覆盖第一有源层11，以保护第一有源层。这里对于栅绝缘层的具体形成方式不做限定，示例的，可以采用CVD(Chemical Vapor Deposition，化学气相沉积)法形成栅绝缘层，该栅绝缘层的材料可以是氧化硅、氮化硅及有机材料等绝缘材料。
在S02、至少向所述第一有源层的掺杂区进行离子注入之后、且在S03、形成第二有源层之前，S08、形成如图2所示的层间介质层6(又称ILD层)，层间介质层6覆盖栅金属层(即第一栅极12和第二栅极22)，以保护栅金属层。该层间介质层的材料可以是氧化硅、氮化硅及有机材料等绝缘材料。
上述阵列基板还可以包括图2所示的衬底7，TFT1和TFT2均形成在衬底7上；当然，为了能够产生电场，上述阵列基板还可以包括像素电极和\或公共电极；进一步的，为了避免TFT1的第一有源层受光线影响，上述阵列基板还可以包括设置在TFT1的第一有源层之下的遮光层(Light Shield)等，这里仅详细介绍与发明点相关的结构，其余结构可参考现有技术。
实施例二
本发明实施例提供了一种阵列基板，该阵列基板采用实施例一提供的任一项的制作方法形成。该阵列基板具有工艺集成度高，生产成本低的特点。该阵列基板可以是普通的阵列基板，也可以是COA(Color Filter on Array)基板，COA基板指把彩膜层做在阵列基板上的基板，这里不做限定。
通过调整实施例一中制作方法的顺序，可以形成多种结构的阵列基板。下面提供一具体结构的阵列基板。参考图2所示，该阵列基板包括：衬底7，在衬底7上依次设置的第一有源层11、覆盖第一有源层11的栅绝缘层5、栅金属层(第一栅极12和第二栅极22)、覆盖栅金属层的层间介质层6、源漏金属层，其中，源漏金属层包括：第一源极13和第一漏极14、第二源极23和第二漏极24，第一源极13和第一漏极14通过贯穿层间介质层6和栅绝缘层5的过孔与第一有源层11电连接，第二源极23和第二漏极24与第一有源层11直接接触实现电连接。当然，为了便于后续膜层的制作，例如像素电极、公共电极等，参考图2所示，上述阵列基板还包括：覆盖源漏金属层的平坦层8，该平坦层具有平坦化和绝缘作用，其材料可以是有机绝缘材料。
实施例三
本发明实施例提供了一种显示装置，包括：实施例二提供的阵列基板。上述显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。该显示装置具有工艺集成度高，生产成本低，功耗低，稳定性高的特点。另外，这里对于该显示装置的尺寸和应用场景不做限定；其可以是大尺寸显示装置，还可以是小尺寸、可穿戴显示装置，例如：手环等；其可以应用在室内，也可以应用在户外，由于该显示装置具有功耗低的特点，应用在户外更显优势。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

1.一种阵列基板的制作方法，其特征在于，所述方法包括：
形成第一有源层；所述第一有源层的材料为多晶硅；
至少向所述第一有源层的掺杂区进行离子注入，所述掺杂区用于与对应的源极和漏极电连接；
形成第二有源层；所述第二有源层的材料为非晶态的金属氧化物；
在至少向所述第一有源层的掺杂区进行离子注入、且在形成所述第二有源层之后，采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态。
2.根据权利要求1所述的制作方法，其特征在于，所述方法还包括：
形成栅金属层，所述栅金属层包括：第一栅极和第二栅极；其中，所述第一栅极与所述第一有源层的位置对应，所述第二栅极与所述第二有源层位置对应；
形成源漏金属层，所述源漏金属层包括：第一源极和第一漏极、第二源极和第二漏极；所述第一源极和所述第一漏极分别与所述第一有源层电连接，所述第二源极和所述第二漏极分别与所述第二有源层电连接。
3.根据权利要求2所述的制作方法，其特征在于，所述阵列基板分为：显示区域和包围所述显示区域的非显示区域；
所述第一有源层、所述第一栅极、所述第一源极和所述第一漏极均形成在所述非显示区域；
所述第二有源层、所述第二栅极、所述第二源极和所述第二漏极均形成在所述显示区域。
4.根据权利要求1所述的制作方法，其特征在于，所述至少向所述第一有源层的掺杂区进行离子注入具体为：
仅向所述第一有源层的掺杂区进行离子注入。
5.根据权利要求1所述的制作方法，其特征在于，所述采用活化工艺，以使得所述第一有源层中注入的离子活化、所述第二有源层的材料从非晶态转变为微晶态包括：
将所述阵列基板所处的环境温度调节至550℃-650℃，并持续0.5h-1.0h。
6.根据权利要求1所述的制作方法，其特征在于，所述金属氧化物为氧化锌、或者是在所述氧化锌中掺杂有铟、镓、锡、镁中的至少一种的金属氧化物。
7.根据权利要求1-6任一项所述的制作方法，其特征在于，所述方法的制作顺序依次为：形成第一有源层、形成栅金属层、至少向所述第一有源层的掺杂区进行离子注入、形成第二有源层、采用活化工艺、形成源漏金属层。
8.根据权利要求7所述的制作方法，其特征在于，所述方法还包括：
在所述形成第一有源层之后、且在所述形成栅金属层之前，形成栅绝缘层，所述栅绝缘层覆盖所述第一有源层；
在所述至少向所述第一有源层的掺杂区进行离子注入之后、且在形成第二有源层之前，形成层间介质层，所述层间介质层覆盖所述栅金属层。
9.一种阵列基板，其特征在于，采用权利要求1-8任一项所述的制作方法形成。
10.一种显示装置，其特征在于，包括：权利要求9所述的阵列基板。
CN201610817595.9A 2016-09-12 2016-09-12 一种阵列基板及其制作方法、显示装置 Pending CN106298648A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610817595.9A CN106298648A (zh) 2016-09-12 2016-09-12 一种阵列基板及其制作方法、显示装置
US15/751,131 US20200091198A1 (en) 2016-09-12 2017-07-13 Array substrate, manufacturing method thereof, and display device
PCT/CN2017/092781 WO2018045822A1 (zh) 2016-09-12 2017-07-13 阵列基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610817595.9A CN106298648A (zh) 2016-09-12 2016-09-12 一种阵列基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
CN106298648A true CN106298648A (zh) 2017-01-04

Family

ID=57710093

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610817595.9A Pending CN106298648A (zh) 2016-09-12 2016-09-12 一种阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US20200091198A1 (zh)
CN (1) CN106298648A (zh)
WO (1) WO2018045822A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106952928A (zh) * 2017-03-30 2017-07-14 深圳市华星光电技术有限公司 一种tft背板的制作方法及tft背板
WO2018045822A1 (zh) * 2016-09-12 2018-03-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN109887936A (zh) * 2019-03-25 2019-06-14 合肥京东方光电科技有限公司 阵列基板及其制作方法
WO2019174333A1 (zh) * 2018-03-15 2019-09-19 京东方科技集团股份有限公司 制作阵列基板的方法、阵列基板和显示装置
CN110993613A (zh) * 2019-11-27 2020-04-10 武汉华星光电技术有限公司 阵列基板及其制造方法
CN111081719A (zh) * 2019-12-12 2020-04-28 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN112331680A (zh) * 2020-11-13 2021-02-05 武汉华星光电技术有限公司 阵列基板及其制备方法
CN113611712A (zh) * 2021-07-29 2021-11-05 武汉华星光电技术有限公司 阵列基板、显示面板及其制作方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123654A (zh) * 2017-05-26 2017-09-01 京东方科技集团股份有限公司 阵列基板及其制备方法和显示装置
CN208422916U (zh) * 2018-08-07 2019-01-22 京东方科技集团股份有限公司 阵列基板及显示装置
CN111524927B (zh) * 2020-04-30 2023-10-24 京东方科技集团股份有限公司 驱动基板及其制备方法和显示装置
CN112951845A (zh) * 2021-01-25 2021-06-11 武汉华星光电技术有限公司 阵列基板
CN114927532B (zh) * 2022-04-27 2023-04-21 惠科股份有限公司 阵列基板及其制作方法和显示面板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080230770A1 (en) * 2007-03-20 2008-09-25 Young-Soo Yoon Organic light-emitting display panel and method of manufacturing the same
CN104867921A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板及利用该薄膜晶体管基板的显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI224868B (en) * 2003-10-07 2004-12-01 Ind Tech Res Inst Method of forming poly-silicon thin film transistor
US20070173040A1 (en) * 2006-01-09 2007-07-26 Freescale Semiconductor, Inc. Method of reducing an inter-atomic bond strength in a substance
KR101082174B1 (ko) * 2009-11-27 2011-11-09 삼성모바일디스플레이주식회사 유기전계발광 표시 장치 및 그의 제조 방법
TWI611463B (zh) * 2016-06-29 2018-01-11 友達光電股份有限公司 金屬氧化物半導體層的結晶方法及半導體結構
CN106169481B (zh) * 2016-07-20 2019-04-05 武汉华星光电技术有限公司 柔性阵列基板及其制备方法、柔性显示装置
CN106298648A (zh) * 2016-09-12 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080230770A1 (en) * 2007-03-20 2008-09-25 Young-Soo Yoon Organic light-emitting display panel and method of manufacturing the same
CN104867921A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板及利用该薄膜晶体管基板的显示装置

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018045822A1 (zh) * 2016-09-12 2018-03-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
US10347666B2 (en) 2017-03-30 2019-07-09 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for fabricating a TFT backplane and TFT backplane
WO2018176589A1 (zh) * 2017-03-30 2018-10-04 深圳市华星光电技术有限公司 一种tft背板的制作方法及tft背板
CN106952928B (zh) * 2017-03-30 2018-10-23 深圳市华星光电技术有限公司 一种tft背板的制作方法及tft背板
CN106952928A (zh) * 2017-03-30 2017-07-14 深圳市华星光电技术有限公司 一种tft背板的制作方法及tft背板
WO2019174333A1 (zh) * 2018-03-15 2019-09-19 京东方科技集团股份有限公司 制作阵列基板的方法、阵列基板和显示装置
US11923382B2 (en) 2018-03-15 2024-03-05 Boe Technology Group Co., Ltd. Method of fabricating array substrate, array substrate and display device
CN109887936A (zh) * 2019-03-25 2019-06-14 合肥京东方光电科技有限公司 阵列基板及其制作方法
US11393853B2 (en) 2019-03-25 2022-07-19 Hefei Boe Optoelectronics Technology Co., Ltd. Array substrate and manufacturing method thereof
CN110993613A (zh) * 2019-11-27 2020-04-10 武汉华星光电技术有限公司 阵列基板及其制造方法
CN111081719A (zh) * 2019-12-12 2020-04-28 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN112331680A (zh) * 2020-11-13 2021-02-05 武汉华星光电技术有限公司 阵列基板及其制备方法
CN113611712A (zh) * 2021-07-29 2021-11-05 武汉华星光电技术有限公司 阵列基板、显示面板及其制作方法
CN113611712B (zh) * 2021-07-29 2023-10-17 武汉华星光电技术有限公司 阵列基板、显示面板及其制作方法

Also Published As

Publication number Publication date
WO2018045822A1 (zh) 2018-03-15
US20200091198A1 (en) 2020-03-19

Similar Documents

Publication Publication Date Title
CN106298648A (zh) 一种阵列基板及其制作方法、显示装置
CN113257840B (zh) 显示设备
US9502517B2 (en) Array substrate and fabrication method thereof, and display device
CN105931988B (zh) Amoled像素驱动电路的制作方法
US9589995B2 (en) TFT substrate having three parallel capacitors
CN109326624B (zh) 像素电路、其制造方法及显示装置
CN103094354B (zh) 阵列基板及其制造方法、显示装置
CN105702623B (zh) Tft阵列基板的制作方法
KR102089244B1 (ko) 더블 게이트형 박막 트랜지스터 및 이를 포함하는 유기 발광 다이오드 표시장치
CN107331669A (zh) Tft驱动背板的制作方法
US20150372021A1 (en) Display device, array substrate and method for manufacturing the same
US20160027801A1 (en) Array substrate, manufacturing method thereof and display panel
CN106252362B (zh) 一种阵列基板及其制备方法
CN104538458A (zh) 一种显示装置、阵列基板、薄膜晶体管及其制作方法
US20170294459A1 (en) Display device
CN103745954B (zh) 显示装置、阵列基板及其制造方法
US20130134514A1 (en) Thin film transistor and method for fabricating the same
CN109427820A (zh) 一种基板及其制备方法、显示面板
US20160079326A1 (en) Pixel structure of electroluminescent display panel and method of fabricating the same
CN105070729A (zh) 一种阵列基板和显示装置
WO2018023955A1 (zh) Oled显示装置的阵列基板及其制造方法
CN110190071B (zh) 显示基板及其制备方法、显示装置
US9997580B2 (en) Pixel structure and manufacturing method thereof, array substrate, display device
CN104103646A (zh) 一种低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置
CN105336626A (zh) 与数据线导通的薄膜晶体管的制备方法及薄膜晶体管

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170104

RJ01 Rejection of invention patent application after publication