WO2019179128A1 - 阵列基板的制造方法、阵列基板、显示面板和显示装置 - Google Patents

阵列基板的制造方法、阵列基板、显示面板和显示装置 Download PDF

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WO2019179128A1
WO2019179128A1 PCT/CN2018/114396 CN2018114396W WO2019179128A1 WO 2019179128 A1 WO2019179128 A1 WO 2019179128A1 CN 2018114396 W CN2018114396 W CN 2018114396W WO 2019179128 A1 WO2019179128 A1 WO 2019179128A1
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Prior art keywords
pattern
metal
substrate
layer
photoresist
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PCT/CN2018/114396
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English (en)
French (fr)
Inventor
付方彬
郭会斌
白金超
王守坤
韩皓
贾宜訸
宋勇志
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/471,619 priority Critical patent/US20210366940A1/en
Publication of WO2019179128A1 publication Critical patent/WO2019179128A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, a display panel, and a display device.
  • a plurality of arrayed pixel units are generally disposed on the array substrate in the display panel, and each of the pixel units is respectively connected to the gate lines and the data lines disposed on the array substrate.
  • Each of the pixel units includes a Thin Film Transistor (TFT), and each of the TFTs includes a gate pattern, an active layer pattern, and a source and drain pattern.
  • the gate lines, the data lines, the gate patterns, and the source and drain patterns are generally metal patterns formed using a metal material.
  • a metal pattern in the array substrate is usually formed by a photolithography process.
  • a metal layer is first formed on the substrate, and then the metal layer is sequentially subjected to photoresist coating, exposure, development, etching, and photoresist stripping to obtain the metal. pattern.
  • the photoresist is typically stripped by dry etching.
  • the photoresist when the photoresist is stripped by dry etching, the photoresist may react with the metal layer to affect the electrical conductivity of the finally formed metal pattern.
  • Embodiments of the present application provide an array substrate manufacturing method, an array substrate, a display panel, and a display device.
  • the technical solution of the embodiment of the present application is as follows:
  • a method of fabricating an array substrate comprising:
  • the base substrate on which the metal layer, the protective layer and the photoresist are formed is processed by a photolithography process to obtain a metal pattern.
  • the metal pattern is a source/drain metal pattern; before the metal layer is formed on the substrate, the method further comprises: forming an active layer on the substrate.
  • the forming a metal layer on the base substrate comprises: forming the metal layer on a side of the active layer away from the base substrate.
  • the material forming the protective layer is a transparent insulating material.
  • the insulating material does not react with the metal material used to form the metal layer.
  • the metal material forming the metal layer is copper.
  • the material forming the protective layer is silicon nitride or silicon dioxide.
  • the forming a protective layer on a side of the metal layer away from the substrate substrate comprises:
  • a protective layer is formed on the side of the metal layer away from the base substrate by magnetron sputtering.
  • the substrate substrate formed with the metal layer, the protective layer and the photoresist is processed by a photolithography process to obtain a metal pattern, including:
  • the photoresist pattern is removed by dry etching to obtain the metal pattern.
  • the metal pattern is a source/drain metal pattern; before the metal layer is formed on the substrate, the method further comprises: forming an active layer on the substrate;
  • Performing an exposure process on the photoresist to obtain a photoresist pattern including:
  • the method further includes:
  • a portion of the remaining active layer that is not covered by the remaining photoresist pattern is formed by dry etching.
  • the metal pattern is away from the substrate
  • a protective layer pattern is also formed on one side, and the method further includes:
  • the material forming the passivation layer is the same as the material forming the protective layer.
  • an array substrate comprising:
  • a protective layer pattern on a side of the metal pattern away from the base substrate, the protective layer pattern for protecting the metal pattern.
  • an orthographic projection of the protective layer pattern on the substrate substrate coincides with an orthographic projection of the metal pattern on the substrate substrate.
  • the metal pattern is a source/drain metal pattern; the array substrate further includes: an active layer pattern on a side of the metal pattern adjacent to the substrate.
  • the array substrate further includes: a passivation layer on a side of the protective layer pattern away from the base substrate.
  • the material forming the protective layer pattern is a transparent insulating material, and the insulating material does not react with the metal material for forming the metal pattern.
  • the metal material forming the metal pattern is copper.
  • the material forming the protective layer pattern is silicon nitride or silicon dioxide.
  • a display panel comprising: the array substrate of the other aspect described above.
  • a display device comprising: the display panel according to the above aspect.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present application
  • FIG. 2 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a process of forming an array substrate according to an embodiment of the present application.
  • FIG. 4 is a schematic view of the photoresist after exposure processing and development processing in sequence according to an embodiment of the present application
  • FIG. 5 is a schematic view of the embodiment of the present application after removing a portion of the protective layer that is not covered by the photoresist pattern;
  • FIG. 6 is a schematic view of a portion of a metal layer removed from a photoresist layer without being covered by a photoresist pattern according to an embodiment of the present application;
  • FIG. 7 is a schematic view of the embodiment of the present application after removing a portion of the active layer that is not covered by the photoresist pattern;
  • FIG. 8 is a schematic diagram of the half exposed portion in the photoresist pattern removed and the portion of the remaining protective layer covered by the half exposed portion provided by the embodiment of the present application;
  • FIG. 9 is a schematic view of the embodiment of the present application after removing a portion of the remaining metal layer that is not covered by the remaining photoresist pattern;
  • FIG. 10 is a schematic diagram of a portion of a remaining active layer that is not covered by a remaining photoresist pattern after forming a recess according to an embodiment of the present application;
  • FIG. 11 is a schematic view of the photoresist pattern after removing the photoresist pattern provided by the embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • the photoresist in addition to stripping the photoresist by dry etching, the photoresist can be stripped by wet etching.
  • the etching solution may be etched to the metal layer for forming the source/drain metal pattern, so that The metal of the metal layer diffuses into the channel of the TFT, affecting the electrical characteristics of the channel of the TFT.
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application. As shown in FIG. 1 , the method may include the following steps.
  • step 101 a metal layer is formed on the base substrate.
  • a layer of metallic copper may be deposited on the substrate as a metal layer by a magnetron sputtering process.
  • a protective layer is formed on a side of the metal layer away from the substrate, and the protective layer is used to protect the metal layer.
  • the material forming the protective layer may be a transparent insulating material, and the insulating material does not react with the metal material for forming the metal layer.
  • step 103 a photoresist is formed on a side of the protective layer away from the substrate.
  • the photoresist may be a photosensitive resin material.
  • step 104 the base substrate on which the metal layer, the protective layer and the photoresist are formed is processed by a photolithography process to obtain a metal pattern.
  • the metal pattern may be a gate line, a data line, a gate pattern, or a source-drain pattern.
  • the lithography process may include: exposure, development, etching, and photoresist stripping, and the photoresist stripping process may be a dry etching process.
  • the method for fabricating the array substrate may protect the metal layer from being formed by forming a protective layer between the metal layer and the photoresist when the array substrate is manufactured.
  • the photoresist is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer to ensure the electrical conductivity of the finally formed metal pattern.
  • FIG. 2 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present application.
  • the embodiment of the present application is mainly described by taking a source-drain metal pattern in an array substrate as an example. Referring to Figure 2, the method includes the following steps:
  • step 201 an active layer is formed on the base substrate.
  • the base substrate may be a transparent glass substrate, and the material forming the active layer may be amorphous silicon (a-Si).
  • FIG. 3 is a schematic diagram of a process for forming an array substrate according to an embodiment of the present application.
  • a plasma enhanced chemical vapor deposition (PECVD) process may be used first.
  • a certain thickness of the amorphous silicon layer 021 is deposited on the base substrate 01, and then a higher conductivity ohmic contact layer 022 is deposited on the side of the amorphous silicon layer 021 away from the substrate 101 by a PECVD process.
  • PECVD plasma enhanced chemical vapor deposition
  • the ohmic contact layer 022 may be a heavily doped N-type semiconductor layer, for example, the ohmic contact layer 022 may be a phosphorus-doped amorphous silicon doped layer, and the amorphous silicon layer 021 and the ohmic contact layer 022 may constitute the active layer 02.
  • a gate metal pattern 03 and a gate insulating layer 04 have been formed on the base substrate 01; correspondingly, the active layer 02 may be formed on the gate insulating layer 04. It is away from the side of the base substrate 01.
  • a metal layer is formed on a side of the active layer away from the substrate.
  • a metal layer may be deposited on the side of the active layer away from the substrate by using a magnetron sputtering process.
  • the metal material forming the metal layer may be copper.
  • the metal layer 05 may be formed on the side of the active layer 02 away from the base substrate 01.
  • a protective layer is formed on a side of the metal layer away from the substrate.
  • a protective layer may be formed on the side of the metal layer away from the substrate by magnetron sputtering.
  • the protective layer is mainly used to protect the metal layer from direct contact with the photoresist.
  • the material forming the protective layer may be an insulating material, and the insulating material does not react with the metal material for forming the metal layer, so that the influence of the protective layer on the conductive characteristics of the finally formed metal pattern can be avoided.
  • the insulating material forming the protective layer may be a transparent material, so that the influence of the protective layer on the transmittance of the array substrate can be avoided, thereby avoiding the transmittance of the protective layer to the display panel including the array substrate. influences.
  • the insulating material can be etched away by a dry etching process to ensure that the protective layer can be stripped.
  • the material forming the protective layer may be silicon nitride (SiNX) or silicon dioxide (SiO 2 ).
  • the protective layer 06 may be formed on the side of the metal layer 05 away from the base substrate 01.
  • step 204 a photoresist is formed on a side of the protective layer away from the substrate.
  • a layer of photoresist 07 may be applied on the side of the protective layer 06 away from the substrate 101.
  • the photoresist 07 may cover the protective layer 06 in a whole layer.
  • the photoresist 07 may be formed of a photosensitive resin material, and the photoresist 07 may be a positive photoresist or a negative photoresist.
  • step 205 the photoresist is sequentially subjected to exposure processing and development processing to obtain a photoresist pattern.
  • the photoresist may be exposed by using a mask having a light-transmissive region or an opaque region having the same shape as the metal pattern according to the shape of the metal pattern to be formed, and the developer is used.
  • the exposed photoresist is developed to obtain a photoresist pattern.
  • the mask 10 may further include a semi-transmissive region 10a, and the semi-transmissive region 10a is lining
  • the orthographic projection on the base substrate coincides with the area of the channel where the TFT is to be formed.
  • 4 is a schematic view of the photoresist 07 sequentially subjected to exposure processing and development processing according to an embodiment of the present application. Accordingly, after developing the exposed photoresist 07 with a developing solution, a photoresist pattern can be obtained. 071.
  • the photoresist pattern 071 may include a half exposure portion 0711.
  • a mask-type resist photoresist 07 having the same opaque region 10b as that of the source-drain metal pattern to be formed may be employed. Performing an exposure process, and developing the photoresist 07 after the exposure to obtain a photoresist pattern 071 as shown in FIG. 4; if the photoresist 07 is a negative photoresist, it may be used to form The mask of the light-transmissive region having the same shape of the source-drain metal pattern exposes the photoresist, and the photoresist after the exposure is developed to obtain a photoresist pattern 071 as shown in FIG.
  • step 206 the portion of the protective layer that is not covered by the photoresist pattern is removed by dry etching.
  • the portion of the protective layer 06 shown in FIG. 4 that is not covered by the photoresist pattern 071 may be removed by dry etching.
  • FIG. 5 illustrates that the protective layer 06 is not lithographically removed.
  • step 207 the portion of the metal layer not covered by the photoresist pattern is removed by wet etching.
  • a portion of the metal layer 05 shown in FIG. 5 that is not covered by the photoresist pattern 071 may be removed by wet etching.
  • FIG. 6 illustrates that the metal layer 05 is not lithographically removed.
  • the film layer formed by removing the non-metal material is generally removed by dry etching, and the film layer formed of the metal material is removed by wet etching.
  • step 208 the portion of the active layer not covered by the photoresist pattern, the half exposed portion of the photoresist pattern, and the portion of the remaining protective layer covered by the half exposed portion are removed by dry etching. .
  • the half exposure portion is located in a region for forming a channel of the TFT.
  • the orthographic portion of the half-exposed portion on the active layer coincides with the region on the active layer for forming the channel of the TFT.
  • the portion of the active layer 02 shown in FIG. 6 that is not covered by the photoresist pattern 071, the half-exposed portion 0711 in the photoresist pattern 071, and the remaining protection may be removed by dry etching.
  • FIG. 7 shows a schematic view after removing a portion of the active layer 02 that is not covered by the photoresist pattern 071
  • FIG. 8 shows a portion of the active layer 02 that is not covered by the photoresist pattern 071
  • the embodiment of the present application is to remove the half-exposed portion 0711 in the photoresist pattern 071 by dry etching, and the portion of the remaining protective layer 06 covered by the half-exposure portion 0711 as an example, and may also be The half-exposed portion 0711 in the photoresist pattern 071 shown in FIG. 7, and the portion of the remaining protective layer 06 covered by the half-exposed portion 0711 are subjected to ashing treatment to remove the half-exposed portion 0711 in the photoresist pattern 071. And the portion of the remaining protective layer 06 covered by the half-exposed portion 0711.
  • step 209 the portion of the remaining metal layer that is not covered by the remaining photoresist pattern is removed by wet etching.
  • the portion of the remaining metal layer 05 shown in FIG. 8 that is not covered by the remaining photoresist pattern 0712 may be removed by wet etching.
  • FIG. 9 illustrates the removal of the remaining metal layer.
  • step 210 a portion of the remaining active layer that is not covered by the remaining photoresist pattern is formed by dry etching.
  • a portion of the remaining active layer 02 shown in FIG. 9 that is not covered by the remaining photoresist pattern 0712 may be formed by dry etching to form a trench of the TFT.
  • FIG. 10 shows a schematic view after a portion of the remaining active layer 02 that is not covered by the remaining photoresist pattern 0712 is formed into a groove (not shown in FIG. 10).
  • step 211 the photoresist pattern is removed by dry etching to obtain a metal pattern.
  • the remaining photoresist pattern 0712 shown in FIG. 10 may be removed by dry etching to obtain a metal pattern 051.
  • FIG. 11 shows a schematic view after removing the remaining photoresist pattern 0712. As shown in FIG. 11, after removing the remaining photoresist pattern 0712 shown in FIG. 10, the metal pattern 051 is away from the substrate 111. A protective layer pattern 061 is also formed on one side. The metal pattern 051 shown in FIG. 11 may be a source/drain metal pattern.
  • the metal pattern 051 and the protective layer pattern 061 are described in step 211. According to the description of the above steps 208 and 209, the protective layer pattern 061 is actually formed in step 208, and the metal pattern 051 is actually in the step. Formed in 209.
  • the protective layer pattern is disposed between the metal pattern and the photoresist, the metal pattern is not in direct contact with the photoresist, and therefore, when the photoresist pattern is removed by dry etching, The photoresist does not react with the metal pattern, thereby effectively ensuring the electrical conductivity of the finally formed metal pattern.
  • the photoresist pattern can also be removed by wet etching. Since the protective layer is disposed between the metal pattern and the photoresist pattern, the etching solution can be prevented from being etched into the metal pattern. It is possible to prevent the metal from diffusing into the TFT channel to affect its electrical characteristics, thereby effectively ensuring the performance of the finally formed metal pattern.
  • a passivation layer is formed on a side of the protective layer pattern away from the substrate.
  • a passivation (PVX) layer may be formed on the side of the protective layer pattern away from the substrate substrate by plasma enhanced chemical vapor deposition, and the passivation layer may also function as an electrolytic medium.
  • the material forming the passivation layer may be the same as the material forming the protective layer, for example, the material forming the passivation layer may be silicon nitride or silicon dioxide.
  • the passivation layer 08 may be formed on the side of the protective layer pattern 061 shown in FIG. 11 away from the base substrate 01, thereby obtaining an array substrate.
  • FIG. 12 is a schematic structural view showing an array substrate.
  • the protective layer pattern can be used as a part of the passivation layer.
  • the film thickness of the passivation layer may be smaller than the film thickness of the passivation layer which is required to be formed when the protective layer pattern is not provided, in order to avoid the influence of the setting of the protective layer pattern on the characteristics of the passivation layer.
  • the film thickness of the passivation layer can be controlled by controlling the time of deposition of the passivation layer material. When the passivation layer is formed by vapor deposition, when the deposition time of the passivation layer material is long, the final passivation layer is thicker, and the deposition time of the passivation layer material is proportional to the film thickness.
  • the method for fabricating the array substrate may protect the metal layer from being formed by forming a protective layer between the metal layer and the photoresist when the array substrate is manufactured.
  • the photoresist is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer to ensure the electrical conductivity of the finally formed metal pattern.
  • FIG. 12 is an embodiment of the present invention.
  • An array substrate can be manufactured by using the method for manufacturing the array substrate shown in FIG. 1 or FIG. 2 .
  • the array substrate may include: a base substrate 01; a metal pattern 051 on the base substrate 01; and a protective layer pattern 061 on a side of the metal pattern 051 away from the base substrate 01.
  • the protective layer pattern 061 is used to protect the metal pattern 051.
  • the array substrate formed by the embodiment of the present application forms a protective layer between the metal layer and the photoresist during the manufacturing process, and the protective layer can protect the metal layer to avoid the lithography.
  • the glue is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer, thereby ensuring the electrical conductivity of the finally formed metal pattern, thereby ensuring the array.
  • the performance of the substrate is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer, thereby ensuring the electrical conductivity of the finally formed metal pattern, thereby ensuring the array.
  • the orthographic projection of the protective layer pattern 061 on the substrate substrate 01 coincides with the orthographic projection of the metal pattern 051 on the substrate substrate 01.
  • the metal pattern 051 may be a source/drain metal pattern.
  • the array substrate may further include: an active layer pattern on a side of the metal pattern 051 near the substrate substrate 01. 023. And a gate pattern 02 and a gate insulating layer 04 between the active layer pattern 023 and the base substrate 01, and the gate insulating layer 04 is located between the gate pattern 02 and the active layer pattern 023.
  • the array substrate may further include: a passivation layer 08 on a side of the protective layer pattern 061 away from the substrate substrate 01.
  • the material forming the passivation layer 08 is the same as the material forming the protective layer pattern 061.
  • the material forming the protective layer pattern 061 is a transparent insulating material, and the insulating material does not react with the metal material for forming the metal pattern 051.
  • the metal material forming the metal pattern 051 may be copper; the material forming the protective layer pattern 061 may be silicon nitride or silicon dioxide.
  • the array substrate formed by the embodiment of the present application forms a protective layer between the metal layer and the photoresist during the manufacturing process, and the protective layer can protect the metal layer to avoid the lithography.
  • the glue is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer, thereby ensuring the electrical conductivity of the finally formed metal pattern, thereby ensuring the array.
  • the performance of the substrate is in direct contact with the metal layer, and when the photoresist is stripped by dry etching, the photoresist can be prevented from reacting with the metal layer, thereby ensuring the electrical conductivity of the finally formed metal pattern, thereby ensuring the array.
  • the embodiment of the present application provides a display panel, and the display panel may include: an array substrate as shown in FIG.
  • the display panel can be a liquid crystal display panel or an Organic Light-Emitting Diode (OLED) display panel.
  • OLED Organic Light-Emitting Diode
  • the embodiment of the present application provides a display device, which may include an array substrate as shown in FIG.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an OLED panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

Abstract

本申请公开了一种阵列基板的制造方法、阵列基板、显示面板和显示装置。所述方法包括：在衬底基板上形成金属层；在所述金属层远离所述衬底基板的一侧形成保护层，所述保护层用于保护所述金属层；在所述保护层远离所述衬底基板的一侧形成光刻胶；采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案。本申请通过在金属层和光刻胶之间形成保护层，保护层可以对金属层进行保护，避免光刻胶与金属层直接接触，在采用干法刻蚀的方式剥离光刻胶时，可以避免光刻胶与金属层发生反应，保证了最终形成的金属图案的导电性能。

Description

阵列基板的制造方法、阵列基板、显示面板和显示装置
本申请要求于2018年03月23日提交的申请号为201810247365.2、发明名称为“阵列基板及其制造方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板的制造方法、阵列基板、显示面板和显示装置。
背景技术
显示面板中的阵列基板上一般设置有多个阵列排布的像素单元，每个像素单元分别与阵列基板上设置的栅线和数据线连接。每个像素单元包括一个薄膜晶体管(Thin Film Transistor，TFT)，每个TFT包括栅极图案、有源层图案以及源漏极图案。栅线、数据线、栅极图案以及源漏极图案一般为采用金属材料形成的金属图案。
通常采用光刻工艺形成阵列基板中的金属图案。在形成金属图案的过程中，需要先在衬底基板上形成金属层，然后对该金属层依次进行光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等处理，以得到该金属图案。一般采用干法刻蚀的方式剥离光刻胶。
但是，采用干法刻蚀的方式剥离光刻胶时，该光刻胶可能与金属层发生反应，影响最终形成的金属图案的导电性能。
发明内容
本申请实施例提供了一种阵列基板制造方法、阵列基板、显示面板和显示装置。本申请实施例的技术方案如下：
一方面，提供了一种阵列基板的制造方法，所述方法包括：
在衬底基板上形成金属层；
在所述金属层远离所述衬底基板的一侧形成保护层，所述保护层用于保护所述金属层；
在所述保护层远离所述衬底基板的一侧形成光刻胶；
采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案。
可选地，所述金属图案为源漏极金属图案；在衬底基板上形成金属层之前，所述方法还包括：在所述衬底基板上形成有源层。
可选地，所述在衬底基板上形成金属层，包括：在所述有源层远离所述衬底基板的一侧形成所述金属层。
可选地，形成所述保护层的材料为透明的绝缘材料。
可选地，所述绝缘材料不与用于形成所述金属层的金属材料反应。
可选地，形成所述金属层的金属材料为铜。
可选地，形成所述保护层的材料为氮化硅或者二氧化硅。
可选地，所述在所述金属层远离所述衬底基板的一侧形成保护层，包括：
采用磁控溅射的方式在所述金属层远离所述衬底基板的一侧形成保护层。
可选地，所述采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案，包括：
对所述光刻胶依次进行曝光处理和显影处理，得到光刻胶图案；
采用干法刻蚀的方式去除所述保护层中未被所述光刻胶图案覆盖的部分；
采用湿法刻蚀的方式去除所述金属层中未被所述光刻胶图案覆盖的部分；
采用干法刻蚀的方式去除所述光刻胶图案得到所述金属图案。
可选地，所述金属图案为源漏极金属图案；在衬底基板上形成金属层之前，所述方法还包括：在所述衬底基板上形成有源层；
所述对所述光刻胶进行曝光处理，得到光刻胶图案，包括：
采用具有半透光区域的掩膜板对所述光刻胶进行曝光处理；
对曝光后的所述光刻胶进行显影处理，得到光刻胶图案，所述光刻胶图案中包括半曝光部分；
在采用干法刻蚀的方式去除所述光刻胶图案得到所述金属图案之前，所述方法还包括：
采用干法刻蚀的方式去除所述有源层中未被所述光刻胶图案覆盖的部分，所述光刻胶图案中的半曝光部分，以及剩余的所述保护层中被所述半曝光部分覆盖的部分；
采用湿法刻蚀的方式去除剩余的所述金属层中，未被剩余的所述光刻胶图案覆盖的部分；
采用干法刻蚀的方式，在剩余的所述有源层中未被剩余的所述光刻胶图案覆盖的部分形成凹槽。
可选地，在采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案之后，所述金属图案远离所述衬底基板的一侧还形成有保护层图案，所述方法还包括：
在所述保护层图案远离所述衬底基板的一侧形成钝化层；
形成所述钝化层的材料与形成所述保护层的材料相同。
另一方面，提供了一种阵列基板，所述阵列基板包括：
衬底基板；
位于所述衬底基板上的金属图案；以及，
位于所述金属图案远离所述衬底基板的一侧的保护层图案，所述保护层图案用于保护所述金属图案。
可选地，所述保护层图案在所述衬底基板上的正投影与所述金属图案在所述衬底基板上的正投影重合。
可选地，所述金属图案为源漏极金属图案；所述阵列基板还包括：位于所述金属图案靠近所述衬底基板的一侧的有源层图案。
可选地，所述阵列基板还包括：位于所述保护层图案远离所述衬底基板的一侧的钝化层。
可选地，形成所述保护层图案的材料为透明的绝缘材料，且所述绝缘材料不与用于形成所述金属图案的金属材料反应。
可选地，形成所述金属图案的金属材料为铜。
可选地，形成所述保护层图案的材料为氮化硅或者二氧化硅。
再一方面，提供了一种显示面板，所述显示面板包括：如上述另一方面所述的阵列基板。
又一方面，提供了一种显示装置，所述显示装置包括：如上述再一方面所述的显示面板。
附图说明
图1是本申请实施例提供的一种阵列基板的制造方法的流程图；
图2是本申请实施例提供的另一种阵列基板的制造方法的流程图；
图3是本申请实施例提供的一种形成阵列基板的过程中的示意图；
图4是本申请实施例提供的对光刻胶依次进行曝光处理和显影处理之后的示意图；
图5是本申请实施例提供的去除保护层中未被光刻胶图案覆盖的部分之后的示意图；
图6是本申请实施例提供的去除金属层中未被光刻胶图案覆盖的部分之后的示意图；
图7是本申请实施例提供的去除有源层中未被光刻胶图案覆盖的部分之后的示意图；
图8是本申请实施例提供的去除光刻胶图案中的半曝光部分，以及剩余的保护层中被半曝光部分覆盖的部分之后的示意图；
图9是本申请实施例提供的去除剩余的金属层中未被剩余的光刻胶图案覆盖的部分之后的示意图；
图10是本申请实施例提供的在剩余的有源层中未被剩余的光刻胶图案覆盖的部分形成凹槽之后的示意图；
图11是本申请实施例提供的去除光刻胶图案之后的示意图；
图12是本申请实施例提供的一种阵列基板的结构示意图。
具体实施方式
发明人所知，除采用干法刻蚀的方式剥离光刻胶之外，还可以采用湿法刻蚀的方式剥离光刻胶。但是在形成阵列基板中TFT的源漏极金属图案时，若采用湿法刻蚀的方式剥离光刻胶，刻蚀液可能会刻蚀到用于形成该源漏极金属图案的金属层，使得金属层的金属扩散到TFT的沟道，影响该TFT的沟道的电学特性。
图1是本申请实施例提供的一种阵列基板的制造方法的流程图，如图1所示，该方法可以包括如下步骤。
在步骤101中、在衬底基板上形成金属层。
例如，可以采用磁控溅射工艺在该衬底基板上沉积一层金属铜作为金属层。
在步骤102中、在该金属层远离衬底基板的一侧形成保护层，该保护层用于保护该金属层。
形成该保护层的材料可以是透明的绝缘材料，且该绝缘材料不与用于形成金属层的金属材料反应。
在步骤103中、在该保护层远离衬底基板的一侧形成光刻胶。
该光刻胶可以为感光树脂材料。
在步骤104中、采用光刻工艺对形成有金属层、保护层和光刻胶的衬底基板进行处理，得到金属图案。
该金属图案可以为栅线、数据线、栅极图案或者源漏极图案。该光刻工艺可以包括：曝光、显影、刻蚀以及光刻胶剥离，该光刻胶剥离的工艺可以为干法刻蚀工艺。
综上所述，本申请实施例提供的阵列基板的制造方法，由于在制造阵列基板时会在金属层和光刻胶之间形成保护层，该保护层可以对该金属层进行保护，避免该光刻胶与该金属层直接接触，进而在采用干法刻蚀的方式剥离光刻胶时，可以避免光刻胶与金属层发生反应，保证了最终形成的金属图案的导电性能。
图2是本申请实施例提供的另一种阵列基板的制造方法的流程图，本申请实施例主要以形成阵列基板中的源漏极金属图案为例进行说明。参见图2，该方法包括如下步骤：
在步骤201中、在衬底基板上形成有源层。
该衬底基板可以为透明的玻璃基板，形成该有源层的材料可以为非晶硅(a-Si)。
示例地，图3是本申请实施例提供的一种形成阵列基板的过程中的示意图，如图3所示，可以先采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺在衬底基板01上沉积一定厚度的非晶硅层021，然后采用PECVD工艺在该非晶硅层021远离衬底基板01的一侧沉积一层导电率较高的欧姆接触层022，该欧姆接触层022可以为重掺杂的N 型半导体层，例如欧姆接触层022可以为掺杂磷的非晶硅掺杂层，该非晶硅层021和该欧姆接触层022可以构成有源层02。
如图3所示，在形成该有源层02之前，该衬底基板01上已形成有栅极金属图案03和栅绝缘层04；相应的，该有源层02可以形成在栅绝缘层04远离衬底基板01的一侧。
在步骤202中、在有源层远离衬底基板的一侧形成金属层。
在本申请实施例中，可以采用磁控溅射工艺在有源层远离衬底基板的一侧沉积一层金属层。形成该金属层的金属材料可以为铜。
示例地，如图3所示，可以在有源层02远离衬底基板01的一侧形成金属层05。
在步骤203中、在金属层远离衬底基板的一侧形成保护层。
在本申请实施例中，可以采用磁控溅射的方式在金属层远离衬底基板的一侧形成保护层，该保护层主要用于保护金属层，避免该金属层与光刻胶直接接触。形成该保护层的材料可以为绝缘材料，且该绝缘材料不与用于形成金属层的金属材料反应，这样一来，可以避免保护层对最终形成的金属图案的导电特性的影响。进一步的，形成该保护层的绝缘材料可以为透明材料，这样一来，可以避免保护层对阵列基板的透光率的影响，从而避免保护层对包括该阵列基板的显示面板的透光率的影响。此外，该绝缘材料可以被干法刻蚀工艺刻蚀掉，以保证该保护层能够被剥离。在本申请实施例中，形成该保护层的材料可以为氮化硅(SiNX)或者二氧化硅(SiO 2)。
示例地，如图3所示，可以在金属层05远离衬底基板01的一侧形成保护层06。
在步骤204中、在保护层远离衬底基板的一侧形成光刻胶。
示例地，如图3所示，可以在保护层06远离衬底基板01的一侧涂覆一层光刻胶07。该光刻胶07可以整层覆盖该保护层06，该光刻胶07可以由感光树脂材料形成，且该光刻胶07可以为正性光刻胶或负性光刻胶。
在步骤205中、对光刻胶依次进行曝光处理和显影处理，得到光刻胶图案。
在本申请实施例中，可以根据待形成的金属图案的形状，采用具有与该金属图案的形状相同的透光区域或不透光区域的掩膜板对光刻胶进行曝光，并采用显影液对曝光后的光刻胶进行显影，从而得到光刻胶图案。
进一步的，若该待形成的金属图案为TFT中的源漏极金属图案，则如图3所示，该掩膜板10中还可以包括半透光区域10a，该半透光区域10a在衬底基板上的正投影与待形成TFT的沟道的区域重合。图4是本申请实施例提供的对光刻胶07依次进行曝光处理和显影处理之后的示意图，相应的，在采用显影液对曝光后的光刻胶07进行显影后，可以得到光刻胶图案071，该光刻胶图案071中可以包括半曝光部分0711。
若该光刻胶07为正性光刻胶，则如图3所示，可以采用具有与待形成的源漏极金属图案的形状相同的不透光区域10b的掩膜版对光刻胶07进行曝光处理，并对曝光之后的光刻胶07进行显影处理，得到如图4所示的光刻胶图案071；若该光刻胶07为负性光刻胶，则可以采用具有与待形成的源漏极金属图案的形状相同的透光区域的掩膜版对光刻胶进行曝光，并对曝光之后的光刻胶进行显影处理，得到如图4所示的光刻胶图案071。
在步骤206中、采用干法刻蚀的方式去除保护层中未被光刻胶图案覆盖的部分。
示例地，可以采用干法刻蚀的方式去除图4所示的保护层06中，未被光刻胶图案071覆盖的部分，进一步地，图5示出了去除保护层06中未被光刻胶图案071覆盖的部分之后的示意图。
在步骤207中、采用湿法刻蚀的方式去除金属层中未被光刻胶图案覆盖的部分。
示例地，可以采用湿法刻蚀的方式去除图5所示的金属层05中，未被光刻胶图案071覆盖的部分，进一步地，图6示出了去除金属层05中未被光刻胶图案071覆盖的部分之后的示意图。
在本申请实施例中，一般采用干法刻蚀的方式进行去除非金属材料形成的膜层，采用湿法刻蚀的方式去除金属材料形成的膜层。
在步骤208中、采用干法刻蚀的方式去除有源层中未被光刻胶图案覆盖的部分，光刻胶图案中的半曝光部分，以及剩余的保护层中被半曝光部分覆盖的部分。
该半曝光部分位于用于形成TFT的沟道的区域。换句话来讲，该半曝光部分在有源层上的正投影区域与有源层上用于形成TFT的沟道的区域重合。
示例地，可以采用干法刻蚀的方式去除图6所示的有源层02中，未被光 刻胶图案071覆盖的部分，光刻胶图案071中的半曝光部分0711，以及剩余的保护层06中被半曝光部分0711覆盖的部分。进一步地，图7示出了去除有源层02中未被光刻胶图案071覆盖的部分之后的示意图，图8示出了去除有源层02中未被光刻胶图案071覆盖的部分，光刻胶图案071中的半曝光部分0711，以及剩余的保护层06中被半曝光部分0711覆盖的部分之后的示意图。
本申请实施例是以采用干法刻蚀的方式去除光刻胶图案071中的半曝光部分0711，以及剩余的保护层06中被半曝光部分0711覆盖的部分为例进行说明的，还可以对图7所示的光刻胶图案071中的半曝光部分0711，以及剩余的保护层06中被半曝光部分0711覆盖的部分进行灰化处理，以去除光刻胶图案071中的半曝光部分0711，以及剩余的保护层06中被半曝光部分0711覆盖的部分。
在步骤209中、采用湿法刻蚀的方式去除剩余的金属层中未被剩余的光刻胶图案覆盖的部分。
示例地，可以采用湿法刻蚀的方式去除图8所示的剩余的金属层05中，未被剩余的光刻胶图案0712覆盖的部分，进一步地，图9示出了去除剩余的金属层05中未被剩余的光刻胶图案0712覆盖的部分之后的示意图。
在步骤210中、采用干法刻蚀的方式，在剩余的有源层中，未被剩余的光刻胶图案覆盖的部分形成凹槽。
示例地，可以采用干法刻蚀的方式，在图9所示的剩余的有源层02中未被剩余的光刻胶图案0712覆盖的部分形成凹槽，进而形成TFT的沟道。进一步地，图10示出了在剩余的有源层02中未被剩余的光刻胶图案0712覆盖的部分形成凹槽(图10中未标出)之后的示意图。
在步骤211中、采用干法刻蚀的方式去除光刻胶图案，得到金属图案。
示例地，可以采用干法刻蚀的方式去除图10所示的剩余的光刻胶图案0712，从而得到金属图案051。进一步地，图11示出了去除剩余的光刻胶图案0712之后的示意图，如图11所示，去除图10所示的剩余的光刻胶图案0712之后，该金属图案051远离衬底基板01的一侧还形成有保护层图案061。图11所示的金属图案051可以为源漏极金属图案。
本申请实施例在步骤211中对金属图案051和保护层图案061进行了描述，根据以上步骤208和步骤209的描述可知，保护层图案061实际在步骤208中已形成，金属图案051实际在步骤209中已形成。
在本申请实施例中，由于金属图案和光刻胶之间设置有保护层图案，则金属图案与光刻胶不直接接触，因此，在采用干法刻蚀的方式去除光刻胶图案时，该光刻胶不会和金属图案发生反应，从而有效的保证了最终形成的金属图案的导电性能。在本申请实施例中，还可以采用湿法刻蚀的方式去除光刻胶图案，由于金属图案和光刻胶图案之间设置有保护层，因此可以避免刻蚀液刻蚀到金属图案，进而可以避免金属扩散到TFT沟道中影响其电学特性，从而有效的保证了最终形成的金属图案的性能。
在步骤212中、在保护层图案远离衬底基板的一侧形成钝化层。
进一步的，可以采用等离子体增强化学的气相沉积法在保护层图案远离衬底基板的一侧形成钝化(Passivation，PVX)层，且该钝化层还可以充当电解介质。形成该钝化层的材料可以与形成保护层的材料相同，例如形成该钝化层的材料可以为氮化硅或者二氧化硅。
示例地，可以在图11所示的保护层图案061远离衬底基板01的一侧形成钝化层08，从而得到阵列基板，进一步地，图12是示出了一种阵列基板的结构示意图。
由于形成保护层图案的材料与形成钝化层的材料相同，因此该保护层图案可以作为钝化层的一部分。钝化层的膜厚可以小于未设置保护层图案时所需形成的钝化层的膜厚，以避免保护层图案的设置对钝化层的特性的影响。可以通过控制钝化层材料的沉积的时间来控制钝化层的膜厚。在采用气相沉积法形成钝化层时，当钝化层材料的沉积时间较长时，最终形成的钝化层会较厚，钝化层材料的沉积时间与其膜厚成正比。
综上所述，本申请实施例提供的阵列基板的制造方法，由于在制造阵列基板时会在金属层和光刻胶之间形成保护层，该保护层可以对该金属层进行保护，避免该光刻胶与该金属层直接接触，进而在采用干法刻蚀的方式剥离光刻胶时，可以避免光刻胶与金属层发生反应，保证了最终形成的金属图案的导电性能。
图12是本申请实施例提供了一种阵列基板，该阵列基板可以采用图1或图2所示的阵列基板的制造方法制造而成。如图12所示，该阵列基板可以包括：衬底基板01；位于该衬底基板01上的金属图案051；以及，位于该金属 图案051远离该衬底基板01的一侧的保护层图案061，该保护层图案061用于保护该金属图案051。
综上所述，本申请实施例提供的阵列基板，该阵列基板在制造过程中，金属层和光刻胶之间形成有保护层，该保护层可以对该金属层进行保护，避免该光刻胶与该金属层直接接触，进而在采用干法刻蚀的方式剥离光刻胶时，可以避免光刻胶与金属层发生反应，保证了最终形成的金属图案的导电性能，进而保证了该阵列基板的性能。
可选地，该保护层图案061在衬底基板01上的正投影与该金属图案051在衬底基板01上的正投影重合。
可选地，如图12所示，该金属图案051可以为源漏极金属图案；相应的，该阵列基板还可以包括：位于该金属图案051靠近衬底基板01的一侧的有源层图案023。以及，位于有源层图案023与衬底基板01之间的栅极图案02和栅绝缘层04，栅绝缘层04位于栅极图案02与有源层图案023之间。
可选地，如图12所示，该阵列基板还可以包括：位于保护层图案061远离衬底基板01的一侧的钝化层08。形成钝化层08的材料与形成保护层图案061的材料相同。
可选地，形成该保护层图案061的材料为透明的绝缘材料，且该绝缘材料不与用于形成金属图案051的金属材料反应。
可选地，形成金属图案051的金属材料可以为铜；形成保护层图案061的材料可以为氮化硅或者二氧化硅。
综上所述，本申请实施例提供的阵列基板，该阵列基板在制造过程中，金属层和光刻胶之间形成有保护层，该保护层可以对该金属层进行保护，避免该光刻胶与该金属层直接接触，进而在采用干法刻蚀的方式剥离光刻胶时，可以避免光刻胶与金属层发生反应，保证了最终形成的金属图案的导电性能，进而保证了该阵列基板的性能。
本申请实施例提供了一种显示面板，该显示面板可以包括：如图12所示的阵列基板。该显示面板可以为液晶显示面板或者有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板。
本申请实施例提供了一种显示装置，该显示装置可以包括：如图12所示的阵列基板。该显示装置可以为：液晶面板、OLED面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种阵列基板的制造方法，所述方法包括：
    在衬底基板上形成金属层；
    在所述金属层远离所述衬底基板的一侧形成保护层，所述保护层用于保护所述金属层；
    在所述保护层远离所述衬底基板的一侧形成光刻胶；
    采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案。
  2. 根据权利要求1所述的方法，其中，所述金属图案为源漏极金属图案；在衬底基板上形成金属层之前，所述方法还包括：
    在所述衬底基板上形成有源层。
  3. 根据权利要求2所述的方法，其中，所述在衬底基板上形成金属层，包括：在所述有源层远离所述衬底基板的一侧形成所述金属层。
  4. 根据权利要求1所述的方法，其中，形成所述保护层的材料为透明的绝缘材料。
  5. 根据权利要求4所述的方法，其中，所述绝缘材料不与用于形成所述金属层的金属材料反应。
  6. 根据权利要求5所述的方法，其中，形成所述金属层的金属材料为铜。
  7. 根据权利要求5所述的方法，其中，形成所述保护层的材料为氮化硅或者二氧化硅。
  8. 根据权利要求1至7任一所述的方法，其中，所述在所述金属层远离所述衬底基板的一侧形成保护层，包括：
    采用磁控溅射的方式在所述金属层远离所述衬底基板的一侧形成保护层。
  9. 根据权利要求1至7任一所述的方法，其中，所述采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案，包括：
    对所述光刻胶依次进行曝光处理和显影处理，得到光刻胶图案；
    采用干法刻蚀的方式去除所述保护层中未被所述光刻胶图案覆盖的部分；
    采用湿法刻蚀的方式去除所述金属层中未被所述光刻胶图案覆盖的部分；
    采用干法刻蚀的方式去除所述光刻胶图案得到所述金属图案。
  10. 根据权利要求9所述的方法，其中，所述金属图案为源漏极金属图案；在衬底基板上形成金属层之前，所述方法还包括：
    在所述衬底基板上形成有源层；
    所述对所述光刻胶依次进行曝光处理和显影处理，得到光刻胶图案，包括：
    采用具有半透光区域的掩膜板对所述光刻胶进行曝光处理；
    对曝光后的所述光刻胶进行显影处理，得到光刻胶图案，所述光刻胶图案中包括半曝光部分；
    在采用干法刻蚀的方式去除所述光刻胶图案得到所述金属图案之前，所述方法还包括：
    采用干法刻蚀的方式去除所述有源层中未被所述光刻胶图案覆盖的部分，所述光刻胶图案中的半曝光部分，以及剩余的所述保护层中被所述半曝光部分覆盖的部分；
    采用湿法刻蚀的方式去除剩余的所述金属层中未被剩余的所述光刻胶图案覆盖的部分；
    采用干法刻蚀的方式，在剩余的所述有源层中未被剩余的所述光刻胶图案覆盖的部分形成凹槽。
  11. 根据权利要求1至7任一所述的方法，其中，在采用光刻工艺对形成有所述金属层、所述保护层和所述光刻胶的衬底基板进行处理，得到金属图案之后，所述金属图案远离所述衬底基板的一侧还形成有保护层图案，所述方法 还包括：
    在所述保护层图案远离所述衬底基板的一侧形成钝化层；
    形成所述钝化层的材料与形成所述保护层的材料相同。
  12. 一种阵列基板，所述阵列基板包括：
    衬底基板；
    位于所述衬底基板上的金属图案；以及，
    位于所述金属图案远离所述衬底基板的一侧的保护层图案，所述保护层图案用于保护所述金属图案。
  13. 根据权利要求12所述的阵列基板，其中，所述保护层图案在所述衬底基板上的正投影与所述金属图案在所述衬底基板上的正投影重合。
  14. 根据权利要求12所述的阵列基板，其中，所述金属图案为源漏极金属图案；所述阵列基板还包括：位于所述金属图案靠近所述衬底基板的一侧的有源层图案。
  15. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括：
    位于所述保护层图案远离所述衬底基板的一侧的钝化层。
  16. 根据权利要求12至15任一所述的阵列基板，其中，形成所述保护层图案的材料为透明的绝缘材料，且所述绝缘材料不与用于形成所述金属图案的金属材料反应。
  17. 根据权利要求12至15任一所述的阵列基板，其中，形成所述金属图案的金属材料为铜。
  18. 根据权利要求12至15任一所述的阵列基板，其中，形成所述保护层图案的材料为氮化硅或者二氧化硅。
  19. 一种显示面板，所述显示面板包括权利要求12至18任一所述的阵列基板。
  20. 一种显示装置，所述显示装置包括权利要求19所述的显示面板。
PCT/CN2018/114396 2018-03-23 2018-11-07 阵列基板的制造方法、阵列基板、显示面板和显示装置 WO2019179128A1 (zh)

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CN109671631B (zh) * 2019-01-07 2020-02-14 成都中电熊猫显示科技有限公司 半导体制备工艺方法
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