WO2017024718A1 - 薄膜晶体管的制作方法和阵列基板的制作方法 - Google Patents

薄膜晶体管的制作方法和阵列基板的制作方法 Download PDF

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WO2017024718A1
WO2017024718A1 PCT/CN2015/098441 CN2015098441W WO2017024718A1 WO 2017024718 A1 WO2017024718 A1 WO 2017024718A1 CN 2015098441 W CN2015098441 W CN 2015098441W WO 2017024718 A1 WO2017024718 A1 WO 2017024718A1
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source
forming
fabricating
drain
photoresist
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PCT/CN2015/098441
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English (en)
French (fr)
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沈奇雨
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/307,827 priority Critical patent/US9881945B2/en
Publication of WO2017024718A1 publication Critical patent/WO2017024718A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method of fabricating a thin film transistor and a method of fabricating an array substrate.
  • the thin film transistor can be classified into an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, and an oxide semiconductor thin film transistor according to different active layer materials.
  • the oxide semiconductor thin film transistor has a large manufacturing process and a high electron mobility, and is widely used in a liquid crystal display.
  • the fabrication process of the oxide semiconductor thin film transistor includes: forming a gate metal layer in a first step, forming a pattern including a gate electrode through a patterning process; and forming a gate insulating layer on the gate electrode in the second step; An oxide semiconductor layer is formed, and a pattern including the active layer is formed through a patterning process; in the fourth step, a source/drain metal layer is formed on the active layer, and a pattern including a source and a drain is formed through a patterning process.
  • the source and drain metal layers are etched using an acidic etching solution to form a pattern including the source and the drain, so that the active layer serves as a channel during the etching process.
  • the region is directly exposed to the acidic etching solution, so that the acidic etching solution causes corrosion to the region, thereby affecting the electrical characteristics of the oxide semiconductor thin film transistor.
  • An object of the present invention is to provide a method for fabricating a thin film transistor and a method for fabricating an array substrate, thereby preventing corrosion of a region serving as a channel in an active layer during etching to form a source and a drain. .
  • a method of fabricating a thin film transistor is provided.
  • a method of fabricating a thin film transistor includes the steps of: fabricating a substrate; forming an oxide semiconductor layer on the substrate; forming a pattern including an active layer through a patterning process; forming on the active layer a source/drain metal layer; and a patterning process including forming a source and a drain, the pattern comprising a source formed between the source and the drain and the active layer as a channel The corresponding opening of the region; wherein the step of forming a pattern including the source and the drain through the patterning process comprises: removing a portion of the source/drain metal layer at the location of the opening by dry etching.
  • the source/drain metal layer at the position where the opening is located that is, the source/drain metal layer corresponding to the region serving as the channel in the active layer
  • an acidic etching solution is not required in the etching process, thereby effectively preventing the region used as a channel in the active layer from being corroded by the acidic etching solution during etching to form the source and the drain.
  • the electrical characteristics of the oxide semiconductor thin film transistor can be effectively improved.
  • the present invention also provides a method for fabricating an array substrate, which comprises a method of fabricating a thin film transistor as described above.
  • the method for fabricating the array substrate includes the method for fabricating the thin film transistor as described above, the method for fabricating the array substrate has the same advantageous effects as the method for fabricating the thin film transistor, and details are not described herein.
  • FIG. 1 is a schematic view of a substrate after forming a pattern including an active layer in an embodiment of the present invention
  • FIG. 2 is a schematic view of a substrate after forming a source/drain metal layer in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a substrate after forming a completely reserved region, a partially reserved region, and a completely removed region according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a substrate after removing a source/drain metal layer at a position where a completely removed region is located in an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a substrate after removing a portion of a photoresist in a reserved region according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a substrate after forming a pattern including a source and a drain in an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a substrate after forming a pattern including a gate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a substrate after forming a gate insulating layer according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a substrate after forming a first pixel electrode according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a substrate after forming a passivation layer according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a substrate after forming a second pixel electrode according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor, and the method for fabricating the thin film transistor includes:
  • a pattern including a source and a drain is formed through a patterning process, the pattern including an opening formed between the source and the drain corresponding to a region in the active layer to serve as a channel.
  • the step of forming a pattern including the source and the drain through a patterning process comprises: removing a portion of the source/drain metal layer at the position where the opening is located by dry etching.
  • the present invention provides a method for fabricating a thin film transistor.
  • the method for fabricating the thin film transistor is to remove the source/drain metal layer at the position of the opening by dry etching, that is, the area of the active layer used as a channel.
  • the source and drain metal layers so that an acidic etching solution is not required during the etching process, thereby effectively preventing the region used as a channel in the active layer during etching to form the source and the drain. It is corroded by an acidic etching solution, and the electrical characteristics of the oxide semiconductor thin film transistor can be effectively improved.
  • the source and drain metal layers at the position of the opening are removed by using dry etching, so that the etching barrier layer is not required, thereby enabling the source and the drain.
  • the opening between the openings is small, so that the channel length is small, which ensures the oxide semiconductor thin film transistor.
  • the electrical characteristics and the small size of the oxide semiconductor thin film transistor are advantageous for improving the aperture ratio and resolution of the display device.
  • the substrate in the embodiment of the present invention is a substrate substrate 1 and a collective name of a gate metal layer and a gate insulating layer formed on the substrate substantially 1, that is, the substrate includes the substrate 1 and is formed.
  • a gate metal layer and a gate insulating layer are on the substrate substantially 1.
  • an oxide semiconductor layer is deposited on the substrate by a plasma enhanced physical vapor deposition process; for example, the thickness of the oxide semiconductor layer may be 30 nm to 80 nm, and the material of the oxide semiconductor layer may be indium gallium zinc oxide .
  • a photoresist is coated on the formed oxide semiconductor layer and covered with a mask, and the photoresist is exposed and developed to pattern the photoresist.
  • the photoresist-free oxide semiconductor layer is removed by wet etching, and the photoresist is stripped to form a pattern including the active layer 2.
  • the photoresist layer covered by the photoresist may be removed by using an acidic etching solution, and the acidic etching solution may be a strong corrosive acid such as hydrochloric acid or sulfuric acid.
  • a source/drain metal layer may be deposited on the substrate on which the active layer 2 is formed by a plasma physical vapor deposition process.
  • the material of the source/drain metal layer may be a low-resistance metal such as copper or molybdenum which can be dry etched.
  • the structure of the substrate is as shown in FIG. 2.
  • the source/drain metal layer 3 covers the entire substrate.
  • the step of forming a pattern including the source and the drain through a patterning process before the portion of the source/drain metal layer at the position where the opening is removed by dry etching is removed Can include:
  • the photoresist with a mask and exposing to form a first region where the photoresist is not exposed at all, a second region where the photoresist is partially exposed, and a third region where the photoresist is completely exposed, wherein
  • the first zone 4 corresponds to the location of the source and the drain, the second zone 5 corresponds to the location of the opening, and the third zone 6 corresponds to other locations;
  • a portion of the source and drain metal layers at the position where the photoresist is completely removed is removed by wet etching (after wet etching, the structure of the substrate is as shown in FIG. 4, and the passive drain at the position of the third region 6 is shown.
  • the metal layer 3 is covered, and the source/drain metal layer 3 at the position of the second region 5 and the first region 4 remains due to the shielding of the photoresist;
  • the photoresist of the second region is removed to expose the source and drain metal layers at the locations where the openings are located.
  • the photoresist of the second region 5 is removed, so that the source/drain metal layer 3 at the position between the source and the drain is exposed, and at the same time, The photoresist of the region 4 is thinned, and the source/drain metal layer 3 at the position where the opening is located can be removed by subsequent dry etching, and the source and drain at the position of the first region 4 due to the shielding of the photoresist
  • the epitaxial metal layer 3 remains, which in turn forms the source 7 and drain 8 of FIG. 6, with an opening 9 between the source 7 and the drain 8.
  • the mask used in masking and exposing the photoresist may be a single slit mask, a semi-transparent mask or a gray scale mask.
  • the method of fabricating the substrate includes the following steps:
  • a gate insulating layer is formed on the gate.
  • FIG. 7 a partial structure of the thin film transistor that has been completed is as shown in FIG. Referring to FIG. 7, an embodiment of the present invention forms a gate metal layer on the base substrate, And the specific content of the step of forming a pattern including the gate through the patterning process is described in detail as follows:
  • a gate metal layer is deposited on the substrate by a plasma physical vapor deposition process.
  • the gate metal layer may be a single layer structure formed of low-resistance metals such as aluminum, molybdenum, copper, or aluminum/molybdenum or molybdenum. /Multilayer structure formed of aluminum/molybdenum or the like.
  • a photoresist is coated on the formed gate metal layer and covered with a mask, and the photoresist is exposed and developed to pattern the photoresist.
  • the photoresist metal-free gate metal layer is removed by wet etching, and the photoresist is stripped to form a pattern including the gate 10.
  • the photoresist metal-free gate metal layer may be removed by using an acidic etching solution, and the acidic etching liquid may be a strong corrosive acid such as hydrochloric acid or sulfuric acid.
  • a gate insulating layer 11 is deposited on the substrate by a plasma chemical enhanced vapor deposition process.
  • the material of the gate insulating layer 11 may be, for example, silicon nitride, silicon dioxide or a high-resistance organic insulating material.
  • an embodiment of the present invention provides a most specific manufacturing method of a thin film transistor, and the manufacturing method includes the following steps:
  • a pattern including source 7 and drain 8 is formed by a patterning process as shown in FIGS. 3-6.
  • Embodiments of the present invention provide a method for fabricating an array substrate, and a method for fabricating the array substrate A method of fabricating a thin film transistor according to the first embodiment.
  • the method for fabricating the array substrate according to the embodiment of the present invention includes the method for fabricating the thin film transistor according to the first embodiment. Therefore, the method for fabricating the array substrate has the same beneficial effects as the method for fabricating the thin film transistor, and details are not described herein. .
  • the method for fabricating the array substrate further includes:
  • the first pixel electrode is annealed.
  • the specific content of forming the first pixel electrode is as follows:
  • a transparent conductive layer is deposited on the substrate by a plasma physical vapor deposition process.
  • a photoresist is coated on the formed transparent conductive layer and covered with a mask, and the photoresist is exposed and developed to pattern the photoresist.
  • the photoresist-free transparent conductive layer is removed by wet etching, and the photoresist is stripped to form a pattern including the first pixel electrode 12.
  • the material of the transparent conductive layer may be indium tin oxide, zinc oxide or the like.
  • the transparent etching layer covered by the photoresist can be removed by using an acidic etching solution, and the acidic etching liquid can be a strong corrosive acid such as hydrochloric acid or sulfuric acid.
  • the first pixel electrode 12 is a plate electrode.
  • the annealing atmosphere may be air (for example, ultra-pure clean air) or nitrogen
  • the annealing temperature may be 230 ° C to 280 ° C
  • the annealing time may be 20 min to 40 min.
  • the transparent conductive material can be recrystallized, thereby reducing the lattice defects of the first pixel electrode 12, and is not easily corroded by the acidic etching liquid used for subsequently etching the oxide semiconductor layer and the source/drain metal layer. And the electrical performance is improved.
  • the method for fabricating the array substrate further includes:
  • the second pixel electrode is annealed.
  • a passivation layer 13 is deposited on the substrate by a plasma enhanced chemical vapor deposition process.
  • the material of the passivation layer 13 may be: silicon dioxide, silicon nitride or a composite material of silicon dioxide and silicon nitride.
  • the embodiment of the present invention further includes the step of annealing the portions of the array substrate that have been formed after forming the passivation layer 13 to recrystallize the oxide semiconductor to improve the electrical consistency of the active layer 2.
  • the annealing temperature may be 280 ° C
  • the annealing time may be 20 min to 40 min.
  • a specific implementation of forming the second pixel electrode is as follows: First, a transparent conductive layer is deposited on the substrate by a plasma physical vapor deposition process. Then, a photoresist is coated on the formed transparent conductive layer and covered with a mask, and the photoresist is exposed and developed to pattern the photoresist. Next, the photoresist-free transparent conductive layer is removed by wet etching, and the photoresist is stripped to form a pattern including the second pixel electrode 14.
  • the material of the transparent conductive layer may be indium tin oxide, zinc oxide or the like.
  • the transparent etching layer covered by the photoresist can be removed by using an acidic etching solution, and the acidic etching liquid can be a strong corrosive acid such as hydrochloric acid or sulfuric acid.
  • the second pixel electrode 14 is a slit electrode or a strip electrode.
  • the first pixel electrode 4 is a plate electrode
  • the second pixel electrode 14 is a slit electrode or a strip electrode, so that a multi-dimensional electric field is formed between the first pixel electrode 4 and the second pixel electrode 14.
  • liquid crystal molecules directly between the second pixel electrode 14 and the second pixel electrode 14 can be deflected, thereby improving the working efficiency of the liquid crystal molecules and increasing the light transmission efficiency.
  • the annealing atmosphere may be air (for example, ultra-pure clean air) or nitrogen, the annealing temperature may be 230 ° C to 280 ° C, and the annealing time may be 20 min to 40 min.
  • the transparent conductive material can be recrystallized, so that the lattice defects in the second pixel electrode 14 are reduced, are not easily corroded, and electrical properties are improved.
  • an embodiment of the present invention provides an array substrate.
  • the manufacturing method of the body includes the following steps:
  • An oxide semiconductor layer is formed on the gate insulating layer 11, and a pattern including the active layer 2 is formed by a patterning process as shown in FIG. 1;
  • the second pixel electrode 14 is annealed.

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Abstract

一种薄膜晶体管的制作方法和阵列基板的制作方法，包括：制作基板（1）；在基板上形成氧化物半导体层；经过构图工艺形成包括有源层（2）的图形；在有源层（2）上形成源漏极金属层（3）；经过构图工艺形成包括源极（7）和漏极（8）的图形，源极（7）和漏极（8）之间具有与有源层（2）中用以作为沟道的区域相对应的开口（9）；其中，经过构图工艺形成包括源极（7）和漏极（8）的图形的步骤包括：通过干法刻蚀去除开口（9）所在位置处的源漏极金属层（3）的一部分。该方法可用于制作薄膜晶体管。

Description

薄膜晶体管的制作方法和阵列基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及薄膜晶体管的制作方法和阵列基板的制作方法。
背景技术
目前，常用的液晶显示器为薄膜晶体管液晶显示器。薄膜晶体管按有源层材料不同可以分为非晶硅薄膜晶体管、多晶硅薄膜晶体管、氧化物半导体薄膜晶体管。其中，由于氧化物半导体薄膜晶体管具有制作工艺简单、电子迁移率高等优点，进而被大规模应用于液晶显示器中。
目前，氧化物半导体薄膜晶体管的制作过程包括：第一步，形成栅极金属层，经过构图工艺形成包括栅极的图形；第二步，在栅极上形成栅极绝缘层；第三步，形成氧化物半导体层，经过构图工艺形成包括有源层的图形；第四步，在有源层上形成源漏极金属层，经过构图工艺形成包括源极和漏极的图形。
在上述第四步中，需要使用酸性刻蚀液对源漏极金属层进行刻蚀以形成包括源极和漏极的图形，因此在刻蚀过程中，有源层中用以作为沟道的区域直接暴露在酸性刻蚀液中，从而使得酸性刻蚀液会对该区域造成腐蚀，进而影响氧化物半导体薄膜晶体管的电学特性。
为解决该问题，目前存在一种方案，其中，在有源层上方先形成一层刻蚀阻挡层，再形成源漏极金属层，进而对源漏极金属层进行湿法刻蚀以形成源极和漏极的方式，解决在刻蚀形成源极和漏极的过程中有源层中用以作为沟道的区域受到腐蚀的问题。但是，在这种方案中，源极和漏极需要分别通过刻蚀阻挡层上的过孔与有源层连接，由于形成过孔工艺的限制，使得现有技术中源极和漏极之间的间距较大，进而使得沟道长度较大，不利于提升氧化物半导体薄膜晶体管的电学特性，且使得氧化物半导体薄膜晶体管的尺寸较大，不利于提 高显示装置的开口率和解析度。
因此，需要一种能够防止有源层被腐蚀并且不会导致氧化物半导体薄膜晶体管电学特性下降的制作方法。
发明内容
本发明的目的在于提供一种薄膜晶体管的制作方法和阵列基板的制作方法，从而，在刻蚀形成源极和漏极的过程中，能够防止有源层中用以作为沟道的区域受到腐蚀。
为达到上述目的，根据本发明的一个方面，提供了薄膜晶体管的制作方法。
在示例性的实施例中，薄膜晶体管的制作方法包括以下步骤：制作基板；在所述基板上形成氧化物半导体层；经过构图工艺形成包括有源层的图形；在所述有源层上形成源漏极金属层；和经过构图工艺形成包括源极和漏极的图形，所述图形包括形成于所述源极与所述漏极之间的与所述有源层中用以作为沟道的区域相对应的开口；其中，所述经过构图工艺形成包括源极和漏极的图形的步骤包括：通过干法刻蚀去除所述开口所在位置处的所述源漏极金属层的一部分。
在本发明提供的薄膜晶体管的制作方法中，由于通过干法刻蚀去除开口所在位置处的源漏极金属层，即有源层中用以作为沟道的区域相对应的源漏极金属层，从而使得在刻蚀过程中不需要使用酸性刻蚀液，进而能够有效防止在刻蚀形成源极和漏极的过程中，有源层中用以作为沟道的区域被酸性刻蚀液腐蚀，进而能够有效改善氧化物半导体薄膜晶体管的电学特性。
此外，本发明还提供了一种阵列基板的制作方法，该阵列基板的制作方法包括如上所述的薄膜晶体管的制作方法。
由于本发明提供的阵列基板的制作方法包括如上所述的薄膜晶体管的制作方法，因此，阵列基板的制作方法具有和薄膜晶体管的制作方法相同的有益效果，此处不再进行赘述。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中的形成包括有源层的图形后的基板的示意图；
图2为本发明实施例中的形成源漏极金属层后的基板的示意图；
图3为本发明实施例中的形成完全保留区、部分保留区和完全去除区后的基板的示意图；
图4为本发明实施例中的去除完全去除区所在位置处的源漏极金属层后的基板的示意图；
图5为本发明实施例中的去除部分保留区光刻胶后的基板的示意图；
图6为本发明实施例中的形成包括源极和漏极的图形后的基板的示意图；
图7为本发明实施例中的形成包括栅极的图形后的基板的示意图；
图8为本发明实施例中的形成栅极绝缘层后的基板的示意图；
图9为本发明实施例中的形成第一像素电极后的基板的示意图；
图10为本发明实施例中的形成钝化层后的基板的示意图；
图11为本发明实施例中的形成第二像素电极后的基板的示意图。
附图标记说明：
1-衬底基板；            2-有源层；             3-源漏极金属层；
4-第一区；              5-第二区；             6-第三区；
7-源极；                8-漏极；               9-开口；
10-栅极；               11-栅极绝缘层；        12-第一像素电极；
13-钝化层；            14-第二像素电极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括：
制作基板；
在所述基板上形成氧化物半导体层；
经过构图工艺形成包括有源层的图形；
在有源层上形成源漏极金属层；和
经过构图工艺形成包括源极和漏极的图形，所述图形包括形成于源极和漏极之间的与有源层中用以作为沟道的区域相对应的开口。
其中，经过构图工艺形成包括源极和漏极的图形的步骤包括：通过干法刻蚀去除开口所在位置处的源漏极金属层的一部分。
本发明实例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法通过干法刻蚀去除开口所在位置处的源漏极金属层，即有源层中用以作为沟道的区域相对应的源漏极金属层，从而使得在刻蚀过程中不需要使用酸性刻蚀液，进而能够有效防止在刻蚀形成源极和漏极的过程中，有源层中用以作为沟道的区域被酸性刻蚀液腐蚀，进而能够有效改善氧化物半导体薄膜晶体管的电学特性。
与已知的技术相比，本发明实施例中通过采用干法刻蚀的方式去除开口所在位置处的源漏极金属层，从而使得无需设置刻蚀阻挡层，进而能够使得源极和漏极之间的开口较小，使沟道长度较小，保证了氧化物半导体薄膜晶体管的 电学特性，且使得氧化物半导体薄膜晶体管的尺寸较小，有利于提高显示装置的开口率和解析度。
示例性地，在形成氧化物半导体层之后，已经完成的薄膜晶体管的部分结构如图1所示。由于之前的步骤与已知技术相同，此处不再详细说明。此外，如无特殊说明，本发明实施例中的基板均为衬底基板1和形成在衬底基本1上栅极金属层和栅极绝缘层的统称，即，基板包括衬底基板1和形成在衬底基本1上栅极金属层和栅极绝缘层。
参照图1，本发明实施例对形成氧化物半导体层的步骤的具体内容详细描述如下：
首先，通过等离子体增强型物理气相沉积工艺在基板上，沉积一层氧化物半导体层；例如，氧化物半导体层的厚度可以为30nm～80nm，氧化物半导体层的材质可以为铟镓锌氧化物。
然后，在形成的氧化物半导体层上涂布一层光刻胶，并使用遮掩板遮盖，对该光刻胶进行曝光和显影，以使光刻胶具有图案化。
接下来，通过湿法刻蚀去除无光刻胶覆盖的氧化物半导体层，并剥离光刻胶，以形成包括有源层2的图形。例如，在湿法刻蚀过程中，可以采用酸性刻蚀液去除无光刻胶覆盖的氧化物半导体层，酸性刻蚀液可以为：盐酸、硫酸等强腐蚀性酸。
示例性地，步骤b中，可以通过等离子体物理气相沉积工艺在形成有有源层2的基板上，沉积一层源漏极金属层。例如，源漏极金属层的材质可以为：铜、钼等可以进行干法刻蚀的低电阻金属。形成源漏极金属层后，基板的结构如图2所示，例如，源漏极金属层3覆盖在整个基板上。
进一步地，在形成源漏极金属层的步骤中，在通过干法刻蚀去除开口所在位置处的源漏极金属层的一部分之前，经过构图工艺形成包括源极和漏极的图形的步骤还可以包括：
在源漏极金属层上涂布一层光刻胶；
使用掩膜板遮盖光刻胶，并进行曝光，以形成光刻胶完全未曝光的第一区、光刻胶部分曝光的第二区和光刻胶完全曝光的第三区，其中，所述第一区4对应于所述源极和所述漏极所在位置，所述第二区5对应于所述开口所在位置，所述第三区6对应于其他位置；
对曝光后的光刻胶进行显影，使得第一区内的光刻胶完全保留、第二区内的光刻胶部分保留、并且第三区内的光刻胶完全去除；
通过湿法刻蚀去除光刻胶完全去除区所在位置处的源漏极金属层的一部分(湿法刻蚀后，基板的结构如图4所示，第三区6所在位置处无源漏极金属层3覆盖，由于光刻胶的遮挡，第二区5和第一区4所在位置处的源漏极金属层3仍然保留)；和
经过灰化工艺，去除第二区的光刻胶，以使开口所在位置处的源漏极金属层暴露。如图5所示，经过灰化工艺后，第二区5的光刻胶被去除，从而使得源极和漏极之间的开口所在位置处的源漏极金属层3暴露，同时，第一区4的光刻胶被减薄，进而可以通过后续的干法刻蚀去除开口所在位置处的源漏极金属层3，而由于光刻胶的遮挡，第一区4所在位置处的源漏极金属层3仍然保留，进而形成图6中的源极7和漏极8，其中，源极7和漏极8之间具有开口9。
此外在对光刻胶进行掩膜和曝光的过程中使用的掩膜板可以为：单狭缝掩膜板、半透掩膜板或者灰阶掩膜板。
此外，制作基板的方法包括以下步骤：
提供衬底基板；
在所述衬底基板上形成栅极金属层；
经过构图工艺形成包括栅极的图形；和
在栅极上形成栅极绝缘层。
示例性地，在形成包括栅极的图形之后，已经完成的薄膜晶体管的部分结构如图7所示。参照图7，本发明实施例对在所述衬底基板上形成栅极金属层、 以及经过构图工艺形成包括栅极的图形的步骤的具体内容详细描述如下：
首先，通过等离子体物理气相沉积工艺在基板上，沉积一层栅极金属层，例如，栅极金属层可以为：铝、钼、铜等低电阻金属形成的单层结构或者铝/钼、钼/铝/钼等形成的多层结构。
然后，在形成的栅极金属层上涂布一层光刻胶，并使用掩膜板遮盖，对该光刻胶进行曝光和显影，以使光刻胶具有图案化。
接下来，通过湿法刻蚀去除对无光刻胶覆盖的栅极金属层，并剥离光刻胶，以形成包括栅极10的图形。例如，在湿法刻蚀过程中，可以采用酸性刻蚀液去除无光刻胶覆盖的栅极金属层，酸性刻蚀液可以为：盐酸、硫酸等强腐蚀性酸。
示例性地，在形成栅极绝缘层之后，已经完成的薄膜晶体管的部分结构如图8所示。参照图8，形成栅极绝缘层的步骤的具体内容详细描述如下：通过等离子体化学增强型气相沉积工艺在基板上，沉积一层栅极绝缘层11。栅极绝缘层11的材质例如可以为：硅的氮化物、二氧化硅或者高电阻有机绝缘材料。
为了便于本领域技术人员理解，本发明实施例提供一种薄膜晶体管的最为具体的制作方法，该制作方法包括以下步骤：
提供衬底基板，在衬底基板上形成栅极金属层，并经过构图工艺形成包括栅极10的图形，如图7所示；
在栅极10上形成栅极绝缘层11，如图8所示；
在栅极绝缘层11上形成氧化物半导体层，经过构图工艺形成包括有源层2的图形，如图1所示；
在有源层2上形成源漏极金属层3，如图2所示；
经过构图工艺形成包括源极7和漏极8的图形，如图3-6所示。
实施例二
本发明实施例提供了一种阵列基板的制作方法，该阵列基板的制作方法包 括实施例一所述的薄膜晶体管的制作方法。
由于本发明实施例提供的阵列基板的制作方法包括实施例一所述的薄膜晶体管的制作方法，因此，阵列基板的制作方法具有和薄膜晶体管的制作方法相同的有益效果，此处不再进行赘述。
进一步地，在形成源漏极金属层，经过构图工艺形成包括源极和漏极的图形的步骤之前，阵列基板的制作方法还包括：
形成第一像素电极，使得第一像素电极的一部分的位置与随后将要形成的薄膜晶体管的漏极的一部分位置对应，如图9所示；和
对第一像素电极进行退火处理。
示例性地，形成第一像素电极的具体内容如下：
首先，通过等离子体物理气相沉积工艺在基板上，沉积一层透明导电层。
然后，在形成的透明导电层上涂布一层光刻胶，并使用掩膜板遮盖，对该光刻胶进行曝光和显影，以使光刻胶具有图案化。
接下来，通过湿法刻蚀去除无光刻胶覆盖的透明导电层，并剥离光刻胶，以形成包括第一像素电极12的图形。例如，透明导电层的材质可以为氧化铟锡、氧化锌等。在湿法刻蚀过程中，可以采用酸性刻蚀液去除无光刻胶覆盖的透明导电层，酸性刻蚀液可以为：盐酸、硫酸等强腐蚀性酸。可选地，第一像素电极12为板状电极。
在对第一像素电极12进行退火处理的过程中，例如，退火气氛可以为空气(例如，超纯干净空气)或者氮气，退火温度可以为230℃～280℃，退火时间可以为20min～40min。经过退火处理后，透明导电物能够再结晶，从而使得第一像素电极12的晶格缺陷减少，而不容易被后续刻蚀氧化物半导体层和源漏极金属层时使用的酸性刻蚀液腐蚀，且电学性能得以提升。
进一步地，在经过构图工艺形成包括源极7和漏极8的图形的步骤之后，阵列基板的制作方法还包括：
在源极和漏极上形成钝化层13，如图10所示；
在所述钝化层上形成第二像素电极，如图11所示；和
对所述第二像素电极进行退火处理。
示例性地，形成钝化层的具体实现方式如下：通过等离子体增强型化学气相沉积工艺在基板上，沉积一层钝化层13。其中，钝化层13的材质可以为：二氧化硅、氮化硅或者二氧化硅和氮化硅的复合材料。
进一步地，本发明实施例还包括在形成钝化层13之后，对目前已经形成的阵列基板各部分进行退火处理的步骤，以使氧化物半导体再结晶，使有源层2的电学一致性提升。示例性地，在该退火处理的过程中，退火温度可以为280℃，退火时间可以为20min～40min。
示例性地，形成第二像素电极的具体实现方式如下：首先，通过等离子体物理气相沉积工艺在基板上，沉积一层透明导电层。然后，在形成的透明导电层上涂布一层光刻胶，并使用掩膜板遮盖，对该光刻胶进行曝光和显影，以使光刻胶具有图案化。接下来，通过湿法刻蚀去除无光刻胶覆盖的透明导电层，并剥离光刻胶，以形成包括第二像素电极14的图形。其中，透明导电层的材质可以为：氧化铟锡、氧化锌等。在湿法刻蚀过程中，可以采用酸性刻蚀液去除无光刻胶覆盖的透明导电层，酸性刻蚀液可以为：盐酸、硫酸等强腐蚀性酸。可选地，第二像素电极14为狭缝电极或者条状电极。
本发明实施例中优选，第一像素电极4为板状电极，第二像素电极14为狭缝电极或者条状电极，以使第一像素电极4和第二像素电极14之间形成多维电场，进而使第二像素电极14间和第二像素电极14正上方的液晶分子都能够产生偏转，从而提高液晶分子工作效率并增大了透光效率。
在对第二像素电极14进行退火处理的过程中，退火气氛可以为空气(例如超纯干净空气)或者氮气，退火温度可以为230℃～280℃，退火时间可以为20min～40min。经过退火处理后，透明导电物能够再结晶，从而使得第二像素电极14中的晶格缺陷减少，而不容易被腐蚀，且电学性能得以提升。
为了便于本领域技术人员理解，本发明实施例提供一种阵列基板的最为具 体的制作方法，该制作方法包括以下步骤：
提供衬底基板，在衬底基板上形成栅极金属层，并经过构图工艺形成包括栅极10的图形，如图7所示；
在栅极10形成栅极绝缘层11，如图8所示；
在栅极绝缘层11上形成第一像素电极12，如图9所示；
对第一像素电极12进行退火处理；
在栅极绝缘层11上形成氧化物半导体层，经过构图工艺形成包括有源层2的图形如图1所示；
在有源层2上形成源漏极金属层3，如图2所示；
经过构图工艺形成包括源极7和漏极8的图形，如图3-6所示；
在源极7和漏极8上形成钝化层13，如图10所示；
对已形成的阵列基板的各部分进行退火处理；
在钝化层13上形成第二像素电极14，如图11所示；
对第二像素电极14进行退火处理。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种薄膜晶体管的制作方法，其特征在于，包括：
    制作基板；
    在所述基板上形成氧化物半导体层；
    经过构图工艺形成包括有源层的图形；
    在所述有源层上形成源漏极金属层；和
    经过构图工艺形成包括源极和漏极的图形，所述图形包括形成于所述源极与所述漏极之间的与所述有源层中用以作为沟道的区域相对应的开口；
    其中，所述经过构图工艺形成包括源极和漏极的图形的步骤包括：通过干法刻蚀去除所述开口所在位置处的所述源漏极金属层的一部分。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，在通过干法刻蚀去除所述开口所在位置处的所述源漏极金属层的一部分的步骤之前，所述经过构图工艺形成包括源极和漏极的图形的步骤还包括：
    在所述源漏极金属层上涂布一层光刻胶；
    使用掩膜板遮盖所述光刻胶，并进行曝光，以形成光刻胶完全未曝光的第一区、光刻胶部分曝光的第二区和光刻胶完全曝光的第三区，其中，所述第一区对应于所述源极和所述漏极所在位置，所述第二区对应于所述开口所在位置，所述第三区对应于其他位置；
    对曝光后的所述光刻胶进行显影，使得第一区内的光刻胶完全保留、第二区内的光刻胶部分保留、并且第三区内的光刻胶完全去除；
    通过湿法刻蚀去除所述第三区所在位置处的所述源漏极金属层的一部分；和
    经过灰化工艺，去除所述光刻胶部分保留区的所述光刻胶，以使所述开口所在位置处的所述源漏极金属层暴露。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其特征在于，所述掩 膜板为单狭缝掩膜板、半透掩膜板或者灰阶掩膜板。
  4. 根据权利要求1-3任一项所述的薄膜晶体管的制作方法，其特征在于，制作基板的方法包括：
    提供衬底基板；
    在所述衬底基板上形成栅极金属层；
    经过构图工艺形成包括栅极的图形；和
    在所述栅极上形成栅极绝缘层。
  5. 一种阵列基板的制作方法，其特征在于，包括如权利要求1-4任一项所述的薄膜晶体管的制作方法。
  6. 根据权利要求5所述的阵列基板的制作方法，其特征在于，在形成源漏极金属层之前，所述阵列基板的制作方法还包括：
    形成第一像素电极，使得所述第一像素电极的一部分的位置与随后将要形成的薄膜晶体管的漏极的一部分的位置对应；
    对所述第一像素电极进行退火处理。
  7. 根据权利要求6所述的阵列基板的制作方法，其特征在于，所述第一像素电极为板状电极。
  8. 根据权利要求6所述的阵列基板的制作方法，其特征在于，在经过构图工艺形成包括源极和漏极的图形的步骤之后，所述阵列基板的制作方法还包括：
    在所述源极和漏极上形成钝化层；
    在所述钝化层上形成第二像素电极；和
    对所述第二像素电极进行退火处理。
  9. 根据权利要求8所述的阵列基板的制作方法，其特征在于，所述第二像素电极为狭缝电极或者条状电极。
  10. 根据权利要求6-9任一项所述的阵列基板的制作方法，其特征在于，在对所述第一像素电极或者所述第二像素电极进行退火处理的过程中，退火气 氛为空气或者氮气，退火温度为230℃～280℃，退火时间为20min～40min。
  11. 根据权利要求8所述的阵列基板的制作方法，其特征在于，所述阵列基板的制作方法还包括：在所述形成钝化层之后，对已形成的阵列基板的各部分进行退火处理。
  12. 根据权利要求11所述的阵列基板的制作方法，其特征在于，在对所述阵列基板进行退火处理的过程中，退火温度为280℃，退火时间为20min～40min。
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